DS8024-RJX/V+

DS8024 Smart Card Interface General Description The DS8024 smart card interface IC is a low-cost, analog front-end for a smart card reader, designed for all ISO 7816, EMV®, and GSM11-11 applications. The DS8024 is a pin-for-pin drop-in replacement for the NXP TDA8024 and is offered in 28-pin TSSOP and SO packages. Applications requiring support for 1.8V smart cards or requiring low power should consider the DS8113, which achieves lower active- and stop-mode power with minimal changes to application hardware and software. Applications Set-Top Box Conditional Access Access Control Banking Applications POS Terminals Debit/Credit Payment Terminals Features o Analog Interface and Level Shifting for IC Card Communication o ±8kV (min) ESD (IEC) Protection on Card Interfaces o Internal IC Card Supply-Voltage Generation: 5.0V ±5%, 80mA (max) 3.0V ±8%, 65mA (max) o Automatic Card Activation and Deactivation Controlled by Dedicated Internal Sequencer o I/O Lines from Host Directly Level Shifted for Smart Card Communication o Flexible Card Clock Generation, Supporting External Crystal Frequency Divided by 1, 2, 4, or 8 o High-Current, Short-Circuit and High-Temperature Protection PIN Pads Automated Teller Machines Pin Configuration Telecommunications Pay/Premium Television TOP VIEW Ordering Information PART DS8024-RJX+ DS8024-RJX/V+ TEMP RANGE -40°C to +85°C -40°C to +85°C CLKDIV1 1 28 AUX2IN CLKDIV2 2 27 AUX1IN PIN-PACKAGE 5V/3V 3 26 I/OIN 28 TSSOP PGND 4 25 XTAL2 CP2 5 24 XTAL1 28 TSSOP DS8024-RRX+ -40°C to +85°C 28 SO Note: Contact the factory for availability of other variants and package options. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive-qualified part. Selector Guide appears at end of data sheet. VDDA 6 DS8024 23 OFF CP1 7 22 GND VUP 8 21 VDD PRES 9 20 RSTIN PRES 10 19 CMDVCC I/O 11 18 N.C. AUX2 12 17 VCC AUX1 13 16 RST CGND 14 15 CLK SO/TSSOP EMV is a registered trademark of EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6220; Rev 4; 4/13 DS8024 Smart Card Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on VDD Relative to GND ...............-0.5V to +6.5V Voltage Range on VDDA Relative to PGND ...........-0.5V to +6.5V Voltage Range on CP1, CP2, and VUP Relative to PGND...............................................-0.5V to +7.5V Voltage Range on All Other Pins Relative to GND......................................-0.5V to (VDD + 0.5V) Maximum Junction Temperature .....................................+125°C Continuous Power Dissipation (multilayer board, TA = +70°C) TSSOP (derate 14mW/°C above +70°C) .................1117.3mW SO (derate 16.7mW/°C above +70°C) .....................1355.9mW Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V POWER SUPPLY Digital Supply Voltage Card Voltage-Generator Supply Voltage Reset Voltage Thresholds VDD 2.7 6.0 VCC = 5V, |ICC| < 80mA 4.0 6.0 VCC = 5V, |ICC| < 30mA 3.0 6.0 VTH2 Threshold voltage (falling) 2.30 2.45 2.60 V VHYS2 Hysteresis 50 100 150 mV ICC = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V 215 mA ICC = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 135 mA ICC = 65mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V 100 mA ICC = 65mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 35 mA Card inactive 500 μA 20 MHz 0 20 MHz VDDA V CURRENT CONSUMPTION Active VDD Current 5V Cards (Including 80mA Draw from 5V Card) IDD_50V Active VDD Current 5V Cards (Current Consumed by DS8024 Only) IDD_IC Active VDD Current 3V Cards (Including 65mA Draw from 3V Card) IDD_30V Active VDD Current 3V Cards (Current Consumed by DS8024 Only) IDD_IC Inactive-Mode Current IDD CLOCK SOURCE Crystal Frequency fXTAL External crystal fXTAL1 XTAL1 Operating Conditions External Capacitance for Crystal Internal Oscillator 0 VIL_XTAL1 Low-level input on XTAL1 (Note 3) -0.3 0.3 x VDD VIH_XTAL1 High-level input on XTAL1 (Note 3) 0.7 x VDD VDD + 0.3 CXTAL1, CXTAL2 (Note 3) fINT 15 V pF 2.7 MHz +150 °C SHUTDOWN TEMPERATURE Shutdown Temperature 2 TSD (Note 3) Maxim Integrated DS8024 Smart Card Interface RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RST PIN Card-Inactive Mode Card-Active Mode Output Low Voltage VOL_RST1 IOL_RST = 1mA 0 0.3 V Output Current IOL_RST1 VO_LRST = 0V 0 -1 mA Output Low Voltage VOL_RST2 IOL_RST = 200μA 0 0.3 V Output High Voltage VOH_RST2 IOH_RST = -200μA VCC 0.5 VCC V Rise Time tR_RST CL = 30pF (Note 3) 0.1 μs Fall Time tF_RST CL = 30pF (Note 3) 0.1 μs Shutdown Current Threshold IRST(SD) Current Limitation IRST(LIMIT) -20 -20 mA +20 mA 2 μs 0.3 V RSTIN to RST Delay tD(RSTIN-RST) Output Low Voltage VOL_CLK1 IOLCLK = 1mA Output Current IOL_CLK1 VOLCLK = 0V 0 -1 mA Output Low Voltage VOL_CLK2 IOLCLK = 200μA 0 0.3 V Output High Voltage VOH_CLK2 IOHCLK = -200μA VCC 0.5 VCC V CLK PIN Card-Inactive Mode Card-Active Mode 0 Rise Time tR_CLK CL = 30pF (Note 3) 8 ns Fall Time tF_CLK CL = 30pF (Note 3) 8 ns Current Limitation ICLK(LIMIT) -70 +70 mA Clock Frequency fCLK Operational (Note 3) 0 10 MHz
CL = 30pF (Note 3) 45 55 % SR CL = 30pF (Note 3) 0.2 Duty Factor Slew Rate V/ns VCC PIN Card-Inactive Mode Output Low Voltage VCC1 ICC = 1mA 0 0.3 V Output Current ICC1 VCC = 0V 0 -1 mA Output Low Voltage VCC2 Card-Active Mode Output Current Shutdown Current Threshold Slew Rate Maxim Integrated ICC2 ICC(5V) < 80mA 4.75 5.00 5.25 ICC(3V) < 65mA 2.78 3.00 3.22 5V card: current pulses of 40nC with I < 200mA, t < 400ns, f < 20MHz (Note 3) 4.6 5.4 3V card: current pulses of 24nC with I < 200mA, t < 400ns, f < 20MHz (Note 3) 2.75 3.25 VCC(5V) = 0 to 5V -80 VCC(3V) = 0 to 3V -65 ICC(SD) VCCSR 120 Up/down, C < 300nF 0.05 0.16 V mA mA 0.22 V/μs 3 DS8024 Smart Card Interface RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DATA LINES (I/O AND I/OIN) I/O  I/OIN Falling Edge Delay Pullup Pulse Active Time Maximum Frequency tD(IO-IOIN) (Note 3) 200 ns tPU (Note 3) 100 ns 1 MHz (Note 3) 10 pF fIOMAX Input Capacitance CI I/O, AUX1, AUX2 PINS Card-Inactive Mode Card-Active Mode Output Low Voltage VOL_IO1 IOL_IO = 1mA 0 0.3 V Output Current IOL_IO1 VOL_IO = 0V 0 -1 mA Internal Pullup Resistor RPU_IO To VCC 9 19 k
Output Low Voltage VOL_IO2 IOL_IO = 1mA 0 0.3 V Output High Voltage VOH_IO2 IOH_IO = < -40μA (3V/5V) VCC V 0.1 μs 11 0.75 x VCC Output Rise/Fall Time Input Low Voltage VIL_IO -0.3 +0.8 Input High Voltage VIH_IO 1.5 VCC tOT CL = 30pF (Note 3) V Input Low Current IIL_IO VIL_IO = 0V 700 μA Input High Current IIH_IO VIH_IO = VCC 20 μA Input Rise/Fall Time tIT (Note 3) 1.2 μs +15 mA Current Limitation Current When Pullup Active IIO(LIMIT) CL = 30pF -15 IPU CL = 80pF, VOH = 0.9 x VDD (Note 3) -1 VOL IOL = 1mA mA I/OIN, AUX1IN, AUX2IN PINS Output Low Voltage Output High Voltage VOH IOH < -40μA Output Rise/Fall Time tOT CL = 30pF, 10% to 90% (Note 3) 0 0.3 V 0.75 x VDD VDD + 0.1 V 0.1 μs V V Input Low Voltage VIL -0.3 0.3 x VDD Input High Voltage VIH 0.7 x VDD VDD + 0.3 Input Low Current IIL_IO VIL = 0V 600 μA Input High Current IIH_IO VIH = VDD 10 μA Input Rise/Fall Time tIT VIL to VIH (Note 3) Integrated Pullup Resistor RPU Pullup to VDD 9 Current When Pullup Active IPU CL = 30pF, VOH = 0.9 x VDD (Note 3) -1 4 11 1.2 μs 13 k
mA Maxim Integrated DS8024 Smart Card Interface RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V) Input Low Voltage VIL -0.3 0.3 x VDD V Input High Voltage VIH 0.7 x VDD VDD + 0.3 V Input Low Current IIL_IO 5 μA Input High Current IIH_IO Integrated Pullup Resistor 0 < VIL < VDD 0 < VIH < VDD RPU Pullup to VDD, 5V/3V only VOL IOL = 2mA 50 85 5 μA 120 kĀ 0.3 V INTERRUPT OUTPUT PIN (OFF) Output Low Voltage 0 Output High Voltage VOH IOH = -15μA 0.75 x VDD Integrated Pullup Resistor RPU Pullup to VDD 12 V 20 28 k
0.3 x VDD V PRES, PRES PINS Input Low Voltage VIL_PRES Input High Voltage VIH_PRES 0.7 x VDD V Input Low Current IIL_PRES VIL_PRES = 0V 40 μA Input High Current IIH_PRES VIH_PRES = VDD 40 μA TIMING Activation Time tACT 160 μs tDEACT 80 μs Window Start t3 95 Window End t5 160 tDEBOUNCE 8 Deactivation Time CLK to Card Start Time PRES/PRES Debounce Time μs ms Note 1: Operation guaranteed at TA = -40°C and TA = +85°C, but not tested. Note 2: IDD_IC measures the amount of current used by the DS8024 to provide the smart card current minus the load. Note 3: Guaranteed by design, but not production tested. Maxim Integrated 5 DS8024 Smart Card Interface Pin Description 6 PIN NAME 1, 2 CLKDIV1, CLKDIV2 FUNCTION 3 5V/3V 5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects 5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card voltages. 4 PGND Analog Ground 5, 7 CP2, CP1 6 VDDA 8 VUP 9 PRES Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active. 10 PRES Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active. Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available. Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100mĀ) between CP1 and CP2. Charge-Pump Supply. Must be equal to or higher than VDD. Connect a supply of at least 3.3V. Charge-Pump Output. Connect a 100nF capacitor (ESR < 100mĀ) between V UP and GND. 11 I/O 12, 13 AUX2, AUX1 Smart Card Data-Line Output. Card data communication line, contact C7. Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1) and C8 (AUX2). 14 CGND Smart Card Ground 15 CLK Smart Card Clock. Card clock, contact C3. 16 RST Smart Card Reset. Card reset output from contact C2. 17 VCC Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF capacitors (ESR < 100m
). 18 N.C. 19 CMDVCC 20 RSTIN 21 VDD Supply Voltage 22 GND Digital Ground 23 OFF Status Output. Active-low interrupt output to the host. Use a 20k
integrated pullup resistor to VDD. 24, 25 XTAL1, XTAL2 26 I/OIN 27, 28 AUX1IN, AUX2IN No Connection. Unused on the DS8024. Activation Sequence Initiate. Active-low input from host. Card Reset Input. Reset input from the host. Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on XTAL1. I/O Input. Host-to-interface chip data I/O line. C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8. Maxim Integrated DS8024 Smart Card Interface Detailed Description The DS8024 is an analog front-end for communicating with 3V and 5V smart cards. Using an integrated charge pump, the DS8024 can operate from a single input voltage. The device translates all communication lines to the correct voltage level and provides power for smart card operation. It can operate from a wide input voltage range (3.3V to 6.0V). The DS8024 is compatible with the NXP TDA8024 and is provided in the same packages. (Note that the PORADJ pin is not present in the DS8024. Most applications do not make use of this VDD GND XTAL1 XTAL2 CLKDIV1 CLKDIV2 POWER-SUPPLY SUPERVISOR CARD VOLTAGE GENERATOR AND CHARGE PUMP CLOCK GENERATION TEMPERATURE MONITOR 5V/3V CMDVCC RSTIN OFF I/OIN AUX1IN AUX2IN VDDA PGND CP1 CP2 VUP CONTROL SEQUENCER VCC CGND RST CLK PRES PRES I/O TRANSCEIVER I/O AUX1 AUX2 input pin, instead using the DS8024’s default reset threshold.) Power Supply The DS8024 can operate from a single supply or a dual supply. The supply pins for the device are VDD, GND, VDDA, and PGND. VDD should be in the range of 2.7V to 6.0V, and is the supply for signals that interface with the host controller. It should, therefore, be the same supply as used by the host controller. All smart card contacts remain inactive during power on or power off. The internal circuits are kept in the reset state until VDD reaches VTH2 + VHYS2 and for the duration of the internal power-on reset pulse, tW. A deactivation sequence is executed when VDD falls below VTH2. An internal charge pump and regulator generate the 3V or 5V card supply voltage (VCC). The charge pump and regulator are supplied by VDDA and PGND. VDDA should be connected to a minimum 3.3V (maximum 6.0V) supply and should be at a potential that is equal to or higher than VDD. The charge pump operates in a 1x (voltage follower) or 2x (voltage doubler) mode depending on the input VDDA and the selected card voltage (5V or 3V). • For 5V cards, the DS8024 operates in a 1x mode for VDDA > 5.8V and in a 2x mode for VDDA < 5.8V. • For 3V cards, the DS8024 operates in a 1x mode for VDDA > 4.1V and in a 2x mode for VDDA < 4.0V. Voltage Supervisor The voltage supervisor monitors the V DD supply. A 220µs reset pulse (tW) is used internally to keep the device inactive during power on or power off of the VDD supply. See Figure 2. DS8024 Figure 1. Functional Diagram VTH2 + VHYS2 VTH2 VDD ALARM (INTERNAL SIGNAL) tW tW POWER ON SUPPLY DROPOUT POWER OFF Figure 2. Voltage Supervisor Behavior Maxim Integrated 7 DS8024 Smart Card Interface The DS8024 card interface remains inactive no matter the levels on the command lines until duration tW after VDD has reached a level higher than VTH2 + VHYS2. When VDD falls below VTH2, the DS8024 executes a card deactivation sequence if its card interface is active. Clock Circuitry The clock signal from the DS8024 to the smart card (CLK) is generated from the clock input on XTAL1 or from a crystal operating at up to 20MHz connected between pins XTAL1 and XTAL2. The inputs CLKDIV1 and CLKDIV2 determine the frequency of the CLK signal, which can be fXTAL, fXTAL/2, fXTAL/4, or fXTAL/8. Table 1 shows the relationship between CLKDIV1 and CLKDIV2 and the frequency of CLK. Do not change the state of pins CLKDIV1 and CLKDIV2 simultaneously; a delay of 10ns minimum between changes is required. The minimum duration of any state of CLK is 8 periods of XTAL1. The hardware in the DS8024 guarantees that the frequency change is synchronous. During a transition of the clock divider, no pulse is shorter than 45% of the smallest period, and the clock pulses before and after the instant of change have the correct width. To achieve a 45% to 55% duty factor on pin CLK when no crystal is present, the input signal on XTAL1 should have a 48% to 52% duty factor. Transition time on XTAL1 should be less than 5% of the period. With a crystal, the duty factor on pin CLK may be 45% to 55% depending on the circuit layout and on the crystal characteristics and frequency. The DS8024 crystal oscillator runs when the device is powered up. If the crystal oscillator is used or the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card at time t4 (see Figures 7 and 8). If the signal applied to XTAL1 is controlled by the host microcontroller, the clock pulse is applied to the card when it is sent by the system microcontroller (after completion of the activation sequence). Table 1. Clock Frequency Selection 8 CLKDIV1 CLKDIV2 fCLK 0 0 fXTAL/8 0 1 fXTAL/4 1 1 fXTAL/2 1 0 fXTAL I/O Transceivers The three data lines I/O, AUX1, and AUX2 are identical. This section describes the characteristics of I/O and I/OIN but also applies to AUX1, AUX1IN, AUX2, and AUX2IN. I/O and I/OIN are pulled high with an 11kΩ resistor (I/O to VCC and I/OIN to VDD) in the inactive state. The first side of the transceiver to receive a falling edge becomes the master. When the master is decided, the opposite side switches to slave mode, ignoring subsequent edges until the master releases. After a time delay tD(EDGE), an n transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. When the master side asserts a logic 1, a p transistor on the slave side is activated during the time delay tPU and then both sides return to their inactive (pulled up) states. This active pullup provides fast low-to-high transitions. After the duration of tPU, the output voltage depends only on the internal pullup resistor and the load current. Current to and from the card I/O lines is limited internally to 15mA. The maximum frequency on these lines is 1MHz. Inactive Mode The DS8024 powers up with the card interface in the inactive mode. Minimal circuitry is active while waiting for the host to initiate a smart card session. • All card contacts are inactive (approximately 200Ω to GND). • Pins I/OIN, AUX1IN, and AUX2IN are in the highimpedance state (11kΩ pullup resistor to VDD). • Voltage generators are stopped. • XTAL oscillator is running (if included in the device). • Voltage supervisor is active. • The internal oscillator is running at its low frequency. Activation Sequence After power-on and the reset delay, the host microcontroller can monitor card presence with signals OFF and CMDVCC, as shown in Table 2. Table 2. Card Presence Indication OFF CMDVCC High High Card present. Low High Card not present. STATUS Maxim Integrated DS8024 Smart Card Interface When a card is inserted into the reader (if PRES is active), the host microcontroller can begin an activation sequence (start a card session) by pulling CMDVCC low. The following events form an activation sequence (Figure 3): 1) Host: CMDVCC is pulled low. 2) DS8024: The internal oscillator changes to high frequency (t0). 3) DS8024: The voltage generator is started simultaneously (t0 = t1). 4) DS8024: VCC rises from 0 to 5V or 3V with a controlled slope (t2 = t1 + 1.5 × T). T is 64 times the internal oscillator period (approximately 25µs). 5) DS8024: I/O, AUX1, and AUX2 are enabled (t3 = t1 + 4T). 6) DS8024: The CLK signal is applied to the C3 contact (t4). 7) DS8024: RST is enabled simultaneously (t5 = t4 = t1 + 7T). An alternate sequence allows the application to control when the clock is applied to the card. 1) Host: Set RSTIN high. 2) Host: Set CMDVCC low. 3) Host: Set RSTIN low between t3 and t5; CLK will now start. 4) DS8024: RST stays low until t5, then RST becomes the copy of RSTIN. 5) DS8024: RSTIN has no further effect on CLK after t5. If the applied clock is not needed, set CMDVCC low with RSTIN low. In this case, CLK starts at t3 (minimum 200ns after the transition on I/O, see Figure 4); after t5, RSTIN can be set high to obtain an answer to request (ATR) from an inserted smart card. Do not perform activation with RSTIN held permanently high. Active Mode When the activation sequence is completed, the DS8024 card interface is in active mode. The host microcontroller and the smart card exchange data on the I/O lines. CMDVCC VCC ATR I/O CLK RSTIN RST I/OIN t0 t1 t2 t3 t4 t5 = tACT Figure 3. Activation Sequence Using RSTIN and CMDVCC Maxim Integrated 9 DS8024 Smart Card Interface CMDVCC VCC ATR I/O CLK 200ns RSTIN RST I/OIN t0 t1 t2 t3 t4 t5 = tACT Figure 4. Activation Sequence at t3 CMDVCC RST CLK I/O VCC t10 t12 t13 t14 t15 tDE Figure 5. Deactivation Sequence 10 Maxim Integrated DS8024 Smart Card Interface Deactivation Sequence When the host microcontroller is done communicating with the smart card, it sets the CMDVCC line high to execute an automatic deactivation sequence and returns the card interface to the inactive mode. The following sequence of events occurs during a deactivation sequence (Figure 5): 1) RST goes low (t10). 2) CLK is held low (t12 = t10 + 0.5 × T), where T is 64 times the period of the internal oscillator (approximately 25µs). 3) I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T). 4) VCC starts to fall (t14 = t10 + 3T). 5) When VCC reaches its inactive state, the deactivation sequence is complete (at tDE). 6) All card contacts become low impedance to GND; I/OIN, AUX1IN, and AUX2IN remain at VDD (pulled up through an internal 11kΩ resistor). 7) The internal oscillator returns to its lower frequency. VCC Generator The card voltage (VCC) generator can supply up to 80mA continuously at 5V or 65mA at 3V. An internal overload detector triggers at approximately 120mA. Current samples to the detector are filtered. This allows spurious current pulses (with a duration of a few µs) up to 200mA to be drawn without causing deactivation. The average current must stay below the specified maximum current value. See the Applications Information section for recommendations to help maintain VCC voltage accuracy. There are two different cases for how the DS8024 reacts to fault detection (Figure 6): • Outside a Card Session (CMDVCC High). Output OFF is low if a card is not in the card reader and high if a card is in the reader. The VDD supply is monitored—a decrease in input voltage generates an internal power-on reset pulse but does not affect the OFF signal. Short-circuit and temperature detection are disabled because the card is not powered up. • Within a Card Session (CMDVCC Low). Output OFF goes low when a fault condition is detected, and an emergency deactivation is performed automatically (Figure 7). When the system controller resets CMDVCC to high, it may sense the OFF level again after completing the deactivation sequence. This distinguishes between a card extraction and a hardware problem (OFF goes high again if a card is present). Depending on the connector’s card-present switch (normally closed or normally open) and the mechanical characteristics of the switch, bouncing can occur on the PRES signals at card insertion or withdrawal. The DS8024 has a debounce feature with an 8ms typical duration (Figure 6). When a card is inserted, output OFF goes high after the debounce time delay. When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on PRES and output OFF goes low. Stop Mode (Low-Power Mode) The DS8024 (like the TDA8024) does not support a lowpower stop mode. For applications requiring low-power support, refer to the DS8113. Fault Detection The DS8024 integrates circuitry to monitor the following fault conditions: • Short-circuit or high current on VCC • Card removal while the interface is activated • VDD dropping below threshold • Card voltage generator operating out of the specified values (VDDA too low or current consumption too high) • Overheating Maxim Integrated Smart Card Power Select The DS8024 supports two smart card VCC voltages: 3V and 5V. The power select is controlled by the 5V/3V signal as shown in Table 3. VCC is 5V if 5V/3V is asserted to a logic-high state, and VCC is 3V if 5V/3V is pulled to a logic-low state. Table 3. VCC Select and Operation Mode 5V/3V CMDVCC VCC SELECT (V) CARD INTERFACE STATUS 0 0 3 Activated 0 1 3 Inactivated 1 0 5 Activated 1 1 5 Inactivated 11 DS8024 Smart Card Interface PRES OFF CMDVCC DEBOUNCE DEBOUNCE VCC DEACTIVATION CAUSED BY CARDS WITHDRAWAL DEACTIVATION CAUSED BY SHORT CIRCUIT Figure 6. Behavior of PRES, OFF, CMDVCC, and VCC OFF PRES RST CLK I/O VCC t10 t12 t13 t14 t15 tDE Figure 7. Emergency Deactivation Sequence (Card Extraction) 12 Maxim Integrated DS8024 Smart Card Interface VDD 100nF 33pF 33pF +3.3V 100nF 100nF +3.3V 100nF XTAL1 GPIO ... XTAL2 GND VDD CP1 CP2 VUP +10μF PGND VDDA CLKDIV1 CLKDIV2 5V/3V PRES VCC ... ... ... GPIO ISOIO0 100kΩ** OFF RSTIN CMDVCC AUX2IN AUX1IN I/OIN RST CLK I/O AUX1 AUX2 DS8024 100nF* 220nF* 100nF* 220nF* CGND MAXQ1103 GPIO ... ... ... GPIO ISOIO1 CLKDIV1 CLKDIV2 5V/3V VCC DS8024 OFF RSTIN CMDVCC AUX2IN AUX1IN I/OIN XTAL1 RST CLK I/O AUX1 AUX2 CGND PRES XTAL2 GND VDD CP1 CP2 VUP PGND 100nF VDDA 100kΩ** +10μF +3.3V 33pF 33pF 100nF +3.3V 100nF 100nF VDD *PLACE A 100nF CAPACITOR CLOSE TO DS8024 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT. **SCHEMATIC ASSUMES A NORMALLY CLOSED CONNECTION TO GROUND IN THE SOCKET. INSERTING A CARD BREAKS THE CONNECTION AND PULLS PRES HIGH. Figure 8. Typical Application Diagram Maxim Integrated 13 DS8024 Smart Card Interface Applications Information Technical Support Performance can be affected by the layout of the application. For example, an additional cross-capacitance of 1pF between card reader contacts C2 (RST) and C3 (CLK) or C2 (RST) and C7 (I/O) can cause contact C2 to be polluted with high-frequency noise from C3 (or C7). In this case, include a 100pF capacitor between contacts C2 and CGND. For technical support, go to https://support.maximintegrated.com/micro. Application recommendations include the following: • Ensure there is ample ground area around the DS8024 and the connector; place the DS8024 very near to the connector; decouple the VDD and VDDA lines separately. These lines are best positioned under the connector. • The DS8024 and the host microcontroller must use the same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V, CMDVCC, and OFF are referenced to VDD; if pin XTAL1 is to be driven by an external clock, also reference this pin to VDD. • Trace C3 (CLK) should be placed as far as possible from the other traces. • The trace connecting CGND to C5 (GND) should be straight (the two capacitors on C1 (VCC) should be connected to this ground trace). • Avoid ground loops among CGND, PGND, and GND. • Decouple VDDA and VDD separately; if the two supplies are the same in the application, they should be connected in a star on the main trace. • Connect a 100nF capacitor (ESR < 100mΩ) between V CC and CGND and place near the DS8024’s VCC pin. • Connect a 100nF or 220nF capacitor (220nF preferred, ESR < 100mΩ) between VCC and CGND and place near the smart card socket’s C1 contact. With all these layout precautions, noise should be kept to an acceptable level and jitter on C3 (CLK) should be less than 100ps. 14 Selector Guide PART CURRENT VOLTAGES SUPPORTED (V) SUPPORTS PINSTOP PACKAGE MODE? DS8024-RJX+ 3.0, 5.0 No 28 TSSOP DS8024-RJX/V+ 3.0, 5.0 No 28 TSSOP DS8024-RRX+ 3.0, 5.0 No 28 SO Note: Contact the factory for availability of other variants and package options. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 SO (300 mils) W28+6 21-0042 90-0109 28 TSSOP U28+1 21-0066 90-0171 Maxim Integrated DS8024 Smart Card Interface Revision History REVISION NUMBER REVISION DATE 0 6/08 Initial release — 1 8/08 Clarified the VDDA specification in the Recommended DC Operating Conditions table 2 2 2/12 Added the automotive TSSOP version to the Ordering Information and Selector Guide; updated the Absolute Maximum Ratings 1, 2, 14 3 7/12 Added footnote to the resistor value on the PRES pin in Figure 8 4 4/13 Clarified t1, t5, and t14 DESCRIPTION PAGES CHANGED 13 9, 11 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 15 © 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.