MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
General Description
The MAX11100 low-power, 16-bit analog-to-digital converter (ADC) features a successive-approximation ADC,
automatic power-down, fast 1.1Fs wake-up, and a highspeed SPI/QSPI™/MICROWIRE®-compatible interface.
The MAX11100 operates with a single +5V analog supply
and features a separate digital supply, allowing direct
interfacing with 2.7V to 5.25V digital logic.
At the maximum sampling rate of 200ksps, the MAX11100
typically consumes 2.45mA. Power consumption is typically 12.25mW (VAVDD = VDVDD = +5V) at a 200ksps
(max) sampling rate. AutoShutdown™ reduces supply
current to 140FA at 10ksps and to less than 10FA at
reduced sampling rates.
Features
S 16-Bit Resolution, No Missing Codes
S +5V Single-Supply Operation
S Adjustable Logic Level (2.7V to 5.25V)
S Input Voltage Range: 0 to VREF
S Internal Track-and-Hold, 4MHz Input Bandwidth
S SPI/QSPI/MICROWIRE-Compatible Serial Interface
S Small 10-Pin µMAX and WLP Packages
S Low Power
2.45mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
Excellent dynamic performance and low power, combined with ease of use and small package size (10-pin
FMAX® and 12-bump WLP), make the MAX11100 ideal
for battery-powered and data-acquisition applications
or for other circuits with demanding power consumption
and space requirements.
Functional Diagram
AVDD
Applications
Motor Control
REF
Industrial Process Control
AIN
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
DVDD
AGND
SCLK
Portable- and Battery-Powered Equipment
Ordering Information appears at end of data sheet.
TRACK-ANDHOLD
16-BIT SAR
ADC
OUTPUT
BUFFER
DOUT
CONTROL
CS
MAX11100
DGND
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
AutoShutdown is a trademark and µMAX is a registered trademark of Maxim Integrated Products, Inc.
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX11100.related
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6046; Rev 1; 1/12
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND........................................................-0.3V to +6V
DVDD to DGND........................................................-0.3V to +6V
DGND to AGND....................................................-0.3V to +0.3V
AIN, REF to AGND................................ -0.3V to (VAVDD + 0.3V)
SCLK, CS to DGND..................................................-0.3V to +6V
DOUT to DGND..................................... -0.3V to (VDVDD + 0.3V)
Maximum Current Into Any Pin........................................ Q50mA
Continuous Power Dissipation (TA = +70NC)
FMAX (derate 5.6mW/NC above +70NC)......................444mW
WLP (derate 16.1mW/NC above +70NC)......1300mW (Note 1)
Operating Temperature Range........................... -40NC to +85NC
Maximum Junction Temperature......................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (FMAX only; soldering, 10s)..............+300NC
Soldering Temperature (reflow).......................................+260NC
Note 1: All WLP devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by
design and characterization.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, CREF = 4.7FF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
16
Relative Accuracy
INL
Differential Nonlinearity
DNL
Transition Noise
(Note 3)
-2
+2
-1
+2
LSB
Q0.65
0.1
1
mV
(Note 4)
Q0.002
Q0.01
%FSR
Offset Drift
Gain Drift
LSB
RMS noise
Offset Error
Gain Error
Bits
(Note 4)
LSBRMS
0.4
ppm/°C
0.2
ppm/°C
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 2)
Signal-to-Noise Plus Distortion
SINAD
86
91.5
dB
Signal-to-Noise Ratio
SNR
87
91.7
dB
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
-106
92
-90
dB
108
dB
Full-Power Bandwidth
-3dB point
4
MHz
Full-Linear Bandwidth
SINAD > 86dB
10
kHz
CONVERSION RATE
Conversion Time
tCONV
Serial Clock Frequency
fSCLK
Aperture Delay
tAD
Aperture Jitter
tAJ
Sample Rate
fS
Track/Hold Acquisition Time
Maxim Integrated
tACQ
(Note 5)
5
0.1
240
Fs
4.8
MHz
15
ns
< 50
fSCLK/24
ps
200
1.1
ksps
Fs
2
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, CREF = 4.7FF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VREF
V
ANALOG INPUT (AIN)
Input Range
VAIN
Input Capacitance
CAIN
Input Leakage Current
0
40
SCLK idle
0.01
pF
10
FA
VAVDD
V
EXTERNAL REFERENCE
Input-Voltage Range
VREF
Input Current
IREF
3.8
VREF = 4.096V, fSCLK = 4.8MHz
60
150
VREF = 4.096V, SCLK idle
0.01
10
CS = DVDD, SCLK idle
0.01
FA
DIGITAL INPUTS (SCLK, CS)
Input High Voltage
VIH
VDVDD = 2.7V to 5.25V
Input Low Voltage
VIL
VDVDD = 2.7V to 5.25V
Input Leakage Current
IIN
VIN = 0 to VDVDD
Input Hysteresis
Input Capacitance
0.7 x
VDVDD
V
Q0.1
0.3 x
VDVDD
V
Q1
FA
VHYST
0.2
V
CIN
15
pF
DIGITAL OUTPUT (DOUT)
Output High Voltage
VOH
ISOURCE = 0.5mA, VDVDD = 2.7V to 5.25V
Output Low Voltage
VOL
ISINK = 2mA, VDVDD = 2.7V to 5.25V
Three-State Output Leakage
Current
Three-State Output Capacitance
VDVDD
- 0.25
V
IL
CS = DVDD
Q0.1
COUT
CS = DVDD
15
0.4
V
Q10
FA
pF
POWER SUPPLIES
Analog Supply
VAVDD
4.75
5.25
V
Digital Supply
VDVDD
2.7
5.25
V
Analog Supply Current
IAVDD
CS = DGND, 200ksps
1.85
2.5
mA
Digital Supply Current
IDVDD
CS = DGND, DOUT = all zeros, 200ksps
0.6
1.0
mA
CS = DVDD, SCLK = idle
0.1
10
FA
VAVDD = VDVDD = 4.75V to 5.25V, fullscale input (Note 6)
68
Shutdown Supply Current
Power-Supply Rejection Ratio
Maxim Integrated
IAVDD +
IDVDD
PSRR
dB
3
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
TIMING CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1.1
UNITS
Acquisition Time
tACQ
SCLK to DOUT Valid
tDO
CDOUT = 50pF
50
ns
CS Fall to DOUT Enable
tDV
CDOUT = 50pF
80
ns
CS Rise to DOUT Disable
tTR
CDOUT = 50pF
80
ns
Fs
CS Pulse Width
tCSW
50
ns
CS Fall to SCLK Rise Setup
tCSS
100
ns
CS Rise to SCLK Rise Hold
tCSH
SCLK High Pulse Width
tCH
65
ns
SCLK Low Pulse Width
tCL
65
ns
SCLK Period
tCP
208
ns
0
ns
TIMING CHARACTERISTICS
(VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Acquisition Time
tACQ
SCLK to DOUT Valid
tDO
CDOUT = 50pF
100
ns
CS Fall to DOUT Enable
tDV
CDOUT = 50pF
100
ns
tTR
CDOUT = 50pF
80
ns
CS Rise to DOUT Disable
1.1
UNITS
tCSW
50
CS Fall to SCLK Rise Setup
tCSS
100
CS Rise to SCLK Rise Hold
tCSH
SCLK High Pulse Width
tCH
CS Pulse Width
Fs
ns
ns
0
ns
65
ns
SCLK Low Pulse Width
tCL
65
ns
SCLK Period
tCP
208
ns
Note 2: VAVDD = VDVDD = +5V.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.
Maxim Integrated
4
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics
(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7FF, VREF = 4.096V, TA = +25NC, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY (DNL)
vs. CODE
0.8
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
32768
16384
8192
24576
49152
40960
65536
0
57344
24576
49152
40960
MIN DNL
-0.5
5.05
5.15
100
MAX11100 toc05
-20
90
80
-40
5.25
70
-60
-80
60
50
40
30
35
60
85
-140
10
0
0
10 20 30 40 50 60 70 80 90 100
1
10
100
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
SFDR vs. FREQUENCY
MAX11100 toc08
0
-10
MAX11100 toc07
120
110
100
90
80
70
60
50
40
30
20
10
0
0
FREQUENCY (kHz)
TEMPERATURE (°C)
-20
-30
THD (dB)
SFDR (dB)
4.95
SINAD vs. FREQUENCY
-120
-1.5
-40
-50
-60
-70
-80
-90
-100
-110
-120
0.1
Maxim Integrated
4.85
20
MIN INL
10
4.75
VAVDD (V)
-100
-15
MIN INL
57344
SINAD (dB)
0.5
-40
-0.5
MAX11100 FFT
MAX11100 toc04
MAX INL
-1.0
MIN DNL
-1.5
65536
0
MAGNITUDE (dB)
INL AND DNL (LSB)
32768
16384
8192
INL AND DNL vs. TEMPERATURE
0
MAX DNL
OUTPUT CODE (DECIMAL)
1.5
MAX DNL
0
-1.0
OUTPUT CODE (DECIMAL)
1.0
0.5
MAX11100 toc06
0
MAX INL
1.0
INL AND DNL (LSB)
0.6
1.5
MAX11100 toc02
0.8
INL (LSB)
1.0
MAX11100 toc01
1.0
INL AND DNL
vs. ANALOG SUPPLY VOLTAGE
MAX11100 toc03
INTEGRAL NONLINEARITY (INL)
vs. CODE
1
10
FREQUENCY (kHz)
100
0
1
10
100
FREQUENCY (kHz)
5
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7FF, VREF = 4.096V, TA = +25NC, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SAMPLE RATE
IAVDD
0.1000
IDVDD
0.0100
MAX11100 toc10
1.88
IAVDD (mA)
SUPPLY CURRENT (mA)
1.0000
1.90
MAX11100 toc09
10.0000
1.86
1.84
1.82
0.0010
1.80
0.0001
10
1
100
4.75
1000
4.85
5.15
5.25
2.0
MAX11100 toc12
20
MAX11100 toc11
2.5
18
16
14
1.5
IAVDD
ISHDN (nA)
SUPPLY CURRENT (mA)
5.05
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
1.0
12
10
8
6
4
0.5
2
IDVDD
0
0
-40
-15
10
35
60
4.75
85
4.85
TEMPERATURE (°C)
5.25
100
75
50
MAX11100 toc14
300
OFFSET ERROR (µV)
125
100
-100
-300
25
-500
0
-40
-15
10
35
TEMPERATURE (°C)
Maxim Integrated
500
MAX11100 toc13
150
4.95
5.05
5.15
SUPPLY VOLTAGE (V)
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT (nA)
4.95
VAVDD (V)
SAMPLE RATE (ksps)
60
85
4.75
4.85
4.95
5.05
5.15
5.25
VAVDD (V)
6
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7FF, VREF = 4.096V, TA = +25NC, unless otherwise noted.)
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
100
-100
MAX11100 toc16
0.006
GAIN ERROR (%FS)
300
0.002
-0.002
-0.006
-300
-0.010
-500
-40
-15
10
35
60
4.75
85
4.85
4.95
93.0
MAX11100 toc17
fIN = 1kHz
92.5
SNR AND SINAD (dB)
0.006
GAIN ERROR (%FS)
5.15
5.25
SIGNAL-TO-NOISE RATIO (SNR) AND
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD) vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0.010
0.002
-0.002
SNR
92.0
91.5
SINAD
91.0
-0.006
90.5
-0.010
-40
-15
10
35
TEMPERATURE (°C)
Maxim Integrated
5.05
VAVDD (V)
TEMPERATURE (°C)
MAX11100 toc18
OFFSET ERROR (µV)
0.010
MAX11100 toc15
500
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
7
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
MAX11100
1
+ REF
2
3
4
AVDD
AGND
SCLK
A
AGND
REF
DGND
CS
B
AIN
AGND
DVDD
C
DOUT
TOP VIEW
DOUT
1
DGND
2
DVDD
3
AGND
AIN
+
10
SCLK
9
CS
8
AGND
4
7
AVDD
5
6
REF
MAX11100
µMAX
WLP
Pin Description
PIN
NAME
FUNCTION
6
REF
External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7FF
capacitor.
WLP
µMAX
A1, B2
A2
7
AVDD
Analog +5V Supply Voltage. Bypass to AGND with a 0.1FF capacitor.
A3, B1,
C2
4, 8
AGND
Analog Ground
A4
10
SCLK
Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
B3
2
DGND
Digital Ground
B4
9
CS
Active-Low Chip-Select Input. Forcing CS high places the MAX11100 shutdown with a typical
current of 0.1FA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
C1
5
AIN
Analog Input
C3
3
DVDD
Digital Supply Voltage. Bypass to DGND with a 0.1FF capacitor.
C4
1
DOUT
Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when
CS is high.
Maxim Integrated
8
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Detailed Description
VDD
The MAX11100 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 16-bit output.
Figure 4 shows the MAX11100 in its simplest configuration. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (FPs).
1mA
DOUT
DOUT
1mA
CLOAD = 50pF
CLOAD = 50pF
DGND
DGND
a) VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
VDD
1mA
DOUT
Analog Input
DOUT
1mA
CLOAD = 50pF
CLOAD = 50pF
DGND
Figure 5 illustrates the input sampling architecture of the
ADC. The voltage applied at REF sets the full-scale input
voltage.
Track-and-Hold (T/H)
DGND
a) VOH TO HIGH-Z
The MAX11100 has two power modes: normal and shutdown. Driving CS high places the MAX11100 in shutdown, reducing the supply current to 0.1FA (typ), while
pulling CS low places the MAX11100 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface timing diagram.
In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
b) VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
CS
tCSW
tCSS
tCL
tCH
tCSH
SCLK
tCP
tDV
tDO
tTR
DOUT
Figure 3. Detailed Serial Interface Timing
Maxim Integrated
9
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
tACQ = 13(RS + RIN) x 35pF
AIN
VREF
AIN
CS
REF
SCLK
DOUT
4.7µF
CS
SCLK
DOUT
MAX11100
AVDD
+5V
To improve the input signal bandwidth under AC conditions, drive AIN with a wideband buffer (> 4MHz) that
can drive the ADC’s input capacitance and settle quickly.
0.1µF
+5V
DVDD
AGND
DGND
0.1µF
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of
interest, use anti-alias filtering.
GND
Figure 4. Typical Operating Circuit
AIN
CSWITCH
3pF
TRACK
REF
CAPACITIVE DAC
CDAC 32pF
HOLD
GND
HOLD
where RIN = 800I, RS = the input signal’s source
impedance, and tACQ is never less than 1.1Fs. A source
impedance less than 1kI does not significantly affect the
ADC’s performance.
Analog Input Protection
ZERO
Internal protection diodes, which clamp the analog input
to AVDD or AGND, allow the input to swing from VAGND
- 0.3V to VAVDD + 0.3V, without damaging the device.
RIN
800Ω
If the analog input exceeds 300mV beyond the supplies,
limit the input current to 10mA.
TRACK
AUTOZERO
RAIL
Figure 5. Equivalent Input Circuit
Digital Interface
Initialization After Power-Up and Starting a
Conversion
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDAC represents a sample of the input.
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic-high on CS places
the MAX11100 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic-low on CS
places the MAX11100 in the fully powered mode.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
16-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDAC to the input
signal again.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance
is charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time must
be allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acquisition time:
Maxim Integrated
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs (Figure 6
and Figure 7). Ensure that the duty cycle on SCLK is
between 40% and 60% at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that
the minimum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset.
10
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
CS
SCLK
tCSS
1
4
tCH
DOUT
tDV
tCL
tACQ
6
8
16
12
D15 D14
D13 D12
D11 D10
D9
D8
24
20
D7
D6
D5
D4
D3
tDO
D2
D1
D0
tCSH
tTR
Figure 6. External Timing Diagram
COMPLETE CONVERSION SEQUENCE
CS
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED DOWN
POWERED UP
TIMING NOT TO SCALE.
Figure 7. Shutdown Sequence
Variations in frequency, duty cycle, or other aspects of
the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence. The
analog input is stored in the capacitive DAC, DOUT
changes from high impedance to logic-low, and the ADC
begins to convert after the sixth clock cycle. SCLK drives
the conversion process and shifts out the conversion
result on DOUT.
SCLK begins shifting out the data (MSB first) after the falling edge of the 8th SCLK pulse. Twenty-four falling clock
edges are needed to shift out the eight leading zeros
and 16 data bits. Extra clock pulses occurring after the
Maxim Integrated
conversion result has been clocked out, and prior to the
rising edge of CS, produce trailing zeros at DOUT and
have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX11100 in
shutdown. For maximum throughput, force CS low again
to initiate the next conversion immediately after the specified minimum time (tCSW).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX11100 in shutdown.
11
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Output Coding and Transfer Function
The data output from the MAX11100 is binary and Figure 8
depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(VREF = 4.096V and 1 LSB = 63FV or 4.096V/65536).
Applications Information
External Reference
The MAX11100 requires an external reference with a
+3.8V and AVDD voltage range. Connect the external
reference directly to REF. Bypass REF to AGND with
a 4.7FF capacitor. When not using a low-ESR bypass
capacitor, use a 0.1FF ceramic capacitor in parallel with
the 4.7FF capacitor. Noise on the reference degrades
conversion accuracy.
The input impedance at REF is 40kI for DC currents.
During a conversion the external reference at REF must
deliver 100FA of DC load current and have an output
impedance of 10I or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX11100’s equivalent input noise (38FVRMS) when
choosing a reference.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 101
FS = VREF
V
1 LSB = REF
65536
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
Maxim Integrated
At the beginning of the acquisition, the internal sampling capacitor array connects to AIN (the amplifier
output), causing some output disturbance. Ensure that
the sampled voltage has settled before the end of the
acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result.
Noise signals synchronous with the sampling interval
result in an effective input offset. Asynchronous signals
produce random noise on the input, whose high-frequency components can be aliased into the frequency band
of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal)
at the inputs. This requires bypassing AIN to AGND, or
buffering the input with an amplifier that has a smallsignal bandwidth of several MHz, or preferably both. AIN
has 4MHz (typ) of bandwidth.
Distortion
11 . . . 110
00 . . . 011
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multiplexed,
switch the input channel immediately after acquisition,
rather than near the end of or after a conversion (Figure 9).
This allows the maximum time for the input buffer amplifier to respond to a large step change in the input signal.
The input amplifier must have a slew rate of at least 2V/Fs
to complete the required output-voltage change before
the beginning of the acquisition time.
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX11100’s
total harmonic distortion (THD = -102dB at 1kHz) at
frequencies of interest. If the chosen amplifier has
insufficient common-mode rejection, which results in
degraded THD performance, use the inverting configuration (positive input grounded) to eliminate errors from
this source. Low temperature-coefficient, gain-setting
resistors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
due to finite amplifier gain, use amplifier circuits with sufficient loop gain at the frequencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX11100’s offset (1mV (max) for
+5V supply), or whose offset can be trimmed while maintaining stability over the required temperature range.
12
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
IN1
IN2
A0
A1
4-TO-1
MUX
MAX11100
IN3
AIN
OUT
IN4
CS
CLK
ACQUISITION
CONVERSION
CS
A0
A1
CHANGE MUX INPUT HERE
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
Serial Interfaces
edge and the output is available in MSB-first format.
Observe the SCLK to DOUT valid timing characteristic. Clock data into the FP on SCLK’s rising edge.
If a serial interface is available, establish the CPU’s
serial interface as master, so that the CPU generates the
serial clock for the MAX11100. Select a clock frequency
between 100kHz and 4.8MHz:
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
The MAX11100’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
1) Use a general-purpose I/O line on the CPU to pull CS low.
2) Activate SCLK for a minimum of 24 clock cycles. The
serial data stream of eight leading zeros followed by
the MSB of the conversion result begins at the falling edge of CS. DOUT transitions on SCLK’s falling
Maxim Integrated
4) With CS high, wait at least 50ns (tCSW) before starting a new conversion by pulling CS low. A conversion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
13
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Data can be output in three 8-bit sequences or continuously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the LSB (D0) and CS
has been kept low, DOUT sends trailing zeros.
CS
I/O
SCK
SCLK
MISO
DOUT
VDD
SPI
SPI and MICROWIRE Interfaces
MAX11100
When using the SPI (Figure 10a) or MICROWIRE (Figure 10b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS (Figure 10c). Three consecutive 8-bit readings are necessary to obtain the entire
16-bit result from the ADC. DOUT data transitions on
the serial clock’s falling edge. The first 8-bit data stream
contains all leading zeros. The second 8-bit data stream
contains the MSB through D8. The third 8-bit data stream
contains D7 through D0.
SS
Figure 10a. SPI Connections
MICROWIRE
I/O
CS
SK
SCLK
SI
DOUT
MAX11100
Figure 10b. MICROWIRE Connections
1ST BYTE READ
1
SCLK
2ND BYTE READ
4
6
12
8
16
CS
0
DOUT*
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
TIMING NOT TO SCALE.
D7
D6
D5
D4
24
D3
D2
D1
D0
HIGH-Z
LSB
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
Maxim Integrated
14
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
CS
CS
SCK
SCLK
MISO
DOUT
VDD
QSPI
MAX11100
SS
Figure 11a. QSPI Connections
1
SCLK
CS
4
6
8
END OF
ACQUISITION
DOUT*
D15 D14
D13 D12
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
16
12
D11
D10
D9
D8
24
20
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
LSB
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
VDD
VDD
SCLK
SCK
DOUT
SDI
CS
I/O
PIC16/17
MAX11100
GND
Figure 12a. SPI Interface Connection for a PIC16/PIC17
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX11100 supports a maximum fSCLK
of 4.8MHz. Figure 11a shows the MAX11100 connected
to a QSPI master and Figure 11b shows the associated
interface timing.
Maxim Integrated
PIC16 with SSP Module and PIC17 Interface
The MAX11100 is compatible with a PIC16/PIC17 microcontroller (FC) using the synchronous serial-port (SSP)
module.
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Table 1 and Table 2.
In SPI mode, the PIC16/PIC17 FC allows 8 bits of data
to be synchronously transmitted and received simultaneously. Three consecutive 8-bit readings (Figure 12b) are
necessary to obtain the entire 16-bit result from the ADC.
DOUT data transitions on the serial clock’s falling edge
and is clocked into the FC on SCLK’s rising edge. The
first 8-bit data stream contains all zeros. The second 8-bit
data stream contains the MSB through D8. The third 8-bit
data stream contains bits D7 through D0.
15
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
1ST BYTE READ
2ND BYTE READ
12
SCLK
16
CS
0
DOUT*
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
D7
TIMING NOT TO SCALE.
D6
D5
D4
24
D3
D2
D1
D0
HIGH-Z
LSB
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
Table 1. Detailed SSPCON Register Contents
CONTROL BIT
MAX11100
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT 7
X
Write Collision Detection Bit
SSPOV
BIT 6
X
Receive Overflow Detect Bit
SSPEN
BIT 5
1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
CKP
BIT 4
0
SSPM3
BIT 3
0
SSPM2
BIT 2
0
SSPM1
BIT 1
0
SSPM0
BIT 0
1
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC/16.
Table 2. Detailed SSPSTAT Register Contents
CONTROL BIT
SMP
BIT 7
CKE
D/A
MAX11100
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
BIT 6
1
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock.
BIT 5
X
Data Address Bit
P
BIT 4
X
STOP Bit
S
BIT 3
X
START Bit
R/W
BIT 2
X
Read/Write Bit Information
UA
BIT 1
X
Update Address
BF
BIT 0
X
Buffer Full Status Bit
Maxim Integrated
16
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-fit straight line fit or a
line drawn between the endpoints of the transfer function,
once offset and gain errors have been nulled. The static
linearity parameters for the MAX11100 are measured
using the endpoint method.
Effective Number of Bits
Effective number of bits (ENOB) indicate the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the full-scale
range of the ADC, calculate the effective number of bits
as follows:
ENOB = (SINAD - 1.76)/6.02
Figure 13 shows the effective number of bits as a function
of the MAX11100’s input frequency.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB guarantees no missing codes
and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock and
the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization noise
error only and results directly from the ADCs resolution
(N bits):
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
V 2 + V3 2 + V4 2 + V5 2
THD
= 20 × log 2
V1
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
16
SNR = (6.02 x N + 1.76)dB
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of
the fundamental input frequency’s RMS amplitude to
the RMS equivalent of all the other ADC output signals,
excluding the DC offset.
SignalRMS
SINAD(dB)
= 20 × log
Noise + Distortion) RMS
(
Maxim Integrated
14
EFFECTIVE NUMBER OF BITS
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first five harmonics, and the
DC offset.
12
10
8
6
4
2
0
0.1
1
10
100
INPUT FREQUENCY (kHz)
Figure 13. Effective Number of Bits vs. Input Frequency
17
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Supplies, Layout, Grounding, and Bypassing
Use PCBs with separate analog and digital ground
planes. Do not use wire-wrap boards. Connect the two
ground planes together at the MAX11100. Isolate the
digital supply from the analog with a low-value resistor
(10I) or ferrite bead when the analog and digital supplies come from the same source (Figure 14).
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX11100EUB+
-40NC to +85NC
10 FMAX
MAX11100EWC+
-40NC to +85NC
12 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Constraints on sequencing the power supplies and
inputs are as follows:
U Apply AGND before DGND.
U Apply AIN and REF after AVDD and AGND are present.
Chip Information
PROCESS: BiCMOS
Package Information
U DVDD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are
low impedance. A 5mA current flowing through a PCB
ground trace impedance of only 0.05I creates an error
voltage of about 250FV, 4 LSB error with a +4V full-scale
system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and digital (especially the SCLK and DOUT) lines parallel to one
another. If one must cross another, do so at right angles.
The ADCs high-speed comparator is sensitive to highfrequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane with
a 0.1FF capacitor in parallel with a 1FF to 10FF low-ESR
capacitor. Keep capacitor leads short for best supplynoise rejection.
AIN
VREF
AIN
CS
REF
SCLK
DOUT
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 FMAX
U10+2
21-0061
90-0330
12 WLP
W121A2+1
21-0009
Refer to
Application
Note 1891
CS
SCLK
DOUT
MAX11100
4.7µF
AVDD
+5V
10Ω
0.1µF
DVDD
0.1µF
AGND
DGND
GND
Figure 14. Powering AVDD and DVDD from a Single Supply
Maxim Integrated
18
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/11
Initial release
1
1/12
Revised the Absolute Maximum Ratings and Electrical Characteristics.
DESCRIPTION
PAGES
CHANGED
—
2–4
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products, Inc.
19
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Maxim Integrated
20
MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
Maxim Integrated
21
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