MAX11105AUT+T

EVALUATION KIT AVAILABLE MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs General Description The   MAX11102/MAX11103/MAX11105/MAX11106/ MAX11110/MAX11111/MAX11115/MAX11116/ MAX11117 are 12-/10-/8-bit, compact, high-speed, lowpower, successive approximation analog-to-digital converters (ADCs). These high-performance ADCs include a high-dynamic range sample-and-hold and a high-speed serial interface. These ADCs accept a full-scale input from 0V to the power supply or to the reference voltage. The MAX11102/MAX11103/MAX11106/MAX11111 feature dual, single-ended analog inputs connected to the ADC core using a 2:1 MUX. The devices also include a separate supply input for data interface and a dedicated input for reference voltage. In contrast, the single-channel devices generate the reference voltage internally from the power supply. Features S 2Msps/3Msps Conversion Rate, No Pipeline Delay S 12-/10-/8-Bit Resolution S 1-/2-Channel, Single-Ended Analog Inputs S Low-Noise 73dB SNR S Variable I/O: 1.5V to 3.6V (Dual-Channel Only) Allows the Serial Interface to Connect Directly to 1.5V, 1.8V, 2.5V, or 3V Digital Systems S 2.2V to 3.6V Supply Voltage S Low Power 3.7mW at 2Msps 5.2mW at 3Msps Very Low Power Consumption at 2.5µA/ksps S External Reference Input (Dual-Channel Devices Only) These ADCs operate from a 2.2V to 3.6V supply and consume only 5.2mW at 3Msps and 3.7mW at 2Msps. The devices include full power-down mode and fast wake-up for optimal power management and a highspeed 3-wire serial interface. The 3-wire serial interface directly connects to SPI, QSPIK, and MICROWIRE® devices without external logic. S 1.3µA Power-Down Current Excellent dynamic performance, low voltage, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low-power consumption and minimal space. S Wide -40NC to +125NC Operation These ADCs are available in a 10-pin TDFN package, 10-pin FMAX® package, and a 6-pin SOT23 package. These devices operate over the -40NC to +125NC temperature range. S SPI-/QSPI-/MICROWIRE-Compatible Serial Interface S 10-Pin, 3mm x 3mm TDFN Package S 10-Pin, 3mm x 5mm µMAX Package S 6-Pin, 2.8mm x 2.9mm SOT23 Package Applications Data Acquisition Portable Data Logging Medical Instrumentation Battery-Operated Systems Communication Systems Automotive Systems Ordering Information PIN-PACKAGE BITS SPEED (Msps) NO. OF CHANNELS TOP MARK MAX11102AUB+ PART 10 FMAX-EP* 12 2 2 +ABBA MAX11102AUB/V+ 10 FMAX-EP* 12 2 2 +ABBR MAX11102ATB+ 10 TDFN-EP* 12 2 2 +AWI MAX11103AUB+ 10 FMAX-EP* 12 3 2 +AAAU MAX11103ATB+ 10 TDFN-EP* 12 3 2 +AWV Ordering Information continued at end of data sheet. Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. µMAX is a registered trademark of Maxim Integrated Products, Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-5245; Rev 8; 7/13 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND.............................................................-0.3V to +4V REF, OVDD, AIN1, AIN2, AIN to GND.........-0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, CHSEL, DOUT TO GND.............-0.3V to the lower of (VOVDD + 0.3V) and +4V AGND to GND.......................................................-0.3V to +0.3V Input/Output Current (all pins)............................................50mA Continuous Power Dissipation (TA = +70NC) 6-Pin SOT23 (derate 8.7mW/NC above +70NC)............696mW 10-Pin TDFN (derate 24.4mW/NC above +70NC)........1951mW 10-Pin FMAX (derate 8.8mW/NC above +70NC)........707.3mW Operating Temperature Range........................ .-40NC to +125NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. MAX11102: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11103: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q1 LSB DC ACCURACY Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Excluding offset and reference errors Q1 LSB Q0.3 Q3 LSB Q1 Q3 LSB Q1.5 LSB Channel-to-Channel Offset Matching Q0.4 LSB Channel-to-Channel Gain Matching Q0.05 LSB DYNAMIC PERFORMANCE (MAX11103: fAIN_ = 1MHz, MAX11102: fAIN_ = 0.5MHz) Signal-to-Noise and Distortion SINAD Signal-to-Noise Ratio SNR Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD MAX11103 70 72 MAX11102 70 72.5 MAX11103 70.5 72 MAX11102 70.5 73 dB dB MAX11103 -85 -75 MAX11102 -85 -76 MAX11103 76 85 MAX11102 77 85 MAX11103: f1 = 1.0003MHz, f2 = 0.99955MHz MAX11102: f1 = 500.15kHz, f2 = 499.56kHz -84 dB dB dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 68dB 2.5 MHz Small-Signal Bandwidth 45 MHz Crosstalk -90 dB 2   Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. MAX11102: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11103: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Throughput Conversion Time Acquisition Time MAX11103 0.03 3 MAX11102 0.02 2 MAX11103 260 MAX11102 391 From CS falling edge Aperture Jitter Serial-Clock Frequency fCLK ns 52 tACQ Aperture Delay Msps ns 4 ns 15 ps MAX11103 0.48 48 MAX11102 0.32 32 0 VREF V Q1 FA MHz ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ 0.002 IILA CAIN_ Track 20 Hold 4 pF EXTERNAL REFERENCE INPUT (REF) Reference Input-Voltage Range Reference Input Leakage Current Reference Input Capacitance 1 VREF IILR Conversion stopped 0.005 CREF VDD + 0.05 V Q1 FA 5 pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200FA Output Low Voltage VOL ISINK = 200FA High-Impedance Leakage Current IOL High-Impedance Output Capacitance Maxim Integrated COUT 0.85 x VOVDD V 4 0.15 x VOVDD V Q1.0 FA pF   3 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. MAX11102: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11103: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (FullPower Mode), No Clock VDD 2.2 3.6 V VOVDD 1.5 VDD V IVDD IOVDD IVDD Power-Down Current IPD Line Rejection MAX11103, VAIN_ = VGND 3.3 MAX11102, VAIN_ = VGND MAX11103, VAIN_ = VGND 2.6 0.33 MAX11102, VAIN_ = VGND mA 0.22 MAX11103 1.98 MAX11102 1.48 Leakage only 1.3 VDD = +2.2V to +3.6V, VREF = 2.2V 0.7 mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled t2 (Note 2) 5 ns t3 (Note 2) 1 ns Figure 2, VOVDD = 2.2V - 3.6V 15 Figure 2, VOVDD = 1.5V - 2.2V 16.5 Data Access Time After SCLK Falling Edge t4 SCLK Pulse Width Low t5 Percentage of clock period (Note 2) 40 60 % SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time t6 Percentage of clock period (Note 2) 40 60 % t7 Figure 3 5 t8 Figure 4 (Note 2) ns ns 2.5 Conversion cycle (Note 2) 14 ns 1 Cycle ELECTRICAL CHARACTERISTICS (MAX11105) (VDD = 2.2V to 3.6V, fSCLK = 32MHz, 50% duty cycle, 2Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q1 LSB DC ACCURACY Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error No missing codes OE Gain Error GE Total Unadjusted Error TUE Bits Excluding offset and reference errors Q1 LSB Q0.3 Q3 LSB Q1 Q3 LSB Q1.5 LSB DYNAMIC PERFORMANCE Signal-to-Noise and Distortion Signal-to-Noise Ratio 4   SINAD fAIN = 500kHz 70 72.5 dB SNR fAIN = 500kHz 70.5 73 dB Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11105) (continued) (VDD = 2.2V to 3.6V, fSCLK = 32MHz, 50% duty cycle, 2Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS Total Harmonic Distortion THD fAIN = 500kHz Spurious-Free Dynamic Range SFDR fAIN = 500kHz MIN 77 TYP MAX -85 -76 85 UNITS dB dB f1 = 500.15 kHz, f2 = 499.56 kHz -84 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 68dB 2.5 MHz 45 MHz Intermodulation Distortion IMD Small-Signal Bandwidth CONVERSION RATE Throughput 0.02 Conversion Time Acquisition Time tACQ Aperture Delay Msps 391 ns 52 ns From CS falling edge Aperture Jitter Serial Clock Frequency 2 fCLK 0.32 0 4 ns 15 ps 32 MHz ANALOG INPUT Input Voltage Range VAIN Input Leakage Current IILA Input Capacitance CAIN 0.002 Track 20 Hold 4 VDD V Q1 FA pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VVDD 0.25 x VVDD 0.15 x VVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200FA Output Low Voltage VOL ISINK = 200FA High-Impedance Leakage Current IOL High-Impedance Output Capacitance 0.85 x VVDD COUT V 0.15 x VVDD V Q1.0 FA 4 pF POWER SUPPLY Positive Supply Voltage VDD Positive Supply Current (Full-Power Mode) IVDD Maxim Integrated 2.2 VAIN = VGND 3.6 V 2.6 mA   5 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11105) (continued) (VDD = 2.2V to 3.6V, fSCLK = 32MHz, 50% duty cycle, 2Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Positive Supply Current (FullPower Mode), No Clock SYMBOL CONDITIONS MIN IPD Line Rejection MAX 1.48 IVDD Power-Down Current TYP Leakage only 1.3 VDD = +2.2V to +3.6V 0.7 UNITS mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup t2 (Note 2) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 2) 1 ns Data Access Time After SCLK Falling Edge t4 Figure 2, VDD = +2.2V to +3.6V SCLK Pulse Width Low t5 Percentage of clock period (Note 2) SCLK Pulse Width High t6 Percentage of clock period (Note 2) Data Hold Time From SCLK Falling Edge t7 Figure 3 5 SCLK Falling Until DOUT HighImpedance t8 Figure 4 (Note 2) Power-Up Time 15 ns 40 60 % 40 60 % ns 2.5 Conversion cycle (Note 2) 14 ns 1 Cycle ELECTRICAL CHARACTERISTICS (MAX11106) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q0.4 LSB Q0.4 LSB Q1 LSB Q1 LSB DC ACCURACY Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Q0.5 0 Excluding offset and reference errors Q0.5 LSB Channel-to-Channel Offset Matching Q0.05 LSB Channel-to-Channel Gain Matching Q0.05 LSB DYNAMIC PERFORMANCE SINAD fAIN_ = 1MHz 61 61.8 dB SNR fAIN_ = 1MHz 61 61.8 dB Total Harmonic Distortion THD fAIN_ = 1MHz Spurious-Free Dynamic Range SFDR fAIN_ = 1MHz Signal-to-Noise and Distortion Signal-to-Noise Ratio 6   -83 75 -74 dB dB Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11106) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Intermodulation Distortion SYMBOL IMD CONDITIONS MIN TYP MAX UNITS f1 = 1.0003MHz, f2 = 0.99955MHz -82 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 60dB 2.5 MHz Small-Signal Bandwidth 45 MHz Crosstalk -90 dB CONVERSION RATE Throughput 0.03 Conversion Time 260 ns 52 ns Acquisition Time tACQ Aperture Delay From CS falling edge Aperture Jitter Serial-Clock Frequency fCLK 0.48 VAIN_ 0 3 Msps 4 ns 15 ps 48 MHz ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance 0.002 IILA CAIN-_ Track 20 Hold 4 VREF V Q1 FA pF EXTERNAL REFERENCE INPUT (REF) Reference Input-Voltage Range Reference Input Leakage Current Reference Input Capacitance 1 VREF IILR Conversion stopped 0.005 CREF VDD + 0.05 V Q1 FA 5 pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input-High Voltage VIH Digital Input-Low Voltage VIL Digital Input Hysteresis 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output-High Voltage VOH ISOURCE = 200µA Output-Low Voltage VOL ISINK = 200µA High-Impedance Leakage Current IOL High-Impedance Output Capacitance Maxim Integrated COUT 0.85 x VOVDD V 4 0.15 x VOVDD V Q1.0 FA pF   7 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11106) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (FullPower Mode) Positive Supply Current (FullPower Mode), No Clock VDD 2.2 3.6 V VOVDD 1.5 VDD V IVDD VAIN_ = VGND 3.3 IOVDD VAIN_ = VGND 0.33 IVDD Power-Down Current IPD Line Rejection 1.98 Leakage only 1.3 VDD = +2.2V to +3.6V, VREF = 2.2V 0.17 mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup t2 (Note 2) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 2) 1 ns Data Access Time After SCLK Falling Edge (Figure 2) t4 SCLK Pulse Width Low t5 Percentage of clock period (Note 2) 40 60 % SCLK Pulse Width High t6 Percentage of clock period (Note 2) 40 60 % Data Hold Time From SCLK Falling Edge t7 Figure 3 5 SCLK Falling Until DOUT HighImpedance t8 Figure 4 (Note 2) Power-Up Time VOVDD = 2.2V - 3.6V 15 VOVDD = 1.5V - 2.2V 16.5 ns ns 2.5 Conversion cycle (Note 2) 14 ns 1 Cycle ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q1 LSB Q1 LSB DC ACCURACY Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error Gain Error Total Unadjusted Error 8   OE GE TUE Bits No missing codes MAX11117 Q0.5 Q1.65 MAX11110 Q0.3 Q1.2 Excluding offset and reference errors, MAX11117 Q0.7 Q1.4 Excluding offset and reference errors, MAX11110 Q0.15 Q1 LSB LSB Q1 LSB Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued) (VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX11117 59 61.5 MAX11110 60.5 61.5 MAX11117 59 61.5 MAX11110 60.5 61.5 MAX UNITS DYNAMIC PERFORMANCE (MAX11117: fAIN = 1MHz, MAX11110: fAIN = 0.5MHz) Signal-to-Noise and Distortion SINAD Signal-to-Noise Ratio SNR Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR dB dB MAX11117 -85 -74 MAX11110 -85 -73 MAX11117 75 MAX11110 75 dB dB MAXX11117: f1 = 1.0003MHz, f2 = 0.99955MHz MAX11110: f1 = 500.15kHz, f2 = 499.56kHz -82 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 60dB 2.5 MHz 45 MHz Intermodulation Distortion IMD Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time MAX11117 0.03 3 MAX11110 0.02 2 MAX11117 260 MAX11110 391 Aperture Delay From CS falling edge Aperture Jitter Serial Clock Frequency fCLK ns 52 tACQ Msps ns 4 ns 15 ps MAX11117 0.48 48 MAX11110 0.32 32 MHz ANALOG INPUT (AIN) Input Voltage Range VAIN Input Leakage Current IILA Input Capacitance CAIN 0 0.002 Track 20 Hold 4 VDD V Q1 FA pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input-High Voltage VIH Digital Input-Low Voltage VIL Digital Input Hysteresis IIL Digital Input Capacitance CIN V 0.25 x VDD 0.15 x VDD VHYST Digital Input Leakage Current Maxim Integrated 0.75 x VDD Inputs at GND or VDD 0.001 2 V V Q1 FA pF   9 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued) (VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (DOUT) Output-High Voltage VOH ISOURCE = 200µA Output-Low Voltage VOL ISINK = 200µA High-Impedance Leakage Current IOL High-Impedance Output Capacitance 0.85 x VDD COUT V 0.15 x VDD V Q1.0 FA 4 pF POWER SUPPLY Positive Supply Voltage 2.2 VDD Positive Supply Current (Full-Power Mode) IVDD Positive Supply Current (Full-Power Mode), No Clock IVDD Power-Down Current IPD Line Rejection 3.6 MAX11117, VAIN = VGND 3.55 MAX11110, VAIN = VGND 2.6 MAX11117 1.98 MAX11110 1.48 Leakage only 1.3 VDD = +2.2V to +3.6V 0.17 V mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup t2 (Note 2) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 2) 1 ns Data Access Time After SCLK Falling Edge t4 Figure 2, VDD = +2.2V to +3.6V SCLK Pulse Width Low t5 Percentage of clock period (Note 2) SCLK Pulse Width High t6 Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time 10   15 ns 40 60 % Percentage of clock period (Note 2) 40 60 % t7 Figure 3 5 t8 Figure 4 (Note 2) Conversion cycle (Note 2) 2.5 ns 14 ns 1 Cycle Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11111) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q0.15 LSB DC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Excluding offset and reference errors Q0.15 LSB 0.45 Q0.7 LSB 0 Q0.2 LSB 0.5 LSB Channel-to-Channel Offset Matching 0.01 LSB Channel-to-Channel Gain Matching 0.01 LSB dB DYNAMIC PERFORMANCE SINAD fAIN_ = 1MHz 49 49.8 Signal-to-Noise Ratio SNR fAIN_ = 1MHz 49 49.8 Total Harmonic Distortion THD fAIN_ = 1MHz Spurious-Free Dynamic Range SFDR fAIN_ = 1MHz Signal-to-Noise and Distortion -75 63 dB -67 67 dB dB f1 = 1.0003MHz, f2 = 0.99955MHz -65 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 49dB Intermodulation Distortion IMD 2.5 MHz Small-Signal Bandwidth 45 MHz Crosstalk -90 dB CONVERSION RATE Throughput 0.03 Conversion Time 260 Acquisition Time From CS falling edge Aperture Jitter Serial-Clock Frequency fCLK 0.48 VAIN_ 0 Msps ns 52 tACQ Aperture Delay 3 ns 4 ns 15 ps 48 MHz ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance 0.002 IILA CAIN_ Track 20 Hold 4 VREF V Q1 FA pF EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range VREF Reference Input Leakage Current IILR Reference Input Capacitance Maxim Integrated CREF 1 Conversion stopped 0.005 5 VDD + 0.05 V Q1 FA pF   11 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11111) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD 0.001 VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200µA (Note 2) Output Low Voltage VOL ISINK = 200µA (Note 2) High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage 0.85 x VOVDD V IOL 0.15 x VOVDD V Q1.0 FA 4 COUT pF VDD 2.2 3.6 V Digital I/O Supply Voltage VOVDD 1.5 VDD V Positive Supply Current (Full-Power Mode) IVDD VAIN_ = VGND 3.3 IOVDD VAIN_ = VGND 0.33 Positive Supply Current (Full-Power Mode), No Clock Power-Down Current 1.98 IVDD IPD Line Rejection Leakage only 1.3 VDD = +2.2V to +3.6V, VREF = 2.2V 0.17 mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled t2 (Note 2) 5 ns t3 (Note 2) 1 ns VOVDD = 2.2V - 3.6V 15 VOVDD = 1.5V - 2.2V 16.5 Data Access Time After SCLK Falling Edge (Figure 2) t4 SCLK Pulse Width Low t5 Percentage of clock period (Note 2) 40 60 % SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time t6 Percentage of clock period (Note 2) 40 60 % t7 Figure 3 5 t8 Figure 4 (Note 2) 12   Conversion cycle (Note 2) 2.5 ns ns 14 ns 1 Cycle Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (VDD = 2.2V to 3.6V. MAX11115: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11116: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q0.25 LSB Q0.25 LSB Q0.45 Q0.75 LSB Q0.04 Q0.5 LSB DC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE No missing codes Excluding offset and reference errors SNR Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD LSB Q0.75 DYNAMIC PERFORMANCE (MAX11116: fAIN = 1MHz MAX11115: fAIN = 500kHz) MAX11116 Signal-to-Noise and Distortion SINAD MAX11115 Signal-to-Noise Ratio Bits 49 49.5 49 49.5 MAX11116 49 49.5 MAX11115 49 49.5 dB dB MAX11116 -70 -66 MAX11115 -75 -67 MAX11116 63 66 MAX11115 63 66 MAX11116: f1 = 1.0003MHz, f2 = 0.99955MHz MAX11115: f1 = 500.15kHz, f2 = 499.56kHz dB dB -65 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 49dB 2.5 MHz 45 MHz Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time MAX11116 0.03 3 MAX11115 0.02 2 MAX11116 260 MAX11115 391 From CS falling edge ns 4 Aperture Jitter Serial-Clock Frequency ns 52 tACQ Aperture Delay ns 15 fCLK Msps ps MAX11116 0.48 48 MAX11115 0.32 32 MHz ANALOG INPUT (AIN) Input Voltage Range VAIN Input Leakage Current IILA Input Capacitance CAIN 0 0.002 Track 20 Hold 4 VDD V Q1 FA pF DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage Maxim Integrated VIH 0.75 x VDD V   13 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (continued) (VDD = 2.2V to 3.6V. MAX11115: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11116: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL Digital Input Low Voltage Digital Input Hysteresis CONDITIONS MIN TYP VIL IIL Digital Input Capacitance CIN UNITS 0.25 x VDD V 0.15 VDD VHYST Digital Input Leakage Current MAX Inputs at GND or VDD 0.001 V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200µA Output Low Voltage VOL ISINK = 200µA High-Impedance Leakage Current IOL High-Impedance Output Capacitance 0.85 x VDD COUT V 0.15 x VDD V Q1.0 FA 4 pF POWER SUPPLY Positive Supply Voltage VDD Positive Supply Current (FullPower Mode) IVDD Positive Supply Current (FullPower Mode), No Clock IVDD Power-Down Current IPD Line Rejection 2.2 3.6 MAX11116, VAIN = VGND 3.55 MAX11115, VAIN = VGND 2.6 MAX11116 1.98 MAX11115 1.48 Leakage only 1.3 VDD = +2.2V to +3.6V 0.17 V mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup t2 (Note 2) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 2) 1 ns Data Access Time After SCLK Falling Edge t4 Figure 2, VDD = +2.2V to +3.6V SCLK Pulse Width Low t5 Percentage of clock period (Note 2) SCLK Pulse Width High t6 Percentage of clock period (Note 2) Data Hold Time From SCLK Falling Edge t7 Figure 3 5 SCLK Falling Until DOUT HighImpedance t8 Figure 4 (Note 2) Power-Up Time Conversion cycle (Note 2) 15 ns 40 60 % 40 60 % 2.5 ns 14 ns 1 Cycle Note 1: All timing specifications given are with a 10pF capacitor. Note 2: Guaranteed by design in characterization; not production tested. 14   Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs SAMPLE SAMPLE t1 t6 CS t5 t2 SCLK DOUT 16 1 2 0 HIGH IMPEDANCE 3 D11 4 D10 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 11 D3 12 D2 13 D1 14 D0 15 0 16 0 HIGH IMPEDANCE (MSB) t3 t4 t7 1 t8 tQUIET tCONVERT tACQ 1/fSAMPLE Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices t7 t4 SCLK SCLK VIH DOUT OLD DATA NEW DATA VIL VIH DOUT OLD DATA NEW DATA VIL Figure 3. Hold Time After SCLK Falling Edge Figure 2. Setup Time After SCLK Falling Edge t8 SCLK DOUT HIGH IMPEDANCE Figure 4. SCLK Falling Edge DOUT Three-State Maxim Integrated   15 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs µMAX Typical Operating Characteristics (MAX11103AUB+, TA = +25°C, unless otherwise noted.) OFFSET ERROR vs. TEMPERATURE DNL (LSB) -0.5 0 MAX11102 toc03 fS = 3.0Msps 0.5 0 3 2 OFFSET ERROR (LSB) fS = 3.0Msps 0.5 INL (LSB) 1.0 MAX11102 toc01 1.0 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX11102 toc02 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 1 0 -1 -0.5 -2 -1.0 -1.0 2000 4000 3000 0 1000 DIGITAL OUTPUT CODE 2000 TEMPERATURE (˚C) GAIN ERROR vs. TEMPERATURE HISTOGRAM FOR 30,000 CONVERSIONS MAX11102 toc04 35,000 30,000 25,000 1 CODE COUNT GAIN ERROR (LSB) 2 0 -1 20,000 15,000 10,000 -2 5000 -3 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2047 2046 TEMPERATURE (˚C) 2048 2049 2050 DIGITAL CODE OUTPUT SNR AND SINAD vs. ANALOG INPUT FREQUENCY THD vs. ANALOG INPUT FREQUENCY -60 MAX11102 toc06 75 fS = 3Msps 74 fS = 3Msps -70 SNR -80 73 THD (dB) SNR AND SINAD (dB) -40 -25 -10 5 20 35 50 65 80 95 110 125 DIGITAL OUTPUT CODE 3 72 SINAD -90 -100 71 -110 70 0 300 600 900 fIN (kHz) 16   -3 4000 3000 MAX11102 toc05 1000 MAX11102 toc07 0 1200 1500 -120 0 300 600 900 1200 1500 fIN (kHz) Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs µMAX Typical Operating Characteristics (continued) (MAX11103AUB+, TA = +25°C, unless otherwise noted.) THD vs. INPUT RESISTANCE MAX11102 toc08 -70 fS = 3Msps 120 THD (dB) 100 -85 90 -90 80 -95 -100 0 300 600 900 1200 1500 20 40 60 80 RIN (I) 1MHz SINE-WAVE INPUT (16,834-POINT FFT PLOT) REFERENCE CURRENT vs. SAMPLING RATE fS = 3.0Msps fIN = 1.0183MHz -20 0 fIN (kHz) 100 200 MAX11102 toc10 0 MAX11102 toc11 SFDR (dB) -80 70 150 -40 IREF (µA) AMPLITUDE (dB) fS = 3.0Msps fIN = 1.0183MHz -75 110 MAX11102 toc09 SFDR vs. ANALOG INPUT FREQUENCY 130 -60 100 AHD3 = -91.2dB -80 AHD2 = -110.3dB 50 -100 0 -120 250 500 750 1000 1250 0 1500 500 1000 ANALOG SUPPLY CURRENT vs. TEMPERATURE 2500 3000 SNR vs. REFERENCE VOLTAGE 2.9 73.0 SNR (dB) IVDD (mA) 3.2 VDD = 3.6V 2000 73.5 MAX11102 toc12 3.5 1500 fS (ksps) FREQUENCY (kHz) 2.6 MAX11102 toc13 0 fS = 3Msps fIN = 1.0183MHz 72.5 72.0 VDD = 3.0V 71.5 2.3 VDD = 2.2V 71.0 2.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) Maxim Integrated 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VREF (V)   17 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs SOT Typical Operating Characteristics (MAX11105AUB+, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE fS = 2.0Msps 0.5 DNL (LSB) 0.5 0 -0.5 0 -0.5 -1.0 -1.0 1000 0 2000 3000 4000 0 1000 DIGITAL OUTPUT CODE OFFSET ERROR vs. TEMPERATURE 3000 4000 GAIN ERROR vs. TEMPERATURE 1 GAIN ERROR (LSB) 1 0 -1 MAX11102 toc17 2 MAX11102 toc16 2 -2 0 -1 -2 -3 -3 -4 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) TEMPERATURE (˚C) HISTOGRAM FOR 30,000 CONVERSIONS SNR AND SINAD vs. ANALOG INPUT FREQUENCY 73.5 MAX11102 toc18 35,000 30,000 fS = 2.0Msps SNR AND SINAD (dB) 25,000 20,000 15,000 10,000 MAX11102 toc19 OFFSET ERROR (LSB) 2000 DIGITAL OUTPUT CODE 3 CODE COUNT MAX11102 toc15 fS = 2.0Msps INL (LSB) 1.0 MAX11102 toc14 1.0 73.0 SNR 72.5 SINAD 72.0 5000 71.5 0 2046 2047 2048 2049 DIGITAL CODE OUTPUT 18   2050 0 200 400 600 800 1000 fIN (kHz) Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs SOT Typical Operating Characteristics (continued) (MAX11105AUB+, TA = +25°C, unless otherwise noted.) THD vs. ANALOG INPUT FREQUENCY SFDR vs. ANALOG INPUT FREQUENCY fS = 2.0Msps -85 fS = 2.0Msps 105 100 SFDR (dB) -95 -100 90 -105 85 -110 80 400 600 800 1000 0 200 400 THD vs. INPUT RESISTANCE 500kHz SINE-WAVE INPUT (16,834-POINT FFT PLOT) fS = 2.0Msps fIN = 500.122kHz 0 AMPLITUDE (dB) -85 -90 -40 -60 AHD3 = -96.5dB -80 AHD2 = -92.0dB -100 -120 -100 0 20 40 60 80 0 100 250 ANALOG SUPPLY CURRENT vs. TEMPERATURE 2.4 1000 SNR vs. REFERENCE VOLTAGE (VDD) VDD = 3.0V fS = 2.0Msps fIN = 500.122kHz 74 SNR (dB) VDD = 3.6V 750 75 MAX11102 toc24 2.6 500 FREQUENCY (kHz) RIN (I) IVDD (mA) 1000 fS = 2.0Msps fIN = 500.122kHz -20 -95 73 VDD = 2.2V 72 1.8 71 1.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) Maxim Integrated 800 fIN (kHz) -80 2.0 600 fIN (kHz) MAX11102 toc23 -75 200 MAX11102 toc22 0 THD (dB) 95 MAX11102 toc25 THD (dB) -90 2.2 MAX11102 toc21 110 MAX11102 toc20 -80 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V)   19 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Pin Configurations TOP VIEW AIN1 1 AIN2 2 AGND 3 REF 4 VDD 5 TOP VIEW + MAX11102 MAX11103 MAX11106 MAX11111 EP* AIN1 1 AIN2 2 DOUT AGND 3 8 OVDD REF 4 7 CHSEL VDD 5 6 CS 10 SCLK 9 TOP VIEW + MAX11102 MAX11103 EP* 10 SCLK 9 DOUT 8 OVDD 7 CHSEL 6 CS VDD 1 + GND 2 MAX11105 MAX11110 MAX11115 MAX11116 MAX11117 AIN 3 6 CS 5 DOUT 4 SCLK SOT23 µMAX TDFN *CONNECT EXPOSED PAD TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND! Pin Description PIN NAME FUNCTION — AIN1 Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to VREF. 2 — AIN2 Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to VREF. — — 3 AIN Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to VDD. — — 2 GND 3 3 — AGND 4 4 — REF External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF capacitor. 5 5 1 VDD Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD range is 2.2V to 3.6V. For the SOT23 package, VDD also defines the signal range of the input signal AIN: 0V to VDD. 6 6 6 CS Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. 7 7 — CHSEL Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion. 8 8 — OVDD Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND. 9 9 5 DOUT Three-State Serial Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB first. See Figure 1. 10 10 4 SCLK Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See Figures 2 and 3. — — EP GND Exposed Pad (TDFN and FMAX only). Connect EP directly to a solid ground plane. Devices do not operate unless EP is connected to ground! TDFN µMAX SOT23 1 1 2 20   Ground. Connect GND to the GND ground plane. Analog Ground. Connect AGND directly the GND ground plane. Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Functional Diagrams VDD CS SCLK CONTROL LOGIC SAR OVDD VDD MAX11102/MAX11103/ MAX11106/MAX11111 OUTPUT BUFFER CS SCLK DOUT CONTROL LOGIC MAX11105/MAX11110/ MAX11115/MAX11116/ MAX11117 OUTPUT BUFFER SAR DOUT CHSEL AIN1 AIN2 AIN MUX CDAC CDAC VREF = VDD REF AGND GND (EP) GND Typical Operating Circuit VDD OVDD VOVDD +3V AIN1 ANALOG INPUTS AIN2 MAX11102 MAX11103 MAX11106 MAX11111 AGND SCK CPU DOUT REF +2.5V SCLK CS MISO SS CHSEL GND (EP) VDD +3V GND ANALOG INPUT Maxim Integrated AIN MAX11105 MAX11110 MAX11115 MAX11116 MAX11117 SCLK SCK DOUT MISO CS CPU SS   21 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Detailed Description These ADCs include a power-down feature allowing minimized power consumption at 2.5FA/ksps for lower throughput rates. The wake-up and power-down feature is controlled by using the SPI interface as described in the Operating Modes section. The MAX11102/MAX11103/MAX11105/MAX11106/MAX11110/ MAX11111/MAX11115/MAX11116/MAX11117 are fast, 12-/10-/8-bit, low-power, single-supply ADCs. The devices operate from a 2.2V to 3.6V supply and consume only 8.3mW (VDD = 3V)/5.2mW (VDD = 2.2V) at 3Msps and 6.2mW (VDD = 3V)/3.7mW (VDD = 2.2V) at 2Msps. The 3Msps devices are capable of sampling at full rate when driven by a 48MHz clock and the 2Msps devices can sample at full rate when driven by a 32MHz clock. The dual-channel devices provide a separate digital supply input (OVDD) to power the digital interface enabling communication with 1.5V, 1.8V, 2.5V, or 3V digital systems. Serial Interface The devices feature a 3-wire serial interface that directly connects to SPI, QSPI, and MICROWIRE devices without external logic. Figures 1 and 5 show the interface signals for a single conversion frame to achieve maximum throughput. The falling edge of CS defines the sampling instant. Once CS transitions low, the external clock signal (SCLK) controls the conversion. The conversion result appears at DOUT, MSB first, with a leading zero followed by the 12-bit, 10-bit, or 8-bit result. A 12-bit result is followed by two trailing zeros, a 10-bit result is followed by four trailing zeros, and an 8-bit result is followed by six trailing zeros. See Figures 1 and 5. The SAR core successively extracts binary-weighted bits in every clock cycle. The MSB appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. All extracted data bits appear successively on the data bus with the LSB appearing during the 13th/11th/9th clock cycle for 12-/10-/8-bit operation. The serial data stream of conversion bits is preceded by a leading “zero” and succeeded by trailing “zeros.” The data output (DOUT) goes into high-impedance state during the 16th clock cycle. The dual-channel devices feature a dedicated reference input (REF). The input signal range for AIN1/AIN2 is defined as 0V to VREF with respect to AGND. The single-channel devices use VDD as the reference. The input signal range of AIN is defined as 0V to VDD with respect to GND. SAMPLE SAMPLE CS SCLK DOUT 16 1 2 D9 0 HIGH IMPEDANCE 3 4 D8 5 D7 6 D6 7 D5 8 D4 9 D3 10 D2 11 D1 12 D0 13 0 14 0 15 0 16 1 0 HIGH IMPEDANCE SAMPLE SAMPLE CS SCLK DOUT 16 HIGH IMPEDANCE 1 2 0 3 D7 4 D6 5 D5 6 D4 7 D3 8 D2 9 D1 10 D0 11 0 12 0 13 0 14 0 15 0 16 1 0 HIGH IMPEDANCE Figure 5. 10-/8-Bit Timing Diagrams 22   Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs To sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. For lower sample rates, the CS falling edge can be delayed leaving DOUT in a high-impedance condition. Pull CS high after the 10th SCLK falling edge (see the Operating Modes section). The source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. The THD vs. Input Resistance graph in the Typical Operating Characteristics shows THD sensitivity as a function of the signal source impedance. Keep the source impedance at a minimum for high-dynamic performance applications. Use a highperformance op amp such as the MAX4430 to drive the analog input, thereby decoupling the signal source and the ADC. Analog Input The devices produce a digital output that corresponds to the analog input voltage within the specified operating range of 0 to VREF for the dual-channel devices and 0 to VDD for the single-channel devices. While the ADC is in conversion mode, the sampling switch is open presenting a pin capacitance, CP (CP = 5pF), to the driving stage. See the Applications Information section for information on choosing an appropriate buffer for the ADC. Figure 6 shows an equivalent circuit for the analog input AIN (for single-channel devices) and AIN1/AIN2 (for dual-channel devices). Internal protection diodes D1/D2 confine the analog input voltage within the power rails (VDD, GND). The analog input voltage can swing from GND - 0.3V to VDD + 0.3V without damaging the device. ADC Transfer Function The output format is straight binary. The code transitions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size for singlechannel devices is VDD/2n and for dual-channel devices is VREF/2n, where n is the resolution. The ideal transfer characteristic is shown in Figure 10. The electric load presented to the external stage driving the analog input varies depending on which mode the ADC is in: track mode vs. conversion mode. In track mode, the internal sampling capacitor CS (16pF) has to be charged through the resistor R (R = 50I) to the input voltage. For faithful sampling of the input, the capacitor voltage on CS has to settle to the required accuracy during the track time. VDD SWITCH CLOSED IN TRACK MODE SWITCH OPEN IN CONVERSION MODE D1 AIN1/AIN2 AIN Normal Mode In normal mode, the devices are powered up at all times, thereby achieving their maximum throughput rates. Figure 7 shows the timing diagram of these devices in normal mode. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. CS R CP Operating Modes The ICs offer two modes of operation: normal mode and power-down mode. The logic state of the CS signal during a conversion activates these modes. The powerdown mode can be used to optimize power dissipation with respect to sample rate. D2 Figure 6. Analog Input Circuit KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE CS SCLK DOUT 1 2 HIGH IMPEDANCE 3 4 5 6 7 8 VALID DATA 9 10 11 12 13 14 15 16 HIGH IMPEDANCE Figure 7. Normal Mode Maxim Integrated   23 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE INVALID DATA INVALID DATA OR HIGH IMPEDANCE HIGH IMPEDANCE Figure 8. Entering Power-Down Mode CS 1 SCLK 2 3 4 DOUT 5 6 7 8 9 10 11 12 13 14 15 16 INVALID DATA (DUMMY CONVERSION) HIGH IMPEDANCE N 1 HIGH IMPEDANCE 2 3 4 5 6 7 8 9 VALID DATA 10 11 12 13 14 15 16 HIGH IMPEDANCE Figure 9. Exiting Power-Down Mode OUTPUT CODE edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down mode. See Figure 8. FS - 1.5 x LSB 111...111 Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3FA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. 111...110 111...101 000...010 000...001 000...000 0 1 2 3 2n-2 2n-1 2n ANALOG INPUT (LSB) FULL SCALE (FS): AIN1/AIN2 = REF (TDFN, µMax) AIN = VDD (SOT) n = RESOLUTION Figure 10. ADC Transfer Function To remain in normal mode, keep CS low until the falling edge of the 10th SCLK cycle. Pulling CS high after the 10th SCLK falling edge keeps the part in normal mode. However, pulling CS high before the 10th SCLK falling 24   Entering Power-Down Mode To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 8). By pulling CS high, the current conversion terminates and DOUT enters high impedance. Exiting Power-Down Mode To exit power-down mode, implement one dummy conversion by driving CS low for at least 10 clock cycles (see Figure 9). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 3Msps operation (48MHz SCLK) is 333ns. The power-up time for 2Msps operation (32MHz SCLK) is 500ns. Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Supply Current vs. Sampling Rate For applications requiring lower throughput rates, the user can reduce the clock frequency (fSCLK) to lower the sample rate. Figure 11 shows the typical supply current (IVDD) as a function of sample rate (fS) for the 3Msps devices. The part operates in normal mode and is never powered down. Figure 13 pertains to the 2Msps devices. VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION 3 3 IVDD (mA) IVDD (mA) 4 4 MAX11102 fig11 5 The user can also power down the ADC between conversions by using the power-down mode. Figure 12 shows for the 3Msps device that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (IVDD) drops accordingly. Figure 14 pertains to the 2Msps devices. 2 2 1 1 0 0 0 500 1000 1500 2000 2500 3000 0 500 Figure 11. Supply Current vs. Sample Rate (Normal Operating Mode, 3Msps Devices) 3.0 1500 2000 Figure 13. Supply Current vs. Sample Rate (Normal Operating Mode, 2Msps Devices) 2.0 VDD = 3V fSCLK = 48MHz 2.5 1000 fS (ksps) fS (ksps) VDD = 3V fSCLK = 32MHz 1.5 IVDD (mA) IVDD (mA) 2.0 1.5 1.0 1.0 0.5 0.5 0 0 0 200 400 600 800 1000 fS (ksps) Figure 12. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 3Msps Devices) Maxim Integrated 0 100 200 300 400 500 fS (ksps) Figure 14. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 2Msps Devices)   25 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Applications Information Dual-Channel Operation The MAX11102/MAX11103/MAX11106/MAX11111 feature dual-input channels. These devices use a channelselect (CHSEL) input to select between analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure 15, the CHSEL signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. Layout, Grounding, and Bypassing For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD power supply, OVDD, and REF affects the ADC’s performance. Bypass the VDD, OVDD, and REF to ground with 0.1FF and 10FF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. 14-Cycle Conversion Mode The ICs can operate with 14 cycles per conversion. Figure 16 shows the corresponding timing diagram. Observe that DOUT does not go into high-impedance mode. Also, observe that tACQ needs to be sufficiently long to guarantee proper settling of the analog input voltage. See the Electrical Characteristics table for tACQ requirements and the Analog Input section for a description of the analog inputs. Choosing an Input Amplifier It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal’s worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CHSEL DOUT DATA CHANNEL AIN1 DATA CHANNEL AIN2 Figure 15. Channel Select Timing Diagram SAMPLE SAMPLE CS SCLK DOUT 1 2 0 3 D11 4 D10 5 D9 6 D8 7 D7 8 D6 (MSB) 9 D5 10 D4 11 D3 12 D2 13 D1 14 D0 1 0 0 tACQ 1/fSAMPLE tCONVERT Figure 16. 14-Clock Cycle Operation 26   Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. Figure 17 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. See the THD vs. Input Resistance graph in the Typical Operating Characteristics. Choosing a Reference For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. Considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. Figure 17 shows a typical application circuit using the MAX6126 to provide the reference voltage. The MAX6033 and MAX6043 are also excellent choices. +5V 0.1µF 10µF VOVDD 3V 100pF COG VDD 500I AIN1 500I MAX4430 VDC 0.1µF 10µF 10I 1 AIN1 470pF COG CAPACITOR -5V 3 0.1µF 2 MAX11102 MAX11103 MAX11106 MAX11111 AIN2 0.1µF 470pF COG CAPACITOR 10µF REF 0.1µF 0.1µF SS 5 10I 1 CPU CHSEL OUTF IN 2 1µF OUTS 0.1µF MAX6126 4 MAX4430 VDC MISO +5V 6 500I 4 DOUT EP 7 500I SCK 10µF 100pF COG AIN2 SCLK CS 10µF +5V 10µF AGND 5 4 OVDD 3 GNDS GND NR 1 0.1µF -5V 3 2 0.1µF 10µF Figure 17. Typical Application Circuit Maxim Integrated   27 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of ±1 LSB or less guarantees no missing codes and a monotonic transfer function. Offset Error The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. Gain Error The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF - 1.5 LSB. SINAD is a dynamic figure of merit that indicates the converter’s noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset:   SIGNAL RMS SINAD(dB) = 20 × log   NOISE + DISTORTION) RMS   (  Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:   V 2 + V32 + V42 + V52  THD = 20 × log 2   V1   Aperture Jitter where V1 is the fundamental amplitude and V2–V5 are the amplitudes of the 2nd- through 5th-order harmonics. Aperture Delay SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels with respect to the carrier (dBc). Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the falling edge of sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio (SNR) SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR (dB) (MAX) = (6.02 x N + 1.76) (dB) In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. 28   Signal-to-Noise Ratio and Distortion (SINAD) Spurious-Free Dynamic Range (SFDR) Full-Power Bandwidth Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. Full-Linear Bandwidth Full-linear bandwidth is the frequency at which the signal-to-noise ratio and distortion (SINAD) is equal to a specified value. Intermodulation Distortion Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are applied into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS. Maxim Integrated MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Ordering Information (continued) PIN-PACKAGE BITS SPEED (Msps) NO. OF CHANNELS TOP MARK MAX11105AUT+ PART 6 SOT23 12 2 1 +ACON MAX11106ATB+ 10 TDFN-EP* 10 3 2 +AWJ MAX11110AUT+ 6 SOT23 10 2 1 +ACOO MAX11111ATB+ 10 TDFN-EP* 8 3 2 +AWL MAX11115AUT+ 6 SOT23 8 2 1 +ACOP MAX11116AUT+ 6 SOT23 8 3 1 +ACOX MAX11117AUT+ 6 SOT23 10 3 1 +ACOY Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information PROCESS: CMOS Maxim Integrated Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 10 TDFN-EP T1033+2 21-0137 90-0061 10 µMAX-EP U10E+3 21-0109 90-0148 6 SOT23 U6+1 21-0058 90-0175   29 MAX11102/03/05/06/10/11/15/16/17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Revision History REVISION NUMBER REVISION DATE 0 4/10 Initial release of the MAX11102/MAX11103/MAX11105/MAX11110/MAX11115/ MAX11116/MAX11117 1 7/10 Initial release of the MAX11106/MAX11111. 2 9/10 Corrected the package code of the µMAX package in the Package Information section. 3 10/10 Changed the typical power consumption to 2.2V in the General Description, Features, and Detailed Description sections. 4 2/11 Update style, change voltage in Figure 17. 4, 5, 8, 9, 10, 12, 13, 14, 27 5 8/11 Updated the Ordering Information and Electrical Characteristics sections. 1, 4, 6, 8, 10, 12, 14, 29 6 10/11 Updated Figures 15 and 16. 26, 27 7 9/12 Corrected top mark information in Ordering Information section. 1, 29 8 7/13 Added automotive package for MAX11102 to Ordering Information. DESCRIPTION PAGES CHANGED — 1­–30 29 1, 22 1 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 30 ©  2013 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.