MAX11156ETC+

EVALUATION KIT AVAILABLE MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN General Description Benefits and Features The MAX11156 18-bit, 500ksps, SAR ADC offers excellent AC and DC performance with true bipolar input range, small size, and internal reference. The MAX11156 measures a ±5V (10VP-P) input range while operating from a single 5V supply. A patented charge-pump architecture allows direct sampling of high-impedance sources. The MAX11156 integrates an optional internal reference and buffer, saving additional cost and space. ● High DC/AC Accuracy Improves Measurementuality • 18-Bit Resolution with No Missing Codes • 500ksps Throughput Rate Without Pipeline Delay/ Latency • 94.6dB SNR and -101.4dB THD at 10kHz • 1.6 LSBRMS Transition Noise • ±0.5 LSB DNL (typ) and ±2.8 LSB INL (typ) ● Highly Integrated ADC Saves Cost and Space • 6ppm/°C (typ) Internal Reference • Internal Reference Buffer • ±5V Bipolar Analog Input Range ● Wide Supply Range and Low Power Simplify Power-Supply Design • 5V Analog Supply • 2.3V to 5V Digital Supply • 25.8mW Power Consumption at 500ksps • 10µA in Shutdown Mode This ADC achieves 94.6dB SNR and -101.4dB THD (typ). The MAX11156 guarantees 18-bit no-missing codes and ±2.8 LSB INL (typ). The MAX11156 communicates using an SPI-compatible serial interface at 2.5V, 3V, 3.3V, or 5V logic. The serial interface can be used to daisy-chain multiple ADCs in parallel for multichannel applications and provides a busy indicator option for simplified system synchronization and timing. The MAX11156 is offered in a 12-pin, 3mm x 3mm, TDFN package and is specified over the -40°C to +85°C temperature range. Applications ● Multi-Industry Standard Serial Interface and Small Package Reduce Size • SPI/QSPI™/MICROWIRE®/DSP-Compatible Serial Interface • 3mm x 3mm Tiny 12-Pin TDFN Package ● Data Acquisition Systems ● Industrial Control Systems/Process Control ● Medical Instrumentation QSPI is a trademark of Motorola, Inc. ● Automatic Test Equipment Selector Guide and Ordering Information appear at end of data sheet. Typical Operating Circuit 1µF MAX9632 14-Bit to 18-Bit SAR ADC Family 1µF OVDD (2.3V TO 5V) SCLK 10Ω ±5V VDD (5V) AIN+ AIN- 4.7nF INTERFACE AND CONTROL 18-BIT ADC MAX11156 REF 10µF 19-6622; Rev 2; 10/15 DIN DOUT CNVST HOST CONTROLLER CONFIGURATION REGISTER INTERNAL REFERENCE REF BUF AGNDS MICROWIRE is a registered trademark of National Semiconductor Corporation. REFIO GND 0.1µF 14-BIT 500ksps 16-BIT 250ksps — MAX11167 MAX11169 MAX11166 MAX11156 MAX11168 MAX11158 — MAX11161 MAX11165 MAX11160 MAX11150 MAX11164 MAX11154 0 to 5V Input External MAX11262 MAX11163 Reference MAX11162 MAX11152 ±5V Input Internal Reference 0 to 5V Input Internal Reference 16-BIT 500ksps 18-BIT 500ksps MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Absolute Maximum Ratings VDD to GND.............................................................-0.3V to +6V OVDD to GND........ -0.3V to the lower of (VDD + 0.3V) and +6V AIN+ to GND......................................................................... Q7V AIN-, REF, REFIO, AGNDS to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V SCLK, DIN, DOUT, CNVST to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V Maximum Current into Any Pin...........................................50mA Continuous Power Dissipation (TA = +70NC) TDFN (derate 18.2mW/NC above +70NC)...................1349mW Operating Temperature Range............................ -40NC to +85NC Junction Temperature.......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................. +300NC Soldering Temperature (reflow)........................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TDFN Junction-to-Ambient Thermal Resistance (qJA)........59.3°C/W Junction-to-Case Thermal Resistance (qJC).............22.5°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -K x VREF +K x VREF V AIN+ to GND -(VDD + 0.1) +(VDD + 0.1) V AIN- to GND -0.1 +0.1 Acquisition phase -10 ANALOG INPUT (Note 3) Input Voltage Range AIN+ to AIN-, K = 5.0/4.096 Absolute Input Voltage Range Input Leakage Current Input Capacitance +0.001 +10 16 Input-Clamp Protection Current Both inputs -20 µA pF +20 mA DC ACCURACY (Note 4) Resolution N 18 No Missing Codes 18 Offset Error -15 Offset Temperature Coefficient Bits ±2.8 +15 ±0.002 Gain Error -10 Gain Error Temperature Coefficient ±3.1 +10 Guaranteed by design LSB LSB/°C -6 ±2.8 +6 LSB -0.9 ±0.5 +0.9 LSB Positive Full-Scale Error -17 +17 LSB Negative Full-Scale Error -15 +15 LSB www.maximintegrated.com DNL LSB LSB/°C ±0.023 Integral Nonlinearity Differential Nonlinearity Bits Maxim Integrated │  2 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Analog Input CMRR Power-Supply Rejection (Note 5) SYMBOL CONDITIONS MIN TYP MAX UNITS CMRR -3.7 PSR -17.8 LSB/V 1.6 LSBRMS Transition Noise LSB/V REFERENCE (Note 7) REF Output Initial Accuracy VREF Reference mode 0 4.092 4.096 4.100 V REF Output Temperature Coefficient TCREF Reference mode 0 -17 ±7.5 +17 ppm/°C REFIO Output Initial Accuracy VREFIO Reference modes 0 and 2 4.092 4.096 4.100 V TCREFIO Reference modes 0 and 2 -15 ±6 +15 ppm/°C 4.096 REFIO Output Temperature Coefficient REFIO Output Impedance Reference modes 0 and 2 REFIO Input Voltage Range Reference mode 1 3 10 Reference Buffer Initial Offset Reference mode 0 -500 Reference Buffer Temperature Coefficient Reference mode 1 -10 External Compensation Capacitor CEXT Required for reference modes 0 and 1, recommended for reference modes 2 and 3 10 REF Voltage Input Range VREF Reference modes 2 and 3 2.5 ±6 kΩ 4.25 V +500 µV +10 µV/°C µF 4.25 V REF Input Capacitance Reference modes 2 and 3 20 pF REF Load Current VREF = 4.096V, Reference modes 2 and 3 144 µA AC ACCURACY (Note 6) VREF = 4.096V, reference mode 3 Signal-to-Noise Ratio (Note 7) SNR www.maximintegrated.com SINAD 94.6 VREF = 4.096V, reference mode 1 94.0 VREF = 2.5V, reference mode 3 90.2 Internal reference, reference mode 0 94.3 VREF = 4.096V, reference mode 3 Signal-to-Noise Plus Distortion (Note 7) 93 91.9 dB 93.9 VREF = 4.096V, reference mode 1 93.2 VREF = 2.5V, reference mode 3 89.7 Internal reference, reference mode 0 93.3 dB Maxim Integrated │  3 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Spurious-Free Dynamic Range SYMBOL CONDITIONS SFDR MIN TYP 97 103.1 Total Harmonic Distortion THD -102 Intermodulation Distortion (Note 8) IMD -119.7 MAX UNITS dB -97 dB dBFS SAMPLING DYNAMICS Throughput Sample Rate 0.01 Transient Response Full-scale step -3dB point Full-Power Bandwidth 500 ksps 400 ns 6 -0.1dB point MHz > 0.2 Aperture Delay 2.5 ns Aperture Jitter 50 psRMS POWER SUPPLIES Analog Supply Voltage Interface Supply Voltage Analog Supply Current VDD 4.75 VOVDD IVDD 2.3 IOVDD 5.25 V 5.0 6.0 7.5 Reference mode = 2, 3 3.0 3.6 4.0 6.3 10 VOVDD = 2.3V 1.7 2.0 VOVDD = 5.25V 4.4 5.0 0.9 10 OVDD Shutdown Current Power Dissipation V Reference mode = 0, 1 VDD Shutdown Current Interface Supply Current 5.25 VDD = 5V, VOVDD = 3.3V, Reference mode = 2, 3 25.8 VDD = 5V, VOVDD = 3.3V, Reference Mode = 0, 1 37.8 mA µA mA µA mW DIGITAL INPUTS (DIN, SCLK, CNVST) Input Voltage High VIH Input Voltage Low VIL Input Hysteresis 0.7 x VOVDD 0.3 x VOVDD ±0.05 x VOVDD VHYS Input Capacitance CIN Input Current IIN V V 10 VIN = 0V or VOVDD -10 V pF +10 µA DIGITAL OUTPUT (DOUT) Output Voltage High www.maximintegrated.com VOH ISOURCE = 2mA VOVDD - 0.4 V Maxim Integrated │  4 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Output Voltage Low SYMBOL VOL CONDITIONS MIN TYP ISINK = 2mA Three-State Leakage Current -10 Three-State Output Capacitance MAX UNITS 0.4 V +10 µA 15 pF TIMING (Note 9) Time Between Conversions Conversion Time Acquisition Time CNVST Pulse Width SCLK Period (CS Mode) SCLK Period (Daisy-Chain Mode) tCYC tCONV tACQ tCNVPW tSCLK tSCLK 2 100000 µs CNVST rising to data available 1.35 1.5 µs tACQ = tCYC - tCONV 0.5 µs CS mode 5 ns VOVDD > 4.5V 14 VOVDD > 2.7V 20 VOVDD > 2.3V 26 VOVDD > 4.5V 16 VOVDD > 2.7V 24 VOVDD > 2.3V 30 ns ns SCLK Low Time tSCLKL 5 ns SCLK High Time tSCLKH 5 ns SCLK Falling Edge to Data Valid Delay tDDO CNVST Low to DOUT D15 MSB Valid (CS Mode) tEN CNVST High or Last SCLK Falling Edge to DOUT High Impedance tDIS VOVDD > 4.5V 12 VOVDD > 2.7V 18 VOVDD > 2.3V 23 VOVDD > 2.7V 14 VOVDD < 2.7V 17 CS Mode 20 VOVDD > 4.5V 3 VOVDD > 2.7V 5 VOVDD > 2.3V 6 ns ns ns DIN Valid Setup Time from SCLK Falling Edge tSDINSCK DIN Valid Hold Time from SCLK Falling Edge tHDINSCK 0 ns SCLK Valid Setup Time to CNVST Falling Edge tSSCKCNF 3 ns SCLK Valid Hold Time to CNVST Falling Edge tHSCKCNF 6 ns www.maximintegrated.com ns Maxim Integrated │  5 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500Ksps, VREF = 4.096V, Reference Mode 3; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C. Limits over the operating range are guaranteed by design and device characterization Note 3: See the Analog Inputs and Overvoltage Input Clamps sections. Note 4: Static performance limits are guaranteed by design and device characterization. For definitions, see the Definitions section. Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the VDD supply voltage. Note 6: 10kHz sine wave input, -0.1dB below full scale. Note 7: See Table 4 for definition of the reference modes. Note 8: fIN1 = 9.4kHz, fIN2 = 10.7kHz, Each tone at -6.1dB below full scale. Note 9: CLOAD = 65pF on DOUT. Typical Operating Characteristics (VDD = 5V, VOVDD = 3.3V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3, TA = +25NC, unless otherwise noted.) OFFSET AND GAIN ERROR vs. TEMPERATURE 5 OFFSET ERROR GAIN ERROR 8 toc02 2 4 0.8 2 0.4 0 -1 DNL (LSB) 1.2 1 0 -2 0.0 -0.4 60 85 4.85 4.95 5.05 5.15 -2.0 5.25 VDD (V) INTEGRAL NONLINEARITY vs. CODE MAX DNL 1.5 4.0 3.0 OUTPUT CODE (DECIMAL) DNL vs. TEMPERATURE 2.0 SINGLE DEVICE 5.0 0.0 -1.0 -2.0 -3.0 2 0.5 0.0 -0.5 262144 229376 www.maximintegrated.com 196608 163840 131072 98304 65536 32768 0 OUTPUT CODE (DECIMAL) -2.0 1 0 -1 -2 -3 -1.5 -5.0 AVERAGE OF 128 DEVICES MIN INL 3 -1.0 -4.0 MAX INL 4 INL (LSB) DNL (LSB) 1.0 INL vs. TEMPERATURE 5 AVERAGE OF 128 DEVICES MIN DNL 1.0 2.0 -6.0 4.75 262144 10 35 TEMPERATURE (°C) 229376 -15 196608 -10 163840 -1.6 -5 131072 -8 98304 -1.2 -4 65536 -0.8 -6 32768 -4 -3 0 -2 -40 SINGLE DEVICE 1.6 AVERAGE OF 128 DEVICES GAIN ERROR DIFFERENTIAL NONLINEARITY vs. CODE 2.0 6 6.0 INL (LSB) OFFSET ERROR 3 ERROR (LSB) ERROR (LSB) 4 OFFSET AND GAIN ERROR vs. VDD SUPPLY VOLTAGE 10 AVERAGE OF 128 DEVICES -4 -40 -15 10 35 TEMPERATURE (°C) 60 85 -5 -40 -15 10 35 TEMPERATURE (°C) 60 85 Maxim Integrated │  6 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5V, VOVDD = 3.3V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3, TA = +25NC, unless otherwise noted.) DNL vs. VDD SUPPLY VOLTAGE 2.0 MAX DNL AVERAGE OF 128 DEVICES MIN DNL 1.5 MAX INL 4 AVERAGE OF 128 DEVICES NUMBER OF OCCURRENCES INL (LSB) 0.0 -0.5 1 0 -1 -2 -1.0 -3 4 5 6 7 8 9 10 11 12 13 14 15 toc011 50 MAGNITUDE (dB) VREF (V) -10 -8 -6 -4 -2 0 2 4 THERMAL DRIFT (ppm/°C) www.maximintegrated.com 6 8 10 12 4.0990 -12 4.0985 -14 4.0980 4.0961 4.0960 4.0959 4.0957 -16 4.0975 -40 4.0955 4.0970 4.0962 0 4.0965 4.0963 4.0956 4.0960 FFT PLOT 0 AVERAGE OF 200 DEVICES -20 10 4.0955 REF PIN VOLTAGE (V) 4.0958 20 4.0950 4.0964 50 30 REF 10 0 85 INTERNAL REFERENCE VOLTAGES vs. VDD VOLTAGE 4.0965 303 DEVICES MEAN = 2.1ppm/°C STDEV = 1.9ppm/°C 40 60 20 4.0945 303 DEVICES MEAN = -7.3ppm/°C STDEV = 1.9ppm/°C 35 TEMPERATURE (°C) REF PIN THERMAL DRIFT SLOPE 25°C TO -40°C 25°C TO +85°C 10 30 4.0940 -15 40 4.0935 -40 toc12 303 DEVICES MEAN = 4096.0mV STDEV = 1.2mV STDEV = 282ppm 4.0930 131074 131073 131072 131071 131070 4.090 131069 0 131068 4.092 131067 2000 131066 4.094 131065 4000 INITIAL ERROR VOLTAGE ON REF PIN 60 NUMBER OF OCCURRENCES 3 VREF (V) NUMBER OF OCCURRENCES 2 4.096 6000 OUTPUT CODE (DECIMAL) NUMBER OF OCCURRENCES 1 4.098 8000 131076 OUTPUT CODE (DECIMAL) 4.100 10000 60 5.25 131075 15 DEVICES 4.102 12000 70 5.15 131074 4.104 SINGLE DEVICE STDEV = 0.78 LSBRMS 14000 5.05 INTERNAL REFERENCE VOLTAGE (REF PIN) vs. TEMPERATURE OUTPUT NOISE HISTOGRAM WITH 4 SAMPLE AVERAGE 16000 VDD (V) 131073 4.95 131072 4.85 131071 0 4.75 131070 5.25 131069 5.15 VDD (V) 131068 5.05 1000 131067 4.95 2000 131066 4.85 3000 131065 4.75 4000 131064 -5 5000 131063 -2.0 6000 131062 -4 7000 131061 -1.5 SINGLE DEVICE STDEV =1.55 LSBRMS 8000 2 0.5 OUTPUT NOISE HISTOGRAM NO AVERAGE 9000 MIN INL 3 1.0 DNL (LSB) INL vs. VDD SUPPLY VOLTAGE 5 NSAMPLE = 4096 FIN = 10000Hz VIN = -0.1DBFS REF MODE = 3 VREF = 4.096 V SINGLE DEVICE SNR = 94.8DB SINAD = 94.1DB SFDR = 102.7DB THD = -102.3DB -60 -80 -100 -120 4.75 4.85 4.95 5.05 VDD (V) 5.15 5.25 -140 0 50 100 150 200 250 FREQUENCY (kHz) Maxim Integrated │  7 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5V, VOVDD = 3.3V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3, TA = +25NC, unless otherwise noted.) TWO TONES IMD -80 15.0 90 14.5 88 -100 -120 86 -140 84 5.0 7.0 9.0 11.0 13.0 15.0 0.1 1.0 90 60 THD AND SFDR vs. VDD SUPPLY VOLTAGE 100 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES 4.75 4.85 4.95 5.05 VDD (V) www.maximintegrated.com SNR SINAD -40 -15 94 92 90 88 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES 10 35 60 86 85 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES 4.75 4.85 4.95 5.15 5.25 CMR vs. INPUT FREQUENCY -30 -50 -40 -60 -60 -80 -70 -80 1.0 10.0 FREQUENCY (kHz) 5.25 100.0 1000.0 VVDD = 5.0 ± 250mV VOVDD = 3.3V SINGLE DEVICE -50 -70 0.1 5.15 PSR vs. VDD SUPPLY FREQUENCY -20 -40 -90 5.05 VDD (V) PSR (dB) CMR (dB) SFDR AND -THD (dB) 95 VAIN+ = VAIN- = ±100mV 102 100.0 SNR AND SINAD vs. VDD SUPPLY VOLTAGE 98 100 SFDR 10.0 96 -30 THD 104 96 1.0 TEMPERATURE (°C) 106 98 0.1 SFDR 105 85 85 VIN = -0.1dBFS AVERAGE OF 128 DEVICES FREQUENCY (kHz) SFDR AND THD vs. TEMPERATURE 90 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES 108 100.0 SNR AND SINAD (dB) SFDR AND -THD (dB) SNR AND SINAD (dB) 92 10 35 TEMPERATURE (°C) 10.0 110 94 -15 95 80 13.5 THD SINAD -40 100 85 115 SNR 96 86 105 FREQUENCY (kHz) SNR and SINAD vs. TEMPERATURE 88 110 90 14.0 FREQUENCY (kHz) 98 THD 115 94 92 SFDR 120 15.5 -60 SFDR AND -THD vs. FREQUENCY 125 16.0 VIN = -0.1dBFS AVERAGE OF 128 DEVICES ENOB 96 SINAD (dB) MAGNITUDE (dB) -40 SINAD SFDR AND -THD (dB) -20 SINAD and ENOB vs. FREQUENCY 98 NSAMPLE = 16384 fIN1 = 9368.9Hz VIN1 = -6.1dBFS fIN2 = 10651Hz VIN2 = -6.1dBFS SINGLE DEVICE IMD = -116.9dBFS ENOB (bits) 0 0.1 1.0 10.0 100.0 1000.0 FREQUENCY (kHz) Maxim Integrated │  8 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5V, VOVDD = 3.3V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3, TA = +25NC, unless otherwise noted.) VDD SUPPLY CURRENT vs. TEMPERATURE 8 REF MODE 0 & 1 REF MODE 2 & 3 7 IVDD (mA) IOVDD (mA) 2 AVERAGE OF 128 DEVICES REF MODE 2 & 3 1 3 -40 -15 10 35 TEMPERATURE (°C) 60 0 85 500ksps -40 -15 10 35 60 3 2 3.25 3.75 VOVDD (V) www.maximintegrated.com 4.85 4.95 4 4.25 4.75 5.25 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 5.05 5.15 5.25 AVERAGE OF 128 DEVICES IVDD 6 VDD (V) VDD AND OVDD SHUTDOWN CURRENT vs. SUPPLY VOLTAGE IOVDD 8 2 1 2.75 4.75 10 IVDD AVERAGE OF 128 DEVICES SHUTDOWN CURRENT (µA) 4 2.25 2 85 VDD AND OVDD SHUTDOWN CURRENT vs. TEMPERATURE 10 CDOUT = 65pF AVERAGE OF 128 DEVICES 10ksps 5 3 TEMPERATURE (°C) OVDD SUPPLY CURRENT vs. OVDD SUPPLY VOLTAGE 6 5 4 SHUTDOWN CURRENT (µA) IVDD (mA) REF MODE 0 & 1 7 3 4 IOVDD (mA) 10ksps VDD SUPPLY CURRENT vs. VDD SUPPLY VOLTAGE 8 CDOUT = 65pF AVERAGE OF 128 DEVICES 6 5 0 500ksps 4 6 2 OVDD SUPPLY CURRENT vs. TEMPERATURE 5 AVERAGE OF 128 DEVICES IOVDD 8 6 4 2 0 2.25 2.75 3.25 3.75 4.25 VDD or VOVDD (V) 4.75 5.25 Maxim Integrated │  9 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Pin Configuration TOP VIEW REF 2 VDD 3 AIN+ 4 AIN- 5 GND 6 12 AGNDS + REFIO 1 MAX11156 EP 11 OVDD 10 DIN 9 SCLK 8 DOUT 7 CNVST TDFN Pin Description PIN NAME I/O FUNCTION 1 REFIO I/O External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGNDS. 2 REF I/O External Reference Input/Reference Buffer Decoupling. Bypass to AGNDS in close proximity with a X5R or X7R 10µF 16V capacitor. See the Layout, Grounding, and Bypassing section. 3 VDD I Analog Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF per PCB. 4 AIN+ I Positive Analog Input 5 AIN- I Negative Analog Input. Connect AIN- to the analog ground plane or to a remote-sense ground. 6 GND I Power-Supply Ground 7 CNVST I Convert Start Input. The rising edge of CNVST initiates conversions. The falling edge of CNVST with SCLK high enables the serial interface. 8 DOUT O Serial Data Output. DOUT will change stated on the falling edge of SCLK. 9 SCLK I Serial Clock Input. Clocks data out of the serial interface when the device is selected. 10 DIN I Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 11 OVDD I Digital Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF capacitor per PCB. 12 AGNDS I Analog Ground Sense. Zero current reference for the on-board DAC and reference source. Reference for REFIO and REF. — EP — www.maximintegrated.com Exposed Pad. Connect to PCB GND. Maxim Integrated │  10 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Functional Diagram DIN AIN+ AIN- INTERFACE AND CONTROL 18-BIT ADC MAX11156 AGNDS SCLK DOUT CNVST CONFIGURATION REGISTER CONFIGURATION REGISTER VDD OVDD SW2 SW1 INTERNAL REFERENCE 10kΩ REF BUF GND REF B5 0 0 1 1 B4 0 1 0 1 REFERENCE MODE 0 1 2 3 REFERENCE SWITCH STATE SW2 CLOSED CLOSED OPEN OPEN SW1 CLOSED OPEN CLOSED OPEN REFIO Detailed Description The MAX11156 is an 18-bit single-channel, pseudodifferential ADC with a maximum throughput rates of 500ksps. This ADC includes a precision internal reference that allows for measuring a bipolar input voltage range of Q5V. Input ranges of ±3.05V to ±5.19V can be obtained by applying external reference. Both inputs (AIN+ and AIN-) are sampled with a pseudo-differential on-chip track-andhold exhibiting no pipeline delay or latency, making these ADCs ideal for multiplexed applications. The MAX11156 measures a true bipolar voltage of Q5V (10VP-P) and the inputs are protected for up to Q20mA of overrange current. This ADC is powered from a 4.75V to 5.25V analog supply (VDD) and a separate 2.3V to 5.25V digital supply (OVDD). The MAX11156 requires 500ns to acquire the input sample on an internal track-and-hold and then convert the sampled signal to 18 bits of accuracy using an internally clocked converter. Analog Inputs The MAX11156 ADC consists of a true sampling pseudodifferential input stage with high-impedance, capacitive inputs. The internal T/H circuitry feature a small-signal bandwidth of about 6MHz to provide 18-bit accurate www.maximintegrated.com sampling in 500ns. This allows for accurate sampling of a number of scanned channels through an external multiplexer. The MAX11156 can thus convert input signals on AIN+ in the range of -(K O VREF + AIN-) to +(K O VREF + AIN-) where K = 5.000/4.096. AIN+ should also be limited to ±(VDD + 0.1V) for accurate conversions. AIN- has an input range of -0.1V to +0.1V and should be connected to the ground reference of the input signal source. The MAX11156 performs a true differential sample on inputs between AIN+ and AIN- with good common-mode rejection (see the Typical Operating Circuit). This allows for improved sampling of remote transducer inputs. Many traditional ADCs with single supplies that measure bipolar input signals use resistive divider networks directly on the analog inputs. These networks increase the complexity of the input signal conditioning. However, the MAX11156 includes a patented input switch architecture which allows direct sampling onto the input sample and hold capacitor without the use of scaling resistor networks. This results in zero source loading errors when the sample and hold is allowed to fully settle. This architecture requires a minimum sample rate of 10Hz to maintain accurate conversions over the designed temperature and supply ranges. Maxim Integrated │  11 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Overvoltage Input Clamps The MAX11156 includes an input clamping circuit that activates when the input voltage at AIN+ is above (VDD + 300mV) or below -(VDD + 300mV). The clamp circuit remains high impedance while the input signal is within the range of Q(VDD + 100mV) and draws little to no current. However, when the input signal exceeds this range the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of Q(VDD + 100mV). To make use of the input clamps, connect a resistor (RS) between the AIN+ input and the voltage source to limit the voltage at the analog input and to ensure the fault current into the devices does not exceed Q20mA. Note that the voltage at the AIN+ input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: RS = VFAULT MAX − 7V 20mA where VFAULTMAX is the maximum voltage that the source produces during a fault condition. Figure 1 and Figure 2 illustrate the clamp circuit voltage current characteristics for a source impedance RS = 1280I. While the input voltage is within the Q(VDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. Internal/External Reference (REFIO) Configuration The MAX11156 includes a standard SPI interface that selects internal or external reference modes of operation through an input configuration register (see the Input Configuration Interface section). The MAX11156 features an internal bandgap reference circuit (VREFIO = 4.096V) that is buffered with an internal reference buffer that drives the REF pin. The MAX11156 configure register allows four combinations of reference configuration. These reference mode are: Reference Mode 00: ADC reference is provided by the internal bandgap feed out the REFIO pin, noise filtered with an external capacitor on the REFIO pin, then buffered by the internal reference buffer and decoupled with an external capacitor on the REF pin. In this mode the ADC requires no external reference source. Reference Mode 01: ADC reference is provided externally and feeds into the REFIO pin, buffered with the internal reference buffer and decoupled with an external capacitor on the REF pin. This mode is typically used when a common reference source is needed for more than one MAX11156. Reference Mode 10: The internal bandgap is used as a reference source output and feed out to the REFIO pin. However, the internal reference buffer is in a shutdown state and the REF pin is high impedance. This state would typically be used to provide a common reference source to a set of external reference buffers for several MAX11156. MAX11156 INPUT CLAMP CHARACTERISTICS 25 25 AIN+ PIN 20 10 ICLAMP (mA) ICLAMP (mA) INPUT SOURCE 15 10 5 0 -5 -10 5 0 -5 -10 -15 -15 RS = 1280I VDD = 5.0V -20 -25 AIN+ PIN 20 INPUT SOURCE 15 MAX11156 INPUT CLAMP CHARACTERISTICS -40 -30 -20 -10 0 10 20 30 40 SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V) Figure 1. Input Clamp Characteristics www.maximintegrated.com RS = 1280I VDD = 5.0V -20 -25 -8 -6 -4 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V) Figure 2. Input Clamp Characteristics (Zoom In) Maxim Integrated │  12 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Reference Mode 11: The internal bandgap reference source as well as the internal reference buffer are both in a shutdown state. The REF pin is in a high-impedance state. This mode would typically be used when an external reference source and external reference buffer is used to drive all MAX11156 parts in a system. capacitor charges during the acquisition period. During this acquisition period, the settling of the sampled voltage is affected by the source resistance and the input sampling capacitance. Sampling error can be estimated by modeling the time constant of the total input capacitance and the driving source impedance. Regardless of the reference mode used, the MAX11156 requires a low-impedance reference source on the REF pin to support 18-bit accuracy. When using the internal reference buffer, externally bypass the reference buffer output using at least a 10FF, low-inductance, low-ESR capacitor placed as close as possible to the REF pin, thus minimizing additional PCB inductance. When using the internal bandgap reference source, bypass the REFIO pin with a 0.1FF capacitor to ground. If providing an external reference and using the internal reference buffer, drive the REFIO pin directly with an external reference source in the range of 3.0V to 4.25V. Finally, if disabling the MAX11156 internal bandgap reference source and internal reference buffer, drive the REF pin with a reference voltage in the range of 2.5V to 4.25V and place at least a 10FF, low-inductance, low-ESR capacitor placed as close as possible to the REF pin . Although the MAX11156 is easy to drive, an amplifier buffer is recommended if the source impedance is such that when driving a switch capacitor of ~20pF a significant settling error in the desired sampling period will occur. If this is the case, it is recommended that a configuration shown in the Typical Operating Circuit is used where at least a 500pF capacitor is attached to the AIN+ pin. This capacitance reduces the size of the transient at the start of the acquisition period, which in some buffers will cause an input signal dependent offsets. When using the MAX11156 in external reference mode, it is recommended that an external reference buffer be used. For bypass capacitors on the REF pin, X7R or X5R ceramic capacitors in a 1210 case size or smaller have been found to provide adequate bypass performance. Y5U or Z5U ceramic capacitors are not recommended due to their high voltage and temperature coefficients. Maxim offers a wide range of precision references ideal for 18-bit accuracy. Table 1 lists some of the options recommended. Input Amplifier The conversion results are accurate when the ADC acquires the input signal for an interval longer than the input signal's settling time. The ADC input sampling Regardless of whether an external buffer amp is used or not, the time constant, RSOURCE × CLOAD, of the input should not exceed tACQ/13, where RSOURCE is the total signal source impedance, CLOAD is the total capacitance at the ADC input (external and internal) and tACQ is the acquisition period. Thus to obtain accurate sampling in a 500ns acquisition time a source impedance of less than 1042Ω should be used if driving the ADC directly. When driving the ADC from a buffer, it is recommended a series resistance (5Ω to 50Ω typical) between the amplifier and the external input capacitance as shown in the Typical Operating Circuit. We report some amplifier features to select the ADC driver. 1) Fast settling time: For multichannel multiplexed applications the driving operational amplifier must be able to settle to 18-bit resolution when a full-scale step is applied during the minimum acquisition time. 2) Low noise: It is important to ensure that the driver amplifier has a low average noise density appropriate for the desired bandwidth of the application. When the MAX11156 is used with its full bandwidth Table 1. MAX11156 External Reference Recommendations PART VOUT (V) TEMPERATURE COEFFICIENT (MAX) INITIAL ACCURACY (%) NOISE (0.1Hz TO 10Hz) (µVP-P) PACKAGE MAX6126 2.5, 3, 4.096, 5.0 3 (A), 5 (B) 0.06 1.35 µMAX-8 SO-8 MAX6325 2.5 1 0.04 1.5 SO-8 MAX6341 4.096 1 0.02 2.4 SO-8 www.maximintegrated.com Maxim Integrated │  13 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN of 6MHz, it is preferable to use an amplifier that will produce an output noise spectral density of less than 6nV/√Hz, to ensure the overall SNR is not degraded significantly. It is recommended to insert an external RC filter at the MAX11156 AIN+ input to attenuate outof-band input noise and preserve the ADC's SNR. The effective RMS noise at the MAX11156 AIN+ input is 65FV, thus additional noise from a buffer circuit should be significantly lower in order to achieve the maximum SNR performance. 3FFFE OUTPUTCODE (HEX) 20001 3) THD performance: The input buffer amplifier used should have a comparable THD performance with that of the MAX11156 to ensure the THD of the digitized signal is not degraded. +FS - 1LSB 5 x VREF +FS = 4.096 -5 x VREF -FS = 4.096 3FFFF LSB = 20000 TRANSITION +FS - (-FS) 262144 1FFFF 1FFFE 00001 Table 2 summarizes the operational amplifiers that are compatible with the MAX11156. The MAX9632 has sufficient bandwidth, low enough noise and distortion to support the full performance of the MAX11156. The MAX9633 is a dual amp and can support buffering for true pseudo-differential sampling. 00000 -FS +FS 0 +FS - 1.5 × LSB -FS + 0.5 × LSB INPUT VOLTAGE (LSB) Transfer Function Figure 3. Bipolar Transfer Function The ideal transfer characteristic for the MAX11156 is shown in Figure 3. The precise location of various points on the transfer function are given in Table 3. Table 2. List of Recommended ADC Driver Op Amps for MAX11156 INPUT-NOISE DENSITY (nV/√Hz) SMALL-SIGNAL BANDWIDTH (MHz) SLEW RATE (V/µs) THD (dB) ICC (mA) COMMENTS MAX9632 0.9 55 30 -128 3.9 Single amp, low noise, low THD MAX9633 3 27 18 -130 3.5/ amplifier AMPLIFIER Dual amp, low noise, low THD Table 3. Transfer Function Example CODE TRANSITION BIPOLAR INPUT (V) DIGITAL OUTPUT CODE (HEX) +FS - 1.5 LSB +4.999943 3FFFE - 3FFFF Midscale + 0.5 LSB +0.000019 20000 - 20001 Midscale 0 20000 Midscale - 0.5 LSB -0.000019 1FFFF - 20000 -FS + 0.5 LSB -4.999981 00000 - 00001 www.maximintegrated.com Maxim Integrated │  14 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Input Configuration Interface Configuring in CS Mode An SPI interface clocked at up to 50MHz controls the MAX11156. Input configuration data is clocked into the configuration register on the falling edge of SCLK through the DIN pin. The data on DIN is used to program the ADC configuration register. The construct of this register is illustrated in Table 4. The configuration register defines the output interface mode, the reference mode, and the power-down state of the MAX11156. Figure 4 details the timing for loading the input configuration register when the MAX11156 is connected in CS mode (see Figure 6 and Figure 8 for hardware connections). The load process is enabled on the falling edge of CNVST when SCLK is held high. The configuration data is clocked into the configuration register through DIN on the next 8 SCLK falling edges. Pull CNVST high to complete the input configuration register load process. DIN should idle high outside an input configuration register read. Table 4. ADC Configuration Register BIT NAME MODE REF BIT DEFAULT STATE 7:6 LOGIC STATE 00 5:4 00 CS Mode, No-Busy Indicator 01 CS Mode, with Busy Indicator 10 Daisy-Chain Mode, No-Busy Indicator 11 Daisy-Chain Mode, with Busy Indicator 00 Reference Mode 0. Internal reference and reference buffer are both powered on. 01 Reference Mode 1. Internal reference is turned off, but internal reference buffer powered on. Apply the external reference voltage at REFIO. 10 Reference Mode 2. Internal reference is powered on, but the internal reference buffer is powered off. This mode allows for internal reference to be used with an external reference buffer. 11 Reference Mode 3. Internal reference and reference buffer are both powered off. Apply an external reference voltage at REF. 0 Normal Mode. All circuitry is fully powered up at all times. 1 Static Shutdown. All circuitry is powered down. 0 Reserved, Set to 0 00 SHDN 3 0 Reserved 2:0 0 FUNCTION CNVST tHSCKCNF tSSCKCNF SCLK 0 1 2 3 tHDINSCK DIN B7 4 5 6 7 B2 B1 B0 tSDINSCK B6 B5 B4 B3 Figure 4. Input Configuration Timing in CS Mode www.maximintegrated.com Maxim Integrated │  15 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN CNVST tHSCKCNF tSSCKCNF SCLK 0 1 2 3 4 tSDINSCK DIN 5 6 7 0 1 2 3 4 5 6 7 B0 B7 B6 B5 B4 B3 B2 B1 B0 tHDINSCK B7 B6 B5 B4 B3 B2 DATA LOADED TO PART B SHIFTED THROUGH PART A B1 DATA LOADED TO PART A Figure 5. Input Configuration Timing in Daisy-Chain Mode Configuring in Daisy-Chain Mode Figure 5 details the configuration register load process when the MAX11156 is connected in a daisy-chain configuration (see Figure 12 and Figure 14 for hardware connections). The load process is enabled on the falling edge of CNVST when SCLK is held high. In daisy-chain mode, the input configuration registers are chained together through DOUT to DIN. Device A’s DOUT will drive device B’s DIN. The input configuration register is an 8-bit, first-in first-out shift register. The configuration data is clocked in N times through 8 O N falling SCLK edges. After the MAX11156 ADC in the chain is loaded with the configuration byte, pull CNVST high to complete the configuration register loading process. Figure 5 illustrates a configuration sequence for loading two devices in a chain. Data loaded into the configuration register alters the state of the MAX11156 on the next conversion cycle after the register is loaded. However, powering up the internal reference buffer or stabilizing the REFIO pin voltage will take several milliseconds to settle to 18-bit accuracy. Shutdown Mode The SHDN bit in the configuration register forces the MAX11156 into and out of shutdown. Set SHDN to 0 for normal operation. Set SHDN to 1 to shut down all internal circuitry and reset all registers to their default state. Output Interface The MAX11156 can be programmed into one of four output modes; CS modes with and without busy indicator and daisy-chain modes with and without busy indicator. When operating without busy indication, the user must externally timeout the maximumADC conversion time before commencing readback. When operating in one of the two www.maximintegrated.com busy indication modes, the user can connect the DOUT output of the MAX11156 to an interrupt input on the digital host and use this interrupt to trigger the output data read. Regardless of the output interface mode used, digital activity should be limited to the first half of the conversion phase. Having SCLK or DIN transitions near the sampling instance can also corrupt the input sample accuracy. Therefore, keep the digital inputs quiet for approximately 25ns before and 10ns after the rising edge of CNVST. These times are denoted as tSQ and tHQ in all subsequent timing diagrams. In all interface modes, the data on DOUT is valid on both SCLK edges. However, the input setup time into the receiving digital host will be maximized when data is clocked into that digital host on the falling SCLK edge. Doing so will allow for higher data transfer rates between the MAX11156 and the digital host and consequently higher converter throughput. In all interface modes, it is recommended that the SCLK be idled low to avoid triggering an input configuration write on the falling edge of CNVST. If at anytime the device detects a high SCLK state on a falling edge of CNVST, it will enter the input configuration write mode and will write the state of DIN on the next 8 falling SCLK edges to the input configuration register. In all interface modes, all data bits from a previous conversion must be read before reading bits from a new conversion. When reading out conversion data, if too few SCLK falling edges are provided and all data bits are not read out, only the remaining unread data bits will be outputted during the next readout cycle. In such an event, the output data in every other readout cycle will appear to have been truncated as only the leftover bits from the previous readout cycle are outputted. Maxim Integrated │  16 MAX11156 This is an indication to the user that there are insufficient SCLK falling edges in a given readout cycle. Table 5 provides a guide to aid in the selection of the appropriate output interface mode for a given application. CS No-Busy Indicator Mode The CS no-busy indicator mode is ideally suited for maximum throughput when a single MAX11156 is connected to a SPI-compatible digital host. The connection diagram is shown in Figure 6, and the corresponding timing is provided in Figure 7. A rising edge on CNVST completes the acquisition, initiates the conversion, and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. If CNVST is brought low during a conversion and held low throughout the maximum conversion time, the MSB will be output at the end of the conversion. When the conversion is complete, the MAX11156 enters the acquisition phase. Drive CNVST low to output the MSB onto DOUT. The remaining data bits are then clocked by subsequent SCLK falling edges. DOUT returns to high impedance after the 18th SCLK falling edge, or when CNVST goes high. 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Table 5. ADC Output Interface Mode Selector Guide MODE TYPICAL APPLICATION AND BENEFITS CS Mode, No-Busy Indicator Single or multiple ADCs connected to SPIcompatible digital host. Ideally suited for maximum throughput. CS Mode, With Busy Indicator Single ADC connected to SPI-compatible digital host with interrupt input. Ideally suited for maximum throughput. Daisy-Chain Mode, No-Busy Indicator Multiple ADCs connected to a SPIcompatible digital host. Ideally suited for multichannel simultaneous sampled isolated applications. Daisy-Chain Mode, With Busy Indicator Multiple ADCs connected to a SPIcompatible digital host with interrupt input. Ideally suited for multichannel simultaneous sampled isolated applications. CONVERT DIGITAL HOST CNVST DOUT DATA IN DIN CONFIG MAX11156 SCLK CLK Figure 6. CS No-Busy Indicator Mode Connection Diagram www.maximintegrated.com Maxim Integrated │  17 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN CS with Busy Indicator Mode A rising edge on CNVST completes the acquisition, initiates the conversion and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. The CS with busy indicator mode is shown in Figure 8 where a single ADC is connected to a SPI-compatible digital host with interrupt input. The corresponding timing is given in Figure 9. tCNVPW CNVST tCYC DIN ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSCKCNF tSCLK tSCLKL tHSCKCNF 1 SCLK 2 3 D17 D16 17 18 tSCLKH tDDO tEN DOUT 16 D15 tDIS D1 D0 Figure 7. CS No Busy Indicator Mode Timing CONVERT OVDD DIGITAL HOST CNVST MAX11156 SCLK 10kΩ DOUT DATA IN IRQ DIN CONFIG CLK Figure 8. CS With Busy Indicator Mode Connection Diagram www.maximintegrated.com Maxim Integrated │  18 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN tCNVPW CNVST tCYC DIN ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCLK tSSCKCNF tSCLKL tHSCKCNF SCLK 1 2 3 4 17 tDDO DOUT BUSY BIT D17 D16 D15 18 19 tSCLKH tDIS D1 D0 Figure 9. CS With Busy Indicator Mode Timing When the conversion is complete, DOUT transitions from high impedance to a low logic level, signaling to the digital host through the interrupt input that data readback can commence. The MAX11156 then enters the acquisition phase. The data bits are then clocked out, MSB first, by www.maximintegrated.com subsequent SCLK falling edges. DOUT returns to high impedance after the 19th SCLK falling edge or when CNVST goes high, and is then pulled to OVDD through the external pullup resistor. Maxim Integrated │  19 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Multichannel CS Configuration, Asynchronous or Simultaneous Sampling The multichannel CS configuration is generally used when multiple MAX11156 ADCs are connected to an SPIcompatible digital host. Figure 10 shows the connection diagram example using two MAX11156 devices. Figure 11 shows the corresponding timing. Asynchronous or simultaneous sampling is possible by controlling the CS1 and CS2 edges. In Figure 10, the DOUT bus is shared with the digital host limiting the throughput rate. However, maximum throughput is possible if the host accommodates each ADC’s DOUT pin independently. A rising edge on CNVST completes the acquisition, initiates the conversion and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. However, CNVST must be returned high before the minimum conversion time for proper operation so that another conversion is not initiated with insufficient acquisition time and data correctly read out of the device. When the conversion is complete, the MAX11156 enters the acquisition phase. Each ADC result can be read by bringing its CNVST input low, which consequently outputs the MSB onto DOUT. The remaining data bits are then clocked by subsequent SCLK falling edges. For each device, its DOUT will return to a high-impedance state after the 18th SCLK falling edge or when CNVST goes high. This control allows multiple devices to share the same DOUT bus. CS2 CS1 CNVST CNVST DOUT MAX11156 DEVICE A DOUT DIGITAL HOST MAX11156 DIN SCLK DEVICE B DIN CONFIG SCLK DATA IN CLK Figure 10. Multichannel CS Configuration Diagram www.maximintegrated.com Maxim Integrated │  20 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN tCNVPW tCNVPW CNVSTA(CS1) tCYC CNVSTB(CS2) DIN tACQ tCONV ACQUISITION CONVERSION tSSCKCNF ACQUISITION SCLK 1 2 tEN DOUT tSCLK tSCLKL tHSCKCNF 3 17 tDDO D17 D16 18 tSCLKH D15 19 20 21 35 tEN tDIS tDIS D1 D0 D17 36 D16 D15 D1 D0 Figure 11. Multichannel CS Configuration Timing Daisy-Chain, No-Busy Indicator Mode The daisy-chain mode with no-busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity. Simultaneous sampling of multiple ADC channels is realized on the serial interface where data readback is analogous to clocking a shift register. Figure 12 shows a connection diagram of two MAX11156s configured in a daisy chain. The corresponding timing is given in Figure 13. A rising edge on CNVST completes the acquisition and initiates the conversion. Once a conversion is initiated, it continues to completion irrespective of the state of CNVST. When a conversion is complete, the MSB is presented onto DOUT and the MAX11156 returns to the acquisition phase. The remaining data bits are stored within an internal shift register. To read these bits out, CNVST is brought low and each bit is shifted out on subsequent SCLK falling edge. The DIN input of each ADC in the chain is used to transfer conversion data from the previous ADC into the internal shift register of the next ADC, thus allowing for data to be clocked through the multichip chain on each SCLK falling edge. Each ADC in the chain outputs its MSB data first requiring 18 × N clocks to read back N ADCs. www.maximintegrated.com In daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. For instance, with a 5ns digital host setup time and 3V interface, up to four MAX11156 devices running at a conversion rate of 279ksps can be daisy-chained. Daisy-Chain with Busy Indicator Mode The daisy-chain mode with busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity while providing a conversion complete indication that can be used to interrupt a host processor to read data. Simultaneous sampling of multiple ADC channels is realized on the serial interface where data readback is analogous to clocking a shift register. The daisy-chain mode with busy indicator is shown in Figure 14 where three MAX11156s are connected to a SPI-compatible digital host with corresponding timing given in Figure 15. A rising edge on CNVST completes the acquisition and initiates the conversion. Once a conversion is initiated, it continues to completion irrespective of the state of CNVST. When a conversion is complete, the busy indicator is presented onto each DOUT and the MAX11156 returns to the acquisition phase. The busy indicator for the last ADC Maxim Integrated │  21 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN in the chain can be connected to an interrupt input on the digital host. The digital host should insert a 50ns delay from the receipt of this interrupt before reading out data from all ADCs to ensure that all devices in the chain have completed conversion. clocked through the multichip chain on each SCLK falling edge. The total of number of falling SCLKs needed to read back all data from N ADCs is 18 × N + 1 edges, the one additional SCLK falling edge required to clock out the busy mode bit from the host side ADC. The conversion data is stored within an internal shift register. To read these bits out, CNVST is brought low and each bit is shifted out on subsequent SCLK falling edge. The DIN input of each ADC in the chain is used to transfer conversion data from the previous ADC into the internal shift register of the next ADC, thus allowing for data to be In daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. For instance, with a 5ns digital host setup time and 3V interface, up to four MAX11156 devices running at a conversion rate of 276ksps can be daisy-chained on a 3-wire port. CONFIG CONVERT CNVST DIN CNVST MAX11156 DA DOUT MAX11156 DIN DEVICE A DEVICE B SCLK SCLK DIGITAL HOST DB DOUT DATA IN CLK Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram tCNVPW CNVST tCYC DIN tCONV ACQUISITION tACQ CONVERSION ACQUISITION SCLK 1 2 3 DB17 DB16 tHSCKCNF 16 17 18 19 20 DB1 DB0 DA17 DA16 34 35 36 DA1 DA0 tSCLKH tDDO DOUTB tSSCKCNF tSCLK tSCLKL DB15 Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing www.maximintegrated.com Maxim Integrated │  22 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN CONFIG CONVERT CNVST DIN MAX11156 CNVST DA DOUT DIN CNVST MAX11156 DOUT DB DIN MAX11156 DOUT DEVICE A DEVICE B DEVICE C SCLK SCLK SCLK DC DIGITAL HOST DATA IN IRQ CLK Figure 14. Daisy-Chain Mode with Busy Indicator Connection Diagram tCNVPW CNVST tCYC DIN tCONV ACQUISITION tACQ ACQUISITION CONVERSION SCLK 1 2 3 4 tSSCKCNF tSCLK tSCLKH 17 tDDO 18 19 20 21 33 34 35 36 37 53 tHSCKCNF 54 55 DA1 DA0 tSCLKL DOUTA = DINB BUSY DA17 DA16 DA15 BIT DA1 DA0 DOUTB = DINC BUSY DB17 DB16 DB15 BIT DB1 DB0 DA17 DA18 DA1 DA0 DOUTC BUSY DC17 DC16 DC15 BIT DC1 DC0 DB17 DB16 DB1 DB0 DA17 DA16 Figure 15. Daisy-Chain Mode with Busy Indicator Timing www.maximintegrated.com Maxim Integrated │  23 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Layout, Grounding, and Bypassing Offset Error For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect the GND and AGNDS pins on the MAX11156 to this ground plane. Keep the ground return to the power-supply low impedance and as short as possible for noise-free operation. For the MAX11156, the offset error is defined at the center of code 0x20000. The center of code 0x20000 should occur with an analog input voltage of exactly 0V. The offset error is defined as the deviation between the actual analog input voltage required to produce the center of code 0x20000 and the ideal analog input of 0V, expressed in LSBs. A 4.7nF C0G (or NPO) ceramic capacitor should be placed between AIN+ and the ground plane as close as possible to the MAX11156. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. For best performance, connect the REF output to the ground plane with a 16V, 10FF ceramic chip capacitor with a X5R or X7R dielectric in a 1210 or smaller case size. Ensure that all bypass capacitors are connected directly into the ground plane with an independent via. Bypass VDD and OVDD to the ground plane with 0.1FF ceramic capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10FF decoupling capacitor to VDD and OVDD per PCB. For best performance, bring a VDD power plane from the analog interface side of the MAX11156 and a OVDD power plane from the digital interface side of the device. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Gain Error Gain error is defined as the difference between the actual change in analog input voltage required to produce a top code transition minus a bottom code transition, and the ideal change in analog input voltage range to produce the same code transitions. It is expressed in LSB. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the fullscale analog input power to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the power signal to the power noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s power to the power of all the other ADC output signals: Signal   = 10 × log  SINAD(dB)  (Noise + Distortion)  Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of less than Q1 LSB guarantees no missing codes and a monotonic transfer function. www.maximintegrated.com Maxim Integrated │  24 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Effective Number of Bits Aperture Delay The effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: SINAD − 1.76 ENOB = 6.02 Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Total Harmonic Distortion A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Total harmonic distortion (THD) is the ratio of the power contained in the first five harmonics of the converted data to the power of the fundamental. This is expressed as: THD = 10 × log P2 + P3 + P4 + P5 P1 where P1 is the fundamental power and P2 through P5 is the power of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Small-Signal Bandwidth Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as full-power input bandwidth frequency. Spurious-free dynamic range (SFDR) is the ratio of the power of the fundamental (maximum signal component) to the power of the next-largest frequency component. www.maximintegrated.com Maxim Integrated │  25 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Selector Guide PART BITS INPUT RANGE (V) REFERENCE PACKAGE MAX11262 14 0 to 5 External 3mm x 5mm µMAX-10 500 MAX11160 16 0 to 5 Internal 3mm x 5mm µMAX-10 500 MAX11161 16 0 to 5 Internal 3mm x 5mm µMAX-10 250 MAX11162 16 0 to 5 External 3mm x 5mm µMAX-10 500 MAX11163 16 0 to 5 External 3mm x 5mm µMAX-10 250 MAX11164 16 0 to 5 Internal/External 3mm x 3mm TDFN-12 500 MAX11165 16 0 to 5 Internal/External 3mm x 3mm TDFN-12 250 MAX11166 16 ±5 Internal/External 3mm x 3mm TDFN-12 500 MAX11167 16 ±5 Internal/External 3mm x 3mm TDFN-12 250 MAX11168 16 ±5 Internal 3mm x 5mm µMAX-10 500 MAX11169 16 ±5 Internal 3mm x 5mm µMAX-10 250 MAX11150 18 0 to 5 Internal 3mm x 5mm µMAX-10 500 MAX11152 18 0 to 5 External 3mm x 5mm µMAX-10 500 MAX11154 18 0 to 5 Internal/External 3mm x 3mm TDFN-12 500 MAX11156 18 ±5 Internal/External 3mm x 3mm TDFN-12 500 MAX11158 18 ±5 Internal 3mm x 5mm µMAX-10 500 Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX11156ETC+T -40°C to +85°C 12 TDFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed Pad. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE PACKAGE OUTLINE LAND TYPE CODE NO. PATTERN NO. 12 TDFN-EP www.maximintegrated.com SPEED (ksps) TD1233+1 21-0664 90-0397 Maxim Integrated │  26 MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Revision History REVISION NUMBER REVISION DATE PAGES CHANGED DESCRIPTION 0 3/13 Initial release — 1 1/15 Updated Benefits and Features section 1 2 10/15 Updated Electrical Characteristics table, Typical Operating Characteristics and various text 1-11, 14, 24-26 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │  27