EVALUATION KIT AVAILABLE
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
General Description
Benefits and Features
The MAX11163 is a 16-bit, 250ksps, +5V unipolar pseudodifferential input SAR ADC offering excellent AC and DC
performance in a small standard package.
This ADC typically achieves 93.2dB SNR, -105dB THD, ±0.5
LSB INL, and ±0.2 LSB DNL. The MAX11163 guarantees
16-bit no-missing codes.
The MAX11163 communicates using an SPI-compatible
serial interface at 2.3V, 3V, 3.3V, or 5V logic.
The serial interface can be used to daisy-chain multiple
ADCs for multichannel applications and provides a busy
indicator option for simplified system synchronization and
timing.
The MAX11163 is offered in a 10-pin, 3mm x 5mm,
µMAXM package and is specified over the -40NC to +85NC
temperature range.
Applications
●●
●●
●●
●●
●●
Industrial Process Control
Medical Instrumentation
Test and Measurements
Automatic Test Equipment
Narrowband Receivers
Selector Guide and Ordering Information appear at end of
data sheet.
●● High DC/AC Accuracy Improves Measurement
Quality
• 16-Bit Resolution with No Missing Codes
• 250ksps Throughput Rates Without Pipeline Delay/
Latency
• 93.2dB SNR and -105dB THD at 10kHz
• 0.38 LSBRMS Transition Noise
• ±0.2 LSB DNL (typ) and ±0.5 LSB INL (typ)
●● Wide Supply Range and Low Power Simplify PowerSupply Design
• +5V Analog Supply
• +2.3V to +5V Digital Supply
• 19mW Power Consumption at 250ksps
• 10μA in Shutdown Mode
●● Multi-Industry Standard Serial Interface and Small
Package Reduces Size
• SPI/QSPI™/MICROWIRE®/DSP-Compatible
Serial Interface
• 3mm x 5mm Tiny 10-Pin µMAX Package
μMAX is registered trademark of Maxim Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
Typical Operating Circuit
16-Bit to 18-Bit SAR ADC Family
VDD
(5V)
1µF
10Ω
1µF
SCLK
AIN+
MAX9632
0 TO +5V
16-BIT ADC
4.7nF, COG
Ceramic
AIN-
SDI
INTERFACE AND CONTROL
SDO
CNVST
REF
REF
10µF
MAX11163
GND
19-6794 Rev 3; 11/16
14-BIT/
500ksps
OVDD
(2.3V TO 5V)
HOST
CONTROLLER
16-BIT/
250ksps
16-BIT/
500ksps
18-BIT/
500ksps
±5V Input
Internal
Reference
—
MAX11167
MAX11169
MAX11166 MAX11156
MAX11168 MAX11158
0 to 5V
Input Internal
Reference
—
MAX11161
MAX11165
MAX11160 MAX11150
MAX11164 MAX11154
0 to 5V Input
External
MAX11262 MAX11163
Reference
MAX11162 MAX11152
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Absolute Maximum Ratings
VDD to GND.............................................................-0.3V to +6V
OVDD to GND........ -0.3V to the lower of (VDD + 0.3V) and +6V
AIN+, AIN-, REF
to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V
SCLK, SDI, SDO, CNVST
to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V
Maximum Current into Any Pin...........................................50mA
Continuous Power Dissipation (TA = +70NC)
µMAX (derate 8.8mW/°C above +70°C)......................707mW
Operating Temperature Range............................ -40NC to +85NC
Junction Temperature.......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s)..................................+300NC
Soldering Temperature (reflow)........................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
µMAX
Junction-to-Ambient Thermal Resistance (θJA).......... 113°C/W
Junction-to-Case Thermal Resistance ((θJC)...............36°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 250ksps, VREF = 5V; TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (Note 3)
Input Voltage Range
Absolute Input Voltage Range
Input Leakage Current
AIN+ to AIN-
0
VREF
V
AIN+ to GND
-0.1
VREF +
0.1
V
AIN- to GND
-0.1
+0.1
Acquisition phase
-10
Input Capacitance
+0.001
+10
µA
+20
mA
40
Input-Clamp Protection Current
Both inputs
pF
-20
STATIC PERFOMANCE (Note 4)
Resolution
N
No Missing Codes
Offset Error
16
Bits
16
Bits
-3.5
Offset Error Temperature Coefficient
±0.5
+3.5
±0.006
Gain Error
-7.5
Gain Error Temperature Coefficient
±2
LSB
LSB/°C
+7.5
±0.04
LSB
LSB/°C
Integral Nonlinearity
INL
-1.2
±0.5
+1.2
LSB
Differential Nonlinearity
DNL
-0.5
±0.2
+0.5
LSB
Positive Full-Scale Error
-7.25
+7.25
LSB
Analog Input CMR
CMR
Referred to the output
-2.2
Power-Supply Rejection (Note 5)
PSR
PSR vs. VDD, referred to the output
-4.64
LSB/V
0.38
LSBRMS
Transition Noise
www.maximintegrated.com
LSB/V
Maxim Integrated │ 2
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Electrical Characteristics (continued)
(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 250ksps, VREF = 5V; TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE
REF Voltage Input Range
VREF
2.5
REF Input Capacitance
REF Load Current
VDD
V
20
pF
78.5
µA
93.2
dB
87.6
dB
93.0
dB
DYNAMIC PERFOMANCE (Note 6)
Signal-to-Noise Ratio
92.1
SNR
VREF = 2.5V
Signal-to-Noise Plus Distortion
SINAD
91.6
Spurious-Free Dynamic Range
SFDR
99.2
107
Total Harmonic Distortion
THD
-105
Intermodulation Distortion (Note 7)
IMD
-119.4
dB
-98
dB
dBFS
SAMPLING DYNAMICS
Throughput Sample Rate
0
Transient Response
Full-scale step
-3dB point
Full-Power Bandwidth
250
ksps
400
ns
6
-0.1dB point
MHz
> 0.2
Aperture Delay
2.5
ns
Aperture Jitter
50
psRMS
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
VDD
4.75
5.25
V
VOVDD
2.3
5.25
V
IVDD
2.5
VDD Shutdown Current
Interface Supply Current
IOVDD
OVDD Shutdown Current
Power Dissipation
VOVDD = 2.3V
VOVDD = 5.25V
VDD = 5V, VOVDD = 3.3V
3.5
mA
0.06
10
µA
0.7
0.9
2.0
0.01
19
2.4
10
mA
µA
mW
DIGITAL INPUTS (SDI, SCLK, CNVST)
Input Voltage High
VIH
Input Voltage Low
VIL
0.7 x
VOVDD
V
0.3 x
VOVDD
V
VHYS
±0.05 x
VOVDD
V
Input Capacitance
CIN
10
pF
Input Current
IIN
Input Hysteresis
www.maximintegrated.com
VIN = 0V or VOVDD
-10
+10
µA
Maxim Integrated │ 3
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Electrical Characteristics (continued)
(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 250ksps, VREF = 5V; TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT (SDO)
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
Three-State Leakage Current
VOVDD
- 0.4
V
-10
Three-State Output Capacitance
0.4
V
+10
µA
15
pF
TIMING (Note 8)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
SCLK Period (CS Mode)
SCLK Period (Daisy-Chain Mode)
tACQ
tCNVPW
tSCLK
tSCLK
SCLK Low Time
tSCLKL
SCLK High Time
tSCLKH
SCLK Falling Edge to Data Valid
Delay
tDSDO
CNVST Low to SDO D15 MSB Valid
(CS Mode)
tEN
CNVST High or SDI High or Last
SCLK Falling Edge to SDO High
Impedance
tDIS
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4
tCYC
tCONV
CNVST rising to data available
2.6
µs
3
µs
tACQ = tCYC - tCONV
1
µs
CS mode
5
ns
VOVDD > 4.5V
14
VOVDD > 2.7V
20
VOVDD > 2.3V
25
VOVDD > 4.5V
16
VOVDD > 2.7V
24
VOVDD > 2.3V
30
ns
ns
6
ns
6
ns
VOVDD > 4.5V
12
VOVDD > 2.7V
18
VOVDD > 2.3V
23
VOVDD > 2.7V
14
VOVDD < 2.7V
18
CS mode
20
ns
ns
ns
Maxim Integrated │ 4
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Electrical Characteristics (continued)
(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 250ksps, VREF = 5V; TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDI Valid Setup Time from CNVST
Rising Edge
tSSDISCK 4-wire CS mode
5
ns
SDI Valid Hold Time from SCLK Rising Edge
tHSDISCK 4-wire CS mode
0
ns
SCLK Valid Setup Time from CNVST
tSSCKCNV Daisy-chain mode
Rising Edge
3
ns
SCLK Valid Hold Time from CNVST
Rising Edge
3
ns
6
ns
0
ns
tHSCKCNV Daisy-chain mode
VOVDD > 4.5V, daisy-chain mode 3
SDI Valid Setup Time from SCLK
Falling Edge
tSSDISCK VOVDD > 2.7V, daisy-chain mode 5
SDI Valid Hold Time from SCLK Falling Edge
tHSDISCK Daisy-chain mode
SDI High to SDO High
VOVDD > 2.3V, daisy-chain mode 6
tDSDOSDI
Daisy-chain mode with busy indicator,
VOVDD > 4.5V
10
Daisy-chain mode with busy indicator,
VOVDD > 2.7V
15
Daisy-chain mode with busy indicator,
VOVDD > 2.3V
20
ns
Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of
+25°C. Limits over the operating temperature range are guaranteed by design and device characterization.
Note 3: See the Analog Inputs and Overvoltage Input Clamps sections.
Note 4: Static performance limits are guaranteed by design and device characterization. For definitions, see the Definitions section.
Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the VDD supply voltage.
Note 6: 10kHz sine wave input, -0.1dB below full scale.
Note 7: fIN1 ~ 9.4kHz, fIN2 ~ 10.7kHz, Each tone at -6.1dB below full scale.
Note 8: CLOAD = 65pF on SDO.
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Maxim Integrated │ 5
MAX11163
6-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Typical Operating Characteristics
(VDD = 5V, VOVDD = 3.3V, fSAMPLE = 250ksps, VREF = 5V, TA = +25°C, unless otherwise noted.)
OFFSET AND GAIN ERROR
vs. TEMPERATURE
3
OFFSET ERROR
GAIN ERROR
toc01
OFFSET AND GAIN ERROR
vs. VDD SUPPLY VOLTAGE
4
AVERAGE OF 128 DEVICES
3
2
toc02
AVERAGE OF 128 DEVICES
OFFSET ERROR
GAIN ERROR
2
ERROR (LSB)
ERROR (LSB)
1
0
-1
1
0
-1
-2
-2
-3
-3
-4
-40
-15
10
35
TEMPERATURE (°C)
60
85
4.85
4.95
5.05
5.15
5.25
VDD (V)
INTEGRAL NONLINEARITY vs. CODE
DIFFERENTIAL NONLINEARITY vs. CODE
SINGLE DEVICE
SINGLE DEVICE
0.4
toc04
1.5
toc03
0.5
1.0
0.3
0.2
0.5
0.1
INL (LSB)
DNL (LSB)
4.75
0.0
-0.1
0.0
-0.5
-0.2
-0.3
-1.0
-0.4
MAX INL
toc06
AVERAGE OF 128 DEVICES
MIN INL
1.0
0.5
INL (LSB)
DNL (LSB)
65536
57344
1.5
0.2
0.0
0.0
-0.2
-0.5
-0.4
-1.0
-0.6
49152
toc05
AVERAGE OF 128 DEVICES
MIN DNL
0.4
40960
INL vs. TEMPERATURE
DNL vs. TEMPERATURE
MAX DNL
32768
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
0.6
24576
16384
8192
65536
57344
49152
40960
32768
24576
16384
8192
0
-1.5
0
-0.5
-40
-15
10
35
TEMPERATURE (°C)
www.maximintegrated.com
60
85
-1.5
-40
-15
10
35
TEMPERATURE (°C)
60
85
Maxim Integrated │ 6
MAX11163
6-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Typical Operating Characteristics (continued)
(VDD = 5V, VOVDD = 3.3V, fSAMPLE = 250ksps, VREF = 5V, TA = +25°C, unless otherwise noted.)
DNL vs. VDD SUPPLY VOLTAGE
1.2
MAX DNL
MAX INL
1.0
0.4
0.5
INL (LSB)
0.8
0.0
-0.5
-0.8
-1.0
4.75
4.85
4.95
VDD (V)
5.05
5.15
OUTPUT NOISE HISTOGRAM
NO AVERAGE
28000
-1.5
5.25
toc09
20000
16000
12000
8000
4.85
4.95
5.05
5.15
5.25
OUTPUT NOISE HISTOGRAM WITH
4 SAMPLE AVERAGE
toc10
SINGLE DEVICE
STDEV = 0.23LSBRMS
24000
20000
16000
12000
8000
32773
0
-40
-60
-80
toc12
NSAMPLE = 16384
fIN1 = 9368.9Hz
VIN1 = -6.1dBFS
fIN2 = 10651Hz
VIN2 = -6.1dBFS
SINGLE DEVICE
IMD = -119.7dBFS
-20
MAGNITUDE (dB)
-40
-60
-80
-100
-100
-120
-120
-140
TWO TONES IMD
toc11
NSAMPLE = 4096
fIN = 10101 Hz
VIN = -0.1dBFS
SNR = 93.1dB
SINAD = 93.0dB
SFDR = 109.0dB
-20
32771
OUTPUT CODE (DECIMAL)
FFT PLOT
0
32769
32767
32765
32773
32771
32769
32767
32765
32763
32763
0
OUTPUT CODE (DECIMAL)
MAGNITUDE (dB)
VDD (V)
4000
4000
0
4.75
28000
STDEV = 0.45LSBRMS
NUMBER OF OCCURRENCES
NUMBER OF OCCURRENCES
24000
MIN INL
32000
SINGLE DEVICE
AVERAGE OF 128 DEVICES
0.0
-0.4
-1.2
toc08
1.5
AVERAGE OF 128 DEVICES
MIN DNL
DNL (LSB)
INL vs. VDD SUPPLY VOLTAGE
toc07
0
20
40
60
80
FREQUENCY (kHz)
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100
120
-140
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
FREQUENCY (kHz)
Maxim Integrated │ 7
MAX11163
6-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Typical Operating Characteristics (continued)
(VDD = 5V, VOVDD = 3.3V, fSAMPLE = 250ksps, VREF = 5V, TA = +25°C, unless otherwise noted.)
SINAD AND ENOB vs. FREQUENCY
100
SINAD
VIN = -0.1dBFS
AVERAGE OF 128 DEVICES
ENOB
98
toc13
16.3
92
SFDR AND -THD (dB)
15.3
ENOB (bits)
SINAD (dB)
120
15.8
94
THD
110
105
100
95
90
14.8
90
VIN = -0.1dBFS
85
0.1
1.0
80
14.3
10.0
100.0
0.1
1.0
FREQUENCY (kHz)
SNR AND SINAD vs. TEMPERATURE
toc15
98
SINAD
100.0
toc16
THD
SFDR
110
SFDR AND -THD (dB)
SNR AND SINAD (dB)
10.0
115
94
92
90
86
FREQUENCY (kHz)
SFDR and THD vs. TEMPERATURE
120
SNR
96
88
toc14
SFDR
115
96
88
SFDR AND -THD vs. FREQUENCY
125
fIN = 10kHz
VIN = -0.1dBFS
AVERAGE OF 128 DEVICES
-40
-15
105
100
95
90
10
35
TEMPERATURE (°C)
60
85
85
fIN = 10kHz
VIN = -0.1dBFS
AVERAGE OF 128 DEVICES
-40
-15
SNR and SINAD vs. VDD SUPPLY VOLTAGE
98
35
60
85
toc17
SNR
SINAD
96
SNR AND SINAD (dB)
10
TEMPERATURE (°C)
94
92
90
88
86
fIN = 10kHz
VIN = -0.1dBFS
AVERAGE OF 128 DEVICES
4.75
4.85
4.95
5.05
5.15
5.25
VDD (V)
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Maxim Integrated │ 8
MAX11163
6-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Typical Operating Characteristics (continued)
(VDD = 5V, VOVDD = 3.3V, fSAMPLE = 250ksps, VREF = 5V, TA = +25°C, unless otherwise noted.)
toc18
SFDR
-40
110
VAIN+ = VAIN- = ±100mV
SINGLE DEVICE
-50
CMR (dB)
105
100
-60
-70
95
fIN = 10kHz
VIN = -0.1dBFS
AVERAGE OF 128 DEVICES
90
85
toc19
-30
THD
115
SFDR AND -THD (dB)
CMR vs. INPUT FREQUENCY
THD AND SFDR vs. VDD SUPPLY VOLTAGE
120
4.75
4.85
-80
4.95
5.05
5.15
-90
5.25
0.1
1.0
10.0
VDD (V)
PSR vs. VDD SUPPLY FREQUENCY
-30
-40
toc20
1000.0
VDD SUPPLY CURRENT
vs. TEMPERATURE
4.0
VVDD = 5.0 ± 250mV
VOVDD = 3.3V
SINGLE DEVICE
toc21
AVERAGE OF 128 DEVICES
3.6
IVDD (mA)
-50
PSR (dB)
100.0
FREQUENCY (kHz)
-60
3.2
2.8
-70
2.4
-80
-90
0.1
1.0
10.0
100.0
2.0
1000.0
-40
-15
10
35
TEMPERATURE (°C)
FREQUENCY (kHz)
OVDD SUPPLY CURRENT
vs. TEMPERATURE
4.0
500ksps
IOVDD (mA)
85
toc22
CSDO = 65pF
AVERAGE OF 128 DEVICES
10ksps
3.2
60
2.4
1.6
0.8
0.0
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-40
-15
10
35
TEMPERATURE (°C)
60
85
Maxim Integrated │ 9
MAX11163
6-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Typical Operating Characteristics (continued)
(VDD = 5V, VOVDD = 3.3V, fSAMPLE = 250ksps, VREF = 5V, TA = +25°C, unless otherwise noted.)
VDD SUPPLY CURRENT
vs. VDD SUPPLY VOLTAGE
4.0
toc23
OVDD SUPPLY CURRENT
vs. OVDD SUPPLY VOLTAGE
4.0
500ksps
3.6
3.2
3.2
2.4
1.6
2.8
0.8
2.4
2.0
4.75
4.85
4.95
VDD (V)
5.05
5.15
VDD AND OVDD SHUTDOWN
CURRENT vs. TEMPERATURE
0.4
0.0
5.25
toc25
2.25
SHUTDOWN CURRENT (µA)
SHUTDOWN CURRENT (µA)
0.2
0.1
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10
35
TEMPERATURE (°C)
60
85
3.75
VOVDD (V)
4.25
4.75
5.25
toc26
AVERAGE OF 128 DEVICES
IVDD
0.3
-15
3.25
VDD AND OVDD SHUTDOWN
CURRENT vs. SUPPLY VOLTAGE
IOVDD
-40
2.75
0.5
IVDD
AVERAGE OF 128 DEVICES
0.0
CSDO = 65pF
AVERAGE OF 128 DEVICES
10ksps
IOVDD (mA)
IVDD (mA)
AVERAGE OF 128 DEVICES
toc24
IOVDD
0.4
0.3
0.2
0.1
0.0
2.25
2.75
3.25
3.75
4.25
VDD or VOVDD (V)
4.75
5.25
Maxim Integrated │ 10
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Pin Configuration
TOP VIEW
REF
1
VDD
2
AIN+
3
AINGND
+
10
OVDD
9
SDI
8
SCLK
4
7
SDO
5
6
CNVST
MAX11163
µMAX
Pin Description
PIN
NAME
FUNCTION
1
REF
External Reference Input. Bypass to GND in close proximity with a X5R or X7R 10μF 16V capacitor. See the
Layout, Grounding, and Bypassing section.
2
VDD
Analog Power Supply. Bypass VDD to GND with a 0.1µF capacitor as close as possible to each device and
one 10µF capacitor per board.
3
AIN+
Positive Analog Input
4
AIN-
Negative Analog Input. Connect AIN- to the analog ground plane or to a remote sense ground.
5
GND
Power-Supply Ground
6
CNVST
7
SDO
Serial Data Output. SDO transitions on the falling edge of SCLK.
8
SCLK
Serial Clock Input. Clocks data out of the serial interface when the device is selected.
9
SDI
10
OVDD
Conversion Start Input. The rising edge of CNVST initiates the conversions and selects the interface mode:
daisy-chain or CS. In CS mode, set CNVST low to enable the SDO output. In daisy-chain mode, read the data
when CNVST is high.
Serial Data Input and Mode Select Input. Daisy-chain mode is selected if SDI is low during the CNVST rising
edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs
onto a single SDO line. CS mode is selected if SDI is high during the CNVST rising edge. In this mode, either
SDI or CNVST can enable the serial output signals when low. If SDI or CNVST is low when the conversion is
completed, the busy indicator feature is enabled.
Digital Power Supply. OVDD can range from 2.3V to VDD. Bypass OVDD to GND with a 0.1µF capacitor for
each device and one 10µF capacitor per board.
www.maximintegrated.com
Maxim Integrated │ 11
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Functional Diagram
Detailed Description
Analog Inputs
The MAX11163 is a 16-bit single-channel, pseudodifferential SAR ADC with maximum throughput rates of
250ksps. This ADC measures a unipolar input voltage
interval from 0V to VREF. The external reference interval
ranges from 2.5V to VDD. Both inputs, AIN+ and AIN-, are
sampled with an integrated pseudo-differential track-andhold (T/H) exhibiting no pipeline delay or latency, making
this ADC ideal for multiplexed channel applications.
The MAX11163 ADC consists of a true sampling pseudodifferential input stage with high-impedance, capacitive
inputs. The internal T/H circuitry feature a small-signal bandwidth of about 6MHz to provide 16-bit accurate sampling
in 1Fs. This allows for accurate sampling of a number of
scanned channels through an external multiplexer.
The MAX11163 inputs are protected for up to Q20mA of
overrange current. This ADC is powered from a 4.75V to
5.25V analog supply (VDD) and a separate 2.3V to 5.25V
digital supply (OVDD). The MAX11163 requires 1µs to
acquire the input sample on an internal track-and-hold
and then converts the sampled signal to 16 bits of accuracy
using an internally clocked converter.
AIN+ has a max input range of -0.1V to (VDD + 0.1V). AINhas a max input range of -0.1V to +0.1V.
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The MAX11163 accurately converts input signals on the
AIN+ input in the range of AIN- and (VREF + AIN-).
The MAX11163 performs a true differential sampling on
inputs between AIN+ and AIN- with good common-mode
rejection (see the Typical Operating Circuit). Connecting
AIN- to the ground reference of the input signal source
improves rejection of common-mode noise of remote
transducer inputs.
Maxim Integrated │ 12
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Overvoltage Input Clamps
The MAX11163 includes an input clamping circuit that
activates when the input voltage at AIN+ is above (VDD
+ 300mV) or below -300mV. The clamp circuit remains
high impedance while the input signal is within the range
of -100mV to (VDD + 100mV) and draws little to no current.
However, when the input signal exceeds this range the
clamps begin to turn on. Consequently, to obtain the
highest accuracy, ensure that the input voltage does not
exceed the range of -100mV to (VDD + 100mV).
To make use of the input clamps, connect a resistor (RS)
between the AIN+ input and the voltage source to limit the
voltage at the analog input and to ensure the fault current
into the devices does not exceed Q20mA. Note that the
voltage at the AIN+ input pin limits to approximately 7V
during a fault condition so the following equation can be
used to calculate the value of RS:
RS =
VFAULT MAX − 7V
20mA
where VFAULTMAX is the maximum voltage that the
source produces during a fault condition.
Figure 1 and Figure 2 illustrate the clamp circuit voltage
current characteristics for a source impedance RS = 1170I.
While the input voltage is within the -300mV to (VDD +
300mV) range, no current flows in the input clamps. Once
the input voltage goes beyond this voltage range, the
clamps turn on and limit the voltage at the input pin.
Reference
The MAX11163 requires a low-impedance reference
source on the REF pin to support 16-bit accuracy. Maxim
offers a wide range of precision references ideal for 16-bit
accuracy. Table 1 lists some of the options recommended.
It is recommended that a reference buffer or the output of
one of these recommended reference sources be used
to drive this pin. In addition, an external bypass capacitor
of at least 10µF with low inductance and ESR should be
placed as close as possible to the REF pin, thus minimizing
the PCB inductance. X7R or X5R ceramic capacitors in
a 1210 case size or smaller have been found to provide
adequate bypass performance. Y5U or Z5U ceramic
capacitors are not recommended due to their high voltage
and temperature coefficients.
Table 1. MAX11163 External Reference Recommendations
PART
VOUT (V)
TEMPERATURE
COEFFICIENT (MAX)
INITIAL
ACCURACY (%)
NOISE (0.1HZ TO
10HZ) (ΜVP-P)
PACKAGE
MAX6126
2.5, 3, 4.096, 5.0
3 (A), 5 (B)
0.06
1.35
µMAX-8
SO-8
MAX6325
MAX6341
MAX6350
2.5, 4.096, 5.0
1
0.04, 0.02
1.5, 2.4, 3.0
SO-8
MAX11163 INPUT CLAMP
CHARACTERISTICS
25
INPUT SOURCE
AIN+ PIN
RS = 1170I
VDD = 5.0V
15
CURRENT INTO PIN (mA)
CURRENT INTO PIN (mA)
25
5
-5
INPUT SOURCE
AIN+ PIN
RS = 1170I
VDD = 5.0V
5
-5
-15
-15
-25
15
MAX11163 INPUT CLAMP
CHARACTERISTICS
-25
-30
-20
-10
0
10
20
30
40
VOLTAGE AT AIN+ PIN AND INPUT SOURCE (V)
Figure 1. Input Clamp Characteristics
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-4
-2
0
2
4
6
8
10
VOLTAGE AT AIN+ PIN AND INPUT SOURCE (V)
Figure 2. Input Clamp Characteristics (Zoom In)
Maxim Integrated │ 13
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Input Amplifier
These amplifier features help to select the ADC driver:
Although the MAX11163 is easy to drive, an amplifier buffer
is recommended if the source impedance is such that
when driving a switch capacitor of ~40pF a significant
settling error in the desired acquisition time will occur. If
this is the case, it is recommended that a configuration
shown in the Typical Operating Circuit is used where at
least a 4.7nF capacitor is attached to the AIN+ pin. This
capacitance reduces the size of the transient at the start
of the acquisition period, which in some buffers will cause
an input signal dependent offset.
1) Fast Settling Time: For multichannel multiplexed
applications the driving operational amplifier must
settle to 16-bit resolution when a full-scale step is
applied during the minimum acquisition time.
2) Low Noise: It is important to ensure that the driver
amplifier has a low average noise density appropriate
for the desired bandwidth of the application. In the case
of the MAX11163, settling in a 1µs duration requires
an RC filter bandwidth of approximately 2MHz. With
this bandwidth, it is preferable to use an amplifier that
will produce an output noise-spectral density of less
than 6.4nV/√Hz, to ensure that the overall SNR is not
degraded significantly. It is recommended to insert
an external RC filter at the MAX11163 AIN+ input
to attenuate out-of-band input noise and preserve
the ADC's SNR. The effective RMS noise at the
MAX11163 AIN+ input is 34µV, thus additional noise
from a buffer circuit should be significantly lower to
achieve the maximum SNR performance.
3) THD Performance: The input buffer amplifier used
should have better THD performance than the MAX11163
to ensure the THD of the digitized signal is not degraded.
Table 2 summarizes the operational amplifiers that are
compatible with the MAX11163. The MAX9632 has
sufficient bandwidth, low enough noise and distortion
to support the full performance of the MAX11163. The
MAX9633 is a dual amplifier and can support buffering for
true pseudo-differential sampling.
The conversion results are accurate when the ADC
acquires the input signal for an interval longer than the
input signal's worst-case settling time. The ADC input
sampling capacitor charges during the acquisition period.
During this acquisition period, the settling of the sampled
voltage is affected by the source resistance and the input
sampling capacitance. Sampling error can be estimated
by modeling the time constant of the total input capacitance
and the driving source impedance.
Regardless of whether an external buffer amp is used or
not, the time constant, RSOURCE × CLOAD, of the input
should not exceed tACQ/12, where RSOURCE is the total
signal source impedance, CLOAD is the total capacitance
at the ADC input (external and internal) and tACQ is the
acquisition period. Thus to obtain accurate sampling in
a 1µs acquisition time a source impedance of less than
2.1kΩ should be used if driving the ADC directly. When
driving the ADC from a buffer, a series resistance (5Ω to
15Ω typical) is recommended between the amplifier and
the external input capacitance as shown in the Typical
Operating Circuit.
Transfer Function
The ideal transfer characteristic for the MAX11163 is
shown in Figure 3. The precise location of various points
on the transfer function are given in Table 3.
Table 2. List of Recommended ADC Driver Op Amps for MAX11163
INPUT-NOISE
DENSITY
(NV/√HZ)
SMALL-SIGNAL
BANDWIDTH
(MHZ)
SLEW RATE
(V/ΜS)
THD
(DB)
MAX9632
0.9
55
30
-128
3.9
MAX9633
3
27
18
-130
3.5/amp
AMPLIFIER
www.maximintegrated.com
ICC
(MA)
COMMENTS
Low noise, THD at 10kHz
Low noise, dual amp, THD at 10kHz
Maxim Integrated │ 14
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
ADCs, while the SDO output of one device feeds the SDI
input of the next device in the chain. The 3-wire interface
is simply the CNVST, SCLK, and SDO of the last ADC in
the chain.
The selection of CS or daisy-chain modes is controlled by
the SDI logic level during the rising edge of CNVST. The
CS mode is selected if SDI is high and the daisy-chain
mode is selected if SDI is low. If SDI and CNVST are
connected together, the daisy-chain mode is selected.
In each of the three modes described above (3-wire CS
mode, 4-wire CS mode, and daisy-chain mode), the user
must externally time out the maximum ADC conversion time
before commencing readback. Alternatively, the MAX11163
offers a busy indicator feature on SDO in each mode to
eliminate external timer circuits.
Figure 3. Unipolar Transfer Function
Digital Interface
The MAX11163 includes three digital inputs (CNVST,
SCLK, and SDI) and a single digital output (SDO). The
ADC can be configured for one of six interface modes,
allowing the device to support a wide variety of application
needs.
The 3-wire and 4-wire CS interface modes are compatible with
SPI, QSPI, digital hosts, and DSPs. The 3-wire interface
uses CNVST, SCLK, and SDO for minimal wiring complexity
and is ideally suited for isolated applications. The 4-wire
interface allows CNVST to be independent of output data
readback (SDI) affording the highest level of individual
device control. This configuration is useful for low jitter or
multichannel, simultaneously sampled applications.
The 3-wire daisy-chain mode is the easiest way to configure
a multichannel, simultaneous-sampling system. This system
is built by cascading multiple ADCs into a shift register
structure. The CNVST and SCLK inputs are common to all
When busy indication is enabled, SDO provides a busy
indicator bit to signal the end of conversion. One additional
SCLK is required to flush the SDO busy indication bit prior
to reading back the data. Busy indicator is enabled in CS
mode if CNVST or SDI is low when the ADC conversion
completes. In daisy-chain mode, the busy indicator is
selected based on the state of SCLK at the rising edge
of CNVST. If SCLK is high, the busy indicator is enabled;
otherwise, the busy indicator is not enabled.
The following sections provide specifics for each of the six
serial interface modes. Due to the possibility of performance
degradation, digital activity should only occur after conversion
is completed or limited to the first half of the conversion
phase. Having SCLK or SDI transitions near the sampling
instant can also corrupt the input sample accuracy.
Therefore, keep the digital inputs quiet for approximately
25ns before and 10ns after the rising edge of CNVST.
These times are denoted as tSSCKCNV and tHSCKCNV in
all subsequent timing diagrams.
In all interface modes, the data on SDO is valid on both
SCLK edges. However, input setup time into the receiving
host will be maximized when data is clocked into that host
on the falling SCLK edge. Doing so will allow for higher
data transfer rates between the MAX11163 and the receiving
host and consequently higher converter throughput.
Table 3. Transfer Function Example
CODE TRANSITION
UNIPOLAR INPUT (V)
DIGITAL OUTPUT CODE (HEX)
+FS - 1.5 LSB
4.999886
FFFE - FFFF
Midscale + 0.5 LSB
2.500038
8000 - 8001
Midscale
2.500000
8000
Midscale - 0.5 LSB
2.499962
7FFF - 8000
0.5 LSB
0.000038
0000 - 0001
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Maxim Integrated │ 15
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Shutdown
With SDI connected to OVDD, a rising edge on CNVST
completes the acquisition, initiates the conversion and
forces SDO to high impedance. The conversion continues
to completion irrespective of the state of CNVST, allowing
CNVST to be used as a select line for other devices on the
board. CNVST must be returned high before the minimum
conversion time and held high until the maximum conversion
time to avoid generating the busy signal indicator.
In all interface modes, the MAX11163 can be placed into a
shutdown state by holding SCLK high while pulling CNVST
from high to low. Supply current is reduced to less than
10µA on both VDD and OVDD supplies (see Figure 4). To
wake up from shutdown mode, hold SCLK low and pull
CNVST from high to low.
ADC Modes of Operation
When the conversion is complete, the MAX11163 enters
the acquisition phase. Drive CNVST low to output the
MSB onto SDO. The remaining data bits are then clocked
by subsequent SCLK falling edges. SDO returns to high
impedance after the 16th SCLK falling edge or when
CNVST goes high.
The MAX11163 six modes of operation are summarized in
Table 4. For each of the six modes of operation a typical
application model and list of benefits are described.
CS Mode 3-Wire, No-Busy Indicator
The 3-wire CS mode with no-busy indicator is ideally
suited for isolated applications that require minimal wiring
complexity. In Figure 5, a single ADC is connected to an
SPI-compatible digital host with corresponding timing given
in Figure 6.
CNVST
tSSCLKCNF
tSSCLKCNF
tHSCLKCNF
tHSCLKCNF
SCLK
INTERNAL
SHUTDOWN
SIGNAL
POWERED DOWN
POWERED UP
Figure 4. Entering and Exiting Shutdown Mode
CONVERT
DIGITAL HOST
CNVST
OVDD
SDI
MAX11163
SDO
DATA IN
SCLK
CLK
Figure 5. CS Mode 3-Wire, No-Busy Indicator Connection Diagram (SDI High)
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Maxim Integrated │ 16
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Figure 6. CS Mode 3-Wire, No-Busy Indicator Serial Interface Timing (SDI High)
Table 4. ADC Modes of Operation
MODE
TYPICAL APPLICATION AND BENEFITS
CS Mode 3-Wire, No-Busy Indicator
Single ADC connected to SPI-compatible digital host. Minimal wiring complexity; ideally
suited for isolated applications.
CS Mode 3-Wire, With Busy Indicator
Single ADC connected to SPI-compatible digital host with interrupt input. Minimal wiring
complexity; ideally suited for isolated applications.
CS Mode 4-Wire, No-Busy Indicator
Multiple ADCs connected to SPI-compatible digital host. CNVST used for acquisition and
conversion; ideally suited for low jitter applications and simultaneous sampling. SDI used
to control data readback.
CS Mode 4-Wire, With Busy Indicator
Single ADC connected to SPI-compatible digital host with interrupt input. CNVST used for
acquisition and conversion; ideally suited for low jitter applications.
Daisy-Chain Mode, No-Busy Indicator
Multiple ADCs connected to 3-wire serial interface. Minimal wiring complexity; ideally
suited for multichannel simultaneous sampled isolated applications.
Daisy-Chain Mode, With Busy Indicator
Multiple ADCs connected to 3-wire serial interface with busy indicator. Minimal wiring
complexity; ideally suited for multichannel simultaneous sampled isolated applications.
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Maxim Integrated │ 17
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
CONVERT
OVDD
10kΩ
CNVST
OVDD
SDI
MAX11163
SDO
SCLK
DIGITAL HOST
DATA IN
IRQ
CLK
Figure 7. CS Mode 3-Wire with Busy Indicator Connection Diagram (SDI High)
Figure 8. CS Mode 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
CS Mode 3-Wire, With Busy Indicator
The 3-wire CS mode with busy indicator is shown in Figure
7 where a single ADC is connected to an SPI-compatible
digital host with interrupt input. The corresponding timing is
given in Figure 8.
With SDI connected to OVDD, a rising edge on CNVST
completes the acquisition, initiates the conversion and
forces SDO to high impedance. The conversion continues
to completion irrespective of the state of CNVST allowing
CNVST to be used as a select line for other devices on the
board. CNVST must be returned low before the minimum
conversion time and held low until the busy signal is
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generated. When the conversion is complete, SDO
transitions from high impedance to a low logic level signaling
to the digital host through the interrupt input that data
readback can commence. The MAX11163 then enters the
acquisition phase. The data bits are clocked out, MSB first,
by subsequent SCLK falling edges. SDO returns to high
impedance after the 17th SCLK falling edge or when CNVST
goes high and is then pulled to OVDD through the external
pullup resistor.
Maxim Integrated │ 18
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
CS2
CS1
CONVERT
CNVST
SDI
MAX11163
CNVST
SDO
DIGITAL HOST
MAX11163
SDI
SCLK
SDO
SCLK
DATA IN
CLK
Figure 9. CS Mode 4-Wire, No-Busy Indicator Connection Diagram
tCYC
tCNVPW
tCNVPW
CNVST
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
tSSDICNV
SDI(CS2)
tSCLK
tSSCKCNV
tSCLKL
tHSCKCNV
SCLK
1
2
15
tDSDO
tEN
SDO
3
D15
D14
D13
16
17
tSCLKH
18
19
tDIS
tDIS
D1
D0
D15
32
31
tEN
D14
D13
D1
D0
MODE 4-WIRE, NO BUSY INDICATOR SERIAL INTERFACE TIMING
Figure 10. CS Mode 4-Wire, No-Busy Indicator CS
Serial
Interface Timing
CS Mode 4-Wire, No-Busy Indicator
The 4-wire CS mode with no-busy indicator is ideally suited
for multichannel applications. In this case, the CNVST pin
may be used for low-jitter simultaneous sampling while the
SDI pin(s) are used to control data readback. In Figure 9,
two ADCs are connected to an SPI-compatible digital host
with corresponding timing given in Figure 10.
With SDI high, a rising edge on CNVST completes the
acquisition, initiates the conversion, and forces SDO to
high impedance. This mode requires CNVST to be held
high during the conversion and data readback phases.
Note that if CNVST and SDI are low, SDO is driven low.
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During the conversion, the SDI pin(s) can be used as a
select line for other devices on the board, but must be
returned high before the minimum conversion time and
held high until the maximum conversion time to avoid
generating the busy signal indicator.
When the conversion is complete, the MAX11163 enters
the acquisition phase. ADC data is read by driving its
respective SDI line low, outputting the MSB onto SDO. The
remaining data bits are then clocked by subsequent SCLK
falling edges. SDO returns to high impedance after the
16th SCLK falling edge or when CNVST goes high.
Maxim Integrated │ 19
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
CS1
CONVERT
OVDD
10kΩ
CNVST
SDI
MAX11163
SDO
DIGITAL HOST
DATA IN
IRQ
SCLK
CLK
Figure 11. CS Mode 4-Wire with Busy Indicator Connection Diagram
tCYC
tCNVPW
CNVST
tACQ
tCONV
ACQUISITION
ACQUISITION
CONVERSION
tSSDICNV
tHSDICNV
SDI
tSCLK
tSSCKCNV
tSCLKL
tHSCKCNV
SCLK
1
2
3
BUSY BIT
D15
16
17
tSCLKH
tDSDO
SDO
15
tDIS
D14
D1
D0
Figure 12. CS Mode 4-Wire with Busy Indicator Serial Interface Timing
CS Mode 4-Wire, With Busy Indicator
The 4-wire CS mode with busy indicator is shown in Figure
11 where a single ADC is connected to an SPI-compatible
digital host with interrupt input. The corresponding timing
is given in Figure 12. This mode is ideally suited for single
ADC applications where the CNVST pin may be used for
low-jitter sampling while the SDI pin is used for data readback.
With SDI high, a rising edge on CNVST completes the
acquisition, initiates the conversion and forces SDO to high
impedance. This mode requires CNVST to be held high
during the conversion and data readback phases. Note
that if CNVST and SDI are low, SDO is driven low. During
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the conversion, the SDI pin can be used as a select line
for other devices on the board, but must be returned low
before the minimum conversion time and held low until the
busy signal is generated.
When the conversion is complete SDO transitions from
high impedance to a low logic level signaling to the digital
host through the interrupt input that data readback can
commence. The MAX11163 then enters the acquisition
phase. The data bits are clocked out, MSB first, by subsequent
SCLK falling edges. SDO returns to high impedance
after the 17th SCLK falling edge or when CNVST goes
high and is then pulled to OVDD through the external
pullup resistor.
Maxim Integrated │ 20
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
CONVERT
CNVST
SDI
MAX11163
DEVICE A
DIGITAL HOST
CNVST
SDOA
SDO
SDI
MAX11163
DEVICE B
SCLK
SDOB
SDO
DATA IN
SCLK
CLK
Figure 13. Daisy-Chain Mode, No-Busy Indicator Connection Diagram
tCYC
tCNVPW
CNVST
tACQ
tCONV
ACQUISITION
ACQUISITION
CONVERSION
tSCLK
tSSCKCNV
tHSCKCNV
SCLK
SDOA = SDIB
SDOB
tSCLKL
1
SELECT NO
BUSY
OUTPUT
SELECT
CHAIN MODE
2
3
tSSDISCK
DA15
15
14
tHSDISCK
DA14
16
17
18
DA15
DA14
30
31
32
DA1
DA0
tSCLKH
DA13
DA1
DA0
DB13
DB1
DB0
tDSDO
DB15
DB14
Figure 14. Daisy-Chain Mode, No-Busy Indicator Serial Interface Timing
Daisy-Chain Mode, No-Busy Indicator
The daisy-chain mode with no-busy indicator is ideally suited
for multichannel isolated applications that require minimal
wiring complexity. Simultaneous sampling of multiple ADC
channels is realized on a 3-wire serial interface where data
readback is analogous to clocking a shift register. In Figure
13, two ADCs are connected to an SPI-compatible digital
host with corresponding timing given in Figure 14.
The daisy-chain mode is engaged when the MAX11163
detects the low state on SDI at the rising edge of CNVST.
In this mode, CNVST is brought low and then high to trigger
the completion of the acquisition phase and the start of a
conversion. A low SCLK state on the rising edge of CNVST
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signals to the internal controller that the no-busy indicator
will be output. When in chain mode, the SDO output is
driven active at all times.
When SDI and CNVST are both low, SDO is driven low,
thus engaging the daisy-chain mode of operations on the
downstream MAX11163 parts. For example, in Figure 13
part A has its SDI tied low so the chain mode of operation will
be selected on every conversion. When CNVST goes
low to trigger another conversion, part A’s SDO and
consequently part B’s SDI go low as well. On the next
CNVST rising edge both parts A and B will select the daisychain mode interface.
Maxim Integrated │ 21
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
CONVERT
CNVST
SDI
MAX11163
DEVICE A
CNVST
SDOA
SDO
MAX11163
SDI
DEVICE B
SCLK
DIGITAL HOST
CNVST
SDOB
SDO
MAX11163
SDI
DEVICE C
SCLK
SDO
SDOC
DATA IN
IRQ
SCLK
CLK
Figure 15. Daisy-Chain Mode with Busy Indicator Connection Diagram
tCYC
tCNVPW
CNVST = SDIA
ACQUISITION
tSSCKCNV
tCONV
CONVERSION
SDOB = SDIC
SDOC
tSCLKH
1
SELECT
BUSY
MODE
SELECT
CHAIN
MODE
SELECT
CHAIN
MODE
ACQUISITION
tSCLK
tHSCKCNV
SCLK
SDOA = SDIB
tACQ
2
tSSDISCK
DA15
BUSY
BIT
tDSDOSDI
BUSY
BIT
DB15
15
4
3
16
DA14
DA13
17
18
19
31
32
33
34
35
47
48
49
tSCLKL
tHSDISCK
DA1
tDSDOSDI
DA0
tDSDO
DB14
DB13
tDSDOSDI
DB1
DB0
DA15
DA14
DA1
DA0
tDSDOSDI
BUSY DC15
BIT
tDSDOSDI
DC14
DC13
DC1
DC0
DB15
DB14
DB1
DB0
DA15
DA14
DA1
DA0
MODE WITH BUSY INDICATOR SERIAL INTERFACE TIMING
Figure 16. Daisy-Chain Mode with Busy IndicatorDAISY-CHAIN
Serial Interface
Timing
When a conversion is complete, the MSB is presented onto
SDO, and the MAX11163 returns to the acquisition phase.
The remaining data bits, stored within the internal shift
register, are clocked out on each subsequent SCLK falling
edge. The SDI input of each ADC in the chain is used to
transfer conversion data from the previous ADC into the
internal shift register of the next ADC, thus allowing for data
to be clocked through the multichip chain on each SCLK
falling edge. Each ADC in the chain outputs its MSB data
first requiring 16 × N clocks to read back N ADCs.
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 6ns digital host setup time and 3V interface, up to
four MAX11163 devices running at a conversion rate of
218ksps can be daisy-chained on a 3-wire port.
Daisy-Chain Mode, With Busy Indicator
The daisy-chain mode with busy indicator is shown in
Figure 15 where three ADCs are connected to an SPI-
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compatible digital host with corresponding timing given in
Figure 16.
The daisy-chain mode is engaged when the MAX11163
detects a low state on SDI at the rising edge of CNVST.
Additionally, SDI can be tied directly to CNVST to trigger
the chain interface mode. In this mode, CNVST is brought
low and then high to trigger the completion of the acquisition
phase and the start of a conversion. A high SCLK state on
the rising edge of CNVST signals to the internal controller
that the busy indicator will be outputted. When in daisychain mode, the SDO output is driven active at all times.
When SDI and CNVST are both low, SDO is driven low,
thus engaging the daisy-chain mode of operations on the
downstream MAX11163 parts. For example, in Figure 13,
part A has its SDI tied low so the daisy-chain mode of operation will be selected on every conversion. When CNVST
goes low to trigger another conversion, part A’s SDO and
consequently part B’s SDI go low as well. The same is true
on part C’s SDI input. Consequently, on the next CNVST
Maxim Integrated │ 22
MAX11163
rising edge all parts in the chain will select the daisy-chain
mode interface.
When a conversion is complete, the busy indicator is
presented onto each SDO, and the MAX11163 returns to
the acquisition phase. As each part completes its conversion, it
looks for a busy enable signal on its SDI pin from the earlier
part in the chain. When it sees a busy enable signal on its
input and its own conversion has completed, it enables its
busy output signal on SDO. Thus the busy enable signals
are propagated down the chain and the final busy enable
signal at the host indicates that all devices in the chain
have completed their conversion and all can be readout.
The conversion data bits are stored within the internal shift
register and clocked out on each subsequent SCLK falling
edge. The SDI input of each ADC in the chain is used to
transfer conversion data from the previous ADC into the
internal shift register of the next ADC, thus allowing for data
to be clocked through the multichip chain on each SCLK
falling edge. With busy indicator mode selected, the busy
bit from each part is not chained on the first falling SCLK
edge in the readout pattern. Consequently, the number of
falling SCLKs needed to read back all data from N ADCs is
16 × N + 1 falling edges.
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 6ns digital host setup time and 3V interface, up to
four MAX11163 devices running at a conversion rate of
217ksps can be daisy-chained on a 3-wire port.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines parallel
to one another (especially clock lines), and avoid running
digital lines underneath the ADC package. A single solid
GND plane configuration with digital signals routed from
one direction and analog signals from the other provides
the best performance. Connect the GND pin on the
MAX11163 to this ground plane. Keep the ground return to
the power supply low impedance and as short as possible
for noise-free operation.
A 4.7nF C0G (or NPO) ceramic capacitor should be
placed between AIN+ and the ground plane as close as
possible to the MAX11163. This capacitor reduces the
inductance seen by the sampling circuitry and reduces
the voltage transient seen by the input source circuit. If
AIN- is to be used for remote sense, put a matching 4.7nF
C0G ceramic capacitor as close to this pin as well to minimize
the effect to the inductance in the remote sense line.
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16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
For best performance, decouple the REF output to the
ground plane with a 16V, 10µF or larger ceramic capacitor
with a X5R or X7R dielectric in a 1210 or smaller case
size. Ensure that all bypass capacitors are connected
directly into the ground plane with an independent via.
Bypass VDD and OVDD to the ground plane with 0.1FF
ceramic capacitors on each pin as close as possible to
the device to minimize parasitic inductance. Add at least
one bulk 10FF decoupling capacitor to VDD and OVDD
per PCB. For best performance, bring a VDD power plane
from the analog interface side of the MAX11163 and a
OVDD power plane from the digital interface side of the
device.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than ±1 LSB guarantees no missing codes and a
monotonic transfer function.
Offset Error
For the MAX11163, the offset error is defined at code
center 0x0000. This code center should occur at 0V input
between AIN+ and AIN-. The offset error is the actual voltage
required to produce code center 0x0000, expressed in
LSB.
Gain Error
Gain error is defined as the difference between the actual
change in analog input voltage required to produce a top
code transition minus a bottom code transition, and the
ideal change in analog input voltage range to produce the
same code transitions. It is expressed in LSB.
Maxim Integrated │ 23
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Signal-to-Noise Ratio
Aperture Delay
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the fullscale analog input power to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization noise error only
and results directly from the ADC’s resolution (N bits):
Aperture delay (tAD) is the time delay from the sampling
clock edge to the instant when an actual sample is taken.
SNR = (6.02 x N + 1.76)dB
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
aperture delay.
Small-Signal Bandwidth
In reality, there are other noise sources besides quantization
noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the power signal to
the power noise, which includes all spectral components
not including the fundamental, the first five harmonics,
and the DC offset.
A small -20dBFS analog input signal is applied to an ADC
in a manner that ensures that the signal’s slew rate does
not limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased 3dB.
Signal-to-Noise Plus Distortion
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-power
input bandwidth frequency.
Signal to noise plus distortion (SINAD) is the ratio of RMS
amplitude of the fundamental input frequency to the RMS
equivalent of all the other ADC output signals.
SINAD(dB) = 20 × log
SignalRMS
Full-Power Bandwidth
(Noise + Distortion)RMS
Effective Number of Bits
The effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization
noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
ENOB =
SINAD − 1.76
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the power
contained in the first five harmonics of the converted data
to the power of the fundamental. This is expressed as:
P + P3 + P4 + P5
THD
= 10 × log 2
P
1
where P1 is the fundamental power and P2 through P5 is
the power of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
power of the fundamental (maximum signal component)
to the power of the next-largest frequency component.
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Maxim Integrated │ 24
MAX11163
16-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Selector Guide
PART
BITS
INPUT RANGE (V)
REFERENCE
PACKAGE
SPEED (ksps)
MAX11262
14
0 to 5
External
3mm x 5mm µMAX-10
500
MAX11160
16
0 to 5
Internal
3mm x 5mm µMAX-10
500
MAX11161
16
0 to 5
Internal
3mm x 5mm µMAX-10
250
MAX11162
16
0 to 5
External
3mm x 5mm µMAX-10
500
MAX11163
16
0 to 5
External
3mm x 5mm µMAX-10
250
MAX11164
16
0 to 5
Internal/External
3mm x 3mm TDFN-12
500
MAX11165
16
0 to 5
Internal/External
3mm x 3mm TDFN-12
250
MAX11166
16
±5
Internal/External
3mm x 3mm TDFN-12
500
MAX11167
16
±5
Internal/External
3mm x 3mm TDFN-12
250
MAX11168
16
±5
Internal
3mm x 5mm µMAX-10
500
MAX11169
16
±5
Internal
3mm x 5mm µMAX-10
250
MAX11150
18
0 to 5
Internal
3mm x 5mm µMAX-10
500
MAX11152
18
0 to 5
External
3mm x 5mm µMAX-10
500
MAX11154
18
0 to 5
Internal/External
3mm x 3mm TDFN-12
500
MAX11156
18
±5
Internal/External
3mm x 3mm TDFN-12
500
MAX11158
18
±5
Internal
3mm x 5mm µMAX-10
500
Ordering Information
PART
MAX11163EUB+
Package Information
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
10 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
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For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 µMAX
U10+2
21-0061
90-0330
Maxim Integrated │ 25
MAX11163
6-Bit, 250ksps, +5V Unipolar Input,
SAR ADC, in Tiny 10-Pin µMAX
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
10/13
Initial release
1
4/14
Updated Electrical Characteristics, THD equation, and Selector Guide
2
1/15
Updated Benefits and Features section
3
11/16
General updates, including updates to the Electrical Characteristics table, Selector
Guide, Typical Operating Characteristics section
DESCRIPTION
—
1, 25, 26
1
1–26
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 26
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