MAX11166ETC+T

EVALUATION KIT AVAILABLE MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN General Description Benefits and Features The MAX11166 16-bit, 500ksps, SAR ADC offers excellent AC and DC performance with true bipolar input range, small size, and internal reference. The MAX11166 measures a Q5V (10VP-P) input range while operating from a single 5V supply. A patented charge-pump architecture allows direct sampling of high-impedance sources. The MAX11166 integrates an optional internal reference and buffer, saving additional cost and space. ● Industrial Control Systems/Process Control ● High DC/AC Accuracy Improves Measurement Quality • 16-Bit Resolution with No Missing Codes • 500ksps Throughput Rates Without Pipeline Delay/ Latency • 92.9dB SNR and -103dB THD at 10kHz • 0.5 LSBRMS Transition Noise • ±0.2 LSB DNL (typ) and ±0.4 LSB INL (typ) ● Highly Integrated ADC Saves Cost and Space • ±6ppm/°C Internal Reference • Internal Reference Buffer • ±5V Bipolar Analog Input Range ● Wide Supply Range and Low Power Simplify Power Supply Design • 5V Analog Supply • 2.3V to 5V Digital Supply • 25.5mW Power Consumption at 500ksps • 10μA in Shutdown Mode ● Multi-Industry Standard Serial Interface and Small Package Reduce Size • SPI/QSPI™/MICROWIRE®/DSP-Compatible Serial Interface • 3mm x 3mm Tiny 12-Pin TDFN Package ● Medical Instrumentation QSPI is a trademark of Motorola, Inc. ● Automatic Test Equipment MICROWIRE is a registered trademark of National Semiconductor Corporation. Typical Operating Circuit Selector Guide and Ordering Information appear at end of data sheet. This ADC achieves 92.9dB SNR and -103dB THD. The MAX11166 guarantees 16-bit no-missing codes and Q0.4 LSB INL (typ). The MAX11166 communicates using an SPI-compatible serial interface at 2.5V, 3V, 3.3V, or 5V logic. The serial interface can be used to daisy-chain multiple ADCs in parallel for multichannel applications and provides a busy indicator option for simplified system synchronization and timing. The MAX11166 is offered in a 12-pin, 3mm x 3mm, TDFN package and is specified over the -40NC to +85NC temperature range. Applications ● Data Acquisition Systems VDD (5V) 1µF 1µF ±5V MAX9632 10Ω 14-Bit to 18-Bit SAR ADC Family VOVDD (2.3V TO 5V) AIN+ AIN- 4.7nF 16-BIT ADC INTERFACE AND CONTROL SCLK DIN DOUT CNVST HOST µC MAX11166 REF 10µF REF BUF AGNDS 19-7673; Rev 0; 7/15 INTERNAL REFERENCE GND REFIO 0.1µF ±5V Input Internal Reference 0 to 5V Input Internal Reference 0 to 5V Input External Reference 14-BIT 500ksps 16-BIT 250ksps 16-BIT 500ksps 18-BIT 500ksps — MAX11167 MAX11169 MAX11166 MAX11156 MAX11168 MAX11158 — MAX11161 MAX11165 MAX11160 MAX11150 MAX11164 MAX11154 MAX11262 MAX11163 MAX11162 MAX11152 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Absolute Maximum Ratings VDD to GND.............................................................-0.3V to +6V OVDD to GND........ -0.3V to the lower of (VDD + 0.3V) and +6V AIN+ to GND......................................................................... Q7V AIN-, REF, REFIO, AGNDS to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V SCLK, DIN, DOUT, CNVST to GND................ -0.3V to the lower of (VDD + 0.3V) and +6V Maximum Current into Any Pin...........................................50mA Continuous Power Dissipation (TA = +70NC) TDFN (derate 18.2mW/NC above +70NC)...................1349mW Operating Temperature Range............................ -40NC to +85NC Junction Temperature.......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................. +300NC Soldering Temperature (reflow)........................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TDFN Junction-to-Ambient Thermal Resistance (qJA).......59.3NC/W Junction-to-Case Thermal Resistance (qJC)............22.5NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V; Reference Mode 3, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT (Note 3) Input Voltage Range AIN+ to AIN-, K = Absolute Input Voltage Range Input Leakage Current 5.000 4.096 -K x VREF +K x VREF V AIN+ to GND -(VDD + 0.1) +(VDD + 0.1) V AIN- to GND -0.1 Acquisition phase -10 Input Capacitance +0.1 +0.001 +10 16 Input-Clamp Protection Current Both inputs -20 µA pF +20 mA DC ACCURACY (Note 4) Resolution N No Missing Codes Offset Error 16 Bits 16 Bits -7.5 Offset Temperature Coefficient ±0.8 +7.5 ±0.006 Gain Error -4.3 Gain Error Temperature Coefficient ±1.2 LSB LSB/°C +4.3 ±0.015 LSB LSB/°C Integral Nonlinearity INL TA = TMIN to TMAX -1.2 ±0.4 +1.2 LSB Differential Nonlinearity DNL Guaranteed by design -0.5 ±0.2 +0.5 LSB +8 LSB Positive Full-Scale Error www.maximintegrated.com -8 Maxim Integrated │  2 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V; Reference Mode 3, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS Negative Full-Scale Error Analog Input CMRR Power-Supply Rejection (Note 5) MIN TYP -8 MAX +8 UNITS LSB CMRR -1.1 LSB/V PSR -4.5 LSB/V 0.5 LSBRMS Transition Noise REFERENCE (Note 7) REF Output Initial Accuracy VREF Reference mode 0 REF Output Temperature Coefficient TCREF Reference mode 0 REFIO Output Initial Accuracy VREFIO Reference modes 0 and 2 TCREFIO Reference modes 0 and 2 REFIO Output Temperature Coefficient 4.092 4.092 REFIO Output Impedance Reference modes 0 and 2 REFIO Input Voltage Range Reference mode 1 3.00 Reference Buffer Initial Offset Reference modes 0 and 1 -500 Reference Buffer Temperature Coefficient Reference modes 0 and 1 Required for reference modes 0 and 1, recommended for reference modes 2 and 3 10 REF Voltage Input Range VREF Reference modes 2 and 3 2.5 IREF V ±7.5 ±17 ppm/°C 4.096 4.100 V ±6 ±15 ppm/°C 4.096 ±6 CEXT REF Load Current 4.100 10 External Compensation Capacitor REF Input Capacitance 4.096 kΩ 4.25 V +500 µV ±10 µV/°C µF 4.25 V Reference modes 2 and 3 20 pF VREF = 4.096V, reference modes 2 and 3 146 µA AC ACCURACY (Note 6) VREF = 4.096V, reference mode 3 Signal-to-Noise Ratio (Note 7) SNR fIN = 10kHz Spurious-Free Dynamic Range SINAD SFDR fIN = 10kHz 92.9 VREF = 4.096V, reference mode 1 92.8 VREF = 2.5V, reference mode 3 89.8 Internal reference, reference mode 0 92.9 VREF = 4.096V, reference mode 3 Signal-to-Noise Plus Distortion (Note 7) 91.8 dB 91.1 92.1 VREF = 4.096V, reference mode 1 92.1 VREF = 2.5V, reference mode 3 89.3 Internal reference, reference mode 0 92.3 dB 99.0 -104.3 Total Harmonic Distortion THD -103.0 Intermodulation Distortion (Note 8) IMD -119.7 www.maximintegrated.com dB -97.5 dB dB Maxim Integrated │  3 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V; Reference Mode 3, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 500 ksps 400 ns SAMPLING DYNAMICS Throughput Sample Rate 0.01 Transient Response Full-scale step -3dB point Full-Power Bandwidth 6 -0.1dB point MHz > 0.2 Aperture Delay 2.5 ns Aperture Jitter < 50 psRMS POWER SUPPLIES Analog Supply Voltage Interface Supply Voltage Analog Supply Current VDD 4.75 VOVDD IVDD 2.3 IOVDD 5.25 V 5.0 6.0 7.0 Reference mode = 2, 3 3.0 3.5 4.0 6.1 10 VOVDD = 2.3V 1.5 2.0 VOVDD = 5.25V 4.3 5.0 0.9 10 OVDD Shutdown Current Power Dissipation V Reference mode = 0, 1 VDD Shutdown Current Interface Supply Current 5.25 VDD = 5V, VOVDD = 3.3V, reference mode = 2, 3 25.5 VDD = 5V, VOVDD = 3.3V, reference mode = 0, 1 37.5 mA µA mA µA mW DIGITAL INPUTS (DIN, SCLK, CNVST) Input Voltage High VIH Input Voltage Low VIL Input Hysteresis 0.7 x VOVDD V 0.3 x VOVDD V VHYS ±0.05 x VOVDD V Input Capacitance CIN 10 pF Input Current IIN VIN = 0V or VOVDD -10 +10 µA DIGITAL OUTPUT (DOUT) Output Voltage High VOH ISOURCE = 2mA Output Voltage Low VOL ISINK = 2mA Three-State Leakage Current Three-State Output Capacitance www.maximintegrated.com VOVDD - 0.4 V -10 15 0.4 V +10 µA pF Maxim Integrated │  4 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V; Reference Mode 3, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2 100000 µs CNVST rising to data available 1.35 1.5 µs tACQ = tCYC - tCONV 0.5 µs CS mode 5 ns VOVDD > 4.5V 14 VOVDD > 2.7V 20 VOVDD > 2.3V 26 VOVDD > 4.5V 16 VOVDD > 2.7V 24 VOVDD > 2.3V 30 TIMING (Note 9) Time Between Conversions tCYC Conversion Time tCONV Acquisition Time tACQ CNVST Pulse Width SCLK Period (CS Mode) tCNVPW tSCLK SCLK Period (Daisy-Chain Mode) tSCLK SCLK Low Time tSCLKL SCLK High Time tSCLKH SCLK Falling Edge to Data Valid Delay tDDO CNVST Low to DOUT D15 MSB Valid (CS Mode) tEN CNVST High or Last SCLK Falling Edge to DOUT High Impedance tDIS ns ns 5 ns 5 ns VOVDD > 4.5V 12 VOVDD > 2.7V 18 VOVDD > 2.3V 23 VOVDD > 2.7V 14 VOVDD < 2.7V 17 CS Mode 20 VOVDD > 4.5V 3 VOVDD > 2.7V 5 VOVDD > 2.3V 6 ns ns ns DIN Valid Setup Time from SCLK Falling Edge tSDINSCK DIN Valid Hold Time from SCLK Falling Edge tHDINSCK 0 ns SCLK Valid Setup Time to CNVST Falling Edge tSSCKCNF 3 ns SCLK Valid Hold Time to CNVST Falling Edge tHSCKCNF 6 ns ns Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C. Limits over the operating temperature range are guaranteed by design and device characterization. Note 3: See the Analog Inputs and Overvoltage Input Clamps sections. Note 4: Static Performance limits are guaranteed by design and device characterization. For definitions, see the Definitions section. Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the VDD supply voltage. Note 6: 10kHz sine wave input, -0.1dB below full scale. Note 7: See Table 4 for definition of the reference modes. Note 8: fIN1 ~ 9.4kHz, fIN2 ~ 10.7kHz, Each tone at -6.1dB below full scale. Note 9: CLOAD = 65pF on DOUT. www.maximintegrated.com Maxim Integrated │  5 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (VDD = 5.0V, VOVDD = 3.3V, fSAMPLE = 500ksps; Reference Mode 3, TA = +25°C, unless otherwise noted.) OFFSET AND GAIN ERROR vs. TEMPERATURE 4 Offset Error Gain Error AVERAGE OF 128 DEVICES 2 1 1 0 -1 -3 -3 10 35 TEMPERATURE (°C) 60 -4 85 5.15 5.25 toc04 SINGLE DEVICE 1.0 0.5 INL (LSB) 0.2 0.0 -0.2 -0.4 0.0 -0.5 -1.0 -0.6 -1.5 -0.8 1 INL (LSB) 0.5 0.0 -1 -1.0 -2 -1.5 -3 35 TEMPERATURE (°C) www.maximintegrated.com 60 85 toc06 AVERAGE OF 128 DEVICES MIN INL 0 -0.5 10 MAX INL 3 2 -15 65536 4 1.0 -40 57344 INL vs. TEMPERATURE toc05 AVERAGE OF 128 DEVICES MIN DNL 49152 1.5 40960 MAX DNL 32768 OUTPUT CODE (DECIMAL) DNL vs. TEMPERATURE 2.0 24576 16384 8192 0 65536 57344 49152 40960 32768 24576 16384 8192 0 -2.0 OUTPUT CODE (DECIMAL) DNL (LSB) 5.05 1.5 0.4 -2.0 4.95 2.0 0.6 DNL (LSB) 4.85 INTEGRAL NONLINEARITY vs. CODE toc03 SINGLE DEVICE 0.8 -1.0 4.75 VDD (V) DIFFERENTIAL NONLINEARITY vs. CODE 1.0 Gain Error -1 -2 -15 toc02 AVERAGE OF 128 DEVICES 0 -2 -40 Offset Error 3 2 -4 OFFSET AND GAIN ERROR vs. VDD SUPPLY VOLTAGE 4 ERROR (LSB) ERROR (LSB) 3 toc01 -4 -40 -15 10 35 TEMPERATURE (°C) 60 85 Maxim Integrated │  6 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5.0V, VOVDD = 3.3V, fSAMPLE = 500ksps; Reference Mode 3, TA = +25°C, unless otherwise noted.) DNL vs. VDD SUPPLY VOLTAGE 2.0 MAX DNL AVERAGE OF 128 DEVICES MIN DNL 2 0.5 1 0.0 -1 -1.0 -2 -1.5 -3 4.85 4.95 5.05 5.15 -4 5.25 AVERAGE OF 128 DEVICES MIN INL 4.75 4.85 4.95 VDD (V) OUTPUT NOISE HISTOGRAM NO AVERAGE 28000 NUMBER OF OCCURRENCES 16000 12000 8000 8000 INITIAL ERROR VOLTAGE ON REF PIN 60 50 3 5 6 7 4.098 8 9 10 4.096 11 12 4.094 13 14 4.092 15 30 20 10 4.0990 4.0985 4.0980 4.0975 4.0970 4.0965 4.0960 4.0955 4.0950 4.0945 4.0940 0 4.0935 85 40 4.0930 60 NUMBER OF OCCURRENCES 4 4.100 toc12 303 Devices Mean = 4096.0mV STDEV = 1.2mV STDEV = 282ppm 2 4.102 VREF (V) 32774 32773 32772 32771 32770 15 DEVICES www.maximintegrated.com 32769 toc11 1 TEMPERATURE (°C) 32768 OUTPUT CODE (DECIMAL) INTERNAL REFERENCE VOLTAGE (REF PIN) vs. TEMPERATURE 35 32767 OUTPUT CODE (DECIMAL) 32766 32765 32764 32763 32762 32774 32773 32772 32771 32770 32769 32768 32767 32766 32765 32764 32763 32762 0 10 toc10 SINGLE DEVICE STDEV = 0.23 LSBRMS 12000 0 -15 5.25 16000 4000 -40 5.15 20000 4000 4.090 5.05 24000 20000 4.104 VDD (V) OUTPUT NOISE HISTOGRAM WITH 4 SAMPLE AVERAGE 28000 SINGLE DEVICE STDEV = 0.45 LSBRMS 24000 NUMBER OF OCCURRENCES toc09 toc08 0 -0.5 4.75 MAX INL 3 1.0 -2.0 INL vs. VDD SUPPLY VOLTAGE 4 INL (LSB) DNL (LSB) 1.5 toc07 REF PIN VOLTAGE (V) Maxim Integrated │  7 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5.0V, VOVDD = 3.3V, fSAMPLE = 500ksps; Reference Mode 3, TA = +25°C, unless otherwise noted.) REF PIN THERMAL DRIFT SLOPE 70 60 4.0962 4.0961 40 30 4.0960 4.0959 4.0958 20 4.0957 4.0956 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 THERMAL DRIFT (ppm/°C) 6 8 10 4.0955 12 0 NSAMPLE = 4096 fIN = 10101 Hz VIN = -0.1dBFS SNR = 92.7dB SINAD = 92.4dB SFDR = 107.4dB THD = -104.4dB -40 MAGNITUDE (dB) -60 -80 -120 -120 100 150 200 -140 250 6.0 7.0 8.0 9.0 SINAD and ENOB vs. FREQUENCY SINAD toc17 90 14.5 88 SFDR AND -THD (dB) 15.0 ENOB (bits) SINAD (dB) 92 www.maximintegrated.com FREQUENCY (kHz) 12.0 13.0 14.0 10.0 14.0 100.0 toc18 SFDR THD 110 105 100 95 90 VIN = -0.1dBFS AVERAGE OF 128 DEVICES 85 1.0 11.0 115 15.5 0.1 10.0 120 94 86 toc16 SFDR and -THD vs. FREQUENCY 125 16.0 VIN = -0.1dBFS AVERAGE OF 128 DEVICES ENOB 96 5.25 FREQUENCY (kHz) FREQUENCY (kHz) 98 5.15 -80 -100 50 5.05 -60 -100 0 4.95 NSAMPLE = 16384 fIN1 = 9368.9Hz VIN1 = -6.1dBFS fIN2 = 10651Hz VIN2 = -6.1dBFS Single Device IMD = -119.7dBFS -20 Ref Mode = 3 -40 4.85 TWO TONES IMD toc15 -20 4.75 VDD (V) FFT PLOT 0 -140 toc14 AVERAGE OF 200 DEVICES 4.0963 10 MAGNITUDE (dB) REF 4.0964 50 0 INTERNAL REFERENCE VOLTAGES vs. VDD VOLTAGE 4.0965 303 Devices Mean = 2.1ppm/°C STDEV = 1.9ppm/°C VREF (V) NUMBER OF OCCURRENCES 25°C to -40°C 25°C to +85°C 303 Devices Mean = -7.3ppm/°C STDEV = 1.9ppm/°C toc13 80 0.1 1.0 10.0 100.0 FREQUENCY (kHz) Maxim Integrated │  8 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5.0V, VOVDD = 3.3V, fSAMPLE = 500ksps; Reference Mode 3, TA = +25°C, unless otherwise noted.) SNR and SINAD vs. TEMPERATURE 98 SINAD SFDR AND -THD (dB) SNR AND SINAD (dB) 92 90 -15 SFDR 105 100 95 90 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES -40 THD 110 94 88 toc20 115 SNR 96 86 SFDR and THD vs. TEMPERATURE toc19 10 35 60 85 85 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES -40 -15 10 SNR and SINAD vs. VDD SUPPLY VOLTAGE 98 SINAD toc22 THD SFDR 104.0 102.0 92 100.0 90 88 98.0 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES 4.75 4.85 4.95 5.05 5.15 5.25 96.0 fIN = 10kHz VIN = -0.1dBFS AVERAGE OF 128 DEVICES 4.75 4.85 4.95 VDD (V) 5.15 PSR vs. VDD SUPPLY FREQUENCY toc23 -20 VAIN+ = VAIN- = ±100mV SINGLE DEVICE -40 5.05 5.25 VDD (V) CMR vs. INPUT FREQUENCY -30 toc24 VVDD= 5.0 ± 250mV VOVDD = 3.3V SINGLE DEVICE -30 -50 -40 PSR (dB) CMR (dB) 85 THD AND SFDR vs. VDD SUPPLY VOLTAGE 108.0 106.0 94 -60 -50 -70 -60 -80 -70 -90 60 SFDR AND -THD (dB) SNR AND SINAD (dB) toc21 SNR 96 86 35 TEMPERATURE (°C) TEMPERATURE (°C) 0.1 1.0 10.0 FREQUENCY (kHz) www.maximintegrated.com 100.0 1000.0 -80 0.1 1.0 10.0 100.0 1000.0 FREQUENCY (kHz) Maxim Integrated │  9 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Typical Operating Characteristics (continued) (VDD = 5.0V, VOVDD = 3.3V, fSAMPLE = 500ksps; Reference Mode 3, TA = +25°C, unless otherwise noted.) VDD SUPPLY CURRENT vs. TEMPERATURE 8 Ref Mode 0 & 1 5 IOVDD (mA) 5 toc26 CDOUT = 65pF AVERAGE OF 128 DEVICES 10ksps 4 6 IVDD (mA) 500ksps AVERAGE OF 128 DEVICES Ref Mode 2 & 3 7 toc25 OVDD SUPPLY CURRENT vs. TEMPERATURE 3 2 4 1 3 2 -40 -15 10 35 TEMPERATURE (°C) 60 6 Ref Mode 2 & 3 60 85 toc28 CDOUT = 65pF AVERAGE OF 128 DEVICES 10ksps 5 IOVDD (mA) IVDD (mA) 35 4 5 3 4 2 3 1 4.75 4.85 4.95 VDD (V) 5.05 5.15 VDD AND OVDD SHUTDOWN CURRENT vs. TEMPERATURE 10 0 5.25 toc29 SHUTDOWN CURRENT (µA) 4 2 www.maximintegrated.com 10 35 TEMPERATURE (°C) 60 3.75 VOVDD (V) 85 4.25 4.75 5.25 toc30 AVERAGE OF 128 DEVICES IOVDD 8 6 -15 3.25 VDD AND OVDD SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 10 IOVDD -40 2.75 IVDD 8 0 2.25 IVDD AVERAGE OF 128 DEVICES SHUTDOWN CURRENT (µA) 10 500ksps AVERAGE OF 128 DEVICES 6 2 -15 OVDD SUPPLY CURRENT vs. OVDD SUPPLY VOLTAGE toc27 8 7 -40 TEMPERATURE (°C) VDD SUPPLY CURRENT vs. VDD SUPPLY VOLTAGE Ref Mode 0 & 1 0 85 6 4 2 0 2.25 2.75 3.25 3.75 VDD or VOVDD (V) 4.25 4.75 5.25 Maxim Integrated │  10 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Pin Configuration TOP VIEW REF 2 VDD 3 AIN+ 4 AIN- 5 GND 6 12 AGNDS + REFIO 1 MAX11166 EP 11 OVDD 10 DIN 9 SCLK 8 DOUT 7 CNVST TDFN Pin Description PIN NAME I/O FUNCTION 1 REFIO I/O External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGNDS. 2 REF I/O External Reference Input/Reference Buffer Decoupling. Bypass to AGNDS in close proximity with a X5R or X7R 10µF 16V capacitor. See the Layout, Grounding, and Bypassing section. 3 VDD I Analog Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF per PCB. 4 AIN+ I Positive Analog Input 5 AIN- I Negative Analog Input. Connect AIN- to the analog ground plane or to a remote-sense ground. 6 GND I Power-Supply Ground 7 CNVST I Convert Start Input. The rising edge of CNVST initiates conversions. The falling edge of CNVST with SCLK high enables the serial interface. 8 DOUT O Serial Data Output. DOUT will change stated on the falling edge of SCLK. 9 SCLK I Serial Clock Input. Clocks data out of the serial interface when the device is selected. 10 DIN I Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 11 OVDD I Digital Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF per PCB. 12 AGNDS I Analog Ground Sense. Zero current reference for the on-board DAC and reference source. Reference for REFIO and REF. — EP — www.maximintegrated.com Exposed Pad. Connect to PCB GND. Maxim Integrated │  11 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Functional Diagram DIN AIN+ AIN- INTERFACE AND CONTROL 16-BIT ADC MAX11166 AGNDS SCLK DOUT CNVST CONFIGURATION REGISTER CONFIGURATION REGISTER VDD OVDD SW2 SW1 INTERNAL REFERENCE 10kΩ REF BUF GND REF B5 0 0 1 1 B4 0 1 0 1 REFERENCE MODE 0 1 2 3 REFERENCE SWITCH STATE SW2 CLOSED CLOSED OPEN OPEN SW1 CLOSED OPEN CLOSED OPEN REFIO Detailed Description The MAX11166 is a 16-bit single-channel, pseudodifferential ADC with maximum throughput rates of 500ksps/250ksps. This ADC includes a precision internal reference that allows for measuring a bipolar input voltage range of Q5V. Input ranges of ±3.05V to ±5.19V can be obtained by applying an external reference. Both inputs (AIN+ and AIN-) are sampled with a pseudo-differential on-chip track-and-hold. The MAX11166 measures a true bipolar voltage of Q5V (10VP-P) and the inputs are protected for up to Q20mA of overrange current. This ADC is powered from a 4.75V to 5.25V analog supply (VDD) and a separate 2.3V to 5.25V digital supply (OVDD). The MAX11166 requires 500ns to acquire the input sample on an internal track-and-hold and then convert the sampled signal to 16 bits of accuracy using an internally clocked converter. Analog Inputs The MAX11166 can thus convert input signals on AIN+ in the range of -(K O VREF + AIN-) to +(K O VREF + AIN-) where K = 5.000/4.096. AIN+ should also be limited to ±(VDD + 0.1V) for accurate conversions. AIN- has an input range of -0.1V to +0.1V and should be connected to the ground reference of the input signal source. The MAX11166 performs a true differential sampling on inputs between AIN+ and AIN- with good common-mode rejection (see the Typical Operating Circuit). This allows for improved sampling of remote transducer inputs. Many traditional ADCs with single supplies that measure bipolar input signals use resistive divider networks directly on the analog inputs. These networks increase the complexity of the input signal conditioning. However, the MAX11166 includes a patented input switch architecture that allows direct sampling of high-impedance sources. This architecture requires a minimum sample rate of 10Hz to maintain accurate conversions over the designed temperature and supply ranges. The MAX11166 ADC consists of a true sampling pseudodifferential input stage with high-impedance, capacitive inputs. The internal T/H circuitry feature a small-signal bandwidth of about 6MHz to provide 16-bit accurate sampling in 500ns. This allows for accurate sampling of a number of scanned channels through an external multiplexer. www.maximintegrated.com Maxim Integrated │  12 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Overvoltage Input Clamps The MAX11166 includes an input clamping circuit that activates when the input voltage at AIN+ is above (VDD + 300mV) or below -(VDD + 300mV). The clamp circuit remains high impedance while the input signal is within the range of Q(VDD + 100mV) and draws little to no current. However, when the input signal exceeds this range the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of Q(VDD + 100mV). To make use of the input clamps, connect a resistor (RS) between the AIN+ input and the voltage source to limit the voltage at the analog input and to ensure the fault current into the devices does not exceed Q20mA. Note that the voltage at the AIN+ input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: RS = VFAULT MAX − 7V 20mA where VFAULTMAX is the maximum voltage that the source produces during a fault condition. Figure 1 and Figure 2 illustrate the clamp circuit voltage current characteristics for a source impedance RS = 1280I. While the input voltage is within the Q(VDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. Internal/External Reference (REFIO) Configuration The MAX11166 includes a standard SPI interface that selects internal or external reference modes of operation through an input configuration register (see the Input Configuration Interface section). The MAX11166 features an internal bandgap reference circuit (VREFIO = 4.096V) that is buffered with an internal reference buffer that drives the REF pin. The MAX11166 configure register allows four combinations of reference configuration. These reference mode are: Reference Mode 00: ADC reference is provided by the internal bandgap feed out the REFIO pin, noise filtered with an external capacitor on the REFIO pin, then buffered by the internal reference buffer and decoupled with an external capacitor on the REF pin. In this mode the ADC requires no external reference source. Reference Mode 01: ADC reference is provided externally and feeds into the REFIO pin, buffered with the internal reference buffer and decoupled with an external capacitor on the REF pin. This mode is typically used when a common reference source is needed for more than one MAX11166. Reference Mode 10: The internal bandgap is used as a reference source output and feed out the REFIO pin. However, the internal reference buffer is in a shutdown state and the REF pin is high impedance. This state would typically be used to provide a common reference source to a set of external reference buffers for several MAX11166. MAX11166 INPUT CLAMP CHARACTERISTICS 25 25 AIN+ PIN 20 MAX11166 INPUT CLAMP CHARACTERISTICS INPUT SOURCE AIN+ PIN INPUT SOURCE 15 15 ICLAMP (mA) ICLAMP (mA) 10 5 0 -5 5 -5 -10 -15 -25 -15 RS = 1280I VDD = 5.0V -20 -40 -30 -20 -10 0 10 20 30 40 SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V) Figure 1. Input Clamp Characteristics www.maximintegrated.com -25 RS = 1280I VDD = 5.0V -10 -5 0 5 10 SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V) Figure 2. Input Clamp Characteristics (Zoom In) Maxim Integrated │  13 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Reference Mode 11: The internal bandgap reference source as well as the internal reference buffer are both in a shutdown state. The REF pin is in a high-impedance state. This mode would typically be used when an external reference source and external reference buffer is used to drive all MAX11166 parts in a system. Regardless of the reference mode used, the MAX11166 requires a low-impedance reference source on the REF pin to support 16-bit accuracy. When using the internal reference buffer, externally bypass the reference buffer output using at least a 10FF, low-inductance, low-ESR capacitor placed as close as possible to the REF pin, thus minimizing additional PCB inductance. When using the internal bandgap reference source, bypass the REFIO pin with a 0.1FF capacitor to ground. If providing an external reference and using the internal reference buffer, drive the REFIO pin directly with an external reference source in the range of 3.0V to 4.25V. Finally, if disabling the MAX11166 internal bandgap reference source and internal reference buffer, drive the REF pin with a reference voltage in the range of 2.5V to 4.25V and place at least a 10FF, low-inductance, low-ESR capacitor placed as close as possible to the REF pin . When using the MAX11166 in external reference mode, it is recommended that an external reference buffer be used. For bypass capacitors on the REF pin, X7R or X5R ceramic capacitors in a 1210 case size or smaller have been found to provide adequate bypass performance. Y5U or Z5U ceramics capacitors are not recommended due to their high voltage and temperature coefficients. Maxim Integrated offers a wide range of precision references ideal for 16-bit accuracy. Table 1 lists some of the options recommended. Input Amplifier The conversion results are accurate when the ADC acquires the input signal for an interval longer than the input signal's worst-case settling time. The ADC input sampling capacitor charges during the acquisition period. During this acquisition period, the settling of the sampled voltage is affected by the source resistance and the input sampling capacitance. Sampling error can be estimated by modeling the time constant of the total input capacitance and the driving source impedance. Although the MAX11166 is easy to drive, an amplifier buffer is recommended if the source impedance is such that when driving a switch capacitor of ~20pF a significant settling error in the desired sampling period will occur. If this is the case, it is recommended that a configuration shown in the Typical Operating Circuit is used where at least a 500pF capacitor is attached to the AIN+ pin. This capacitance reduces the size of the transient at the start of the acquisition period, which in some buffers will cause an input signal dependent offsets. Regardless of whether an external buffer amp is used or not, the time constant, RSOURCE × CLOAD, of the input should not exceed tACQ/12, where RSOURCE is the total signal source impedance, CLOAD is the total capacitance at the ADC input (external and internal) and tACQ is the acquisition period. Thus to obtain accurate sampling in a 500ns acquisition time a source impedance of less than 1042Ω should be used if driving the ADC directly. When driving the ADC from a buffer, it is recommended a series resistance (5Ω to 50Ω typical) between the amplifier and the external input capacitance as shown in the Typical Operating Circuit. 1) Fast settling time: For multichannel multiplexed applications the driving operational amplifier must be able to settle to 16-bit resolution when a full-scale step is applied during the minimum acquisition time. 2) Low noise: It is important to ensure that the driver amplifier has a low average noise density appropriate for the desired bandwidth of the application. When the MAX11166 is used with its full bandwidth of 6MHz, it is preferable to use an amplifier that will produce an output noise spectral density of less than 6nV/√Hz, to ensure that the overall SNR is not degraded significantly. It is recommended to insert an external RC filter Table 1. MAX11166 External Reference Recommendations PART VOUT (V) TEMPERATURE COEFFICIENT (MAX) INITIAL ACCURACY (%) NOISE (0.1Hz TO 10Hz) (µVP-P) PACKAGE MAX6126 2.5, 3, 4.096, 5.0 3 (A), 5 (B) 0.06 1.35 µMAX-8 SO-8 MAX6325 MAX6341 MAX6350 2.5, 4.096, 5.0 1 0.04, 0.02 1.5, 2.4, 3.0 SO-8 www.maximintegrated.com Maxim Integrated │  14 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Transfer Function at the MAX11166 AIN+ input to attenuate out-of-band input noise and preserve the ADCs SNR. The effective RMS noise at the MAX11166 AIN+ input is 64FV, thus additional noise from a buffer circuit should be significantly lower in order to achieve the maximum SNR performance. The ideal transfer characteristic for the MAX11166 is shown in Figure 3. The precise location of various points on the transfer function are given in Table 3. 3) THD performance: The input buffer amplifier used should have a comparable THD performance with that of the MAX11166 to ensure the THD of the digitized signal is not degraded. FFFF FFFE OUTPUTCODE (hex) Table 2 summarizes the operational amplifiers that are compatible with the MAX11166. The MAX9632 has sufficient bandwidth, low enough noise and distortion to support the full performance of the MAX11166. The MAX9633 is a dual amp and can support buffering for true pseudodifferential sampling. 8001 5 x VREF 4.096 -5 x VREF -FS = 4.096 +FS = LSB = FULL-SCALE TRANSITION +FS - (-FS) 65536 8000 7FFF 7FFE 0001 0000 -FS -FS + 0.5 × LSB 0 +FS - 1.5 × LSB -FS INPUT VOLTAGE (LSB) Figure 3. Bipolar Transfer Function Table 2. List of Recommended ADC Driver Op Amps for MAX11166 INPUT-NOISE DENSITY (nV/√Hz) SMALL-SIGNAL BANDWIDTH (MHz) SLEW RATE (V/µs) THD (dB) MAX9632 0.9 55 30 -128 3.9 MAX9633 3 27 18 -130 3.5/amp AMPLIFIER ICC (mA) COMMENTS Low noise, THD at 10kHz Low noise, dual amp, THD at 10kHz Table 3. Transfer Function Example CODE TRANSITION BIPOLAR INPUT (V) DIGITAL OUTPUT CODE (HEX) +FS - 1.5 LSB +4.999771 FFFE - FFFF Midscale + 0.5 LSB +0.000076 8000 - 8001 Midscale 0 8000 Midscale - 0.5 LSB -0.000076 7FFF - 8000 -FS + 0.5 LSB -4.999924 0000 - 0001 www.maximintegrated.com Maxim Integrated │  15 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Input Configuration Interface Configuring in CS Mode An SPI interface clocked at up to 50MHz controls the MAX11166. Input configuration data is clocked into the configuration register on the falling edge of SCLK through the DIN pin. The data on DIN is used to program the ADC configuration register. The construct of this register is illustrated in Table 4. The configuration register defines the output interface mode, the reference mode, and the power-down state of the MAX11166. Figure 4 details the timing for loading the input configuration register when the MAX11166 is connected in CS mode (see Figure 6 and Figure 8 for hardware connections). The load process is enabled on the falling edge of CNVST when SCLK is held high. The configuration data is clocked into the configuration register through DIN on the next 8 SCLK falling edges. Pull CNVST high to complete the input configuration register load process. DIN should idle high outside an input configuration register read. Table 4. ADC Configuration Register BIT NAME MODE REF BIT DEFAULT STATE 7:6 LOGIC STATE 00 5:4 00 CS Mode, No-Busy Indicator 01 CS Mode, with Busy Indicator 10 Daisy-Chain Mode, No-Busy Indicator 11 Daisy-Chain Mode, with Busy Indicator 00 Reference Mode 0. Internal reference and reference buffer are both powered on. 01 Reference Mode 1. Internal reference is turned off, but internal reference buffer powered on. Apply the external reference voltage at REFIO. 10 Reference Mode 2. Internal reference is powered on, but the internal reference buffer is powered off. This mode allows for internal reference to be used with an external reference buffer. 11 Reference Mode 3. Internal reference and reference buffer are both powered off. Apply an external reference voltage at REF. 0 Normal Mode. All circuitry is fully powered up at all times. 1 Static Shutdown. All circuitry is powered down. 0 Reserved, Set to 0 00 SHDN 3 0 Reserved 2:0 0 FUNCTION CNVST tHSCKCNF tSSCKCNF SCLK 0 1 2 3 tHDINSCK DIN B7 4 5 6 7 B2 B1 B0 tSDINSCK B6 B5 B4 B3 Figure 4. Input Configuration Timing in CS Mode www.maximintegrated.com Maxim Integrated │  16 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN CNVST tHSCKCNF tSSCKCNF SCLK 0 1 2 3 4 tSDINSCK DIN 5 6 7 0 1 2 3 4 5 6 7 B0 B7 B6 B5 B4 B3 B2 B1 B0 tHDINSCK B7 B6 B5 B4 B3 B2 DATA LOADED TO PART B SHIFTED THROUGH PART A B1 DATA LOADED TO PART A Figure 5. Input Configuration Timing in Daisy-Chain Mode Configuring in Daisy-Chain Mode Output Interface Figure 5 details the configuration register load process when the MAX11166 is connected in a daisy-chain configuration (see Figure 12 and Figure 14 for hardware connections). The load process is enabled on the falling edge of CNVST when SCLK is held high. In daisy-chain mode, the input configuration registers are chained together through DOUT to DIN. Device A’s DOUT will drive device B’s DIN. The input configuration register is an 8-bit, firstin first-out shift register. The configuration data is clocked in N times through 8 O N falling SCLK edges. After the MAX11166 ADCs in the chain are loaded with the configuration byte, pull CNVST high to complete the configuration register loading process. Figure 5 illustrates a configuration sequence for loading two devices in a chain. The MAX11166 can be programmed into one of four output modes; CS modes with and without busy indicator and daisy-chain modes with and without busy indicator. When operating without busy indication, the user must externally timeout the maximum ADC conversion time before commencing readback. When operating in one of the two busy indication modes, the user can connect the DOUT output of the MAX11166 to an interrupt input on the digital host and use this interrupt to trigger the output data read. Data loaded into the configuration register alters the state of the MAX11166 on the next conversion cycle after the register is loaded. However, powering up the internal reference buffer or stabilizing the REFIO pin voltage will take several milliseconds to settle to 16-bit accuracy. Shutdown Mode The SHDN bit in the configuration register forces the MAX11166 into and out of shutdown. Set SHDN to 0 for normal operation. Set SHDN to 1 to shut down all internal circuitry and reset all registers to their default state. www.maximintegrated.com Regardless of the output interface mode used, digital activity should be limited to the first half of the conversion phase. Having SCLK or DIN transitions near the sampling instance can also corrupt the input sample accuracy. Therefore, keep the digital inputs quiet for approximately 25ns before and 10ns after the rising edge of CNVST. These times are denoted as tSQ and tHQ in all subsequent timing diagrams. In all interface modes, the data on DOUT is valid on both SCLK edges. However, the input setup time into the receiving digital host will be maximized when data is clocked into that digital host on the falling SCLK edge. Doing so will allow for higher data transfer rates between the MAX11166 and the digital host and consequently higher converter throughput. In all interface modes, it is recommended that the SCLK be idled low to avoid triggering an input configuration write Maxim Integrated │  17 MAX11166 on the falling edge of CNVST. If at anytime the device detects a high SCLK state on a falling edge of CNVST, it will enter the input configuration write mode and will write the state of DIN on the next 8 falling SCLK edges to the input configuration register. In all interface modes, all data bits from a previous conversion must be read before reading bits from a new conversion. When reading out conversion data, if too few SCLK falling edges are provided and all data bits are not read out, only the remaining unread data bits will be outputted during the next readout cycle. In such an event, the output data in every other readout cycle will appear to have been truncated as only the leftover bits from the previous readout cycle are outputted. This is an indication to the user that there are insufficient SCLK falling edges in a given readout cycle. Table 5 provides a guide to aid in the selection of the appropriate output interface mode for a given application. CS No-Busy Indicator Mode 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Table 5. ADC Output Interface Mode Selector Guide MODE TYPICAL APPLICATION AND BENEFITS CS Mode, No-Busy Indicator Single or multiple ADCs connected to SPIcompatible digital host. Ideally suited for maximum throughput. CS Mode, With Busy Indicator Single ADC connected to SPI-compatible digital host with interrupt input. Ideally suited for maximum throughput. Daisy-Chain Mode, No-Busy Indicator Multiple ADCs connected to a SPIcompatible digital host. Ideally suited for multichannel simultaneous sampled isolated applications. Daisy-Chain Mode, With Busy Indicator Multiple ADCs connected to a SPIcompatible digital host with interrupt input. Ideally suited for multichannel simultaneous sampled isolated applications. The CS no-busy indicator mode is ideally suited for maximum throughput when a single MAX11166 is connected to a SPI-compatible digital host. The connection diagram is shown in Figure 6, and the corresponding timing is provided in Figure 7. A rising edge on CNVST completes the acquisition, initiates the conversion, and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. If CNVST is brought low during a conversion and held low throughout the maximum conversion time, the MSB will be output at the end of the conversion. When the conversion is complete, the MAX11166 enters the acquisition phase. Drive CNVST low to output the MSB onto DOUT. The remaining data bits are then clocked by subsequent SCLK falling edges. DOUT returns to high impedance after the 16th SCLK falling edge, or when CNVST goes high. www.maximintegrated.com CONVERT DIGITAL HOST CNVST MAX11166 DOUT DATA IN DIN CONFIG SCLK CLK Figure 6. CS No-Busy Indicator Mode Connection Diagram Maxim Integrated │  18 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN CS with Busy Indicator Mode A rising edge on CNVST completes the acquisition, initiates the conversion and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. The CS with busy indicator mode is shown in Figure 8 where a single ADC is connected to a SPI-compatible digital host with interrupt input. The corresponding timing is given in Figure 9. tCNVPW CNVST tCYC DIN ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSCKCNF tSCLK tSCLKL tHSCKCNF 1 SCLK 2 3 D15 D14 15 16 tSCLKH tDDO tEN DOUT 14 D13 tDIS D1 D0 Figure 7. CS No Busy Indicator Mode Timing CONVERT OVDD DIGITAL HOST CNVST MAX11166 SCLK 10kΩ DOUT DATA IN IRQ DIN CONFIG CLK Figure 8. CS With Busy Indicator Mode Connection Diagram www.maximintegrated.com Maxim Integrated │  19 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN tCNVPW CNVST tCYC DIN ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCLK tSSCKCNF tSCLKL tHSCKCNF SCLK 1 2 3 4 15 tDDO DOUT BUSY BIT D15 D14 D13 16 17 tSCLKH tDIS D1 D0 Figure 9. CS With Busy Indicator Mode Timing When the conversion is complete, DOUT transitions from high impedance to a low logic level, signaling to the digital host through the interrupt input that data readback can commence. The MAX11166 then enters the acquisition phase. The data bits are then clocked out, MSB first, by www.maximintegrated.com subsequent SCLK falling edges. DOUT returns to high impedance after the 17th SCLK falling edge or when CNVST goes high, and is then pulled to OVDD through the external pullup resistor. Maxim Integrated │  20 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Multichannel CS Configuration, Asynchronous or Simultaneous Sampling The multichannel CS configuration is generally used when multiple MAX11166 ADCs are connected to an SPIcompatible digital host. Figure 10 shows the connection diagram example using two MAX11166 devices. Figure 11 shows the corresponding timing. Asynchronous or simultaneous sampling is possible by controlling the CS1 and CS2 edges. In Figure 10, the DOUT bus is shared with the digital host limiting the throughput rate. However, maximum throughput is possible if the host accommodates each ADC’s DOUT pin independently. A rising edge on CNVST completes the acquisition, initiates the conversion and forces DOUT to high impedance. The conversion continues to completion irrespective of the state of CNVST allowing CNVST to be used as a select line for other devices on the board. However, CNVST must be returned high before the minimum conversion time for proper operation so that another conversion is not initiated with insufficient acquisition time and data correctly read out of the device. When the conversion is complete, the MAX11166 enters the acquisition phase. Each ADC result can be read by bringing its CNVST input low, which consequently outputs the MSB onto DOUT. The remaining data bits are then clocked by subsequent SCLK falling edges. For each device, its DOUT will return to a high-impedance state after the 16th SCLK falling edge or when CNVST goes high. This control allows multiple devices to share the same DOUT bus. CS2 CS1 CNVST CNVST DOUT MAX11166 DEVICE A DOUT DIGITAL HOST MAX11166 DIN SCLK DEVICE B DIN CONFIG SCLK DATA IN CLK Figure 10. Multichannel CS Configuration Diagram www.maximintegrated.com Maxim Integrated │  21 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN tCNVPW tCNVPW CNVSTA(CS1) tCYC CNVSTB(CS2) DIN tACQ tCONV ACQUISITION CONVERSION tSSCKCNF ACQUISITION SCLK 1 2 tEN DOUT tSCLK tSCLKL tHSCKCNF 3 15 tDDO D15 D14 16 tSCLKH D13 17 18 19 31 tEN tDIS tDIS D1 D0 D15 32 D14 D13 D1 D0 Figure 11. Multichannel CS Configuration Timing Daisy-Chain, No-Busy Indicator Mode The daisy-chain mode with no-busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity. Simultaneous sampling of multiple ADC channels is realized on the serial interface where data readback is analogous to clocking a shift register. Figure 12 shows a connection diagram of two MAX11166s configured in a daisy chain. The corresponding timing is given in Figure 13. A rising edge on CNVST completes the acquisition and initiates the conversion. Once a conversion is initiated, it continues to completion irrespective of the state of CNVST. When a conversion is complete, the MSB is presented onto DOUT and the MAX11166 returns to the acquisition phase. The remaining data bits are stored within an internal shift register. To read these bits out, CNVST is brought low and each bit is shifted out on subsequent SCLK falling edge. The DIN input of each ADC in the chain is used to transfer conversion data from the previous ADC into the internal shift register of the next ADC, thus allowing for data to be clocked through the multichip chain on each SCLK falling edge. Each ADC www.maximintegrated.com in the chain outputs its MSB data first requiring 16 × N clocks to read back N ADCs. In daisy-chain mode, the maximum conversion is reduced due to the increased readback time. instance, with a 6ns or less digital host setup time 3V interface, up to four MAX11166 devices running conversion rate of 324ksps can be daisy-chained. rate For and at a Daisy-Chain with Busy Indicator Mode The daisy-chain mode with busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity while providing a conversion complete indication that can be used to interrupt a host processor to read data. Simultaneous sampling of multiple ADC channels is realized on the serial interface where data readback is analogous to clocking a shift register. The daisy-chain mode with busy indicator is shown in Figure 14 where three MAX11166s are connected to a SPI-compatible digital host with corresponding timing given in Figure 15. A rising edge on CNVST completes the acquisition and initiates the conversion. Once a conversion is initiated, it Maxim Integrated │  22 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN continues to completion irrespective of the state of CNVST. When a conversion is complete, the busy indicator is presented onto each DOUT and the MAX11166 returns to the acquisition phase. The busy indicator for the last ADC in the chain can be connected to an interrupt input on the digital host. The digital host should insert a 50ns delay from the receipt of this interrupt before reading out data from all ADCs to ensure that all devices in the chain have completed conversion. The conversion data is stored within an internal shift register. To read these bits out, CNVST is brought low and each bit is shifted out on subsequent SCLK falling edge. The DIN input of each ADC in the chain is used to transfer conversion data from the previous ADC into the internal shift register of the next ADC, thus allowing for data to be clocked through the multichip chain on each SCLK falling edge. The total of number of falling SCLKs needed to read back all data from N ADCs is 16 × N + 1 edges, the one additional SCLK falling edge required to clock out the busy mode bit from the host side ADC. CONFIG CONVERT CNVST DIN CNVST DA DOUT MAX11166 DIN MAX11166 DEVICE A DEVICE B SCLK SCLK DIGITAL HOST DB DOUT DATA IN CLK Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram tCNVPW CNVST tCYC DIN tCONV ACQUISITION tACQ CONVERSION ACQUISITION SCLK 1 2 3 DB15 DB14 tHSCKCNF 14 15 16 17 18 DB1 DB0 DA15 DA14 30 31 32 DA1 DA0 tSCLKH tDDO DOUTB tSSCKCNF tSCLK tSCLKL DB13 Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing www.maximintegrated.com Maxim Integrated │  23 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN CONFIG CONVERT CNVST DIN MAX11166 CNVST DA DOUT DIN CNVST MAX11166 DOUT DB DIN MAX11166 DOUT DEVICE A DEVICE B DEVICE C SCLK SCLK SCLK DC DIGITAL HOST DATA IN IRQ CLK Figure 14. Daisy-Chain Mode with Busy Indicator Connection Diagram tCNVPW CNVST tCYC DIN tCONV ACQUISITION tACQ ACQUISITION CONVERSION tSCLKH SCLK 1 2 3 4 tSSCKCNF tSCLK 15 tDDO 16 17 18 19 31 32 33 34 35 47 tHSCKCNF 48 49 DA1 DA10 tSCLKL DOUTA = DINB BUSY DA15 DA14 DA13 BIT DA1 DA0 DOUTB = DINC BUSY DB15 DB14 DB13 BIT DB1 DB0 DA15 DA14 DA1 DA0 DOUTC BUSY DC15 DC14 DC13 BIT DC1 DC0 DB15 DB14 DB1 DB0 DA15 DA14 Figure 15. Daisy-Chain Mode with Busy Indicator Timing www.maximintegrated.com Maxim Integrated │  24 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN In daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. For instance, with a 6ns or less digital host setup time and 3V interface, up to four MAX11166 devices running at a conversion rate of 322ksps can be daisy-chained on a 3-wire port. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of less than Q1 LSB guarantees no missing codes and a monotonic transfer function. Layout, Grounding, and Bypassing Offset Error For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect the GND and AGNDS pins on the MAX11166 to this ground plane. Keep the ground return to the power-supply low impedance and as short as possible for noise-free operation. A 4.7nF C0G (or NPO) ceramic chip capacitor should be placed between AIN+ and the ground plane as close as possible to the MAX11166. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. For best performance, connect the REF output to the ground plane with a 16V, 10FF ceramic chip capacitor with a X5R or X7R dielectric in a 1210 or smaller case size. Ensure that all bypass capacitors are connected directly into the ground plane with an independent via. Bypass VDD and OVDD to the ground plane with 0.1FF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10FF decoupling capacitor to VDD and OVDD per PCB. For best performance, bring a VDD power plane in on the analog interface side of the MAX11166 and a OVDD power plane from the digital interface side of the device. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For the MAX11166, the offset error is defined at code center 0x8000. This code center should occur at 0V input between AIN+ and AIN-. The offset error is the actual voltage required to produce code center 0x8000, expressed in LSB. Gain Error Gain error is defined as the difference between the actual change in analog input voltage required to produce a top code transition minus a bottom code transition, and the ideal change in analog input voltage range to produce the same code transitions. It is expressed in LSB. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: Signal   RMS  = 20 × log  SINAD(dB) (Noise + Distortion) RMS  Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. www.maximintegrated.com Maxim Integrated │  25 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Effective Number of Bits Aperture Delay The effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. ENOB = SINAD − 1.76 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the power contained in the first five harmonics of the converted data to the power of the fundamental. This is expressed as: P + P3 + P4 + P5   THD = 10 × log  2 P   1 where P1 is the fundamental power and P2 through P5 is the power of the 2nd- through 5th-order harmonics.. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as full-power input bandwidth frequency. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. www.maximintegrated.com Maxim Integrated │  26 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Selector Guide PART BITS INPUT RANGE (V) REFERENCE MAX11262 14 0 to 5 External 3mm x 5mm µMAX-10 500 MAX11160 16 0 to 5 Internal 3mm x 5mm µMAX-10 500 MAX11161 16 0 to 5 Internal 3mm x 5mm µMAX-10 250 MAX11162 16 0 to 5 External 3mm x 5mm µMAX-10 500 MAX11163 16 0 to 5 External 3mm x 5mm µMAX-10 250 MAX11164 16 0 to 5 Internal/External 3mm x 3mm TDFN-12 500 MAX11165 16 0 to 5 Internal/External 3mm x 3mm TDFN-12 250 MAX11166 16 ±5 Internal/External 3mm x 3mm TDFN-12 500 MAX11167 16 ±5 Internal/External 3mm x 3mm TDFN-12 250 MAX11168 16 ±5 Internal 3mm x 5mm µMAX-10 500 MAX11169 16 ±5 Internal 3mm x 5mm µMAX-10 250 MAX11150 18 0 to 5 Internal 3mm x 5mm µMAX-10 500 MAX11152 18 0 to 5 External 3mm x 5mm µMAX-10 500 MAX11154 18 0 to 5 Internal/External 3mm x 3mm TDFN-12 500 MAX11156 18 ±5 Internal/External 3mm x 3mm TDFN-12 500 MAX11158 18 ±5 Internal 3mm x 5mm µMAX-10 500 Ordering Information SPEED (ksps) Package Information PART TEMP RANGE PIN-PACKAGE MAX11166ETC+T -40°C to +85°C 12 TDFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed Pad. www.maximintegrated.com PACKAGE For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 12 TDFN-EP TD1233+1 21-0664 90-0397 Maxim Integrated │  27 MAX11166 16-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN Revision History REVISION NUMBER REVISION DATE 0 7/15 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │  28