EVALUATION KIT AVAILABLE
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
General Description
The MAX11192/MAX11195/MAX11198 is a dual-channel
SAR ADCs with simultaneous sampling at 2Msps, 12-/14/16-bit resolution, and differential inputs. Available in a
tiny 16-pin, 3mm x 2mm ultra TDFN package, this ADC
delivers excellent static and dynamic performance while
operating from a supply voltage over the range of 3.0V to
5.25V. An integrated reference further reduces board area
and component count.
The MAX11192/MAX11195/MAX11198 output conversion
data using an SPI-compatible serial interface with a dual
DOUT bus. Specifications apply over the extended industrial
temperature range of -40°C to +125°C.
Applications
Benefits and Features
●● Tiny 16-Pin, 3mm x 2mm, TDFN Package
●● Up to 2Msps Throughput Rate
●● Two Simultaneous-Sampling ADC Cores
●● 2.5V Integrated Reference and Reference Buffers
●● Two Data Outputs for the Two SimultaneousSampling ADCs
●● No Overhead Clock Cycles; 12/14/16 Clock Cycles
for 12-/14-/16-Bit Result
●● Balanced, Differential Input Range of ±VREF
Ordering Information appears at end of data sheet.
●● Encoders
●● Resolvers
●● LVDT
●● Current Sensing in Motors
●● PLC
Application Diagram
3.3V TO 5.25V 1.8V TO 3.6V
MAX11192
MAX11195
MAX11198
10μF
AVDD
VREF
0.5 x VREF
0V
VREF
0.5 x VREF
0V
+
VREF
0.5 x VREF
0V
VREF
0.5 x VREF
0V
+
+
+
7.5Ω
7.5Ω
1nF
C0G
7.5Ω
7.5Ω
1nF
C0G
OVDD
AGND
OGND
AIN1+
SAR ADC
AIN1-
DOUT1
CNVST
SCLK
AIN2+
DOUT2
SAR ADC
AIN2REFIN/OUT
1μF
19-100018; Rev 0; 9/17
10μF
REF1
1μF
REF2
REFGND
1μF
DUAL
SPI
INTERFACE
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Absolute Maximum Ratings
AVDD to GND, REFGND, OGND.........................-0.3V to +5.5V
OVDD to GND, REFGND, OGND.........................-0.3V to +5.5V
AINn+, AINn- to GND, REFGND, OGND... -0.3V to The lower of
(VAVDD + 0.3V) and +5.5V
REFIN, REF1, REF2 to GND, REFGND, OGND............. -0.3V to
The lower of (VAVDD + 0.3V) and +5.5V
CNVST, SCLK, DOUT1, DOUT2 to OGND...................... -0.3V to
The lower of (VOVDD + 0.3V) and +5.5V
GND to REFGND to OGND..................................-0.3V to +0.3V
Maximum Current Into Any Pin......................... -50mA to +50mA
Continuous Power Dissipation (16 TDFN; TA = +70°C;
derate 16.7mW/°C above +70°C) ( )..........................1333mW
Operating Temperature Range.............................-40°C to 125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300ºC
Soldering Temperature (reflow)........................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
16 TDFN
PACKAGE CODE
T1623CN+1
Outline Number
21-100030
Land Pattern Number
—
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
60
Junction to Case (θJC)
11
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics—MAX11192
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Input Voltage Range
VIN(DIFF)
AINn+ – AINn-
Absolute Input Voltage Range
VIN(RNG)
AINn+/AINn- relative to GND
Common-Mode Input Voltage
Range
CMIRNG
(AINn+ + AINn-)/2
Input Leakage Current
IIN_LEAK
Acquisition phase
Input Capacitance
www.maximintegrated.com
CIN
±VREF
V
-0.1
VAVDD
+ 0.1
V
VREF/2
- 0.1
VREF/2
+ 0.1
V
1
μA
10
pF
Maxim Integrated │ 2
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11192 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+1
Bits
Bits
LSB
STATIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Resolution
No Missing Codes
Offset Error
N
12
12
-1
OE
Offset Error TC
Gain Error
Gain Error TC
Integral Nonlinearity
Differential Nonlinearity
1.2
GE
(Note 2)
-1
(Note 2)
INL
DNL
Analog Input CMR
CMRR
Power-Supply Rejection
PSRR
Power Supply Rejection
PSRR
mLSB/°C
+1
LSB
+0.5
+0.25
mLSB/°C
LSB
LSB
1.2
-0.5
-0.25
Common Mode Range;
VREF/2 - 100mV to VREF/2 + 100mV
75
dB
AVDD
85
dB
OVDD
90
dB
INTERNAL REFERENCE
Initial Accuracy
TA = +25°C
2.498
Temperature Drift
2.500
2.502
5
V
ppm
EXTERNAL REFERENCE
Input Voltage Range
External reference applied to REFIN
2.5
VAVDD
- 0.25
External reference applied to REF1
or REF2
2.5
VAVDD
+ 0.1
V
REFERENCE BUFFERS
Bypass Capacitor
1.0
μF
DYNAMIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
73
73.5
dB
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
73.5
dB
Spurious-Free Dynamic Range
SFDR
10kHz input
102
dB
THD
10kHz input
-108
dB
10kHz input
-100
dB
Total Harmonic Distortion
Crossalk
DYNAMIC PERFORMANCE (VREFIN/OUT = 4.096V, EXTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
10kHz input
Total Harmonic Distortion
Crossalk
73
73.5
dB
73.5
dB
10kHz input
102
dB
10kHz input
-108
dB
-100
dB
SAMPLING DYNAMICS
Throughput
2
Aperture Delay Match
Input -3db Bandwidth
www.maximintegrated.com
f-3dB
Msps
150
ps
50
MHz
Maxim Integrated │ 3
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11192 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.0
5.25
V
3.6
V
POWER SUPPLIES
Analog Supply Voltage
AVDD
3.0
Interface Supply Voltage
OVDD
1.7
Analog Supply Current
I(AVDD)
Interface Supply Current
I(OVDD)
DOUT load: CLOAD = 10pF
5.5
6.2
mA
0.75
1
mA
Analog Standby Current
IS(AVDD)
(Note 3)
1
mA
Interface Standby Current
IS(OVDD)
(Note 3)
1
μA
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
0.8 x
VOVDD
V
0.2 x
VOVDD
V
Input Capacitance
2
pF
Input Leakage
1
μA
DIGITAL OUTPUTS
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
VOVDD
- 0.4
V
VOGND
+ 0.4
V
TIMING
Conversion Period
t1
500
ns
SCLK to DOUT Hold
t2
1
ns
SCLK to DOUT Valid
t3
14
ns
SCLK High
t4
8
ns
SCLK Period
t5
20
ns
SCLK low
t6
8
ns
CNVST Rising Edge to SCLK
Rising Edge
t7
5
ns
SCLK Rising Edge to CNVST
Rising Edge
t8
5
ns
CNVST High
t9
60
ns
CNVST Falling Edge to SCLK
Rising Edge
t10
10
ns
SCLK Falling Edge to CNVST
Falling Edge
t11
0
ns
CNVST Low Time for Valid Sample
t12
400
ns
www.maximintegrated.com
Maxim Integrated │ 4
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11195
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Input Voltage Range
VIN(DIFF)
AINn+ – AINn-
Absolute Input Voltage Range
VIN(RNG)
AINn+/AINn- relative to GND
Common-Mode Input Voltage
Range
CMIRNG
(AINn+ + AINn-)/2
Input Leakage Current
IIN_LEAK
Acquisition phase
Input Capacitance
±VREF
V
-0.1
VAVDD
+ 0.1
V
VREF/2
- 0.1
VREF/2
+ 0.1
V
CIN
1
μA
10
pF
STATIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Resolution
No Missing Codes
Offset Error
N
14
14
-1.5
OE
Offset Error TC
+1.5
4
Gain Error
GE
Gain Error TC
Integral Nonlinearity
Differential Nonlinearity
INL
DNL
(Note 2)
-3.5
(Note 2)
Analog Input CMR
CMRR
Power-Supply Rejection
PSRR
Power Supply Rejection
PSRR
mLSB/°C
+3.5
LSB
+1.0
+0.5
mLSB/°C
LSB
LSB
2
-1.0
-0.5
Bits
Bits
LSB
Common Mode Range;
VREF/2 - 100mV to VREF/2 + 100mV
80
dB
AVDD
85
dB
OVDD
90
dB
INTERNAL REFERENCE
Initial Accuracy
TA = +25°C
2.498
Temperature Drift
2.500
2.502
5
V
ppm
EXTERNAL REFERENCE
Input Voltage Range
External reference applied to REFIN
2.5
VAVDD
- 0.25
External reference applied to REF1
or REF2
2.5
VAVDD
+ 0.1
V
REFERENCE BUFFERS
Bypass Capacitor
1.0
μF
DYNAMIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
10kHz input
Total Harmonic Distortion
Crossalk
www.maximintegrated.com
82
83.7
dB
83.7
dB
10kHz input
115
dB
10kHz input
-117
dB
-100
dB
Maxim Integrated │ 5
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11195 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (VREFIN/OUT = 4.096V, EXTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
10kHz input
Total Harmonic Distortion
Crossalk
84
84.6
dB
84.7
dB
10kHz input
112
dB
10kHz input
-110
dB
-100
dB
SAMPLING DYNAMICS
Throughput
2
Aperture Delay Match
Input -3db Bandwidth
f-3dB
Msps
150
ps
50
MHz
POWER SUPPLIES
Analog Supply Voltage
AVDD
3.0
Interface Supply Voltage
OVDD
1.7
5.0
5.25
V
3.6
V
Analog Supply Current
I(AVDD)
Interface Supply Current
I(OVDD)
DOUT load: CLOAD = 10pF
5.9
6.5
mA
0.75
1.1
mA
Analog Standby Current
IS(AVDD)
(Note 3)
1
mA
Interface Standby Current
IS(OVDD)
(Note 3)
1
μA
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
0.8 x
VOVDD
V
0.2 x
VOVDD
V
Input Capacitance
2
pF
Input Leakage
1
μA
DIGITAL OUTPUTS
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
VOVDD
- 0.4
V
VOGND
+ 0.4
V
TIMING
Conversion Period
t1
500
ns
SCLK to DOUT Hold
t2
1
ns
SCLK to DOUT Valid
t3
14
ns
SCLK High
t4
8
ns
SCLK Period
t5
20
ns
SCLK low
t6
8
ns
CNVST Rising Edge to SCLK
Rising Edge
t7
5
ns
www.maximintegrated.com
Maxim Integrated │ 6
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11195 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Rising Edge to CNVST
Rising Edge
t8
5
ns
CNVST High
t9
60
ns
CNVST Falling Edge to SCLK
Rising Edge
t10
10
ns
SCLK Falling Edge to CNVST
Falling Edge
t11
0
ns
CNVST Low Time for Valid Sample
t12
400
ns
Electrical Characteristics—MAX11198
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Input Voltage Range
VIN(DIFF)
AINn+ – AINn-
Absolute Input Voltage Range
VIN(RNG)
AINn+/AINn- relative to GND
Common-Mode Input Voltage
Range
CMIRNG
(AINn+ + AINn-)/2
Input Leakage Current
IIN_LEAK
Acquisition phase
Input Capacitance
±VREF
V
-0.1
VAVDD
+ 0.1
V
VREF/2
- 0.1
VREF/2
+ 0.1
V
CIN
1
μA
10
pF
STATIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Resolution
No Missing Codes
Offset Error
N
16
16
-4
OE
Offset Error TC
Gain Error
Gain Error TC
Integral Nonlinearity
Differential Nonlinearity
+4
10
GE
(Note 2)
-4
(Note 2)
INL
DNL
Analog Input CMR
CMRR
Power-Supply Rejection
PSRR
Power Supply Rejection
PSRR
mLSB/°C
+4
LSB
+1.5
+0.5
mLSB/°C
LSB
LSB
5
-1.5
-0.5
Common Mode Range;
VREF/2 - 100mV to VREF/2 + 100mV
Bits
Bits
LSB
80.5
dB
AVDD
85
dB
OVDD
90
dB
INTERNAL REFERENCE
Initial Accuracy
Temperature Drift
www.maximintegrated.com
TA = +25°C
2.498
2.500
5
2.502
V
ppm
Maxim Integrated │ 7
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11198 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE
Input Voltage Range
External reference applied to REFIN
2.5
VAVDD
- 0.25
External reference applied to REF1
or REF2
2.5
VAVDD
+ 0.1
V
REFERENCE BUFFERS
Bypass Capacitor
1.0
μF
DYNAMIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
10kHz input
Total Harmonic Distortion
Crossalk
86
89
dB
88.8
dB
10kHz input
115
dB
10kHz input
-117
dB
-100
dB
DYNAMIC PERFORMANCE (VREFIN/OUT = 4.096V, EXTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
10kHz input
Total Harmonic Distortion
Crossalk
90
91.7
dB
91.6
dB
10kHz input
114
dB
10kHz input
-111
dB
-100
dB
SAMPLING DYNAMICS
Throughput
2
Aperture Delay Match
Input -3db Bandwidth
f-3dB
Msps
150
ps
50
MHz
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
AVDD
3.0
OVDD
1.7
I(AVDD)
5.0
5.25
V
3.6
V
6.3
7
mA
0.75
1.2
Interface Supply Current
I(OVDD)
DOUT load: CLOAD = 10pF
Analog Standby Current
IS(AVDD)
(Note 3)
1
mA
mA
Interface Standby Current
IS(OVDD)
(Note 3)
1
μA
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
0.8 x
VOVDD
V
0.2 x
VOVDD
V
Input Capacitance
2
pF
Input Leakage
1
μA
www.maximintegrated.com
Maxim Integrated │ 8
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11198 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
VOVDD
- 0.4
V
VOGND
+ 0.4
V
TIMING
Conversion Period
t1
500
ns
SCLK to DOUT Hold
t2
1
ns
SCLK to DOUT Valid
t3
14
ns
SCLK High
t4
8
ns
SCLK Period
t5
20
ns
SCLK low
t6
8
ns
CNVST Rising Edge to SCLK
Rising Edge
t7
5
ns
SCLK Rising Edge to CNVST
Rising Edge
t8
5
ns
CNVST High
t9
60
ns
CNVST Falling Edge to SCLK
Rising Edge
t10
10
ns
SCLK Falling Edge to CNVST
Falling Edge
t11
0
ns
CNVST Low Time for Valid Sample
t12
400
ns
Note 1: Units are 100% production tested at TA = +25°C and are guaranteed by design and characterization from TA = TMIN to TMAX.
Note 2: Exclude the reference drift and offset error.
Note 3: This current is drawn when the device has completed conversion and SCLK is idle.
www.maximintegrated.com
Maxim Integrated │ 9
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL B)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL A)
toc1A
0.8
0.6
0.6
0.4
0.4
GAIN ERROR
0
-0.2
OFFSET
-0.4
0.8
0.6
GAIN ERROR
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1
-1
-40 -25 -10 5
0.3
0.4
0.2
ERROR (LSB)
GAIN ERROR
0.2
0
OFFSET
0.0
-0.1
GAIN ERROR
0.1
0
-0.2
-0.3
-0.4
-0.4
-1
-0.5
5.25
SUPPLY VOLTAGE(V)
OUTPUT NOISE HISTOGRAM
(CHANNEL A)
toc4A
STDEVA=0
LSB
120000
3.5
4
-0.5
4.5
140000
toc4B
60000
40000
60000
OUTPUT CODE (DECIMAL)
www.maximintegrated.com
toc5A
0.08
0.06
0.02
0.00
-0.04
-0.06
-0.08
-0.10
0
0
0
0
4.5
-0.02
40000
20000
4
0.04
80000
20000
3.5
0.10
STDEVB =
0LSB
120000
3
DNL vs. CODE
(CHANNEL A)
OUTPUT NOISE HISTOGRAM
(CHANNEL B)
100000
80000
2.5
REFERENCE VOLTAGE(V)
DNL (LSB)
100000
3
REFERENCE VOLTAGE(V)
NUMBER OF OCCURRENCES
140000
2.5
OFFSET
-0.1
-0.3
5
5.25
GAIN ERROR
0.2
0.1
-0.2
4.25 4.5 4.75
5
toc3B
0.3
OFFSET
-0.8
4
4.25 4.5 4.75
0.4
-0.6
3.25 3.5 3.75
4
0.5
ERROR (LSB)
0.4
0.6
3.25 3.5 3.75
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE (CHANNEL B)
toc3A
0.5
0.8
3
3
SUPPLY VOLTAGE(V)
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE (CHANNEL A)
toc2B
-0.4
-1
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1
-0.2
OFFSET
-0.4
-0.6
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL B)
ERROR (LSB)
0
-0.2
-0.8
20 35 50 65 80 95 110 125
GAIN ERROR
0.2
OFFSET
TEMPERATURE (°C)
NUMBER OF OCCURRENCES
0.4
-0.6
-40 -25 -10 5
toc2A
1
ERROR (LSB)
0.8
0.2
toc1B
1
ERROR (LSB)
ERROR (LSB)
1
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL A)
OUTPUT CODE (DECIMAL)
0
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
Maxim Integrated │ 10
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
0.10
0.08
0.08
0.06
MAX DNL
0.04
0.02
DNL (LSB)
0.00
-0.02
-0.04
0.04
0.04
0.02
0.02
0.00
-0.08
-0.10
-0.10
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
INL vs. TEMPERATURE
(CHANNEL B)
0.00
-0.06
-0.08
-40 -25 -10 5
-0.10
20 35 50 65 80 95 110 125
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
0.10
0.10
0.08
0.08
0.06
0.06
DNL (LSB)
0.02
0.00
-0.02
MIN INL
-0.04
0.04
0.02
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.08
-0.10
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
www.maximintegrated.com
0.06
MAX DNL
0.04
-0.06
-0.10
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
0.08
MAX INL
-40 -25 -10 5
TEMPERATURE (oC)
0.10
0.04
MIN INL
-0.04
MIN DNL
-0.06
-0.08
MAX INL
-0.02
-0.02
-0.04
MIN DNL
-0.06
0.06
MAX DNL
DNL (LSB)
DNL (LSB)
0.10
0.08
0.06
INL (LSB)
INL vs. TEMPERATURE
(CHANNEL A)
DNL vs. TEMPERATURE
(CHANNEL B)
INL (LSB)
0.10
DNL vs. TEMPERATURE
(CHANNEL A)
MIN DNL
MAX DNL
0.00
-0.02
-0.04
-0.06
MIN DNL
-0.08
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
-0.10
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
Maxim Integrated │ 11
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
0.10
110
0.08
0.08
108
0.06
0.06
MAX INL
0.00
MIN INL
-0.04
0.00
-0.02
MIN INL
-0.04
100
98
96
-0.06
94
-0.08
-0.08
92
-0.10
-0.10
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
90
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
50
100
150
INPUT IMPEDANCE (Ω)
FFT PLOT
(CHANNEL A)
FFT PLOT
(CHANNEL B)
FFT PLOT
(CHANNEL A)
-60
NSAMPLE = 65536
fIN = 10kHz
VIN = -0.1dBFS
SNR = 73.6dB
THD = -104.9dB
SFDR = 102.7dB
-20
-40
MAGNITUDE (dB)
-40
toc12B
0
-80
-100
-120
-60
-40
-100
-120
-60
-80
-100
-120
-140
-140
-140
-160
-160
-160
-180
-180
400
600
800
1000
0
200
400
FREQUENCY (kHz)
-60
-100
-120
-40
-60
-80
-100
-140
600
FREQUENCY (kHz)
www.maximintegrated.com
400
800
1000
-140
600
800
1000
toc14B
0
NSAMPLE =
131072
fIN1 = 8.96kHz
VIN1 =
-6.5dBFS
fIN2 = 10.97kHz
VIN2 =
-6.5dBFS
F6.95Hz=110dBFS
F12.97Hz=110dBFs
IMD=103dB
-20
-40
-60
-80
-100
-120
-160
400
200
FFT PLOT TWO
TONES
NSAMPLE =
131072
fIN1 = 8.96kHz
VIN1 =
-6.5dBFS
fIN2 = 10.97kHz
VIN2 =
-6.5dBFS
F6.95KHz=110dBFS
F12.97KHz=110dBFs
IMD=103dB
-20
-80
200
0
FREQUENCY (kHz)
toc14A
0
toc13B
MAGNITUDE (dB)
-40
-180
1000
FFT PLOT TWO
TONES
NSAMPLE = 32768
fIN = 100kHz
VIN = -0.1dBFS
SNR = 73.5dB
THD = -96.3dB
SFDR = 99.7dB
-20
800
FREQUENCY (kHz)
FFT PLOT
(CHANNEL B)
0
600
MAGNITUDE (dB)
200
NSAMPLE = 32768
fIN = 100kHz
VIN = -0.1dBFS
SNR = 73.6dB
THD = -96.2dB
SFDR = 99.9dB
-20
-80
200
toc13A
0
MAGNITUDE (dB)
toc12A
0
0
AVDD SUPPLY VOLTAGE (V)
-20
-180
CHA
AVDD SUPPLY VOLTAGE (V)
NSAMPLE = 65536
fIN = 10kHz
VIN = -0.1dBFS
SNR = 73.6dB
THD = -105.1dB
SFDR = 103.4dB
0
CHB
102
-0.06
0
MAGNITUDE (dB)
104
0.02
THD (dB)
INL (LSB)
0.02
toc11
106
MAX INL
0.04
-0.02
MAGNITUDE (dB)
THD vs. INPUT IMPEDANCE
0.10
0.04
INL (LSB)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
-120
6
7
8
9
10
11
FREQUENCY (kHz)
12
13
14
-140
6
7
8
9
10
11
12
13
14
FREQUENCY (kHz)
Maxim Integrated │ 12
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. FREQUENCY
(CHANNEL A)
SNR AND SINAD vs. FREQUENCY
(CHANNEL B)
toc15A
toc15B
75
SNR
73
SINAD
72
130
SNR
74
SNR AND SINAD (dB)
SNR AND SINAD (dB)
74
120
73
SINAD
72
71
71
70
70
toc16A
140
THD AND SFDR (dB)
75
THD AND SFDR vs. FREQUENCY
(CHANNEL A)
THD
110
100
90
SFDR
80
70
0
20
40
60
80
100
0
20
FREQUENCY (kHz)
60
80
60
100
0
20
FREQUENCY (kHz)
toc16B
140
toc17B
100
90
SFDR
80
74
73
SNR AND SINAD (dB)
SNR AND SINAD (dB)
THD
110
100
SNR
74
120
80
75
SNR
130
60
SNR AND SINAD vs. TEMPERATURE
(CHANNEL B)
toc17A
75
40
FREQUENCY (kHz)
SNR AND SINAD vs. TEMPERATURE
(CHANNEL A)
THD AND SFDR vs. FREQUENCY
(CHANNEL B)
THD AND SFDR (dB)
40
SINAD
72
71
73
SINAD
72
71
70
0
20
40
60
80
70
100
THD AND SFDR vs. TEMPERATURE
(CHANNEL A)
toc18A
toc19A
75
SNR
130
100
90
SFDR
80
70
THD AND SFDR (dB)
120
110
20 35 50 65 80 95 110 125
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL A)
toc18B
140
THD
120
THD AND SFDR (dB)
-40 -25 -10 5
TEMPERATURE (°C)
THD AND SFDR vs. TEMPERATURE
(CHANNEL B)
130
60
70
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FREQUENCY (kHz)
140
-40 -25 -10 5
74
THD
110
100
90
SFDR
80
SNR AND SINAD (dB)
60
73
SINAD
72
71
70
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
60
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
70
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
Maxim Integrated │ 13
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL B)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL A)
toc19B
75
SINAD
72
130
120
120
THD
THD AND SFDR (dB)
THD AND SFDR (dB)
73
110
100
90
SFDR
80
71
2.5
3
3.5
4
60
4.5
100
90
PSR vs. INPUT FREQUENCY
2.5
3
3.5
4
7
CHB
70
4
3
IOVDD
1
100
1.4
-40 -25 -10 5
IAVDD
3
2
1
0
20 35 50 65 80 95 110 125
0
0.5
1
1.5
2
SAMPLING RATE (Msps)
REFERENCE VOLTAGE
vs. TEMPERATURE
toc25
0.5
toc26
2.505
0.3
1
0.9
CURRENT (uA)
IAVDD
1.1
0.2
0.1
IOVDD
0
-0.1
-0.2
0.8
-0.3
0.7
REFERENCE VOLTAGE (V)
0.4
1.2
CURRENT (mA)
4
OVDD STANDBY CURRENT
vs. TEMPERATURE
1.3
0.6
toc23
TEMPERATURE (°C)
toc24
4.5
IOVDD
INPUT FREQUENCY (kHz)
AVDD STANDBY CURRENT
vs. TEMPERATURE
4
5
5
0
3.5
6
IAVDD
2
60
3
CURRENT vs. SAMPLING RATE
CURRENT (mA)
CURRENT (mA)
80
10
2.5
REFERENCE VOLTAGE (V)
toc22
6
1
60
4.5
8
CHA
PSR (dB)
70
CURRENT vs. TEMPERATURE
toc21
90
50
SFDR
80
VOLTAGE REFERENCE (V)
REFERENCE VOLTAGE (V)
100
THD
110
70
70
toc20B
140
130
74
SNR AND SINAD (dB)
toc20A
140
SNR
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL B)
2.503
2.501
2.499
2.497
-0.4
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
-0.5
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.495
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 14
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
OFFSET AND GAIN ERROR
vs. TEMPERATURE
(CHANNEL B)
OFFSET AND GAIN ERROR
vs. TEMPERATURE (CHANNEL A)
toc1A
5
4
4
3
3
1
0
-1
GAIN ERROR
-2
1
0
-1
-2
0
-1
-4
-4
-4
-5
-5
-40 -25 -10 5
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL A)
toc3A
5.0
4.0
3
3.0
OFFSET
ERROR (LSB)
1
0
GAIN ERROR
1.0
0.0
-1.0
OFFSET
0
-1
-3
-4
-4.0
-4
-5
-5.0
5
5.25
2.5
3
SUPPLY VOLTAGE (V)
OUTPUT NOISE HISTOGRAM
(CHANNEL A)
toc4A
140000
STDEVA = 0.3LSB
3.5
4
REFERENCE VOLTAGE(V)
-5
4.5
toc4B
40000
0
-5
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
www.maximintegrated.com
3
4
5
toc5A
0.02
0.00
-0.02
-0.04
40000
0
4.5
0.04
60000
20000
4
0.06
80000
20000
3.5
0.08
DNL (LSB)
60000
3
0.10
STDEVB = 0.2 LSB
100000
80000
2.5
DNL vs. CODE
(CHANNEL A)
120000
100000
GAIN ERROR
REFERENCE VOLTAGE(V)
OUTPUT NOISE HISTOGRAM
(CHANNEL B)
140000
NUMBER OF OCCURRENCES
120000
5.25
1
-2
4.25 4.5 4.75
5
OFFSET
2
-3.0
4
4.25 4.5 4.75
toc3B
3
GAIN ERROR
-3
3.25 3.5 3.75
4
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL B)
5
-2.0
3
3.25 3.5 3.75
4
2.0
-2
3
SUPPLY VOLTAGE(V)
ERROR (LSB)
toc2B
4
-1
-5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OFFSET AND GAIN ERROR
vs. SUPPLY VOLTAGE
(CHANNEL B)
2
GAIN ERROR
-2
GAIN ERROR
-3
5
ERROR (LSB)
1
-3
20 35 50 65 80 95 110 125
OFFSET
2
-3
-40 -25 -10 5
toc2A
3
OFFSET
TEMPERATURE (°C)
NUMBER OF OCCURRENCES
5
4
2
OFFSET
toc1B
ERROR (LSB)
2
ERROR (LSB)
ERROR (LSB)
5
OFFSET AND GAIN ERROR
vs. SUPPLY VOLTAGE
(CHANNEL A)
-0.06
-0.08
-0.10
-5
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
3
4
5
0
4000
8000
12000
16000
OUTPUT CODE (DECIMAL)
Maxim Integrated │ 15
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
DNL vs. CODE
(CHANNEL B)
INL vs. CODE
(CHANNEL A)
0.40
0.40
0.08
0.30
0.30
0.20
0.20
0.10
0.10
0.06
INL (LSB)
0.02
0.00
-0.02
0.00
-0.10
-0.20
-0.20
-0.08
-0.30
-0.30
-0.10
-0.40
-0.06
0
4000
8000
12000
16000
OUTPUT CODE (DECIMAL)
DNL vs. TEMPERATURE
(CHANNEL A)
0.40
DNL (LSB)
DNL (LSB)
0.20
0.00
-0.10
12000
-0.40
16000
DNL vs. TEMPERATURE
(CHANNEL B)
MIN DNL
toc7B
-0.40
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
0.40
0.40
0.40
0.20
MAX INL
DNL (LSB)
0.20
0.00
-0.20
MIN INL
-0.40
MIN DNL
-0.60
-40 -25 -10 5
20 35 50 65 80 95 110 125
-0.80
TEMPERATURE (oC)
www.maximintegrated.com
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
toc9B
0.40
0.30
0.20
MAX DNL
0.00
-0.10
-0.40
MIN INL
-0.40
20 35 50 65 80 95 110 125
MAX DNL
0.10
0.00
-0.10
MIN DNL
-0.30
-40 -25 -10 5
0.00
-0.60
0.10
-0.20
MAX INL
-0.20
0.30
0.60
16000
0.20
TEMPERATURE (oC)
INL vs. TEMPERATURE
(CHANNEL B)
12000
0.80
MAX DNL
-0.20
-0.30
8000
0.60
0.00
-0.40
4000
INL vs. TEMPERATURE
(CHANNEL A)
0.10
-0.30
0
OUTPUT CODE (DECIMAL)
-0.10
-0.20
-0.80
8000
0.30
MAX DNL
0.10
0.80
4000
OUTPUT CODE (DECIMAL)
0.30
0.20
0
INL (LSB)
0.40
INL (LSB)
0.00
-0.10
-0.04
DNL (LSB)
DNL (LSB)
0.04
INL (LSB)
0.10
INL vs. CODE
(CHANNEL B)
-0.20
MIN DNL
-0.30
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
-0.40
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
Maxim Integrated │ 16
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
toc10A
0.60
0.60
0.40
0.40
MAX INL
INL (LSB)
0.20
0.00
-0.20
-0.40
-0.60
-0.80
AVDD SUPPLY VOLTAGE (V)
www.maximintegrated.com
-0.80
105
100
CHB
95
MIN INL
90
85
-0.60
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
CHA
110
0.00
-0.40
toc11
115
MAX INL
0.20
-0.20
MIN INL
THD vs. INPUT IMPEDANCE
toc10B
0.80
THD (dB)
0.80
INL (LSB)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
80
0
50
100
150
200
INPUT IMPEDANCE (Ω)
Maxim Integrated │ 17
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. FREQUENCY
(CHANNEL A)
toc15A
85
SNR AND SINAD (dB)
83
SINAD
82
81
SNR
83
SINAD
82
40
60
80
80
100
0
20
85
SNR AND SINAD (dB)
THD
100
SFDR
0
20
40
60
80
110
THD
SINAD
82
-40 -25 -10 5
20 35 50 65 80 95 110 125
60
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL A)
toc19A
86
SNR
85
SFDR
THD
90
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
toc18B
100
70
TEMPERATURE (°C)
SNR
83
80
20 35 50 65 80 95 110 125
110
70
www.maximintegrated.com
-40 -25 -10 5
120
80
100
81
140
80
80
84
THD AND SFDR vs. TEMPERATURE
(CHANNEL B)
THD AND SFDR (dB)
THD AND SFDR (dB)
85
SINAD
130
120
60
toc17B
TEMPERATURE (°C)
SFDR
-40 -25 -10 5
40
86
SNR
82
80
100
toc18A
90
20
SNR AND SINAD vs. TEMPERATURE
(CHANNEL B)
toc17A
83
THD AND SFDR vs. TEMPERATURE
(CHANNEL A)
100
0
FREQUENCY (kHz)
84
FREQUENCY (kHz)
140
SFDR
80
60
100
81
70
60
80
SNR AND SINAD (dB)
THD AND SFDR (dB)
120
130
60
86
130
80
90
SNR AND SINAD vs. TEMPERATURE
(CHANNEL A)
toc16B
140
90
100
FREQUENCY (kHz)
THD AND SFDR vs. FREQUENCY
(CHANNEL B)
110
40
SNR AND SINAD (dB)
20
THD
110
70
FREQUENCY (kHz)
60
120
84
81
0
toc16A
140
130
85
84
80
toc15B
86
SNR
THD AND SFDR vs. FREQUENCY
(CHANNEL A)
THD AND SFDR (dB)
86
SNR AND SINAD (dB)
SNR AND SINAD vs. FREQUENCY
(CHANNEL B)
84
SINAD
83
82
81
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
80
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
Maxim Integrated │ 18
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL B)
toc19B
86
82
120
110
100
3
3.5
4
3.5
4
2.5
7
3.5
4
4.5
CURRENT vs. SAMPLING RATE
toc22
8
3
REFERENCE VOLTAGE (V)
CURRENT vs. TEMPERATURE
toc21
CHA
toc23
6
IAVDD
5
80
CHB
CURRENT (mA)
CURRENT (mA)
6
70
5
4
3
2
60
IOVDD
1
1
10
0
100
IAVDD
3
2
1
-40 -25 -10 5
0
20 35 50 65 80 95 110 125
0
0.5
TEMPERATURE (°C)
AVDD STANDBY CURRENT
vs. TEMPERATURE
1.5
2
REFERENCE VOLTAGE
vs. TEMPERATURE
toc25
0.5
1
SAMPLING RATE (Msps)
OVDD STANDBY CURRENT
vs. TEMPERATURE
toc24
1.4
4
IOVDD
INPUT FREQUENCY (kHz)
toc26
2.505
1.2
0.3
CURRENT (µA)
IAVDD
1.1
1
0.9
0.2
0.1
IOVDD
0
-0.1
-0.2
0.8
-0.3
0.7
REFERENCE VOLTAGE (V)
0.4
1.3
CURRENT (mA)
60
4.5
VOLTAGE REFERENCE (V)
90
PSR (dB)
3
THD
90
70
PSR vs. INPUT FREQUENCY
0.6
100
70
REFERENCE VOLTAGE (V)
50
110
80
2.5
SFDR
120
80
60
4.5
100
THD
90
81
2.5
130
SFDR
THD AND SFDR (dB)
THD AND SFDR (dB)
SINAD
83
toc20B
140
130
84
80
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL B)
toc20A
140
SNR
85
SNR AND SINAD (dB)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL A)
2.503
2.501
2.499
2.497
-0.4
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
-0.5
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.495
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 19
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL A)
toc1A
4
3
3
ERROR (LSB)
GAIN ERROR
2
1
0
-1
OFFSET
toc1B
5
4
1
0
-1
2
0
-1
-2
-3
-3
-4
-4
-4
-5
-5
20 35 50 65 80 95 110 125
-2
OFFSET
-40 -25 -10 5
-5
20 35 50 65 80 95 110 125
toc2B
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL A)
toc3A
5.0
4.0
4
3.0
3
ERROR (LSB)
2.0
1
0
-1
-4
-5
3
3.25 3.5 3.75
4
0.0
-1.0
-2.0
OFFSET
4.25 4.5 4.75
5
-4
toc4A
40000
30000
20000
10000
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
www.maximintegrated.com
-5
4.5
2.5
3
4
5
3.5
4
4.5
DNL vs. CODE
(CHANNEL A)
toc5A
0.40
toc4B
STDEVB = 0.9LSB
0.30
60000
0.20
50000
40000
30000
0.10
0.00
-0.10
20000
-0.20
10000
-0.30
0
3
REFERENCE VOLTAGE (V)
DNL (LSB)
NUMBER OF OCCURRENCES
50000
-5
4
OUTPUT NOISE HISTOGRAM
(CHANNEL B)
70000
STDEVA=0.8 LSB
60000
0
3.5
OFFSET
REFERENCE VOLTAGE (V)
OUTPUT NOISE HISTOGRAM
(CHANNEL A)
70000
GAIN ERROR
0
-3
SUPPLY VOLTAGE (V)
5.25
-1
-4.0
3
5
-2
GAIN ERROR
2.5
4.25 4.5 4.75
1
-3.0
-5.0
5.25
4
toc3B
2
OFFSET
1.0
ERROR (LSB)
GAIN ERROR
3.25 3.5 3.75
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL B)
5
3
-3
3
SUPPLY VOLTAGE (V)
4
-2
OFFSET
TEMPERATURE (°C)
5
2
GAIN ERROR
1
-3
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL B)
ERROR (LSB)
3
GAIN ERROR
2
-2
-40 -25 -10 5
toc2A
5
4
TEMPERATURE (°C)
NUMBER OF OCCURRENCES
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL A)
ERROR (LSB)
5
ERROR (LSB)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL B)
-0.40
-5
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
3
4
5
0
10000 20000 30000 40000 50000 60000
OUTPUT CODE (DECIMAL)
Maxim Integrated │ 20
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
DNL vs. CODE
(CHANNEL B)
0.40
1.00
0.30
0.80
0.80
0.60
0.60
0.40
0.40
0.00
0.20
0.00
0.00
-0.20
-0.40
-0.40
-0.60
-0.60
-0.30
-0.80
-0.80
-0.40
-1.00
-0.20
0
10000 20000 30000 40000 50000 60000
OUTPUT CODE (DECIMAL)
0
-1.00
10000 20000 30000 40000 50000 60000
OUTPUT CODE (DECIMAL)
DNL vs. TEMPERATURE
(CHANNEL B)
DNL vs. TEMPERATURE
(CHANNEL A)
0.40
0.30
toc7B
0.80
0.60
0.40
0.00
-0.10
DNL (LSB)
0.20
MAX DNL
0.10
MAX DNL
0.10
0.00
-0.10
MIN DNL
0.00
MIN DNL
-0.40
-0.30
-0.30
-0.60
-0.40
-0.40
TEMPERATURE (oC)
-40 -25 -10 5
-0.80
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
INL vs. TEMPERATURE
(CHANNEL B)
0.40
0.60
0.30
toc9A
MIN INL
0.30
-0.20
0.20
MAX DNL
0.10
0.00
-0.10
MIN DNL
0.10
-0.20
-0.20
-0.60
-0.30
-0.30
-0.80
-0.40
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
www.maximintegrated.com
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
MAX DNL
0.00
-0.10
-0.40
-40 -25 -10 5
toc9B
0.40
DNL (LSB)
0.00
DNL (LSB)
MAX INL
0.20
20 35 50 65 80 95 110 125
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
0.20
0.40
-40 -25 -10 5
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
0.80
MIN INL
-0.20
-0.20
20 35 50 65 80 95 110 125
MAX INL
0.20
-0.20
-40 -25 -10 5
10000 20000 30000 40000 50000 60000
INL vs. TEMPERATURE
(CHANNEL A)
0.30
0.20
0
OUTPUT CODE (DECIMAL)
INL (LSB)
0.40
DNL (LSB)
0.20
-0.20
-0.10
INL vs. CODE
(CHANNEL B)
1.00
INL (LSB)
0.10
INL (LSB)
DNL (LSB)
0.20
INL (LSB)
INL vs. CODE
(CHANNEL A)
-0.40
MIN DNL
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
Maxim Integrated │ 21
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
0.80
0.60
0.40
0.40
0.20
MAX INL
0.00
-0.20
MIN INL
INL (LSB)
0.60
-0.40
-0.60
-0.60
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
www.maximintegrated.com
MAX INL
0.00
-0.20
-0.80
toc11
115
110
0.20
-0.40
-0.80
THD vs. INPUT IMPEDANCE
toc10B
MIN INL
CHA
105
THD (dB)
toc10A
0.80
INL (LSB)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
100
CHB
95
90
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
85
0
50
100
150
200
INPUT IMPEDANCE (Ω)
Maxim Integrated │ 22
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. FREQUENCY
(CHANNEL A)
SNR AND SINAD vs. FREQUENCY
(CHANNEL B)
toc15A
92
88
SINAD
87
86
85
89
88
SINAD
87
86
85
0
20
40
60
80
84
100
0
20
40
60
0
20
40
100
SFDR
90
SNR
90
89
88
SINAD
20
40
60
80
100
THD AND SFDR vs. TEMPERATURE
(CHANNEL A)
94
SFDR
THD
80
THD AND SFDR (dB)
120
110
100
80
60
60
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
THD
90
70
-40 -25 -10 5
93
110
70
toc19A
95
130
120
20 35 50 65 80 95 110 125
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL A)
toc18B
140
SFDR
90
-40 -25 -10 5
TEMPERATURE (°C)
THD AND SFDR vs. TEMPERATURE
(CHANNEL B)
toc18A
100
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FREQUENCY (kHz)
140
-40 -25 -10 5
SINAD
87
SNR AND SINAD (dB)
0
100
toc17B
91
SNR
89
87
80
SNR AND SINAD vs. TEMPERATURE
(CHANNEL B)
88
80
60
FREQUENCY (kHz)
toc17A
70
THD AND SFDR (dB)
SFDR
80
60
100
SNR AND SINAD (dB)
SNR AND SINAD (dB)
THD
110
130
80
91
130
60
90
SNR AND SINAD vs. TEMPERATURE
(CHANNEL A)
toc16B
140
90
100
FREQUENCY (kHz)
THD AND SFDR vs. FREQUENCY
(CHANNEL B)
120
THD
110
70
FREQUENCY (kHz)
THD AND SFDR (dB)
120
THD AND SFDR (dB)
SNR AND SINAD (dB)
SNR AND SINAD (dB)
130
SNR
90
89
toc16A
140
91
SNR
90
84
toc15B
92
91
THD AND SFDR vs. FREQUENCY
(CHANNEL A)
SNR
92
91
90
SINAD
89
88
87
86
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
85
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
Maxim Integrated │ 23
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL B)
toc19B
95
130
91
90
SINAD
89
88
SFDR
120
110
100
THD
90
2.5
3
3.5
4
60
4.5
toc21
100
80
70
60
2.5
3
3.5
4
4.5
7
CHA
70
IAVDD
4
3
100
-40 -25 -10 5
INPUT FREQUENCY (kHz)
1.4
3
1
0
20 35 50 65 80 95 110 125
0
0.5
1
1.5
2
REFERENCE VOLTAGE
vs. TEMPERATURE
toc25
0.5
IOVDD
SAMPLING RATE (Msps)
OVDD STANDBY CURRENT
vs. TEMPERATURE
toc24
IAVDD
4
TEMPERATURE (°C)
AVDD STANDBY CURRENT
vs. TEMPERATURE
toc23
2
IOVDD
1
10
4.5
5
5
0
4
6
2
60
3.5
CURRENT vs. SAMPLING RATE
CURRENT (mA)
CURRENT (mA)
80
3
7
6
1
2.5
REFERENCE VOLTAGE(V)
toc22
8
CHB
90
THD
90
CURRENT vs. TEMPERATURE
PSR vs. INPUT FREQUENCY
toc26
2.505
1.2
0.3
CURRENT (uA)
IAVDD
1.1
1
0.9
0.2
0.1
IOVDD
0
-0.1
-0.2
0.8
2.503
2.501
2.499
2.497
-0.3
0.7
REFERENCE VOLTAGE (V)
0.4
1.3
CURRENT (mA)
100
VOLTAGE REFERENCE (V)
REFERENCE VOLTAGE (V)
0.6
110
70
86
SFDR
120
80
87
50
THD AND SFDR (dB)
92
THD AND SFDR (dB)
SNR AND SINAD (dB)
SNR
toc20B
140
130
93
PSR (dB)
toc20A
140
94
85
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL B)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL A)
-0.4
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
-0.5
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.495
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 24
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Pin Configuration
1
AIN1-
AIN2+
AVDD
AIN1+
AGND
TOP VIEW
16
15
14
REFIN/OUT
2
13
REF1
3
12
REFGND
MAX11192
MAX11195
MAX11198
AIN2-
4
11
REF2
CNVST
5
10
SCLK
OGND
6
9
OVDD
7
8
DOUT2
DOUT1
TDFN
2mm x 3mm
EXPOSED PAD IS CONNECTED TO AGND
www.maximintegrated.com
Maxim Integrated │ 25
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Pin Description
PIN
NAME
1
AIN1+
ADC1 Positive (+) Analog Input
FUNCTION
2
AIN1-
ADC1 Negative (-) Analog Input
3
AIN2+
ADC2 Positive (+) Analog Input
4
AIN2-
ADC2 Negative (-) Analog Input
5
CNVST
Conversion Start Input
6
OGND
Ground (IO Ground)
7
DOUT1
Serial Interface Data Out for ADC1
8
DOUT2
Serial Interface Data Out for ADC2
9
OVDD
IO Supply. Bypass with a 10μF capacitor to ground
10
SCLK
Serial Interface Clock
11
REF2
12
REFGND
REF2 Bypass Pin. Bypass with a 1μF capacitor to ground
Ground (Reference Ground)
13
REF1
14
REFIN/OUT
REF1 Bypass Pin. Bypass with a 1μF capacitor to ground
15
AVDD
Analog Supply Pin. Bypass with a 10μF capacitor to ground
16
AGND
Ground
External Reference Input or Internal Reference Decoupling. Bypass with 1μF capacitor to ground
Functional Diagram
REF1
REF2
+5.0V
REFIN/OUT
AVDD
REFBUFFER
MAX11192
MAX11195
MAX11198
AIN1+
+
AIN1-
AIN2+
AIN2-
VOLTAGE
REFERENCE
REFBUFFER
DOUT1
Interface
SAR ADC
CNVST
+
SCLK
SAR ADC
Interface
DOUT2
REFGND
www.maximintegrated.com
+1.8V
OVDD
AGND
OGND
Maxim Integrated │ 26
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Detailed Description
The MAX11192/MAX11195/MAX11198 are a family of
12-/14-/16-bit, 2-channel, 2Msps, SAR ADCS with simultaneous sampling, balanced differential inputs, and a
separate data output for each channel. These ADCs
feature best-in-class sample rate and resolution in a tiny
2mm x 3mm package. An integrated voltage reference
and reference buffers help to minimize board space,
component count, and system cost. An internal oscillator
sets conversion time, thereby simplifying external timing
requirements.
For fast throughput, the SPI-compatible digital interface
includes two data out pins (DOUT1 and DOUT2). DOUT1
provides conversion data from ADC1, while DOUT2 provides conversion data from ADC2. Data bits are clocked
out on the rising edge of SCLK.
Analog Inputs
The analog inputs of the MAX11192/MAX11195/
MAX11198, AINn+ and AINn-, should be driven with balanced differential signals. The input signals can range
from 0V to VREF. Thus, the differential input interval
VDIFF = (AINn+) - (AINn-) ranges from – VREF to + VREF,
and the full-scale range is:
The nominal resolution step width of the least significant
bit (LSB) is:
LSB
=
FSR
2N
=
2 × VREF
2N
, N = 12/14/16
The differential analog input must be centered with respect
to a common mode signal of VREF/2, with a tolerance of
±100mV. The reference voltage can range from 2.5V to
250mV below the reference supply AVDD. This will guarantee adequate headroom for the internal reference buffers. Figure 1 illustrates signal ranges for AINn+/AINn-, reference voltage VREF and reference supply voltage AVDD.
Figure 2 shows the analog input equivalent circuit of
MAX11192/MAX11195/MAX11198. The ADC samples
both inputs, AINn+ and AINn-, with a differential on-chip
track-and-hold exhibiting no pipeline delay or latency.
Each analog input (see Figure 2) has dedicated input
clamps to protect from overranging. Diodes D1 and D2
provide ESD protection and act as a clamp for the input
voltages. Diodes D1/D2 can sustain a maximum forward
current of 100mA. The sampling switches connect the
inputs to the sampling capacitors.
FSR = 2 × VREF
AVDD
V
D1
VREF + 250mV ≤ VAVDD ≤ 5.25V
AINn+
AVDD
≥ 250mV
VREF
AINn+
D1
AINn-
www.maximintegrated.com
VDC
AVDD
0.5VREF
Figure 1. Input Signal Ranges
CIN 7pF
D2
VREF ≤ 5V
0V
RON
250Ω
AINnTIME
D2
RON
250Ω
CIN 7pF
Figure 2. Simplified Model of Input Sampling Circuit
Maxim Integrated │ 27
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Figure 3 shows the timing of the conversion cycle's track,
SAR conversion, and read data operations. In the track
phase, starting with the rising edge of CNVST, the sample
switches are closed and the analog inputs are directly
connected to the sample capacitors. The source resistance
determines the charging of the sample capacitor to the
input voltage. The falling edge of CNVST is the sampling
instant for the ADCs. At this instant, the track phase ends,
the sample switches open, and the ADC enters into the
successive approximation (SAR) conversion phase. In the
conversion phase, a comparator compares the voltage
on the sample capacitor against the internal DAC value,
which cycles through values of binary-weighted fractions
of VREF using the successive approximation technique.
The final result is read through the SPI bus. Note that
ADC1 and ADC2 operate in parallel and conversion data
is available simultaneously through DOUT1 and DOUT2.
The ADCs go back into track phase on the rising edge
of CNVST. To achieve accurate conversion results, each
ADC should track its input signal for an interval longer than
the input signal's settling time. If the signal cannot settle
within the allocated track time due to excessive source
resistance, external ADC drivers are recommended to
achieve faster settling. Note that, since the MAX11192/
MAX11195/MAX11198 has a fixed conversion time set
by an internal oscillator, reducing the sample rate can
increase the track time.
The settling behavior is determined by the time constant
in the sampling network. The time constant depends upon
the total resistance (source resistance + switch resistance, RON) and total capacitance (sampling capacitor
CIN, external input capacitor, PCB parasitic capacitors,
1 / SAMPLE RATE
DOUT1/2
1) Fast settling time: For a multichannel multiplexed
circuit,the ADC driver amplifier must be able to settle
with an error less than 0.5 LSB during the minimum
track time when a full-scale step is applied.
2) Low noise: It is important to ensure that the ADC
driver has a sufficiently low noise density in the bandwidth of interest. When the MAX11192/MAX11195/
MAX11198 is used with its full bandwidth of 50MHz, it
is preferable to use an amplifier with an output noise
spectral density of less than 6nV√Hz, to ensure that
the overall SNR is not degraded significantly. It is recommended to insert an external RC filter at the ADC
input to attenuate out-of-band input noise.
3) To take full advantage of the ADC’s excellent dynamic
performance, we recommend the use of ADC drivers
with equal or even better THD performance. This will
ensure that the ADC drivers do not limit distortion performance in the signal path. The ADC drivers listed in
Table 1 are all excellent choices.
1 / SAMPLE RATE
SAR CONVERSION 2
TRACK 3
MSB
MSB-1
MSB-2
LSB+2
LSB+1
READ DATA (SAMPLE 1)
LSB
MSB
MSB-1
CLK N-2
CLK 2
CLK 1
CLK N
CLK N-2
SAMPLE 3
CLK N-1
SAMPLE 2
SAR CONVERSION 3
CLK 3
SAMPLE 1
CLK 2
CLK
TRACK 2
CLK 1
CNVST
SAR CONVERSION 1
When an ADC driver amplifier is used, it is recommended to use a series resistance (typically 5Ω to 50Ω)
between the amplifier and the ADC inputs, as shown in
the Application Diagram. The following are some of the
requirements for the ADC driver amplifier.
1 / SAMPLE RATE
CLK 3
TRACK 1
etc). Modeling the input circuit with a single pole network,
the time constant, RTOTAL× CLOAD, of the input should
not exceed tTRACK/12, where RTOTAL is the total resistance (source resistance + switch resistance), CLOAD is
the total capacitance (sampling capacitor, external input
capacitor, PCB parasitic capacitor), and tTRACK is the
track time.
MSB-2
LSB+2
LSB+1
CLK N
Input Settling
CLK N-1
MAX11192/MAX11195/
MAX11198
LSB
READ DATA (SAMPLE 2)
Figure 3. Conversion Timing: Track, SAR Conversion, and Read Operations
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Maxim Integrated │ 28
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Table 1. ADC Driver Amplifier Recommendations
AMPLIFIER
INPUT-NOISE
DENSITY
(NV/√Hz)
SMALL-SIGNAL
BANDWIDTH
(MHZ)
SLEW
RATE
(V/ΜS)
THD
(DB)
ICC
(MA)
MAX
OFFSET
(MV)
MAX44263
12.7
15
7
-110
0.75
0.05
Low current, low THD at
10kHz
MAX44242
5
10
8
-124
1.2
0.6
High voltage 2.7V to 20V,
low THD at 1kHz
MAX9632
1
55
30
-128
3.9
0.125
+2.5V
+2.5V
REF1
REF2
COMMENTS
Low noise, low THD at
10kHz
+2.5V
+3.3V to
+5.25V
REFIN/OUT
AVDD
REFBUFFER
VOLTAGE
REFERENCE
+1.8V
OVDD
REFBUFFER
MAX11192
MAX11195
MAX11198
Figure 4. Internal Reference
Input Filtering
Noisy input signals should be filtered prior to the ADC
driver amplifier input with an appropriate filter to minimize
noise. The RC network shown in the Application Diagram
is mainly designed to reduce the load transient seen by
the amplifier when the ADC starts the track phase. This
network has to satisfy the settling time requirement and
provides the benefit of limiting the noise bandwidth.
Voltage Reference Configurations
Using An Internal Reference
The MAX11192/MAX11195/MAX11198 feature a 2.5V
integrated reference with built-in reference buffers that
help to reduce component count and board space. When
using internal reference, only bypass capacitors are
required on the REF1, REF2, and REFIN/OUT pins (see
www.maximintegrated.com
Figure 4). The REF1/REF2 pins require external bypass
capacitors of at least 1μF.
Using An External Reference
To use an external reference (see Figure 5), drive the
REFIN/OUT pin directly with an external reference voltage source, ensuring that the reference voltage is no
greater than AVDD - 250mV. This will allow the on-chip
reference buffers to operate with sufficient supply headroom. The REF1/REF2 pins require external bypass
capacitors of at least 1μF.
Table 2 lists excellent choices for low-noise, low-temperature drift external references.
Transfer Function
Figure 6 shows the ideal transfer characteristics for the
MAX11192/MAX11195/MAX11198.
Maxim Integrated │ 29
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
+VREF
REF1
+VREF
+VREF
VOLTAGE
REFERENCE
VREF + 0.25V
TO
5.25V
REFIN/OUT
REF2
AVDD
REFBUFFER
VOLTAGE
REFERENCE
+1.8V
OVDD
REFBUFFER
MAX11192
MAX11195
MAX11198
Figure 5. External Reference
Table 2. External Reference Recommendations
REFERENCE
INITIAL
ACCURACY (%)
TEMPERATURE DRIFT
MAX (PPM/°C)
NOISE (ΜVP-P)
COMMENTS
MAX6070
±0.04
15
7
Low noise
MAX6133
±0.04
3
16
Very low drift
MAX6072
±0.04
6
9
Dual reference
OUTPUT CODE
(TWO’S COMPLEMENT)
FS - 1.5 x LSB
011...111
011...110
LSB=
011...101
2 x VREF
2N
N = 12/14/16
100...010
100...001
100...000
-2N-1 -2N-1+1 -2N-1+2
2N-1-2 2N-1-1
2N-1
VIN = (AIN+)-(AIN-)
DIFFERENTIAL
ANALOG INPUT
(LSB)
2 x VREF
ZERO SCALE
VIN = -VREF
FULL SCALE (FS)
VIN = +VREF
Figure 6. Ideal ADC Transfer Characteristics
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Maxim Integrated │ 30
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Digital Interface
the ADCs enter track mode. To complete a conversion,
the time between CNVST falling and rising edge must
be at least the minimum of the conversion time t12 (see
Figure 11). The conversion data can then be read immediately after the rising edge of the next CNVST pulse,
which should not occur before the minimum conversion
time value (t12) has elapsed. guard against digital noise
from the data bus, corrupting the sample.
Conversion data may be read in the track phase, the conversion phase, or both. Outlined below are the specifics
of the various ways to read conversion data.
The input signals of the two ADC channels are sampled
simultaneously on the falling edge of CNVST and the conversion is initiated. At the end of the conversion, the ADCs
go idle until the next rising edge of CNVST, at which point
INITIATE READ RIGHT AFTER
CNVST RISING EDGE
DOUT 1/2
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB MSB MSB-1 MSB-2
READ DATA (SAMPLE 1)
CLK N
CLK 1
CLK 2
CLK N
CLK 3
CLK 1
CLK
SAR CONVERSION 3
SAMPLE 3
CLK N-1
SAMPLE 2
CLK 2
SAMPLE 1
CNVST
TRACK 3
SAR CONVERSION 2
CLK N-2
TRACK 2
1 / SAMPLE RATE
CLK N-1
SAR CONVERSION 1
CLK N-2
TRACK 1
1 / SAMPLE RATE
CLK 3
1 / SAMPLE RATE
LSB+2 LSB+1 LSB
READ DATA (SAMPLE 2)
Figure 7. Convert and Data Read
INITIATE READ RIGHT AFTER CNVST FALLING EDGE
1 / SAMPLE RATE
DOUT 1/2
MSB MSB-1 MSB-2
SAR CONVERSION 3
LSB+1 LSB
READ DATA (SAMPLE 1)
MSB MSB-1 MSB-2
CLK N
CLK N-1
CLK 3
CLK 1
CLK N
SAMPLE 3
CLK N-1
CLK 3
CLK
SAMPLE 2
CLK 2
SAMPLE 1
1 / SAMPLE RATE
SAR CONVERSION 2 TRACK 3
TRACK 2
CLK 1
CNVST
SAR CONVERSION 1
CLK 2
1 / SAMPLE RATE
TRACK 1
LSB+1 LSB
READ DATA (SAMPLE 2)
Figure 8. Reading Data After Falling Edge of CNVST
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Maxim Integrated │ 31
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
1 / SAMPLE RATE
t ≥ t12
CNVST
DOUT 1/2
CLK N
CLK N-1
CLK N-2
CLK 3
CLK
CLK 2
CLK 1
SAMPLE 1
LSB+2 LSB+1 LSB
MSB MSB-1 MSB-2
READ DATA (SAMPLE 1)
Figure 9. Convert and Data Read in a Single Conversion Period
t < t12
DOUT 1/2
MSB MSB-1 MSB-2
CLK 3
CLK 2
CLK 1
CLK N-2
SAMPLE 3
CLK 3
CLK
SAR CONVERSION 3
TRACK 3
SAMPLE 2
CLK 2
SAMPLE 1
CLK 1
CNVST
TRACK 2
1 / SAMPLE RATE
CLK N
SAR CONVERSION 1
TRACK 1
CONVERSION 2
ABORTED
CLK N-1
1 / SAMPLE RATE
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
READ DATA (SAMPLE 1)
Figure 10. Conversion Abort Data Read
t1
t12
t9
SAMPLE EDGE
70% OVDD
70% OVDD
CNVST
t8
t7
t11
t10
t4
t6
t5
70% OVDD
SCLK
30% OVDD
t3
t2
DOUT1/2
70% OVDD
Figure 11. Interface Timing Specifications
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Maxim Integrated │ 32
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Applications Information
Interfacing to Common Input Signals
Real-world signals typically require conditioning before
they can be digitized by an ADC. The following outlines
common examples of analog signal processing circuits.
The ADCs in the MAX11192/MAX11195/MAX11198
accept differential input signals with unipolar common
mode. Refer to THD vs. Input Impedance to use buffers
to minimize distortion. The three following examples show
input signal conditioning approaches to common signal
path configurations.
Differential Unipolar Input
The circuit in Figure 12 shows how amplifiers can be
configured to buffer a differential unipolar input signal.
Single-Ended Unipolar Input
The circuit in Figure 13 shows how a single-ended, unipolar
signal can interface with the MAX11192/MAX11195/
MAX11198. This signal conditioning circuit transforms a
0V to +VREF single-ended input signal to a fully differential
output signal with a signal peak-to-peak amplitude of 2 x
VREF and common-mode voltage of VREF/2. In this case,
the single-ended signal source drives the high-impedance
input of the first amplifier. This amplifier drives the AIN1+
input, and the second stage amplifier with a peak-to-peak
amplitude of VREF and a common-mode output voltage of
VREF/2. The second amplifier inverts this signal to generate
AIN1-, the inverted version of AIN1+.
Single-Ended Bipolar Input
Figure 14 shows a signal conditioning circuit that transforms
a -2 x VREF to +2 x VREF single-ended bipolar input
signal to a balanced differential output signal with a peakto-peak amplitude of 2 x VREF and a common-mode
voltage VREF/2.
The single-ended bipolar input signal drives the inverting
input of the first amplifier. This amplifier inverts and adds
an offset to the input signal. It also drives the AIN1- input
and the second stage amplifier with a peak-to-peak
amplitude of VREF and a common-mode output voltage of
VREF/2. The second amplifier is also in inverting configuration
and drives the AIN1+ input. This amplifier adds an offset to
generate a signal with a peak-to-peak amplitude of VREF
and a common-mode output voltage of VREF/2. The input
impedance, seen by the signal source, is determined by
the input resistor of the first-stage inverting amplifier. The
input impedance must be chosen carefully based on the
output impedance of the signal source.
3.3V TO 5.25V
VREF
-
0.5 x VREF
+
RS
0V TO VREF
0V
-
0.5 x VREF
+
AGND
OGND
OVDD
AIN1+
CS
COG
VREF
AVDD
1.7V TO 3.6V
AIN1-
SAR ADC
RS
CNVST
VREF TO 0V
SCLK
AIN2+
0V
AIN2-
MAX11192
MAX11195
MAX11198
DOUT1
REFIN/OUT
SAR ADC
REF1 REF2
DSP
SPI
INTERFACE
DOUT2
REFGND
Figure 12. Unipolar Differential Input
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Maxim Integrated │ 33
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
3.3V TO 5.25V
VREF
-
0.5 x
VREF
RS
0V TO VREF
+
AVDD
1.7V TO 3.6V
AGND
OVDD
OGND
AIN1+
R
R
CS
COG
0V
-
RS
DSP
CNVST
VREF TO 0V
+
VREF +
2
DOUT1
SAR ADC
AIN1-
SCLK
AIN2+
MAX11192
MAX11195
MAX11198
DOUT2
SAR ADC
AIN2REFIN/OUT
SPI
INTERFACE
REF1 REF2
REFGND
Figure 13. Unipolar Single-Ended Input
3.3V TO 5.25V
R
+2 x VREF
-2 x VREF
-
R
4R
0V
-
4R
2 x VREF +-
+
R
R
VREF +
2 -
1.7V TO 3.6V
MAX11192
RS
0V TO VREF
+
AVDD
AGND
OGND
OVDD
AIN1+
CS
COG
AIN1-
SAR ADC
RS
DOUT1
CNVST
VREF TO 0V
SCLK
AIN2+
MAX11192
MAX11195
MAX11198
AIN2REFIN/OUT
SAR ADC
REF1 REF2
DSP
SPI
INTERFACE
DOUT2
REFGND
Figure 14. Bipolar Single-Ended Input
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Maxim Integrated │ 34
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Layout, Grounding, and Bypassing
seen by the driving stage of the ADC input. For best
performance, connect the REF1/2 output to the ground
plane with a 16V, 10μF ceramic chip capacitor with a X5R
dielectric in a 1210 or smaller case size. Ensure that all
bypass capacitors are connected directly into the ground
plane with an independent via.
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines parallel
to one another (especially clock lines), and avoid running
digital lines underneath the ADC package. A single solid
GND plane configuration with digital signals routed from
one direction and analog signals from the other provides
the best performance. Connect the GND pins of the
MAX11192/MAX11195/MAX11198 to this ground plane.
Keep the ground return path to the power supply low
impedance and as short as possible. A 1nF C0G ceramic
chip capacitor should be placed between AINn+ and
AINn- as close as possible to the MAX11192/MAX11195/
MAX11198. This capacitor reduces the voltage transient
Bypass AVDD and OVDD to the ground plane with 10μF
ceramic chip capacitors on each pin as close as possible to
the device to minimize parasitic inductance. For best
performance, bring the AVDD power plane in from
the analog interface side of the MAX11192/MAX11195/
MAX11198 and the OVDD power plane from the digital
interface side of the device. Figure 15 shows the PCB
top layer of a sample layout with optimal placement of
passive components.
GND
REF2
REF1
REFIN/
OUT
AVDD
14
13
12
11
10
OVDD
9
15
8
DOUT2
16
7
DOUT1
1
2
3
4
AINP1
AINN1
AINP2
AINN2
GND
5
6
GND
Figure 15. PCB Layout Example for MAX11192/MAX11195/MAX11198
www.maximintegrated.com
Maxim Integrated │ 35
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Ordering Information
PART NUMBER
RESOLUTION
TEMP RANGE
PIN-PACKAGE
INTERNAL REFERENCE
MAX11192ATE+
12
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11192ATE+T
12
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11195ATE+
14
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11195ATE+T
14
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11198ATE+
16
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11198ATE+T
16
-40°C to +125°C
16 TDFN-EP*
2.5V
Denotes a lead(Pb)-free/RoHS-compliant package.
T = tape and reel.
*EP = Exposed Pad
www.maximintegrated.com
Maxim Integrated │ 36
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/17
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 37
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