EVALUATION KIT AVAILABLE
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
General Description
The MAX11192/MAX11195/MAX11198 is a dual-channel
SAR ADCs with simultaneous sampling at 2Msps, 12-/14/16-bit resolution, and differential inputs. Available in a
tiny 16-pin, 3mm x 2mm ultra TDFN package, this ADC
delivers excellent static and dynamic performance while
operating from a supply voltage over the range of 3.0V to
5.25V. An integrated reference further reduces board area
and component count.
The MAX11192/MAX11195/MAX11198 output conversion
data using an SPI-compatible serial interface with a dual
DOUT bus. Specifications apply over the extended industrial
temperature range of -40°C to +125°C.
Applications
Benefits and Features
●● Tiny 16-Pin, 3mm x 2mm, TDFN Package
●● Up to 2Msps Throughput Rate
●● Two Simultaneous-Sampling ADC Cores
●● 2.5V Integrated Reference and Reference Buffers
●● Two Data Outputs for the Two SimultaneousSampling ADCs
●● No Overhead Clock Cycles; 12/14/16 Clock Cycles
for 12-/14-/16-Bit Result
●● Balanced, Differential Input Range of ±VREF
Ordering Information appears at end of data sheet.
●● Encoders
●● Resolvers
●● LVDT
●● Current Sensing in Motors
●● PLC
Application Diagram
3.3V TO 5.25V 1.8V TO 3.6V
MAX11192
MAX11195
MAX11198
10μ F
AVDD
VREF
0.5 x VREF
0V
VREF
0.5 x VREF
0V
+
VREF
0.5 x VREF
0V
VREF
0.5 x VREF
0V
+
+
+
7.5Ω
7.5Ω
OVDD
AGND
OGND
AIN1+
1nF
C0G
SAR ADC
AIN1-
DOUT1
CNVST
7.5Ω
7.5Ω
SCLK
AIN2+
1nF
C0G
DOUT2
SAR ADC
AIN2REFIN/OUT
1μ F
19-100018; Rev 1; 9/17
10μ F
REF1
1μ F
REF2
REFGND
1μ F
DUAL
SPI
INTERFACE
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Absolute Maximum Ratings
AVDD to GND, REFGND, OGND.........................-0.3V to +5.5V
OVDD to GND, REFGND, OGND.........................-0.3V to +5.5V
AINn+, AINn- to GND, REFGND, OGND... -0.3V to The lower of
(VAVDD + 0.3V) and +5.5V
REFIN, REF1, REF2 to GND, REFGND, OGND............. -0.3V to
The lower of (VAVDD + 0.3V) and +5.5V
CNVST, SCLK, DOUT1, DOUT2 to OGND...................... -0.3V to
The lower of (VOVDD + 0.3V) and +5.5V
GND to REFGND to OGND..................................-0.3V to +0.3V
Maximum Current Into Any Pin......................... -50mA to +50mA
Continuous Power Dissipation (16 TDFN; TA = +70°C;
derate 16.7mW/°C above +70°C) ( )..........................1333mW
Operating Temperature Range.............................-40°C to 125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300ºC
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
16 TDFN
PACKAGE CODE
T1623CN+1
Outline Number
21-100030
Land Pattern Number
—
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
60
Junction to Case (θJC)
11
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics—MAX11192
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Input Voltage Range
VIN(DIFF)
AINn+ – AINn-
Absolute Input Voltage Range
VIN(RNG)
AINn+/AINn- relative to GND
Common-Mode Input Voltage
Range
CMIRNG
(AINn+ + AINn-)/2
Input Leakage Current
IIN_LEAK
Acquisition phase
Input Capacitance
www.maximintegrated.com
CIN
±VREF
V
-0.1
VAVDD
+ 0.1
V
VREF/2
- 0.1
VREF/2
+ 0.1
V
1
μA
10
pF
Maxim Integrated │ 2
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11192 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+1
Bits
Bits
LSB
STATIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Resolution
No Missing Codes
Offset Error
N
12
12
-1
OE
Offset Error TC
Gain Error
Gain Error TC
Integral Nonlinearity
Differential Nonlinearity
1.2
GE
(Note 2)
-1
(Note 2)
INL
DNL
Analog Input CMR
CMRR
Power-Supply Rejection
PSRR
Power Supply Rejection
PSRR
mLSB/°C
+1
LSB
+0.5
+0.25
mLSB/°C
LSB
LSB
1.2
-0.5
-0.25
Common Mode Range;
VREF/2 - 100mV to VREF/2 + 100mV
75
dB
AVDD
85
dB
OVDD
90
dB
INTERNAL REFERENCE
Initial Accuracy
TA = +25°C
2.498
Temperature Drift
2.500
2.502
5
V
ppm
EXTERNAL REFERENCE
Input Voltage Range
External reference applied to REFIN
2.5
VAVDD
- 0.25
External reference applied to REF1
or REF2
2.5
VAVDD
+ 0.1
V
REFERENCE BUFFERS
Bypass Capacitor
1.0
μF
DYNAMIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
Spurious-Free Dynamic Range
SFDR
THD
Total Harmonic Distortion
Crossalk
73
73.5
dB
10kHz input
73.5
dB
10kHz input
102
dB
10kHz input
-108
dB
10kHz input
-100
dB
73.5
dB
73.5
dB
DYNAMIC PERFORMANCE (VREFIN/OUT = 4.096V, EXTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
10kHz input
102
dB
THD
10kHz input
-108
dB
10kHz input
-100
dB
Total Harmonic Distortion
Crossalk
73
SAMPLING DYNAMICS
Throughput
2
Aperture Delay Match
Input -3db Bandwidth
www.maximintegrated.com
f-3dB
Msps
150
ps
50
MHz
Maxim Integrated │ 3
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11192 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.0
5.25
V
3.6
V
5.5
6.2
mA
0.75
1
mA
POWER SUPPLIES
Analog Supply Voltage
AVDD
3.0
Interface Supply Voltage
OVDD
1.7
Analog Supply Current
I(AVDD)
Interface Supply Current
I(OVDD)
DOUT load: CLOAD = 10pF
Analog Standby Current
IS(AVDD)
(Note 3)
1
mA
Interface Standby Current
IS(OVDD)
(Note 3)
1
μA
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
0.8 x
VOVDD
V
0.2 x
VOVDD
V
Input Capacitance
2
pF
Input Leakage
1
μA
DIGITAL OUTPUTS
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
VOVDD
- 0.4
V
VOGND
+ 0.4
V
TIMING
Conversion Period
t1
500
ns
SCLK to DOUT Hold
t2
1
ns
SCLK to DOUT Valid
t3
14
ns
SCLK High
t4
8
ns
SCLK Period
t5
20
ns
SCLK low
t6
8
ns
CNVST Rising Edge to SCLK
Rising Edge
t7
5
ns
SCLK Rising Edge to CNVST
Rising Edge
t8
5
ns
CNVST High
t9
60
ns
CNVST Falling Edge to SCLK
Rising Edge
t10
10
ns
SCLK Falling Edge to CNVST
Falling Edge
t11
0
ns
CNVST Low Time for Valid Sample
t12
400
ns
www.maximintegrated.com
Maxim Integrated │ 4
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11195
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Input Voltage Range
VIN(DIFF)
AINn+ – AINn-
Absolute Input Voltage Range
VIN(RNG)
AINn+/AINn- relative to GND
Common-Mode Input Voltage
Range
CMIRNG
(AINn+ + AINn-)/2
Input Leakage Current
IIN_LEAK
Acquisition phase
Input Capacitance
±VREF
V
-0.1
VAVDD
+ 0.1
V
VREF/2
- 0.1
VREF/2
+ 0.1
V
CIN
1
μA
10
pF
STATIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Resolution
No Missing Codes
Offset Error
N
14
14
-1.5
OE
Offset Error TC
+1.5
4
Gain Error
GE
Gain Error TC
Integral Nonlinearity
Differential Nonlinearity
INL
DNL
(Note 2)
-3.5
(Note 2)
Analog Input CMR
CMRR
Power-Supply Rejection
PSRR
Power Supply Rejection
PSRR
mLSB/°C
+3.5
LSB
+1.0
+0.5
mLSB/°C
LSB
LSB
2
-1.0
-0.5
Bits
Bits
LSB
Common Mode Range;
VREF/2 - 100mV to VREF/2 + 100mV
80
dB
AVDD
85
dB
OVDD
90
dB
INTERNAL REFERENCE
Initial Accuracy
TA = +25°C
2.498
Temperature Drift
2.500
2.502
5
V
ppm
EXTERNAL REFERENCE
Input Voltage Range
External reference applied to REFIN
2.5
VAVDD
- 0.25
External reference applied to REF1
or REF2
2.5
VAVDD
+ 0.1
V
REFERENCE BUFFERS
Bypass Capacitor
1.0
μF
DYNAMIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
Total Harmonic Distortion
Crossalk
www.maximintegrated.com
82
83.7
dB
83.7
dB
10kHz input
115
dB
10kHz input
-117
dB
10kHz input
-100
dB
Maxim Integrated │ 5
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11195 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
84
84.6
dB
84.7
dB
DYNAMIC PERFORMANCE (VREFIN/OUT = 4.096V, EXTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
10kHz input
112
dB
THD
10kHz input
-110
dB
10kHz input
-100
dB
Total Harmonic Distortion
Crossalk
SAMPLING DYNAMICS
Throughput
2
Aperture Delay Match
Input -3db Bandwidth
f-3dB
Msps
150
ps
50
MHz
POWER SUPPLIES
Analog Supply Voltage
AVDD
3.0
Interface Supply Voltage
OVDD
1.7
5.0
5.25
V
3.6
V
5.9
6.5
mA
0.75
1.1
mA
Analog Supply Current
I(AVDD)
Interface Supply Current
I(OVDD)
DOUT load: CLOAD = 10pF
Analog Standby Current
IS(AVDD)
(Note 3)
1
mA
Interface Standby Current
IS(OVDD)
(Note 3)
1
μA
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
0.8 x
VOVDD
V
0.2 x
VOVDD
V
Input Capacitance
2
pF
Input Leakage
1
μA
DIGITAL OUTPUTS
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
VOVDD
- 0.4
V
VOGND
+ 0.4
V
TIMING
Conversion Period
t1
500
ns
SCLK to DOUT Hold
t2
1
ns
SCLK to DOUT Valid
t3
14
ns
SCLK High
t4
8
ns
SCLK Period
t5
20
ns
SCLK low
t6
8
ns
CNVST Rising Edge to SCLK
Rising Edge
t7
5
ns
www.maximintegrated.com
Maxim Integrated │ 6
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11195 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Rising Edge to CNVST
Rising Edge
t8
5
ns
CNVST High
t9
60
ns
CNVST Falling Edge to SCLK
Rising Edge
t10
10
ns
SCLK Falling Edge to CNVST
Falling Edge
t11
0
ns
CNVST Low Time for Valid Sample
t12
400
ns
Electrical Characteristics—MAX11198
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Input Voltage Range
VIN(DIFF)
AINn+ – AINn-
Absolute Input Voltage Range
VIN(RNG)
AINn+/AINn- relative to GND
Common-Mode Input Voltage
Range
CMIRNG
(AINn+ + AINn-)/2
Input Leakage Current
IIN_LEAK
Acquisition phase
Input Capacitance
±VREF
V
-0.1
VAVDD
+ 0.1
V
VREF/2
- 0.1
VREF/2
+ 0.1
V
CIN
1
μA
10
pF
STATIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Resolution
No Missing Codes
Offset Error
N
16
16
-4
OE
Offset Error TC
Gain Error
Gain Error TC
Integral Nonlinearity
Differential Nonlinearity
+4
10
GE
(Note 2)
-4
(Note 2)
INL
DNL
Analog Input CMR
CMRR
Power-Supply Rejection
PSRR
Power Supply Rejection
PSRR
mLSB/°C
+4
LSB
+1.5
+0.5
mLSB/°C
LSB
LSB
5
-1.5
-0.5
Common Mode Range;
VREF/2 - 100mV to VREF/2 + 100mV
Bits
Bits
LSB
80.5
dB
AVDD
85
dB
OVDD
90
dB
INTERNAL REFERENCE
Initial Accuracy
Temperature Drift
www.maximintegrated.com
TA = +25°C
2.498
2.500
5
2.502
V
ppm
Maxim Integrated │ 7
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11198 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE
Input Voltage Range
External reference applied to REFIN
2.5
VAVDD
- 0.25
External reference applied to REF1
or REF2
2.5
VAVDD
+ 0.1
V
REFERENCE BUFFERS
Bypass Capacitor
1.0
μF
DYNAMIC PERFORMANCE (VREFIN/OUT = 2.5V, INTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
THD
Total Harmonic Distortion
Crossalk
86
89
dB
88.8
dB
10kHz input
115
dB
10kHz input
-117
dB
10kHz input
-100
dB
91.7
dB
91.6
dB
DYNAMIC PERFORMANCE (VREFIN/OUT = 4.096V, EXTERNAL REFERENCE)
Signal-to-Noise Ratio
SNR
10kHz input
Signal-to-Noise And Distortion Ratio
SINAD
10kHz input
Spurious-Free Dynamic Range
SFDR
10kHz input
114
dB
THD
10kHz input
-111
dB
10kHz input
-100
dB
Total Harmonic Distortion
Crossalk
90
SAMPLING DYNAMICS
Throughput
2
Aperture Delay Match
Input -3db Bandwidth
f-3dB
Msps
150
ps
50
MHz
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
AVDD
3.0
OVDD
1.7
I(AVDD)
5.0
5.25
V
3.6
V
6.3
7
mA
0.75
1.2
mA
Interface Supply Current
I(OVDD)
DOUT load: CLOAD = 10pF
Analog Standby Current
IS(AVDD)
(Note 3)
1
mA
Interface Standby Current
IS(OVDD)
(Note 3)
1
μA
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
0.8 x
VOVDD
V
0.2 x
VOVDD
V
Input Capacitance
2
pF
Input Leakage
1
μA
www.maximintegrated.com
Maxim Integrated │ 8
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Electrical Characteristics—MAX11198 (continued)
(fSample = 2MSPS; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX (Note 1). Typical values
are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS
Output Voltage High
VOH
ISOURCE = 2mA
Output Voltage Low
VOL
ISINK = 2mA
VOVDD
- 0.4
V
VOGND
+ 0.4
V
TIMING
Conversion Period
t1
500
ns
SCLK to DOUT Hold
t2
1
ns
SCLK to DOUT Valid
t3
14
ns
SCLK High
t4
8
ns
SCLK Period
t5
20
ns
SCLK low
t6
8
ns
CNVST Rising Edge to SCLK
Rising Edge
t7
5
ns
SCLK Rising Edge to CNVST
Rising Edge
t8
5
ns
CNVST High
t9
60
ns
CNVST Falling Edge to SCLK
Rising Edge
t10
10
ns
SCLK Falling Edge to CNVST
Falling Edge
t11
0
ns
CNVST Low Time for Valid Sample
t12
400
ns
Note 1: Units are 100% production tested at TA = +25°C and are guaranteed by design and characterization from TA = TMIN to TMAX.
Note 2: Exclude the reference drift and offset error.
Note 3: This current is drawn when the device has completed conversion and SCLK is idle.
www.maximintegrated.com
Maxim Integrated │ 9
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL B)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL A)
toc1A
0.8
0.6
0.6
0.4
0.4
GAIN ERROR
0
-0.2
OFFSET
-0.4
0.8
0.6
GAIN ERROR
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
20 35 50 65 80 95 110 125
3
TEMPERATURE (°C)
0.3
0.4
0.2
ERROR (LSB)
GAIN ERROR
0.2
0
-0.2
OFFSET
0.1
0.0
-0.1
GAIN ERROR
-0.2
0.1
0
-0.2
-0.3
-0.4
-1
-0.5
5
5.25
OUTPUT NOISE HISTOGRAM
(CHANNEL A)
toc4A
STDEVA=0
LSB
120000
3.5
4
4.5
2.5
toc4B
60000
40000
4.5
toc5A
0.08
0.06
100000
80000
4
0.10
STDEVB =
0LSB
120000
3.5
DNL vs. CODE
(CHANNEL A)
OUTPUT NOISE HISTOGRAM
(CHANNEL B)
140000
3
REFERENCE VOLTAGE(V)
0.04
DNL (LSB)
100000
3
REFERENCE VOLTAGE(V)
NUMBER OF OCCURRENCES
140000
-0.5
2.5
SUPPLY VOLTAGE(V)
OFFSET
-0.1
-0.4
4.25 4.5 4.75
GAIN ERROR
0.2
-0.3
4
5.25
toc3B
0.3
OFFSET
-0.8
3.25 3.5 3.75
5
0.4
-0.6
3
4.25 4.5 4.75
0.5
ERROR (LSB)
0.4
0.6
4
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE (CHANNEL B)
toc3A
0.5
0.8
3.25 3.5 3.75
SUPPLY VOLTAGE(V)
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE (CHANNEL A)
toc2B
1
-0.4
OFFSET
-1
-40 -25 -10 5
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL B)
ERROR (LSB)
0
-0.2
-0.8
20 35 50 65 80 95 110 125
GAIN ERROR
0.2
-0.4
OFFSET
TEMPERATURE (°C)
NUMBER OF OCCURRENCES
0.4
-0.6
-40 -25 -10 5
toc2A
1
ERROR (LSB)
0.8
0.2
toc1B
1
ERROR (LSB)
ERROR (LSB)
1
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL A)
80000
60000
0.02
0.00
-0.02
-0.04
40000
-0.06
0
0
OUTPUT CODE (DECIMAL)
www.maximintegrated.com
-0.08
-0.10
0
20000
0
20000
OUTPUT CODE (DECIMAL)
0
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
Maxim Integrated │ 10
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
DNL vs. TEMPERATURE
(CHANNEL A)
0.10
0.10
0.08
0.08
DNL (LSB)
0.00
-0.04
0.04
0.04
0.02
0.02
0.00
-0.08
-0.10
-0.10
-40 -25 -10 5
20 35 50 65 80 95 110 125
INL vs. TEMPERATURE
(CHANNEL B)
-0.06
-0.10
20 35 50 65 80 95 110 125
-40 -25 -10 5
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
0.10
0.10
0.08
0.08
0.08
0.06
0.06
MAX INL
DNL (LSB)
0.02
0.00
-0.02
MIN INL
0.04
0.02
0.02
0.00
-0.02
-0.04
-0.06
-0.06
-0.08
-0.08
-0.10
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
www.maximintegrated.com
MAX DNL
0.00
-0.02
-0.04
MIN DNL
-0.06
MIN DNL
-0.08
-0.10
-40 -25 -10 5
0.06
MAX DNL
0.04
-0.04
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
0.10
0.04
MIN INL
-0.08
-40 -25 -10 5
TEMPERATURE (oC)
0.00
-0.04
MIN DNL
-0.06
-0.08
MAX INL
-0.02
-0.02
-0.04
MIN DNL
-0.06
INL (LSB)
0.06
MAX DNL
DNL (LSB)
DNL (LSB)
0.04
-0.02
0.08
0.06
MAX DNL
0.02
0.10
INL (LSB)
0.06
INL vs. TEMPERATURE
(CHANNEL A)
DNL vs. TEMPERATURE
(CHANNEL B)
-0.10
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
Maxim Integrated │ 11
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
0.10
110
0.08
0.08
108
0.06
0.06
MAX INL
0.00
MIN INL
-0.04
0.00
-0.02
MIN INL
-0.04
CHB
102
100
98
96
-0.06
-0.06
94
-0.08
-0.08
92
-0.10
-0.10
CHA
90
0
50
100
150
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
INPUT IMPEDANCE (Ω)
FFT PLOT
(CHANNEL A)
FFT PLOT
(CHANNEL B)
FFT PLOT
(CHANNEL A)
NSAMPLE = 65536
fIN = 10kHz
VIN = -0.1dBFS
SNR = 73.6dB
THD = -105.1dB
SFDR = 103.4dB
-40
-60
-40
-80
-100
-120
0
NSAMPLE = 65536
fIN = 10kHz
VIN = -0.1dBFS
SNR = 73.6dB
THD = -104.9dB
SFDR = 102.7dB
-20
MAGNITUDE (dB)
-20
toc12B
0
-60
-40
-80
-100
-120
-60
-80
-120
-140
-140
-160
-160
-160
-180
-180
400
600
800
1000
0
200
400
FREQUENCY (kHz)
toc13B
-60
0
200
400
toc14A
-80
-100
-120
-40
-60
-80
-100
800
1000
FFT PLOT TWO TONES
(CHANNEL B)
NSAMPLE =
131072
fIN1 = 8.96kHz
VIN1 =
-6.5dBFS
fIN2 = 10.97kHz
VIN2 =
-6.5dBFS
F6.95KHz=110dBFS
F12.97KHz=110dBFs
IMD=103dB
-20
600
FREQUENCY (kHz)
0
MAGNITUDE (dB)
-40
-180
1000
FFT PLOT TWO TONES
(CHANNEL A)
NSAMPLE = 32768
fIN = 100kHz
VIN = -0.1dBFS
SNR = 73.5dB
THD = -96.3dB
SFDR = 99.7dB
-20
800
FREQUENCY (kHz)
FFT PLOT
(CHANNEL B)
0
600
toc14B
0
NSAMPLE =
131072
fIN1 = 8.96kHz
VIN1 =
-6.5dBFS
fIN2 = 10.97kHz
VIN2 = -6.5dBFS
F6.95Hz=
-110dBFS
F12.97Hz=
-110dBFs
IMD = 103dB
-20
MAGNITUDE (dB)
200
toc13A
-100
-140
0
200
NSAMPLE = 32768
fIN = 100kHz
VIN = -0.1dBFS
SNR = 73.6dB
THD = -96.2dB
SFDR = 99.9dB
-20
MAGNITUDE (dB)
toc12A
0
MAGNITUDE (dB)
104
0.02
THD (dB)
INL (LSB)
0.02
toc11
106
MAX INL
0.04
-0.02
MAGNITUDE (dB)
THD vs. INPUT IMPEDANCE
0.10
0.04
INL (LSB)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
-40
-60
-80
-100
-140
-120
-160
-180
0
200
400
600
FREQUENCY (kHz)
www.maximintegrated.com
800
1000
-120
-140
-140
6
7
8
9
10
11
FREQUENCY (kHz)
12
13
14
6
7
8
9
10
11
12
13
14
FREQUENCY (kHz)
Maxim Integrated │ 12
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. FREQUENCY
(CHANNEL A)
SNR AND SINAD vs. FREQUENCY
(CHANNEL B)
toc15A
75
toc15B
75
SNR
130
SINAD
72
120
73
THD AND SFDR (dB)
SNR AND SINAD (dB)
74
73
SINAD
72
71
71
70
70
toc16A
140
SNR
74
SNR AND SINAD (dB)
THD AND SFDR vs. FREQUENCY
(CHANNEL A)
THD
110
100
90
SFDR
80
70
0
20
40
60
80
100
60
0
20
FREQUENCY (kHz)
60
80
100
0
20
FREQUENCY (kHz)
toc16B
140
toc17B
100
90
SFDR
80
74
SNR AND SINAD (dB)
SNR AND SINAD (dB)
THD
110
100
SNR
74
120
80
75
SNR
130
60
SNR AND SINAD vs. TEMPERATURE
(CHANNEL B)
toc17A
75
40
FREQUENCY (kHz)
SNR AND SINAD vs. TEMPERATURE
(CHANNEL A)
THD AND SFDR vs. FREQUENCY
(CHANNEL B)
THD AND SFDR (dB)
40
73
SINAD
72
71
73
SINAD
72
71
70
70
60
0
20
40
60
80
THD AND SFDR vs. TEMPERATURE
(CHANNEL A)
-40 -25 -10 5
toc18A
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL A)
toc18B
140
toc19A
75
SNR
130
120
110
100
90
SFDR
80
70
THD AND SFDR (dB)
120
74
THD
110
100
90
SFDR
80
SNR AND SINAD (dB)
THD
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
THD AND SFDR vs. TEMPERATURE
(CHANNEL B)
130
THD AND SFDR (dB)
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FREQUENCY (kHz)
140
70
-40 -25 -10 5
100
73
SINAD
72
71
70
60
60
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
70
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
Maxim Integrated │ 13
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11192 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL B)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL A)
toc19B
75
72
120
THD
THD AND SFDR (dB)
SINAD
130
120
THD AND SFDR (dB)
73
110
100
90
SFDR
80
71
100
90
3
3.5
4
4.5
60
3
3.5
4
2.5
CHA
CHB
70
4.5
toc23
5
IAVDD
CURRENT (mA)
CURRENT (mA)
80
4
6
7
6
3.5
CURRENT vs. SAMPLING RATE
toc22
8
3
REFERENCE VOLTAGE (V)
CURRENT vs. TEMPERATURE
toc21
90
5
4
3
4
IAVDD
3
2
2
60
IOVDD
1
50
1
IOVDD
0
1
10
0
-40 -25 -10 5
100
INPUT FREQUENCY (kHz)
0
0.5
1.5
2
REFERENCE VOLTAGE
vs. TEMPERATURE
toc25
0.5
1
SAMPLING RATE (Msps)
OVDD STANDBY CURRENT
vs. TEMPERATURE
toc24
1.4
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
AVDD STANDBY CURRENT
vs. TEMPERATURE
toc26
2.505
0.4
1.3
1
0.9
CURRENT (uA)
IAVDD
1.1
0.2
0.1
IOVDD
0
-0.1
-0.2
0.8
-0.3
0.7
REFERENCE VOLTAGE (V)
0.3
1.2
CURRENT (mA)
4.5
VOLTAGE REFERENCE (V)
PSR vs. INPUT FREQUENCY
PSR (dB)
70
2.5
REFERENCE VOLTAGE (V)
100
SFDR
80
60
2.5
THD
110
70
70
toc20B
140
130
74
SNR AND SINAD (dB)
toc20A
140
SNR
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL B)
2.503
2.501
2.499
2.497
-0.4
0.6
-0.5
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
2.495
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 14
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
OFFSET AND GAIN ERROR
vs. TEMPERATURE
(CHANNEL B)
OFFSET AND GAIN ERROR
vs. TEMPERATURE (CHANNEL A)
toc1A
5
4
4
3
3
1
0
-1
GAIN ERROR
-2
1
0
-1
-2
0
-1
-4
-4
-4
-5
-5
-5
-40 -25 -10 5
3
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL A)
toc3A
5.0
4.0
3
3.0
OFFSET
ERROR (LSB)
0
-1
GAIN ERROR
1.0
0.0
-1.0
OFFSET
1
0
-1
-2
-3
-4
-4.0
-4
-5
-5.0
5
5.25
toc4A
140000
3
3.5
4
REFERENCE VOLTAGE(V)
4.5
2.5
toc4B
140000
NUMBER OF OCCURRENCES
40000
4.5
toc5A
0.08
0.06
100000
60000
4
0.10
120000
0.04
DNL (LSB)
80000
3.5
DNL vs. CODE
(CHANNEL A)
STDEVB = 0.2 LSB
100000
3
REFERENCE VOLTAGE(V)
OUTPUT NOISE HISTOGRAM
(CHANNEL B)
STDEVA = 0.3LSB
120000
GAIN ERROR
-5
2.5
SUPPLY VOLTAGE (V)
OUTPUT NOISE HISTOGRAM
(CHANNEL A)
5.25
OFFSET
2
-3.0
4.25 4.5 4.75
5
toc3B
3
GAIN ERROR
-3
4
4.25 4.5 4.75
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL B)
5
-2.0
3.25 3.5 3.75
4
4
2.0
1
3
3.25 3.5 3.75
SUPPLY VOLTAGE(V)
ERROR (LSB)
toc2B
4
-2
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OFFSET AND GAIN ERROR
vs. SUPPLY VOLTAGE
(CHANNEL B)
2
GAIN ERROR
-2
GAIN ERROR
TEMPERATURE (°C)
ERROR (LSB)
1
-3
5
OFFSET
2
-3
20 35 50 65 80 95 110 125
toc2A
3
OFFSET
-3
-40 -25 -10 5
NUMBER OF OCCURRENCES
5
4
2
OFFSET
toc1B
ERROR (LSB)
2
ERROR (LSB)
ERROR (LSB)
5
OFFSET AND GAIN ERROR
vs. SUPPLY VOLTAGE
(CHANNEL A)
80000
60000
0.02
0.00
-0.02
-0.04
40000
-0.06
20000
20000
0
0
-5
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
www.maximintegrated.com
3
4
5
-0.08
-0.10
-5
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
3
4
5
0
4000
8000
12000
16000
OUTPUT CODE (DECIMAL)
Maxim Integrated │ 15
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
DNL vs. CODE
(CHANNEL B)
INL vs. CODE
(CHANNEL A)
0.40
0.40
0.08
0.30
0.30
0.20
0.20
0.10
0.10
INL (LSB)
0.02
0.00
-0.02
0.00
-0.10
-0.20
-0.20
-0.08
-0.30
-0.30
-0.10
-0.40
-0.06
0
4000
8000
12000
8000
12000
16000
0
DNL vs. TEMPERATURE
(CHANNEL B)
DNL vs. TEMPERATURE
(CHANNEL A)
0.40
0.20
DNL (LSB)
0.10
0.00
-0.10
toc7B
MIN DNL
0.40
MAX DNL
0.00
-0.30
-0.40
-40 -25 -10 5
20 35 50 65 80 95 110 125
MIN DNL
0.00
-0.80
20 35 50 65 80 95 110 125
-40 -25 -10 5
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
0.80
0.40
0.40
0.60
0.30
0.30
0.40
0.20
MAX INL
DNL (LSB)
0.20
0.00
-0.20
MIN INL
0.00
-0.10
-0.40
-0.20
-0.60
-0.30
-0.80
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
www.maximintegrated.com
toc9B
MAX DNL
0.10
0.00
-0.10
MIN DNL
-0.20
MIN DNL
-0.30
-0.40
-40 -25 -10 5
0.20
MAX DNL
0.10
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
INL vs. TEMPERATURE
(CHANNEL B)
MIN INL
-0.40
-0.60
-40 -25 -10 5
TEMPERATURE (oC)
MAX INL
0.20
-0.20
-0.20
-0.40
16000
0.60
0.10
-0.30
12000
0.80
-0.10
-0.20
8000
INL vs. TEMPERATURE
(CHANNEL A)
0.30
MAX DNL
4000
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
0.30
0.20
4000
INL (LSB)
0.40
-0.40
0
16000
OUTPUT CODE (DECIMAL)
DNL (LSB)
0.00
-0.10
-0.04
DNL (LSB)
DNL (LSB)
0.04
INL (LSB)
0.10
0.06
INL (LSB)
INL vs. CODE
(CHANNEL B)
-0.40
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
Maxim Integrated │ 16
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
toc10A
0.60
0.60
0.40
0.40
MAX INL
INL (LSB)
0.20
0.00
-0.20
110
MAX INL
0.20
0.00
105
100
CHB
95
MIN INL
90
85
-0.60
-0.80
-0.80
80
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
INPUT IMPEDANCE (Ω )
FFT PLOT
(CHANNEL A)
FFT PLOT
(CHANNEL B)
FFT PLOT
(CHANNEL A)
NSAMPLE = 131072
fIN = 10kHz
VIN = -0.1dBFS
SNR = 83.8dB
THD = -112.1dB
SFDR = 116dB
-40
-60
toc12B
0
NSAMPLE = 131072
fIN = 10kHz
VIN = -0.1dBFS
SNR = 83.9dB
THD = -110.6dB
SFDR = 115.2dB
-20
-40
MAGNITUDE (dB)
-20
-80
-100
-120
0
-60
-80
-100
-120
-80
-100
-120
-140
-160
-160
-180
-180
800
1000
-180
0
200
400
FREQUENCY (kHz)
-60
0
-40
-80
-100
-120
-60
-80
-100
-120
-140
-160
-140
-180
-160
0
200
400
600
FREQUENCY (kHz)
www.maximintegrated.com
200
400
800
1000
600
800
FFT PLOT TWO TONES
(CHANNEL B)
toc14A
NSAMPLE =
131072
fIN1 = 8.93kHz
VIN1 =
-6.5dBFS
fIN2 = 10.93kHz
VIN2 =
-6.5dBFS
F6.93KHz=120dBFS
F12.92KHz=120dBFs
IMD=113.5dB
-20
MAGNITUDE (dB)
-40
0
1000
1000
FREQUENCY (kHz)
FFT PLOT TWO TONES
(CHANNEL A)
toc13B
NSAMPLE = 131072
fIN = 100kHz
VIN = -0.1dBFS
SNR = 83.5dB
THD = -99.9dB
SFDR = 101.4dB
-20
800
FREQUENCY (kHz)
FFT PLOT
(CHANNEL B)
0
600
0
toc14B
NSAMPLE =
131072
fIN1 = 8.93kHz
VIN1 =
-6.5dBFS
fIN2 = 10.93kHz
VIN2 =
-6.5dBFS
F6.93Hz=119dBFS
F12.92Hz=119dBFs
IMD=112.5dB
-20
MAGNITUDE (dB)
600
200
toc13A
-60
-160
400
150
NSAMPLE = 131072
fIN = 100kHz
VIN = -0.1dBFS
SNR = 83.4dB
THD = -104.2dB
SFDR = 101.6dB
-40
-140
200
100
-20
-140
0
50
0
MAGNITUDE (dB)
toc12A
0
MAGNITUDE (dB)
CHA
-0.40
-0.60
toc11
115
-0.20
MIN INL
-0.40
MAGNITUDE (dB)
THD vs. INPUT IMPEDANCE
toc10B
0.80
THD (dB)
0.80
INL (LSB)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
-40
-60
-80
-100
-120
-140
-160
6
7
8
9
10
11
FREQUENCY (kHz)
12
13
14
6
7
8
9
10
11
12
13
14
FREQUENCY (kHz)
Maxim Integrated │ 17
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. FREQUENCY
(CHANNEL A)
toc15A
85
toc15B
86
83
SNR AND SINAD (dB)
84
SINAD
82
81
SNR
83
SINAD
82
40
60
80
100
20
FREQUENCY (kHz)
SFDR
80
40
60
80
100
0
20
40
85
SNR AND SINAD (dB)
120
THD
100
90
SFDR
100
toc17B
86
85
SNR
84
83
80
SNR AND SINAD vs. TEMPERATURE
(CHANNEL B)
toc17A
86
130
60
FREQUENCY (kHz)
SNR AND SINAD vs. TEMPERATURE
(CHANNEL A)
toc16B
140
SINAD
82
SNR
84
83
SINAD
82
80
81
70
80
60
0
20
40
60
80
110
THD
90
THD AND SFDR (dB)
120
70
70
60
THD
90
80
TEMPERATURE (°C)
www.maximintegrated.com
84
SINAD
83
82
81
60
20 35 50 65 80 95 110 125
SNR
85
110
100
toc19A
86
SFDR
120
80
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL A)
toc18B
130
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
140
SFDR
-40 -25 -10 5
-40 -25 -10 5
THD AND SFDR vs. TEMPERATURE
(CHANNEL B)
toc18A
100
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
THD AND SFDR vs. TEMPERATURE
(CHANNEL A)
140
80
-40 -25 -10 5
100
FREQUENCY (kHz)
130
81
SNR AND SINAD (dB)
THD AND SFDR (dB)
90
FREQUENCY (kHz)
THD AND SFDR vs. FREQUENCY
(CHANNEL B)
110
100
60
0
SNR AND SINAD (dB)
20
THD
110
70
80
0
THD AND SFDR (dB)
120
84
81
80
toc16A
140
130
85
SNR
THD AND SFDR vs. FREQUENCY
(CHANNEL A)
THD AND SFDR (dB)
86
SNR AND SINAD (dB)
SNR AND SINAD vs. FREQUENCY
(CHANNEL B)
80
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
Maxim Integrated │ 18
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11195 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL B)
toc19B
86
SINAD
83
82
80
120
110
100
THD
90
3
3.5
4
110
100
80
70
70
60
2.5
3
3.5
4
4.5
2.5
VOLTAGE REFERENCE (V)
REFERENCE VOLTAGE (V)
toc21
CHA
7
90
3.5
4
4.5
CURRENT vs. SAMPLING RATE
toc22
8
3
REFERENCE VOLTAGE (V)
CURRENT vs. TEMPERATURE
PSR vs. INPUT FREQUENCY
100
THD
90
80
4.5
SFDR
120
60
2.5
toc23
6
IAVDD
5
80
CHB
70
CURRENT (mA)
6
CURRENT (mA)
5
4
3
4
IAVDD
3
2
2
60
IOVDD
1
50
1
IOVDD
0
1
10
0
-40 -25 -10 5
100
INPUT FREQUENCY (kHz)
AVDD STANDBY CURRENT
vs. TEMPERATURE
0
0.5
1.5
2
REFERENCE VOLTAGE
vs. TEMPERATURE
toc25
0.5
1
SAMPLING RATE (Msps)
OVDD STANDBY CURRENT
vs. TEMPERATURE
toc24
1.4
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
toc26
2.505
0.4
1.3
0.3
1.2
CURRENT (µA)
IAVDD
1.1
1
0.9
0.2
0.1
IOVDD
0
-0.1
-0.2
0.8
-0.3
0.7
REFERENCE VOLTAGE (V)
PSR (dB)
130
SFDR
THD AND SFDR (dB)
THD AND SFDR (dB)
84
toc20B
140
130
81
CURRENT (mA)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL B)
toc20A
140
SNR
85
SNR AND SINAD (dB)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL A)
2.503
2.501
2.499
2.497
-0.4
0.6
-0.5
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
2.495
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 19
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL A)
toc1A
4
3
3
ERROR (LSB)
GAIN ERROR
2
1
0
-1
OFFSET
toc1B
5
4
4
1
0
-1
2
0
-1
-2
-3
-3
-4
-4
-4
-5
-5
-2
OFFSET
20 35 50 65 80 95 110 125
3
TEMPERATURE (°C)
toc2B
5
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL A)
toc3A
5.0
4.0
4
3.0
3
0
-1
0.0
-1.0
-2.0
OFFSET
-2
GAIN ERROR
-3
-4.0
-4
-5.0
4
4.25 4.5 4.75
5
5.25
3
3.5
4
toc4B
40000
30000
20000
10000
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
www.maximintegrated.com
3
4
5
4.5
toc5A
0.30
60000
0.20
50000
40000
30000
0.10
0.00
-0.10
20000
-0.20
10000
-0.30
0
4
0.40
DNL (LSB)
NUMBER OF OCCURRENCES
50000
3.5
DNL vs. CODE
(CHANNEL A)
STDEVB = 0.9LSB
60000
3
REFERENCE VOLTAGE (V)
70000
STDEVA=0.8 LSB
-3
2.5
OUTPUT NOISE HISTOGRAM
(CHANNEL B)
toc4A
70000
-4
4.5
REFERENCE VOLTAGE (V)
OUTPUT NOISE HISTOGRAM
(CHANNEL A)
-5
OFFSET
-5
2.5
SUPPLY VOLTAGE (V)
0
GAIN ERROR
0
-4
3.25 3.5 3.75
5.25
-1
-3.0
3
5
1
-3
-5
4.25 4.5 4.75
toc3B
2
OFFSET
1.0
ERROR (LSB)
ERROR (LSB)
2.0
1
4
OFFSET AND GAIN ERROR vs.
REFERENCE VOLTAGE
(CHANNEL B)
5
3
GAIN ERROR
3.25 3.5 3.75
SUPPLY VOLTAGE (V)
4
-2
OFFSET
-5
-40 -25 -10 5
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL B)
2
GAIN ERROR
1
-3
TEMPERATURE (°C)
ERROR (LSB)
3
GAIN ERROR
2
20 35 50 65 80 95 110 125
toc2A
5
-2
-40 -25 -10 5
NUMBER OF OCCURRENCES
OFFSET AND GAIN ERROR vs.
SUPPLY VOLTAGE (CHANNEL A)
ERROR (LSB)
5
ERROR (LSB)
OFFSET AND GAIN ERROR vs.
TEMPERATURE (CHANNEL B)
-0.40
-5
-4
-3
-2
-1
0
1
2
OUTPUT CODE (DECIMAL)
3
4
5
0
10000 20000 30000 40000 50000 60000
OUTPUT CODE (DECIMAL)
Maxim Integrated │ 20
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
DNL vs. CODE
(CHANNEL B)
INL vs. CODE
(CHANNEL A)
1.00
1.00
0.30
0.80
0.80
0.60
0.60
0.40
0.40
INL (LSB)
DNL (LSB)
0.10
0.00
0.20
0.00
0.20
0.00
-0.20
-0.20
-0.40
-0.40
-0.60
-0.60
-0.30
-0.80
-0.80
-0.40
-1.00
-0.10
-0.20
0
10000 20000 30000 40000 50000 60000
-1.00
0
OUTPUT CODE (DECIMAL)
10000 20000 30000 40000 50000 60000
0
OUTPUT CODE (DECIMAL)
DNL vs. TEMPERATURE
(CHANNEL B)
DNL vs. TEMPERATURE
(CHANNEL A)
0.40
0.40
0.30
0.30
INL vs. TEMPERATURE
(CHANNEL A)
toc7B
0.80
0.60
0.40
0.20
MAX DNL
DNL (LSB)
0.10
0.00
-0.10
MAX DNL
0.10
0.00
-0.10
MIN DNL
0.00
MIN DNL
-0.40
-0.30
-0.30
-0.60
-0.40
-0.40
-0.80
-40 -25 -10 5
TEMPERATURE (oC)
20 35 50 65 80 95 110 125
-40 -25 -10 5
TEMPERATURE (oC)
INL vs. TEMPERATURE
(CHANNEL B)
0.40
0.60
0.30
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
toc9A
0.30
MIN INL
-0.20
0.20
MAX DNL
0.10
DNL (LSB)
0.00
DNL (LSB)
MAX INL
0.20
0.00
-0.10
MIN DNL
0.10
-0.20
-0.20
-0.60
-0.30
-0.30
-0.80
-0.40
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
www.maximintegrated.com
MAX DNL
0.00
-0.10
-0.40
-40 -25 -10 5
toc9B
0.40
0.20
0.40
20 35 50 65 80 95 110 125
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
0.80
MIN INL
-0.20
-0.20
20 35 50 65 80 95 110 125
MAX INL
0.20
-0.20
-40 -25 -10 5
10000 20000 30000 40000 50000 60000
OUTPUT CODE (DECIMAL)
INL (LSB)
0.20
DNL (LSB)
INL (LSB)
0.40
0.20
INL (LSB)
INL vs. CODE
(CHANNEL B)
MIN DNL
-0.40
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
Maxim Integrated │ 21
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL A)
toc10A
0.80
0.60
0.60
0.40
0.40
0.20
INL (LSB)
MAX INL
0.00
-0.20
THD vs. INPUT IMPEDANCE
toc10B
110
CHA
0.00
-0.40
-0.40
-0.60
-0.60
-0.80
105
MAX INL
0.20
MIN INL
-0.20
MIN INL
toc11
115
THD (dB)
0.80
INL (LSB)
INL vs. AVDD SUPPLY VOLTAGE
(CHANNEL B)
100
CHB
95
90
-0.80
85
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
0
50
100
FFT PLOT
(CHANNEL A)
-60
-40
-80
-100
-120
-60
-80
-100
-120
-140
-140
-160
-160
-180
0
200
400
600
800
NSAMPLE = 131072
fIN = 100kHz
VIN = -0.1dBFS
SNR = 87.2dB
THD = -108.4dB
SFDR = 101.6dB
-20
MAGNITUDE (dB)
MAGNITUDE (dB)
-40
toc13A
0
NSAMPLE = 131072
fIN = 10kHz
VIN = -0.1dBFS
SNR = 89.3dB
THD = -113.3dB
SFDR = 118.6dB
-20
-180
1000
0
200
400
FREQUENCY (kHz)
FFT PLOT TWO TONES
(CHANNEL A)
-60
toc14A
0
NSAMPLE =
131072
fIN1 = 8.96kHz
VIN1 =
-6dBFS
fIN2 = 10.97kHz
VIN2 =
-6dBFS
F6.95KHz=129dBFS
F12.97KHz=129dBFs
IMD=123dB
-20
-40
MAGNITUDE (dB)
MAGNITUDE (dB)
-40
-80
-100
-120
-60
-80
-100
-120
-140
-160
400
600
FREQUENCY (kHz)
www.maximintegrated.com
800
1000
NSAMPLE =
131072
fIN1 = 8.96kHz
VIN1 =
-6dBFS
fIN2 = 10.97kHz
VIN2 =
-6dBFS
F6.95Hz=122dBFS
F12.97Hz=122dBFs
IMD=116dB
-40
-60
-80
-100
-120
-140
-160
-180
200
1000
toc14B
0
-20
-140
0
800
FFT PLOT TWO TONES
(CHANNEL B)
MAGNITUDE (dB)
toc13B
NSAMPLE = 131072
fIN = 100kHz
VIN = -0.1dBFS
SNR = 87.2dB
THD = -108.2dB
SFDR = 101.7dB
-20
600
FREQUENCY (kHz)
FFT PLOT
(CHANNEL B)
0
200
FFT PLOT
(CHANNEL A)
toc12A
0
150
INPUT IMPEDANCE (Ω )
-160
6
7
8
9
10
11
FREQUENCY (kHz)
12
13
14
6
7
8
9
10
11
12
13
14
FREQUENCY (kHz)
Maxim Integrated │ 22
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. FREQUENCY
(CHANNEL A)
SNR AND SINAD vs. FREQUENCY
(CHANNEL B)
toc15A
92
130
SNR
88
SINAD
87
86
85
120
THD AND SFDR (dB)
SNR AND SINAD (dB)
90
89
89
88
SINAD
87
86
85
84
20
40
60
80
100
THD
110
100
90
SFDR
80
70
84
0
toc16A
140
91
SNR
90
SNR AND SINAD (dB)
toc15B
92
91
THD AND SFDR vs. FREQUENCY
(CHANNEL A)
60
0
20
FREQUENCY (kHz)
40
60
80
100
0
20
40
FREQUENCY (kHz)
SNR AND SINAD vs. TEMPERATURE
(CHANNEL A)
THD AND SFDR vs. FREQUENCY
(CHANNEL B)
toc16B
140
80
100
SNR AND SINAD vs. TEMPERATURE
(CHANNEL B)
toc17A
91
60
FREQUENCY (kHz)
toc17B
91
130
110
100
90
SFDR
90
SNR AND SINAD (dB)
SNR AND SINAD (dB)
89
88
80
SINAD
87
60
0
20
40
60
80
toc18B
100
THD
80
THD AND SFDR (dB)
110
94
100
80
60
60
TEMPERATURE (°C)
THD
90
70
20 35 50 65 80 95 110 125
93
110
70
toc19A
95
SFDR
120
www.maximintegrated.com
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL A)
130
120
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
140
SFDR
-40 -25 -10 5
-40 -25 -10 5
THD AND SFDR vs. TEMPERATURE
(CHANNEL B)
toc18A
90
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
THD AND SFDR vs. TEMPERATURE
(CHANNEL A)
140
87
-40 -25 -10 5
100
FREQUENCY (kHz)
THD AND SFDR (dB)
89
88
70
130
SNR
90
SINAD
SNR AND SINAD (dB)
THD AND SFDR (dB)
SNR
THD
120
SNR
92
91
90
SINAD
89
88
87
86
85
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
Maxim Integrated │ 23
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Typical Operating Characteristics—MAX11198 (continued)
(fSAMPLE = 2Msps; VAVDD = 5.0V, VOVDD = 1.8V; VREFIN/OUT = 2.5V (Internal Reference); TA = TMIN to TMAX. Typical values are at
TA = +25ºC, unless otherwise noted.)
SNR AND SINAD vs. REFERENCE
VOLTAGE (CHANNEL B)
toc19B
95
130
92
91
90
SINAD
89
88
SFDR
120
110
100
THD
90
110
100
80
70
70
86
85
60
60
2.5
3
3.5
4
4.5
2.5
3.5
4
2.5
4.5
toc21
7
CHB
70
5
5
4
3
10
IOVDD
0
-40 -25 -10 5
100
INPUT FREQUENCY (kHz)
20 35 50 65 80 95 110 125
0
toc25
0.5
1
1.5
2
REFERENCE VOLTAGE
vs. TEMPERATURE
OVDD STANDBY CURRENT
vs. TEMPERATURE
toc24
0.5
SAMPLING RATE (Msps)
TEMPERATURE (°C)
AVDD STANDBY CURRENT
vs. TEMPERATURE
1.4
3
1
0
1
IAVDD
4
2
IOVDD
1
50
toc23
6
2
60
4.5
IAVDD
CURRENT (mA)
CURRENT (mA)
CHA
4
7
6
80
3.5
CURRENT vs. SAMPLING RATE
toc22
8
3
REFERENCE VOLTAGE(V)
CURRENT vs. TEMPERATURE
PSR vs. INPUT FREQUENCY
90
3
VOLTAGE REFERENCE (V)
REFERENCE VOLTAGE (V)
100
THD
90
80
87
SFDR
120
THD AND SFDR (dB)
THD AND SFDR (dB)
toc26
2.505
0.4
1.3
1.2
0.3
CURRENT (uA)
IAVDD
1.1
1
0.9
0.2
0.1
IOVDD
0
-0.1
-0.2
0.8
2.503
2.501
2.499
2.497
-0.3
0.7
REFERENCE VOLTAGE (V)
SNR AND SINAD (dB)
SNR
toc20B
140
130
93
PSR (dB)
toc20A
140
94
CURRENT (mA)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL B)
THD AND SFDR vs. REFERENCE
VOLTAGE (CHANNEL A)
-0.4
0.6
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
2.495
-0.5
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 24
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Pin Configuration
1
AIN1-
AIN2+
AVDD
AIN1+
AGND
TOP VIEW
16
15
14
REFIN/OUT
2
13
REF1
3
12
REFGND
MAX11192
MAX11195
MAX11198
AIN2-
4
11
REF2
CNVST
5
10
SCLK
OGND
6
9
OVDD
7
8
DOUT2
DOUT1
TDFN
2mm x 3mm
EXPOSED PAD IS CONNECTED TO AGND
www.maximintegrated.com
Maxim Integrated │ 25
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Pin Description
PIN
NAME
1
AIN1+
ADC1 Positive (+) Analog Input
FUNCTION
2
AIN1-
ADC1 Negative (-) Analog Input
3
AIN2+
ADC2 Positive (+) Analog Input
4
AIN2-
ADC2 Negative (-) Analog Input
5
CNVST
Conversion Start Input
6
OGND
Ground (IO Ground)
7
DOUT1
Serial Interface Data Out for ADC1
8
DOUT2
Serial Interface Data Out for ADC2
9
OVDD
IO Supply. Bypass with a 10μF capacitor to ground
10
SCLK
Serial Interface Clock
11
REF2
REF2 Bypass Pin. Bypass with a 1μF capacitor to ground
12
REFGND
Ground (Reference Ground)
13
REF1
14
REFIN/OUT
REF1 Bypass Pin. Bypass with a 1μF capacitor to ground
15
AVDD
Analog Supply Pin. Bypass with a 10μF capacitor to ground
16
AGND
Ground
External Reference Input or Internal Reference Decoupling. Bypass with 1μF capacitor to ground
Functional Diagram
+5.0V
REF1
REF2
REFIN/OUT
AVDD
REFBUFFER
MAX11192
MAX11195
MAX11198
VOLTAGE
REFERENCE
REFBUFFER
+1.8V
OVDD
DOUT1
AIN1+
+
Interface
SAR ADC
AIN1-
AIN2+
CNVST
SCLK
+
SAR ADC
Interface
AIN2-
DOUT2
REFGND
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AGND
OGND
Maxim Integrated │ 26
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Detailed Description
The MAX11192/MAX11195/MAX11198 are a family of
12-/14-/16-bit, 2-channel, 2Msps, SAR ADCS with simultaneous sampling, balanced differential inputs, and a
separate data output for each channel. These ADCs
feature best-in-class sample rate and resolution in a tiny
2mm x 3mm package. An integrated voltage reference
and reference buffers help to minimize board space,
component count, and system cost. An internal oscillator
sets conversion time, thereby simplifying external timing
requirements.
For fast throughput, the SPI-compatible digital interface
includes two data out pins (DOUT1 and DOUT2). DOUT1
provides conversion data from ADC1, while DOUT2 provides conversion data from ADC2. Data bits are clocked
out on the rising edge of SCLK.
Analog Inputs
The analog inputs of the MAX11192/MAX11195/
MAX11198, AINn+ and AINn-, should be driven with balanced differential signals. The input signals can range
from 0V to VREF. Thus, the differential input interval
VDIFF = (AINn+) - (AINn-) ranges from – VREF to + VREF,
and the full-scale range is:
The nominal resolution step width of the least significant
bit (LSB) is:
LSB
=
FSR
2N
=
2 × VREF
2N
, N = 12/14/16
The differential analog input must be centered with respect
to a common mode signal of VREF/2, with a tolerance of
±100mV. The reference voltage can range from 2.5V to
250mV below the reference supply AVDD. This will guarantee adequate headroom for the internal reference buffers. Figure 1 illustrates signal ranges for AINn+/AINn-, reference voltage VREF and reference supply voltage AVDD.
Figure 2 shows the analog input equivalent circuit of
MAX11192/MAX11195/MAX11198. The ADC samples
both inputs, AINn+ and AINn-, with a differential on-chip
track-and-hold exhibiting no pipeline delay or latency.
Each analog input (see Figure 2) has dedicated input
clamps to protect from overranging. Diodes D1 and D2
provide ESD protection and act as a clamp for the input
voltages. Diodes D1/D2 can sustain a maximum forward
current of 100mA. The sampling switches connect the
inputs to the sampling capacitors.
FSR = 2 × VREF
AVDD
V
D1
VREF + 250mV ≤ VAVDD ≤ 5.25V
RON
250Ω
AINn+
AVDD
≥ 250mV
VREF
VDC
AINn+
AVDD
0.5VREF
D1
AINn-
0V
Figure 1. Input Signal Ranges
www.maximintegrated.com
CIN 7pF
D2
VREF ≤ 5V
RON
250Ω
AINnTIME
D2
CIN 7pF
Figure 2. Simplified Model of Input Sampling Circuit
Maxim Integrated │ 27
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
The ADCs go back into track phase on the rising edge
of CNVST. To achieve accurate conversion results, each
ADC should track its input signal for an interval longer than
the input signal's settling time. If the signal cannot settle
within the allocated track time due to excessive source
resistance, external ADC drivers are recommended to
achieve faster settling. Note that, since the MAX11192/
MAX11195/MAX11198 has a fixed conversion time set
by an internal oscillator, reducing the sample rate can
increase the track time.
The settling behavior is determined by the time constant
in the sampling network. The time constant depends upon
the total resistance (source resistance + switch resistance, RON) and total capacitance (sampling capacitor
CIN, external input capacitor, PCB parasitic capacitors,
1 / SAMPLE RATE
3) To take full advantage of the ADC’s excellent dynamic
performance, we recommend the use of ADC drivers
with equal or even better THD performance. This will
ensure that the ADC drivers do not limit distortion performance in the signal path. The ADC drivers listed in
Table 1 are all excellent choices.
SAMPLE 1
1 / SAMPLE RATE
SAR CONVERSION 2
TRACK 3
MSB
MSB-1
MSB-2
READ DATA (SAMPLE 1)
LSB
MSB
CLK 2
LSB+1
CLK 1
LSB+2
CLK N
SAMPLE 3
CLK N-2
SAMPLE 2
SAR CONVERSION 3
MSB-1
CLK 3
TRACK 2
CLK N-1
DOUT1/2
SAR CONVERSION 1
CLK 2
CLK
2) Low noise: It is important to ensure that the ADC
driver has a sufficiently low noise density in the bandwidth of interest. When the MAX11192/MAX11195/
MAX11198 is used with its full bandwidth of 50MHz, it
is preferable to use an amplifier with an output noise
spectral density of less than 6nV√Hz, to ensure that
the overall SNR is not degraded significantly. It is recommended to insert an external RC filter at the ADC
input to attenuate out-of-band input noise.
1 / SAMPLE RATE
CLK 1
CNVST
1) Fast settling time: For a multichannel multiplexed
circuit,the ADC driver amplifier must be able to settle
with an error less than 0.5 LSB during the minimum
track time when a full-scale step is applied.
CLK 3
TRACK 1
When an ADC driver amplifier is used, it is recommended to use a series resistance (typically 5Ω to 50Ω)
between the amplifier and the ADC inputs, as shown in
the Application Diagram. The following are some of the
requirements for the ADC driver amplifier.
MSB-2
LSB+2
LSB+1
CLK N
Figure 3 shows the timing of the conversion cycle's track,
SAR conversion, and read data operations. In the track
phase, starting with the rising edge of CNVST, the sample
switches are closed and the analog inputs are directly
connected to the sample capacitors. The source resistance
determines the charging of the sample capacitor to the
input voltage. The falling edge of CNVST is the sampling
instant for the ADCs. At this instant, the track phase ends,
the sample switches open, and the ADC enters into the
successive approximation (SAR) conversion phase. In the
conversion phase, a comparator compares the voltage
on the sample capacitor against the internal DAC value,
which cycles through values of binary-weighted fractions
of VREF using the successive approximation technique.
The final result is read through the SPI bus. Note that
ADC1 and ADC2 operate in parallel and conversion data
is available simultaneously through DOUT1 and DOUT2.
etc). Modeling the input circuit with a single pole network,
the time constant, RTOTAL× CLOAD, of the input should
not exceed tTRACK/12, where RTOTAL is the total resistance (source resistance + switch resistance), CLOAD is
the total capacitance (sampling capacitor, external input
capacitor, PCB parasitic capacitor), and tTRACK is the
track time.
CLK N-1
Input Settling
CLK N-2
MAX11192/MAX11195/
MAX11198
LSB
READ DATA (SAMPLE 2)
Figure 3. Conversion Timing: Track, SAR Conversion, and Read Operations
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Maxim Integrated │ 28
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Table 1. ADC Driver Amplifier Recommendations
AMPLIFIER
INPUT-NOISE SMALL-SIGNAL
DENSITY
BANDWIDTH
(NV/√Hz)
(MHZ)
SLEW
RATE
(V/ΜS)
THD
(DB)
ICC
(MA)
MAX
OFFSET
(MV)
COMMENTS
MAX44263
12.7
15
7
-110
0.75
0.05
Low current, low THD at
10kHz
MAX44242
5
10
8
-124
1.2
0.6
High voltage 2.7V to 20V,
low THD at 1kHz
MAX9632
1
55
30
-128
3.9
0.125
+2.5V
+2.5V
REF1
REF2
Low noise, low THD at
10kHz
+2.5V
+3.3V to
+5.25V
REFIN/OUT
AVDD
REFBUFFER
VOLTAGE
REFERENCE
+1.8V
OVDD
REFBUFFER
MAX11192
MAX11195
MAX11198
Figure 4. Internal Reference
Input Filtering
Noisy input signals should be filtered prior to the ADC
driver amplifier input with an appropriate filter to minimize
noise. The RC network shown in the Application Diagram
is mainly designed to reduce the load transient seen by
the amplifier when the ADC starts the track phase. This
network has to satisfy the settling time requirement and
provides the benefit of limiting the noise bandwidth.
Voltage Reference Configurations
Using An Internal Reference
The MAX11192/MAX11195/MAX11198 feature a 2.5V
integrated reference with built-in reference buffers that
help to reduce component count and board space. When
using internal reference, only bypass capacitors are
required on the REF1, REF2, and REFIN/OUT pins (see
www.maximintegrated.com
Figure 4). The REF1/REF2 pins require external bypass
capacitors of at least 1μF.
Using An External Reference
To use an external reference (see Figure 5), drive the
REFIN/OUT pin directly with an external reference voltage source, ensuring that the reference voltage is no
greater than AVDD - 250mV. This will allow the on-chip
reference buffers to operate with sufficient supply headroom. The REF1/REF2 pins require external bypass
capacitors of at least 1μF.
Table 2 lists excellent choices for low-noise, low-temperature drift external references.
Transfer Function
Figure 6 shows the ideal transfer characteristics for the
MAX11192/MAX11195/MAX11198.
Maxim Integrated │ 29
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
+VREF
+VREF
+VREF
VOLTAGE
REFERENCE
VREF + 0.25V
TO
5.25V
REF1
REFIN/OUT
REF2
AVDD
REFBUFFER
VOLTAGE
REFERENCE
+1.8V
OVDD
REFBUFFER
MAX11192
MAX11195
MAX11198
Figure 5. External Reference
Table 2. External Reference Recommendations
REFERENCE
INITIAL
ACCURACY (%)
TEMPERATURE DRIFT
MAX (PPM/°C)
MAX6070
±0.04
15
7
Low noise
MAX6133
±0.04
3
16
Very low drift
MAX6072
±0.04
6
9
Dual reference
OUTPUT CODE
(TWO’S COMPLEMENT)
NOISE (ΜVP-P)
COMMENTS
FS - 1.5 x LSB
011...111
011...110
LSB=
011...101
2 x VREF
2N
N = 12/14/16
100...010
100...001
100...000
-2N-1 -2N-1+1 -2N-1+2
2N-1-2 2N-1-1
2N-1
VIN = (AIN+)-(AIN-)
DIFFERENTIAL
ANALOG INPUT
(LSB)
2 x VREF
ZERO SCALE
VIN = -VREF
FULL SCALE (FS)
VIN = +VREF
Figure 6. Ideal ADC Transfer Characteristics
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Maxim Integrated │ 30
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Digital Interface
the ADCs enter track mode. To complete a conversion,
the time between CNVST falling and rising edge must
be at least the minimum of the conversion time t12 (see
Figure 11). The conversion data can then be read immediately after the rising edge of the next CNVST pulse,
which should not occur before the minimum conversion
time value (t12) has elapsed. guard against digital noise
from the data bus, corrupting the sample.
Conversion data may be read in the track phase, the conversion phase, or both. Outlined below are the specifics
of the various ways to read conversion data.
The input signals of the two ADC channels are sampled
simultaneously on the falling edge of CNVST and the conversion is initiated. At the end of the conversion, the ADCs
go idle until the next rising edge of CNVST, at which point
INITIATE READ RIGHT AFTER
CNVST RISING EDGE
LSB+2 LSB+1 LSB MSB MSB-1 MSB-2
READ DATA (SAMPLE 1)
CLK N
CLK 1
MSB MSB-1 MSB-2
CLK 2
DOUT 1/2
CLK N
CLK 1
CLK 3
CLK
SAR CONVERSION 3
SAMPLE 3
CLK N-1
SAMPLE 2
CLK 2
SAMPLE 1
CNVST
TRACK 3
SAR CONVERSION 2
CLK N-2
TRACK 2
1 / SAMPLE RATE
CLK N-1
SAR CONVERSION 1
CLK N-2
TRACK 1
1 / SAMPLE RATE
CLK 3
1 / SAMPLE RATE
LSB+2 LSB+1 LSB
READ DATA (SAMPLE 2)
Figure 7. Convert and Data Read
INITIATE READ RIGHT AFTER CNVST FALLING EDGE
1 / SAMPLE RATE
LSB+1 LSB
READ DATA (SAMPLE 1)
MSB MSB-1 MSB-2
CLK N
CLK N-1
CLK 3
MSB MSB-1 MSB-2
CLK 1
DOUT 1/2
CLK N
CLK
SAR CONVERSION 3
SAMPLE 3
CLK N-1
CLK 3
SAMPLE 2
CLK 2
SAMPLE 1
1 / SAMPLE RATE
SAR CONVERSION 2 TRACK 3
TRACK 2
CLK 1
CNVST
SAR CONVERSION 1
CLK 2
1 / SAMPLE RATE
TRACK 1
LSB+1 LSB
READ DATA (SAMPLE 2)
Figure 8. Reading Data After Falling Edge of CNVST
www.maximintegrated.com
Maxim Integrated │ 31
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
1 / SAMPLE RATE
t ≥ t12
CNVST
DOUT 1/2
CLK N
CLK N-1
CLK N-2
CLK 3
CLK
CLK 2
CLK 1
SAMPLE 1
LSB+2 LSB+1 LSB
MSB MSB-1 MSB-2
READ DATA (SAMPLE 1)
Figure 9. Convert and Data Read in a Single Conversion Period
t < t12
DOUT 1/2
MSB MSB-1 MSB-2
CLK 3
CLK 2
CLK 1
CLK N-2
SAMPLE 3
CLK 3
CLK
SAR CONVERSION 3
TRACK 3
SAMPLE 2
CLK 2
SAMPLE 1
CLK 1
CNVST
TRACK 2
1 / SAMPLE RATE
CLK N
SAR CONVERSION 1
TRACK 1
CONVERSION 2
ABORTED
CLK N-1
1 / SAMPLE RATE
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
READ DATA (SAMPLE 1)
Figure 10. Conversion Abort Data Read
t1
t12
t9
SAMPLE EDGE
70% OVDD
70% OVDD
CNVST
t8
t7
t11
t10
t4
t6
t5
70% OVDD
SCLK
30% OVDD
t3
t2
70% OVDD
DOUT1/2
Figure 11. Interface Timing Specifications
www.maximintegrated.com
Maxim Integrated │ 32
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Applications Information
Interfacing to Common Input Signals
Real-world signals typically require conditioning before
they can be digitized by an ADC. The following outlines
common examples of analog signal processing circuits.
The ADCs in the MAX11192/MAX11195/MAX11198
accept differential input signals with unipolar common
mode. Refer to THD vs. Input Impedance to use buffers
to minimize distortion. The three following examples show
input signal conditioning approaches to common signal
path configurations.
Differential Unipolar Input
The circuit in Figure 12 shows how amplifiers can be
configured to buffer a differential unipolar input signal.
Single-Ended Unipolar Input
The circuit in Figure 13 shows how a single-ended, unipolar
signal can interface with the MAX11192/MAX11195/
MAX11198. This signal conditioning circuit transforms a
0V to +VREF single-ended input signal to a fully differential
output signal with a signal peak-to-peak amplitude of 2 x
VREF and common-mode voltage of VREF/2. In this case,
the single-ended signal source drives the high-impedance
input of the first amplifier. This amplifier drives the AIN1+
input, and the second stage amplifier with a peak-to-peak
amplitude of VREF and a common-mode output voltage of
VREF/2. The second amplifier inverts this signal to generate
AIN1-, the inverted version of AIN1+.
Single-Ended Bipolar Input
Figure 14 shows a signal conditioning circuit that transforms
a -2 x VREF to +2 x VREF single-ended bipolar input
signal to a balanced differential output signal with a peakto-peak amplitude of 2 x VREF and a common-mode
voltage VREF/2.
The single-ended bipolar input signal drives the inverting
input of the first amplifier. This amplifier inverts and adds
an offset to the input signal. It also drives the AIN1- input
and the second stage amplifier with a peak-to-peak
amplitude of VREF and a common-mode output voltage of
VREF/2. The second amplifier is also in inverting configuration
and drives the AIN1+ input. This amplifier adds an offset to
generate a signal with a peak-to-peak amplitude of VREF
and a common-mode output voltage of VREF/2. The input
impedance, seen by the signal source, is determined by
the input resistor of the first-stage inverting amplifier. The
input impedance must be chosen carefully based on the
output impedance of the signal source.
3.3V TO 5.25V
VREF
-
0.5 x VREF
+
RS
0V TO VREF
0V
-
0.5 x VREF
+
AGND
OGND
OVDD
AIN1+
CS
COG
VREF
AVDD
1.7V TO 3.6V
SAR ADC
DOUT1
AIN1-
RS
CNVST
VREF TO 0V
SCLK
AIN2+
0V
AIN2-
MAX11192
MAX11195
MAX11198
REFIN/OUT
SAR ADC
REF1 REF2
DSP
SPI
INTERFACE
DOUT2
REFGND
Figure 12. Unipolar Differential Input
www.maximintegrated.com
Maxim Integrated │ 33
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
3.3V TO 5.25V
VREF
-
0.5 x
VREF
RS
0V TO VREF
+
AVDD
1.7V TO 3.6V
AGND
OVDD
OGND
AIN1+
R
R
CS
COG
0V
-
DOUT1
SAR ADC
AIN1-
RS
DSP
CNVST
VREF TO 0V
+
VREF +
2
SCLK
AIN2+
MAX11192
MAX11195
MAX11198
DOUT2
SAR ADC
AIN2-
REFIN/OUT
SPI
INTERFACE
REF1 REF2
REFGND
Figure 13. Unipolar Single-Ended Input
3.3V TO 5.25V
R
+2 x VREF
4R
-
4R
-2 x VREF
-
R
0V
2 x VREF +-
+
R
R
VREF +
2 -
1.7V TO 3.6V
MAX11192
RS
0V TO VREF
+
AVDD
AGND
OGND
OVDD
AIN1+
CS
COG
SAR ADC
DOUT1
AIN1-
RS
CNVST
VREF TO 0V
SCLK
AIN2+
MAX11192
MAX11195
MAX11198
AIN2-
REFIN/OUT
SAR ADC
REF1 REF2
DSP
SPI
INTERFACE
DOUT2
REFGND
Figure 14. Bipolar Single-Ended Input
www.maximintegrated.com
Maxim Integrated │ 34
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Layout, Grounding, and Bypassing
seen by the driving stage of the ADC input. For best
performance, connect the REF1/2 output to the ground
plane with a 16V, 10μF ceramic chip capacitor with a X5R
dielectric in a 1210 or smaller case size. Ensure that all
bypass capacitors are connected directly into the ground
plane with an independent via.
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines parallel
to one another (especially clock lines), and avoid running
digital lines underneath the ADC package. A single solid
GND plane configuration with digital signals routed from
one direction and analog signals from the other provides
the best performance. Connect the GND pins of the
MAX11192/MAX11195/MAX11198 to this ground plane.
Keep the ground return path to the power supply low
impedance and as short as possible. A 1nF C0G ceramic
chip capacitor should be placed between AINn+ and
AINn- as close as possible to the MAX11192/MAX11195/
MAX11198. This capacitor reduces the voltage transient
Bypass AVDD and OVDD to the ground plane with 10μF
ceramic chip capacitors on each pin as close as possible to
the device to minimize parasitic inductance. For best
performance, bring the AVDD power plane in from
the analog interface side of the MAX11192/MAX11195/
MAX11198 and the OVDD power plane from the digital
interface side of the device. Figure 15 shows the PCB
top layer of a sample layout with optimal placement of
passive components.
GND
REF2
REF1
REFIN/
OUT
AVDD
OVDD
14
13
12
11
10
9
15
8
DOUT2
16
7
DOUT1
1
2
3
4
AINP1
AINN1
AINP2
AINN2
GND
5
6
GND
Figure 15. PCB Layout Example for MAX11192/MAX11195/MAX11198
www.maximintegrated.com
Maxim Integrated │ 35
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Ordering Information
PART NUMBER
RESOLUTION
TEMP RANGE
PIN-PACKAGE
INTERNAL REFERENCE
MAX11192ATE+
12
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11192ATE+T
12
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11195ATE+
14
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11195ATE+T
14
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11198ATE+
16
-40°C to +125°C
16 TDFN-EP*
2.5V
MAX11198ATE+T
16
-40°C to +125°C
16 TDFN-EP*
2.5V
Denotes a lead(Pb)-free/RoHS-compliant package.
T = tape and reel.
*EP = Exposed Pad
www.maximintegrated.com
Maxim Integrated │ 36
MAX11192/MAX11195/
MAX11198
12-/14-/16-Bit, 2Msps, Dual Simultaneous
Sampling SAR ADCs with Internal Reference
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
4/17
Initial release
1
9/17
Added MAX11195 and MAX11198 part numbers to data sheet
—
1–37
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 37
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