Evaluates: MAX11270
MAX1127X Family Evaluation Kit
General Description
The evaluation kit (EV kit) demonstrates the MAX1127X
family of 24-bit, 64ksps delta-sigma ADCs with integrated
PGA. The EV kit includes a graphical user interface (GUI)
that provides communication from the target device to the
PC. The EV kit can operate in multiple modes:
Features and Benefits
●● High-Speed USB, FMC Connector, and PMOD
Connector
●● 5MHz SPI Interface
●● Various Sample Sizes and Sample Rates
1) Standalone Mode: In “Standalone” mode, the EV
kit is connected to the PC through a USB cable and
performs a subset of the complete EV kit functions
with limitation for sample rate and size.
●● Collects Up to 1 Million Samples (with FPGA Platform)
2) FPGA Mode: In “FPGA” mode, the EV kit is connected to an Avnet ZedBoard™ through a low-pincount FMC connector. ZedBoard features a Xilinx®
Zynq®-7000 SoC that connects to the PC through an
Ethernet port, which allows the GUI to perform different operations with full control over mezzanine card
functions. The EV kit with FPGA platform performs
the complete suite of evaluation tests for the target IC
●● Sync In and Sync Out for Coherent Sampling
(with FPGA Platform)
3) User-Supplied SPI Mode: In addition to the USB
and FMC interfaces, the EV kit provides two 12-pin
PMOD-style headers for user-supplied SPI interface,
to connect the signals for RDYB, SCLK, DIN, DOUT,
and CSB.
The EV kit includes Windows XP®-, Windows® 7 and
Windows 8.1-compatible software to exercise the features
of the IC. The EV kit GUI allows different sample sizes,
adjustable sampling rates, on-board or external reference
options, and graphing software that includes the FFT and
histogram of the sampled signals with the ability to save
plots in .jpg or .csv formats.
The ZedBoard board accepts a +12V AC-DC wall adapter.
The EV kit can be powered by the ZedBoard or by a local
12V supply. The EV kit has on-board transformers and
digital isolators to separate the IC from the ZedBoard/
on-board processor.
The MAX11270 EV kit comes installed
MAX11270EUG+ in a 24-pin TSSOP package.
with
a
ZedBoard is a trademark of Avnet, Inc.
Xilinx and Zynq are registered trademarks and Xilinx is a registered service mark of Xilinx, Inc.
Windows and Windows XP are registered trademarks and registered service marks of Microsoft Corporation.
19-7592; Rev 0; 4/15
●● Time Domain, Frequency Domain, and Histogram
Plotting
●● Save Plots as jpg, bmp or csv
●● On-Board DAC (MAX542) for DC Signal-Level
Generation
●● On-Board Voltage Reference (MAX6126)
●● Proven PCB Layout
●● Fully Assembled and Tested
●● Windows XP-, Windows 7-, and Windows
8.1-Compatible Software
●● Savable ADC Configurations
Ordering Information appears at end of data sheet.
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
MAX11270 EV Kit Photo
System Block Diagram
+
MAX44241
ISOLATED
DC-DC
+
MAX11270
ADC
U25
DAC_OUT+
ADC_REFP
+
SCLK_ADC
ADC_INP
MAX44241
MAX44241
ADC_INN
+
EXT_REFP
MAX44241
EXT_REFN
DAC_OUT-
MAX6126
ADC_REFN
+
DAC_OUT-
MAX9632
MAX542
DAC
U15
MAX9632 x2
F
M
C
CS_ADC
RDYB_ADC
DOUT_ADC
DIN_ADC
ADC_REFP
ADC_REFN
SCLK_DAC
DAC_OUT+
SYNC IN,
SYNC OUT
CS_DAC
DIN_DAC
LDAC
I
S
O
L
A
T
I
O
N
H
E
A
D
E
R
FTDI
U
S
B
FPGA ZedBoard
USER-SUPPLIED
SPI
PC - USB
MAX6126
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Maxim Integrated │ 2
MAX1127X Family Evaluation Kit
MAX11270 EV Kit Files
FILE
MAX11270EVKitSetupV1.1.exe
Boot.bin
DECRIPTION
Application Program
(GUI)
ZedBoard Firmware
(SD Card to boot Zynq)
Quick Start
Required Equipment
●● MAX11270 EV kit
●● +12V (500mA) power supply
●● Micro-USB cable
●● ZedBoard development board (optional – Not Included
with EV kit)
●● Function generator (optional)
●● Windows XP, Windows 7, or Windows 8.1 PC with a
spare USB port
Note: In the following sections, software-related items are
identified by bolding. Text in bold refers to items directly
from the EV system software. Text in bold and underline
refers to items from the Windows operating system.
Procedure
The EV kit is fully assembled and tested. Follow the steps
below to verify board operation:
Evaluates: MAX11270
7) From the Device menu, select Standalone and click
Search for USB Device. Then select Standalone
again and select a device in the list. Verify that the
lower left status bar indicates the EV kit hardware is
Connected.
For FPGA mode (when connected to a ZedBoard):
8) Connect the Ethernet cable from the PC to the
ZedBoard and configure the Internet Protocol Version
4 (TCP/Ipv4) properties in the local area connection to IP address 192.168.1.2 and subnet Mask to
255.255.255.0.
9) Verify that the ZedBoard SD card contains the
boot.bin file for the MAX11270 EV kit.
10) Connect the EV kit FMC connector to the ZedBoard
FMC connector. Gently press them together.
11) Verify that all jumpers are in their default positions for
the ZedBoard (Table 1) and EV kit (Table 2).
12) Connect the 12V wall adapter power supply to the
ZedBoard. Leave the ZedBoard powered off. Connect
the PC to the ZedBoard with an Ethernet cable.
13) Enable the power supply by sliding SW8 to ON.
14) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu, select
FPGA. Verify that the lower left status bar indicates
the EV kit hardware is Connected.
For either Standalone or FPGA mode:
1) Visit www.maximintegrated.com/evkitsoftware to
download the latest version of the EV kit software,
MAX11270EVK.ZIP. Save the EV kit software to a
temporary folder and uncompress the ZIP file.
15) Connect the positive terminal of the function generator
to the IN+ test point on the EV kit. Connect the negative terminal of the function generator to the IN- test
point on the EV kit. Disable the function generator.
2) Install the EV kit software and USB driver on your computer by running the MAX11270EVKitSetupV1.1.exe
program inside the temporary folder. The program
files are copied to your PC and icons are created in
the Windows Start | Programs menu. At the end of
the installation process, the installer will launch the
installer for the FTDIChip CDM drivers.
16) Enable the function generator. Configure the signal
source to generate a 1kHz, 1VP-P sinusoidal wave
with +500mV offset.
For Standalone mode:
3) Verify that all jumpers are in their default positions for
the EV kit (Table 2).
4) Connect the PC to the EV kit using a micro-USB
cable.
5) Connect the +12V adapter to the EV kit.
6) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. Verify that the lower left status
bar indicates the EV kit hardware is Connected.
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17) In the Calibration group, select Self Offset/Gain in
the drop-down list and then click Calibrate.
18) Click on the Scope tab.
19) Check the Remove DC checkbox to remove the DC
component of the sampled data.
20) Click the Capture button to read sampled data from
the ADC.
21) The EV kit software appears as shown in Figure 4.
22) Verify the frequency is approximately 1kHz displayed
on the right. The scope graph has buttons in the
upper-right corner that allow zooming in to detail.
Maxim Integrated │ 3
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Table 1. ZedBoard Jumper Settings (Optional)
JUMPER
SHUNT
POSITION
J18
1-2
JP11
2-3
JP10
1-2
DESCRIPTION
VDDIO set for 3.3V
JP9
1-2
JP8
2-3
JP7
2-3
JP10
—
J12
—
J20
—
Connected to 12V wall adapter
SW8
Off
ZedBoard power switch, off while connecting boards
Boot from SD card
SD card installed
Table 2. MAX1127X EV Kit User Configuration Jumper Settings*
JUMPER
J2 (Red)
J3 (Red)
J4 (Red)
J5 (Red)
J6 (Black)
SHUNT
POSITION
1-2
Connects the +10V rail to test point +10VEXT for external power (op amp + supply)
2-3*
Connects the +10V rail to LDO U2 (op amp + supply)
1-2
Connects the +15V rail to test point +15EXT for external power (powers U2)
2-3*
Connects the +15V rail to isolation transformer (powers U2)
1-2
Set ADC DVDD to +3.3V
2-3*
Set ADC DVDD to +2.0V
1-2*
Connect ADC AVSS to GND (unipolar mode – also set J8 for unipolar)
2-3
Connect ADC AVSS to -1.8V (bipolar mode – also set J8 for bipolar)
1-2
Apply an offset of ADC_REFP (2.5V default) to amplifier U24
2-3
Apply an offset of 2.5V to amplifier U24
Open*
J7 (Black)
J15 (Red)
J17 (Red)
J18 (Red)
J20 (Red)
J21 (Black)
No offset for amplifier U24
1-2
Apply an offset of ADC_REFP (2.5V default) to amplifier U27
2-3
Apply an offset of 2.5V to amplifier U27
Open*
J8 (Red)
DESCRIPTION
No offset for amplifier U27
1-2
Connect ADC AVDD to +1.8V (bipolar mode)
2-3*
Connect ADC AVDD to 3.6V (unipolar mode)
1-2*
Connects ZedBoard +12V to main power supply (U3). Diode D2 protects supplies.
Open
Disconnects ZedBoard +12V from main power supply
1-2
Connects U5 input to GND
3-4
Connects U5 input to test point -15VEXT for external power
5-6*
Connects U5 input to isolation transformer
1-2
Do not connect
3-4
Do not connect
5-6
Connects U5 output to GND, which sets the reference for the -10V supply (op amp - supply)
1-2*
Connects on-board FTDI chip to 3.3V, necessary for standalone mode
Open
Disconnects on-board FTDI chip power. This jumper does not interfere with the ZedBoard.
1-2*
Drive ADC REFP pin with on-board voltage reference
2-3
Drive ADC REFP pin with external voltage reference
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Maxim Integrated │ 4
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Table 2. MAX1127X EV Kit User Configuration Jumper Settings* (continued)
JUMPER
J22 (Black)
J23 (Black)
J24 (Black)
J25 (Black)
J26, J27
(Black)
J28 (Black)
J29 (Black)
J30 (Black)
J36 (Black)
J37 (Red)
J40 (Black)
J44 (Black)
J45 (Black)
J46 (Red)
SHUNT
POSITION
DESCRIPTION
1-2
Ground test point CH_D-
3-4
Ground test point CH_D+
1-2*
Drive ADC REFN pin with on-board voltage reference
2-3
Drive ADC REFN pin with external voltage reference
1-2
Ground test point CH_C-
3-4
Ground test point CH_C+
1-2*
Connect output of U23 (CH_C) to U24 inverting input
3-4
Connect CH_D- to U24 inverting input
5-6
Connect output of U23 (CH_C) to U24 noninverting input
7-8
Connect CH_D+ to U24 noninverting input
1-2*
Set both jumpers to align with silkscreen text “EXT” to drive ADC_INP and ADC_INN with
test points IN+ and IN- (also external connector J10 is on same net)
3-4
Set both jumpers to align with silkscreen text “AMP” to drive ADC_INP and ADC_INN with U27 and
U24 amplifiers
5-6
Set both jumpers to align with silkscreen text “DAC” to drive ADC_INP and ADC_INN with DAC_
OUT+ and DAC_OUT-
7-8
Set both jumpers to align with silkscreen text “REF” to drive ADC_INP and ADC_INN with ADC_
REFP and ADC_REFN voltage reference
9-10
Ground ADC_INP and INN
1-2
Ground test point CH_A-
3-4
Ground test point CH_A+
1-2*
Connect output of U26 (CH_A) to U27 inverting input
3-4
Connect CH_B- to U27 inverting input
5-6
Connect output of U26 (CH_A) to U27 noninverting input
7-8
Connect CH_B+ to U27 noninverting input
1-2
Ground test point CH_B-
3-4
Ground test point CH_B+
1-2
Drive ADC CLK pin with signal from SMA connector J34
2-3*
Drive ADC CLK pin with signal from on-board oscillator U20
1-2*
Connect ADC to the DVDD voltage selection jumper J4
open
Attach amp meter between pins 1-2 to measure current consumed by ADC DVDD
1-2*
Connect ADC RST to DVDD (normal operation)
2-3
Connect ADC RST to GND (reset state)
1-2*
Sets U18 noninverting input to 0V. Gain = -1 with offset = 0. Drives DAC_OUT-.
2-3
Sets U18 noninverting input to 2.5V. Gain = -1 with offset = 2.5V. Drives DAC_OUT-.
1-2*
Sets U17 noninverting input to 0V. Gain = -1 with offset = 0. Drives DAC_OUT+.
2-3
Sets U17 noninverting input to 2.5V. Gain = -1 with offset = 2.5V. Drives DAC_OUT+.
1-2*
Enables main power supply (U3)
Open
Disables main power supply (U3)
*Red test points and red jumpers are used for power settings.
Black test points are used for ground points.
White test points are used for all signal points, black jumpers for signal settings.
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Maxim Integrated │ 5
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Table 3. MAX1127X EV Kit User Off-Board Connectors
CONNECTOR
REFERENCE
DESIGNATOR
DESCRIPTION
J1
USB connector for standalone mode
J9
External reference input for EXT_REFP and EXT_REFN
J10
External input for ADC IN+ and IN-
J12, J16
External power connections, 12V. Both wall adapter and screw terminals are provided. When ZedBoard is
used, these connectors are not necessary if jumper J15 is installed.
J13
External connections for AVDD and AVSS
J14
External enable, driven by GPIO1 via FET
J19
Serial EEPROM signal
J31
Sync clock input, SMA
J32
PMOD A, connects to ADC, 12-pin connector
J33
PMOD B, connects to DAC, 12-pin connector
J34
External clock input, SMA
J35
DAC SPI port signal
J38, J41
Sync clock out, SMA
J39
ADC SPI port signal
J42
Split sync clock in, SMA
J43
FMC connector for use with ZedBoard
General Description of Software
The main window of the EV kit software contains several tabs: ADC Config, DAC Config, Function Generator,
Scope, DMM, Histogram, FFT, and ADC Registers. The
ADC Config tab and ADC Registers tab provide control
to communicate with the MAX1127X registers. The DAC
Config tab and Function Generator tab provide control to
communicate with the MAX542. The other four tabs are
used for evaluating the sample data read from the ADC.
ADC Config Tab
The ADC Config tab provides an interface for configuring the IC from a functional perspective. The main block
provides for calibration, GPIO control, input path selection, data format, filtering, power, and clocking. To read
all the configuration settings, click the Read All button in
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the Serial Interface block. When a setting is changed,
the register associated with that setting is automatically
written. The Status Log at the bottom of the GUI shows
the value and register that was changed.
The primary mode for calibration is using the drop-down
list to select a calibration mode, followed by clicking the
Calibrate button. The checkboxes for Self Offset, Self
Gain, System Offset, and System Gain allow for the
user to enable or disable the calibration values. The calibration values can also be changed manually by entering
a hex value in the SPI numeric box.
The Power block allows the user to put the part in a
power-down or standby state by selecting one of these
options in the drop-down list. The configuration settings can be reset back to default by clicking the Reset
Maxim Integrated │ 6
MAX1127X Family Evaluation Kit
Registers button. For the Clock source selection, the IC
internal clock is always a valid option. If the external clock
is selected, a clock must be applied at the IC CLK pin by
setting jumper J36 to either SMA or OSC. Once the above
configurations are completed, start conversion by clicking
Convert in the Serial Interface block. To read the data
and status, click Read Data and Status on the lower right
of the GUI.
Evaluates: MAX11270
To save a configuration, select Save ADC Config As…
in the File menu. This saves all the ADC register values
to an XML file. To load a configuration, select Load ADC
Config in the File menu. When the XML file is loaded, all
the register values in the file are written to the ADC.
Figure 1. MAX1127X EV Kit Software (ADC Config Tab)
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Maxim Integrated │ 7
MAX1127X Family Evaluation Kit
DAC Config Tab
In standalone mode, the ADC and DAC cannot operate concurrently. It is recommended to use FPGA
mode when using the DAC for function generation.
The DAC Config tab sheet provides an interface for
configuring the MAX542 to drive the DAC_OUT+ and
DAC_OUT- pins. Set J45 Offset and J44 Offset to match
the jumper positions on the EV Kit. These jumper positions apply DC offset to DAC_OUT+ and DAC_OUT-,
see the DAC amplifier section for more details. To write a
value to the DAC, select the output of interest in the dropdown list, enter a value in the numeric box and then click
DAC Single Shot. The outputs on the right display the
voltage outputs and the decimal code written to the DAC.
Evaluates: MAX11270
The voltage outputs are calculated based on the DAC
code and jumper offsets.
The Calibration section of the DAC Config tab can be
used to calibrate the calculated voltages to be closer to
the measured voltages. Select which output to calibrate
with the radio buttons. Enter the maximum and minimum
voltage for this output in the Ideal (V) numeric boxes. Find
the measured voltages of the output for the maximum
and minimum values using the DAC Single Shot to set
the DAC output to the ideal voltages. Enter the measured
voltages in the Measured (V) numeric boxes and click
Calculate to find the new offset and gain. Check the
Enable Calibration to use these values to calculate the
voltage outputs.
Figure 2. MAX1127X EV Kit Software (DAC Config Tab)
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Maxim Integrated │ 8
MAX1127X Family Evaluation Kit
Function Generator
When using the FPGA mode, the Function Generator
tab allows the user to generate a signal with the DAC.
Select the Number of Samples, DAC Update Rate, and
Signal Frequency. Click Calculate to get the Adjust
Frequency for the DAC signal needed for coherent sampling. Then select the Signal Type, Amplitude, Phase, and
Offset to set up the waveform desired for the DAC. Click
Evaluates: MAX11270
Generate to find the DAC codes for the waveform and
generate the waveform on the DAC. The waveform codes
sent to the DAC is displayed on the graph. The Average,
RMS, Maximum, Minimum, and Peak to Peak are also
calculated and displayed on the right. To save the DAC
code waveform, go to Options > Save Graph > Function
Generator. This saves the settings on the left and the
data in the graph to a csv file.
Figure 3. MAX1127X EV Kit Software (Function Generator Tab)
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Maxim Integrated │ 9
MAX1127X Family Evaluation Kit
Scope Tab
The Scope tab sheet is used to capture data and display it in the time domain. Sample Rate and Number
of Samples can also be set in this tab if they were not
appropriately adjusted in other tabs. The Display Unit
drop-down list allows counts and voltages. Once the
desired configuration is set, click on the Capture button.
The right side of the tab sheet displays details of the wave-
Evaluates: MAX11270
form, such as Average, Standard Deviation, Maximum,
Minimum, and Fundamental Frequency. Figure 4 displays
the ADC data when a sinusoidal signal is applied at the
inputs on the EV kit.
To save the captured data to a file, go to Options > Save
Graph > Scope. This saves the setting on the left and the
data captured to a csv file.
Figure 4. MAX1127X EV Kit Software (Scope Tab)
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Maxim Integrated │ 10
MAX1127X Family Evaluation Kit
DMM Tab
The DMM tab sheet provides captured data as a digital
multimeter. Once the desired configuration is set, click on
the Capture button. Figure 5 displays the results shown
Evaluates: MAX11270
by the DMM tab when ADC_INP and ADC_INN (J26 and
J27 set as 7-8) are set to REF, see Table 2 for jumper
positions.
Figure 5. MAX1127X EV Kit Software (DMM Tab)
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Maxim Integrated │ 11
MAX1127X Family Evaluation Kit
Histogram Tab
The Histogram tab sheet is used to display a histogram of
the captured data. Sampling rate and number of samples
can also be set in this tab if they were not appropriately
adjusted in other tabs. Once the desired configuration is
set, click on the Capture button. The right side of the tab
sheet displays details of the histogram such as Average,
Standard Deviation, Maximum, Minimum, Peak-to-Peak
Evaluates: MAX11270
Noise, Effective Resolution, and Noise-Free Resolution.
To use this histogram feature, apply a DC voltage at the
input. Figure 5 displays the results shown by the DMM tab
when ADC_INP and ADC_INN are set to REF, see Table
2 for jumper positions.
To save the histogram data to a file, go to Options > Save
Graph > Histogram. This saves the setting on the left
and the histogram data captured to a csv file.
Figure 6. MAX1127X EV Kit Software (Histogram Tab)
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Maxim Integrated │ 12
MAX1127X Family Evaluation Kit
FFT Tab
The FFT tab sheet is used to display the frequency domain
FFT of the captured data. Sample Rate and Number of
Samples can also be set in this tab if they were not appropriately adjusted in other tabs. Once the desired configuration is set, click on the Capture button. The right side of
Evaluates: MAX11270
the tab displays the performance based on the FFT, such
as Fundamental Frequency, THD, SNR, SINAD, SFDR,
ENOB, and Noise Floor.
To save the FFT data to a file, go to Options > Save
Graph > FFT. This saves the setting on the left and the
FFT data captured to a csv file.
Figure 7. MAX1127X EV Kit Software (FFT Tab)
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Maxim Integrated │ 13
MAX1127X Family Evaluation Kit
ADC Registers Tab
The ADC Registers tab sheet shows the ADC registers
on the left. The middle section shows the bits and bit
descriptions of the selected register. Click Read All to
read all registers and refresh the window with the register
settings. To write a register first, select the hex value in
the Value (Hex) column, type the desired hex value and
press Enter.
Evaluates: MAX11270
The Command Byte is on the right side of the tab sheet.
This byte precedes all SPI transactions and is described
in the ADC data sheet. To send a command byte, enter a
hex value in the Numeric box and click the Send button.
The command byte has two different formats including
Conversion Mode and Register Access Mode. Select the
radio button for the desired mode to see the bit description in the table.
Figure 8. MAX1127X EV Kit Software (ADC Registers Tab)
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Maxim Integrated │ 14
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Detailed Description of Hardware
This EV kit provides a proven layout to demonstrate the
performance of the MAX1127X 24-bit delta-sigma ADC.
Included in the EV kit are digital isolators (MAX14934),
ultra-low-noise LDOs (MAX8842) to all supply pins of
the IC, an on-board reference (MAX6126), a precision
amplifier (MAX44241) for the analog inputs, 16-bit DAC
(MAX542) with precision amplifiers (MAX9632), and syncin and sync-out signals for coherent sampling.
An on-board controller is provided to allow for evaluation
in standalone mode, which has limitations on maximum
sample size and it cannot perform coherent sampling.
The EV kit can be used with FPGA mode to achieve larger
sample depth and coherent sampling.
The ADC has several input options which are selected by
J26 and J27. The external option allows for wires attached
to the screw terminals at J10. The amplifier option allows
for signals at testpoints CH_A to CH_D. The DAC option
allows for inputs to be driven from an on-board DAC. The
REF options connect the inputs to the voltage reference
of the ADC.
User-Supplied SPI
To evaluate the ADC on this EV kit with a user-supplied
SPI bus, disconnect from the FMC bus and remove
jumper J20. Apply the user-supplied SPI signals to SCLK,
CSB, DIN, and DOUT at the PMOD_A header (J32).
Make sure the return ground is connected to PMOD
ground. To communicate to the on-board DAC connect
the user-supplied SPI signals to CSB, SCLK, DIN, and
LDAC at the PMOD_B header (J33). Make sure the return
ground is connected to PMOD ground.
The on-board FTDI chip used for standalone mode does
not conflict with the user-supplied SPI if it is powered off
by removing jumper J20.
Caution: Do not plug this header into a standard PMOD
interface found on other FPGA or microcontroller products. The signal definition is unique to this EV kit.
User-Supplied AVDD
The AVDD supply is set to 3.6V or 1.8V by jumper J8.
For user-supplied AVDD, remove the jumper from J8 and
apply AVDD to the screw-terminals/testpoint at J13. Make
sure that this external supply has the correct relation to
system ground.
Bipolar Powered vs. Unipolar Powered
The ADC supports both unipolar and bipolar ranges. For
unipolar mode, jumper J8 pins 2-3 to power AVDD with
3.6V and jumper J5 pins 1-2 to set AVSS to GND. For
bipolar mode, jumper J8 pins 1-2 to power AVDD with
1.8V and jumper J5 pins 2-3 to set AVSS to -1.8V.
External Clock
When the ADC is configured to use an external clock,
Jumper J36 pins 2-3 to select the on-board oscillator as
the clock source. Jumper J36 pins 1-2 to select the SMA
connector (and user-provided clock) as the clock source.
GPIO
Testpoints are provided for the three GPIO signals from
the ADC, GPIO1, GPIO2, and GPIO3. The ADC Config
tab can configure these as input/output and read/drive the
GPIO pins. GPIO1 connects to a FET which allows J14.1
and TP2 to be connected to ground by driving GPIO1 high
(note that DVDD should be to 3.3V to drive the FET).
ADC Input Amplifiers
The input amplifiers allow for significant flexibility. The
amplifier input stage begins with testpoints labeled CH_A
to CH_D. Each set of testpoints has options to ground
either the inverting or noninverting inputs. The jumper
block J29 and J25 allow for bypassing the first stage of
amplifiers, or connecting the first stage to the second
stage. Jumper J7 can provide an offset of 2.5V to the
CH_A/CH_B signals – leave unpopulated to have an
offset of 0V. Similarly, jumper J6 can provide an offset of
2.5V to the CH_C/CH_D signals – leave unpopulated to
have an offset of 0V.
DAC and DAC Amplifiers
User-Supplied Reference
In Figure 2, the GUI shows a functional diagram of the
DAC and DAC amplifiers. Here jumper J45 can be connected to 2.5V to add a 2.5V offset to the DAC_OUT+
signal, and J44 can be connected to 2.5V to add 2.5V to
the DAC_OUT- signal.
User-Supplied AVSS
The value at DAC_OUT+ and DAC_OUT- are available to
drive to the ADC by use of jumpers J26 and J27.
For user-supplied reference voltage, set jumpers at J21
and J23 to positions 2-3 and apply external reference to
either J9 or to the EXT_REFN and EXT_REFP testpoints.
The AVSS supply is set to GND or -1.8V by Jumper J5.
For user-supplied AVSS, remove the jumper from J5 and
apply AVSS to the screw-terminals/testpoint at J13. Make
sure that this external supply has the correct relation to
system ground.
www.maximintegrated.com
Also, please note that the DAC_OUT+ and DAC_OUTvalues shown by the GUI are only valid if the settings at
J44 and J45 are the same on both the PCB and the GUI.
Maxim Integrated │ 15
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
IN+
CH_A1
3
J28
2
4
MAX44241
MAX44241
+
CH_A+
1
J29
2
3
4
5
6
8
7
-
1
MAX44241
+
J27
3
DAC_OUT+ 5
ADC_REFP
2
ADC_INP
4
6
7
8
ADC_REF/2 9
10
ADC_REFP
CH_B1
3
J30
J7
2
4
+2.5V
MAX1127x
Sigma-Delta ADC
CH_B+
IN-
CH_C1
3
J24
2
4
MAX44241
MAX44241
+
CH_C+
1
J25
2
3
4
5
6
7
8
+
MAX44241
1
DAC_OUT-
J26
2
3
4
5
6
ADC_REFN 7
8
9
10
ADC_INN
ADC_REFP
CH_D1
3
J22
J6
2
4
+2.5V
CH_D+
Figure 9. Analog Front-End
www.maximintegrated.com
Maxim Integrated │ 16
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Table 4. Analog Input Configurations (Ch A - D)
CONFIGURATION
No.
1
2
3
4
DESCRIPTION
Channel A and C
Channel A and C
Channel B and D
Channel B and D
www.maximintegrated.com
SIGNAL-PATH INPUT
CONFIGURATION
Noninverting, differential,
second-order LPF
(default)
Inverting, differential,
second-order LPF
Noninverting, differential,
first-order LPF
Inverting, differential, firstorder LPF
INPUT CONNECTORS
JUMPER POSITIONS
CH_A- and CH_C-
J28: 3-4
J30: 3-4
J24: 3-4
J22: 3-4
J29: 1-2 and 7-8
J25: 1-2 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
Open for unipolar signal
CH_A+ and CH_C+
J28: 1-2
J30: 3-4
J24: 1-2
J22: 3-4
J29: 1-2 and 7-8
J25: 1-2 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
OPEN for unipolar signal
CH_B+ and CH_D+
J28: 1-2 and 3-4
J30: 1-2
J24: 1-2 and 3-4
J22: 1-2
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
Open for unipolar signal
CH_B- and CH_D-
J28: 1-2 and 3-4
J30: 3-4
J24: 1-2 and 3-4
J22: 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
Open for unipolar signal
Maxim Integrated │ 17
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Table 4. Analog Input Configurations (Ch A - D) (continued)
CONFIGURATION
No.
5
6
7
DESCRIPTION
External Inputs
DAC Output
ADC Voltage Reference
www.maximintegrated.com
SIGNAL-PATH INPUT
CONFIGURATION
User-supplied signals
DAC output buffered with
MAX9632
Voltage reference input
to ADC from MAX6126 or
external source (see J21
and J23)
INPUT CONNECTORS
JUMPER POSITIONS
IN+ and IN-
J28: 1-2 and 3-4
J30: 1-2 and 3-4
J24: 1-2 and 3-4
J22: 1-2 and 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 1-2
J27: 1-2
J7: Open
J8: Open
DAC_OUT+ and DAC_
OUT-
J28: 1-2 and 3-4
J30: 1-2 and 3-4
J24: 1-2 and 3-4
J22: 1-2 and 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 5-6
J27: 5-6
J7: Open
J8: Open
ADC_REFP and ADC_
REFN
J28: 1-2 and 3-4
J30: 1-2 and 3-4
J24: 1-2 and 3-4
J22: 1-2 and 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 7-8
J27: 7-8
J7: Open
J8: Open
Maxim Integrated │ 18
ADC_REFN
ADC_REFP
ADC_INN
ADC_INP
ADC_INP
TP
IN
IN
TP
J40
DVDD_ADC
TP
ADC_INN
G4
AVDD
J11
A3.6V
3
2
0
R71
0
R70
AVSS
J8
IN
IN
OUT
1000PF
C114
1000PF
C106
AVDD
GPIO3
GPIO2
GPIO1
DIN_ADC
DOUT_ADC
SYNC_ADC
D3 AND D4 ARE ADDED
BY REWORK ON REVA PCB
3
+3.3V
A3.6V
+1.8V
-1.8V
+2.0V
AGND
+1.8V
2
OUT
OUT
IN
IN
IN
IN
IN
IN
EXT_REFP
EXT_REFN
IN
DAC_OUT+
DAC_OUTAVDD
AVSS
IN
IN
IN
OUT
OUT
OUT
C108
OPEN
0.01UF
C115
*
AVSS
GPIO1
TP
R72
0.01UF
C109
0.01UF
CB6
49.9
12
11
10
9
8
7
6
5
4
3
2
1
CSB
SCLK
CAPP
CAPN
REFP
REFN
AVSS
AINN
AINP
AVSS
AVDD
GPIO1/MB1
RDYB/ICLK
CLK
DGND
GPIO2
GPIO3/MSYNC
RSTB
DVDD
CAPREG
SYNC
DGND
DOUT/MB0
DIN
U25
MAX11270EUG+
13
14
15
16
17
18
19
20
21
22
23
24
IN
C93
0.01UF
IN
1
C95
0.01UF
2
C85
1000PF
PCC02SAAN
J37
SCLK_ADC
CS_ADC
C86
0.1UF
AVSS
1UF
C96
C87
OPEN
OPEN
C83
*
*
0.1UF
CB5
TP
CB4
28
49.9
2
ADC_CAPR
2
DVDD_ADC
0.1UF
OUT
1
CLK
ADC_REFN
TP
TP
-1.8V
J5
J4
ADC_REFP
R63
R55
3
1
3
IN
D4
BAT54S
OUT
+2.0V
+3.3V
R60
10K
10K
R56
C84
1000PF
RDYB_ADC
0
R61
0
R53
J34
73391-0060
ADC_REFN
2
C82
2
4.7UF
ADC_REFP
49.9
R49
DNI
OUTF
7
J23
OUTS
U20
J36
3
2
1
NR
EXT_REFN
VDD
C81
0.1UF
GND
OUTPUT
C80
0.1UF
FXO-HC730-8.192
IN
U21
MAX6126AASA25
6
J21
2
EXT_REFP
SMA CONNECTOR
CLOCK
1 EXTERNAL
2
4
3
5
IN
+3.3V
1
3
1
2
D3
PCC02SAAN
2
BAT54S
1
I.C.
I.C.
8
5
1
3
2
1
4
3
3
1
1
1
3
GNDS
GND
+3.3V
4
2
www.maximintegrated.com
3
E/D
1
AVSS
C77
0.1UF
MAX1127X Family Evaluation Kit
Evaluates: MAX11270
Figure 10a. MAX11270 EV Kit Schematic (Sheet 1 of 6)
Maxim Integrated │ 19
CS_DAC
DIN_DAC
SCLK_DAC
LDAC
+5V
IN
IN
IN
IN
C31
4.7UF
+2.5V
C39
RFB
C32
0.1UF
C54
1UF
C48
1
2
13
IN
NR
2
1
6
7
OUTS
OUTF
MAX6126AASA25
U10
4.7UF
0.1UF
REFS
REFF
LDAC
SCLK
INV
OUT
0.1UF
C52
5
11
6
8
DIN
CS
U15
10UF
C23
C47
0.1UF
+10V
+2.5V
MAX542AESD+
(MAX542V-18)
DGND
3
2
+2.5V
TP
OUT
-10V
1UF
C68
U16
+2.5V
C69
0.1UF
J45
2
6
MAX9632AUA+
OUT
N.C.
-10V
IN+
N.C.
VEE
VCC
INSHDN
7
4
7
10
VDD
AGNDF
1
14
AGNDS
8
5
0.1UF
NC
+10V
10K
R30
1UF
C50
R33
10K
10K
BUFF_OUT
R40
TP
0.1UF
C49
+10V
0.1UF
C61
3
2
+10V
C71
0.001UF
10K
IN+
N.C.
VEE
VCC
INSHDN
R41
OUT
N.C.
1UF
C64
6
U17
MAX9632AUA+
0.1UF
C65
-10V
-10V
1
+5V
7
4
1
3
8
5
C67
J44
2
TP
R29
R42
R44
BUFF_OUT1
R36
10K
10K
10K
10
1UF
C46
+10V
10K
IN+
N.C.
VEE
VCC
INSHDN
0.1UF
C45
+10V
0.1UF
C58
3
2
R43
C72
10PF
OUT
N.C.
1UF
C62
U18
6
C63
0.1UF
MAX9632AUA+
-10V
-10V
1
12
3
4
9
I.C.
I.C.
GND
GNDS
3
4
8
5
1
3
7
4
www.maximintegrated.com
5
8
TP
IN
IN
IN
IN
10
R34
BUFF_OUT2
AGND
+10V
-10V
+5V
C51
0.047UF
C66
0.047UF
C59
G2
TP
DAC_OUTDAC-
TP
OUT
0.047UF
DAC_OUT+
DAC+
TP
OUT
MAX1127X Family Evaluation Kit
Evaluates: MAX11270
Figure 10b. MAX11270 EV Kit Schematic (Sheet 2 of 6)
Maxim Integrated │ 20
J1
USB
SHIELD
5
4
3
2
1
L3
4
5
3
1
2
600
R1
R2
28
28
USB+5V
10K
RB5
15K
RB4
2.2K
RB10
10K
RB15
1
DO
VSS
VCC
RB3
CS
DI
CLK
C19
18PF
CB2
18PF
1
13
3
2
61
3
12MHZ
6
14
TEST
OSCO
OSCI
EEDATA
EECLK
EECS
RESET#
REF
DP
DM
VREGOUT
49
7
8
VREGIN
50
63
62
2
YB1
12K
C15
0.1UF
5
4
CB3
C24
4.7UF
4.7UF
VPLL
2
1
FT2232HL
UB2
ADBUS0
SUSPEND#
PWREN#
BCBUS7
BCBUS6
BCBUS5
BCBUS4
BCBUS3
BCBUS2
BCBUS1
BCBUS0
BDBUS7
BDBUS6
BDBUS5
BDBUS4
BDBUS3
BDBUS2
BDBUS1
BDBUS0
ACBUS7
ACBUS6
ACBUS5
ACBUS4
ACBUS3
ACBUS2
ACBUS1
ACBUS0
ADBUS7
ADBUS6
ADBUS5
ADBUS4
ADBUS3
ADBUS2
ADBUS1
36
60
58
59
55
57
54
52
53
48
45
46
43
44
41
39
40
38
33
34
30
32
29
27
28
26
23
24
21
22
18
19
17
16
0.1UF
RB6
+3.3V_USB
93LC66BT-I/OT
UB1
U3
CONFIG
+3.3V_USB
+1.8V
+3.3V_USB
C16
0.1UF
4
9
VPHY
C22
RB8
USB+5V
C20
4.7UF
0.1UF
C18
0.1UF
C29
RB11
+3.3V_USB
GND
C30
VCORE
GND
0.1UF
RB13
C17
VCORE
GND
AGND
C21
0.1UF
RB17
RB24
0.1UF
GND
GND
RB20
C14
RB21
0.1UF
VCCIO
10
4.7K
DSB1
RB23
28
28
RB26
RB25
28
28
28
RB18
RB19
28
28
28
28
28
RB16
RB14
RB12
RB9
RB7
+3.3V_USB
+3.3V_USB
RB22
+1.8V
VCCIO
GND
10118192-0001LF
11
10
9
8
7
6
12
37
64
VCORE
GND
6
2
20
31
42
56
VCCIO
VCCIO
GND
1
5
11
15
25
35
47
51
10K
10K
10K
10K
10K
10K
10K
10K
A
www.maximintegrated.com
K
IN
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
LDAC_FPGA
CS_DAC_FPGA
SCLK_DAC_FPGA
DIN_DAC_FPGA
SYNC_ADC_FPGA
RDYB_ADC_FPGA
SCLK_ADC_FPGA
DIN_ADC_FPGA
DOUT_ADC_FPGA
CS_ADC_FPGA
OUT
IN
OUT
GND
USB+5V
+3.3V_USB
MAX1127X Family Evaluation Kit
Evaluates: MAX11270
Figure 10c. MAX11270 EV Kit Schematic (Sheet 3 of 6)
Maxim Integrated │ 21
CS_DAC
LDAC
SCLK_DAC
DIN_DAC
CS_ADC
SCLK_ADC
DIN_ADC
SYNC_ADC
DOUT_ADC
RDYB_ADC
IN
IN
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
PBC10SAAN
J35
DVDD_ADC
RB50
RB49
RB51
RB48
DVDD_ADC
VL
I/O VL2
I/O VL7
I/O VL8
9
EN
I/O VL6
8
10
I/O VL5
7
I/O VL4
6
5
I/O VL3
I/O VL1
2
3
4
1
OUT
OUT
OUT
OUT
+3.3V
RDYB_ADC
CS_ADC
SCLK_ADC
DIN_ADC
DOUT_ADC
TEST
CS_DAC
SCLK_DAC
DIN_DAC
LDAC
28
28
28
28
UB3
MAX3002EUP
RB35
RB33
RB32
RB31
1
2
3
4
5
6
7
8
9
10
GND
I/O VCC8
I/O VCC7
I/O VCC6
I/O VCC5
I/O VCC4
I/O VCC3
I/O VCC2
VCC
I/O VCC1
J39
1UF
C76
28
28
28
28
PBC10SAAN
11
12
13
14
15
16
17
18
19
20
1UF
C92
0.1UF
C79
C98
0.1UF
16
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
1UF
C127
9
10
11
12
13
14
15
GND1
NC
IND
INC
INB
INA
INC
IND
NC
OUTC
OUTD
EN
GND1
INB
GND2
INA
OUTB
GND2
OUTA
VCC1
GND1
VCC2
1
LDAC_FPGA
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
0.1UF
C78
0.1UF
C128
C97
0.1UF
CS_ADC_FPGA
DIN_ADC_FPGA
DOUT_ADC_FPGA
SCLK_ADC_FPGA
MAX14934FAWE
GND2
EN
NC
GND1
OUTB
OUTD
IND
OUTA
OUTC
INC
INA
INB
VCC2
GND2
GND1
U22
MAX14934FAWE
U29
VCC1
GND1
VCC1
0.1UF
C129
D3.6V
GND2
EN
OUTD
OUTC
OUTB
OUTA
GND2
VCC2
MAX14934FAWE
U34
VDDIO
12
11
10
9
8
7
J1-2
J1-3
J1-4
J1-5
J1-6
J1-8
J1-9
J1-10
J1-11
J1-12
6
5
4
3
2
1
6
5
4
3
2
1
J1-10
J1-11
J1-12
J1-5
J1-6
J1-9
J1-4
J1-8
J1-2
J1-7
J1-3
J1-1
J32
TSW-106-08-S-D-RA
PMOD PORT A
J1-1
J1-7
TSW-106-08-S-D-RA
J33
PMOD PORT B
12
11
10
9
8
7
VADJ
R59
R62
VDDIO
RDYB_ADC_FPGA
SYNC_ADC_FPGA
+12V_FPGA
SCLK_DAC_FPGA
CS_DAC_FPGA
DIN_DAC_FPGA
VDDIO
DOUT_ADC_FPGA
RDYB_ADC_FPGA
SCLK_ADC_OUT_FPGA
VDDIO
CS_ADC_FPGA
SCLK_ADC_FPGA
DIN_ADC_FPGA
SYNC_ADC_FPGA
CS_DAC_FPGA
SCLK_DAC_FPGA
DIN_DAC_FPGA
LDAC_FPGA
1UF
C75
1UF
C126
1UF
C91
VDDIO
28
28
IN
G40
G39
G38
G37
G36
G35
G34
G33
G32
G31
G30
G29
G28
G27
G26
G25
G24
G23
G22
G21
G20
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
3
4
3
4
33
34
35
36
37
38
39
40
33
34
35
36
37
38
39
40
C40
C38
C39
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
H17
R22
H35
R19
J43
13
14
15
16
17
18
19
20
21
22
23
24
25
13
14
15
16
17
18
19
20
21
22
23
24
25
35
36
37
38
39
40
37
38
39
40
34
36
34
35
33
32
32
33
31
30
29
28
27
31
30
29
28
27
26
12
12
26
11
11
8
9
7
10
8
10
7
9
6
4
5
3
4
6
2
3
5
1
1
H40
C38
1UF
D40
D38
D39
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
ASP-134604-01
R21
H38
H39
H37
H36
R23
R24
R25
R27
H34
H33
H32
H31
H30
H29
H28
R31
R35
H26
H27
R37
H25
H24
H23
H22
H21
H20
H19
R46
R47
H18
R48
R50
R51
R52
R54
R57
R58
R65
H16
H15
H14
H13
H12
H11
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
2
ASP-134604-01
J43
30
29
29
32
28
28
31
27
27
32
26
31
25
26
30
23
24
25
22
23
22
24
20
21
21
19
20
18
16
16
17
15
15
19
14
14
18
13
17
12
13
9
12
8
10
11
10
11
9
7
6
8
7
6
5
2
2
5
1
J43
ASP-134604-01
1
ASP-134604-01
J43
FMC CONNECTOR
VADJ
DIN_DAC_FPGA
CS_ADC_FPGA
SYNC_ADC_FPGA
SCLK_DAC_FPGA
LDAC_FPGA
CS_DAC_FPGA
RDYB_ADC_FPGA
DOUT_ADC_FPGA
SCLK_ADC_OUT_FPGA
SCLK_ADC_FPGA
DIN_ADC_FPGA
SYNC_CLK_IN
SYNC_CLK_OUT
73391-0060
J31
TP
3V3_FPGA
SYNC_CLK_OUT
SYNC_CLK_OUT
SYNC CLK OUT
1
SYNC CLK IN
49.9
R80
49.9
R84
SCK_EEPROM_FPGA
CS_EEPROM_FPGA
SO_EEPROM_FPGA
SI_EEPROM_FPGA
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
5
7
2
1
5
7
2
1
2A
2OE
1A
1OE
2A
2OE
1A
1OE
3
4
5
DI
CLK
CS
GND
VCC
VSS
VCC
1000PF
0.1UF
6
3
GND
6
3
1Y
2Y
74LVC2G125DP
1000PF
0.1UF
C116
U28
VDDIO
2Y
1Y
IN
IN
IN
IN
IN
IN
PBC06SAAN
J19
49.9
R85
SYNC_CLK_IN
1
73391-0060
J42
SYNC_CLK_IN
SYNC CLK IN SPLIT
SYNC CLK IN
TP
GND
SO_EEPROM_FPGA
1
2
3
4
5
6
AGND
GND
D3.6V
DVDD_ADC
+3.3V
5V_FPGA
VDDIO
49.9
R78
49.9
R75
1
J38
73391-0060
GND
SYNC CLK OUT
49.9
R83
74LVC2G125DP
U30
C130
C111
VCC
U12
93LC66BT-I/OT
1
C42
C44
C131
VDDIO
DO
0.1UF
1UF
VDDIO
FPGA INI
SO_EEPROM_FPGA
SI_EEPROM_FPGA
SCK_EEPROM_FPGA
CS_EEPROM_FPGA
6
2
D3.6V
2
4
3
5
8
4
ISOLATED
5
3
4
2
1
J41
73391-0060
5
3
4
2
8
4
IN
www.maximintegrated.com
5
3
4
2
MAX1127X Family Evaluation Kit
Evaluates: MAX11270
Figure 10d. MAX11270 EV Kit Schematic (Sheet 4 of 6)
Maxim Integrated │ 22
GPIO3
GPIO2
TP
TP
CH_C-
CH_D-
RB62
RB66
TP
TP
CH_D+
CH_C+
TP
TP
TP
CH_B-
CH_B+
IN-
TP
TP
CH_A-
CH_A+
TP
TP
TP
100
100
RB64
J22
J24
J30
J28
100K
IN-
IN+
3
1
3
1
3
1
3
1
RB61
100K
RB36
3
1
RB34
RB41
3
1
RB37
RB63
3
1
RB65
RB56
3
1
RB52
1M
4
2
1M
1M
4
2
1M
1M
4
2
1M
1M
4
2
1M
4
2
4
2
4
2
4
2
IN
IN
10K
10K
TP
GPIO3
GPIO2
C_INP1
3
10K
RB39
R68
4
10K
C105
1000PF
A_INP1
RB38
R77
3
TP
4
C124
10K
RB54
1000PF
10K
RB53
R66
INA+
INA-
C99
INA+
INA-
1000PF
R74
1000PF
C118
10K
VSS
VDD
OUTA
+10V
5
2
10K
-10V
VSS
VDD
OUTA
+10V
5
2
-10V
1
OSTTA020161
J9
OSTTA020161
J10
U23
MAX44241AUK+
1
U26
MAX44241AUK+
1
2
1
2
R73
0
R64
0
1UF
1
3
5
7
1
3
5
7
EXT_REFN
EXT_REFP
IN-
1
3
5
7
TP
TP
2
4
6
8
J25
PBC04DAAN
0.1UF
C90
2
4
6
8
J29
PBC04DAAN
0.1UF
C110
+10V
1
3
5
7
IN+
1UF
C88
C112
+10V
RB57
RB55
RB42
RB40
0.1UF
C103
-10V
C100
1UF
0.1UF
C119
R69
10K
10K
R79
10K
10K
EXT_REFN
EXT_REFP
J13
10K
10K
OSTTA020161
J14
OSTTA020161
C107
1000PF
C125
1000PF
TERMINAL BLOCKS
2
4
6
8
2
4
6
8
1UF
C121
-10V
1
2
1
2
RB28
RB30
TP
C_INP2
RB44
3
4
RB27
0
0
INA+
INA-
C102
INA+
INA-
1000PF
R67
10K
10K
RB59
A_INP2
TP
3
4
R76
C122
1000PF
10K
VSS
VDD
2
10K
VSS
VDD
2
OUTA
+10V
5
2
-10V
OUTA
AVSS
QB1
2N7002
PBC03SABN
TP
TP
+2.5V
J6
IN
49.9
RB45
S
D
G
1
AVSS
AVDD
100K
RB60
R81
R82
49.9
RB46
4.99
100
RB58
TP
4.99
+2.5V
ADC_REFP
U24
MAX44241AUK+
1
J7
PBC03SABN
ADC_REFP
AVDD
0
1
U27
MAX44241AUK+
1
3
+10V
5
2
-10V
1
3
IN+
3
www.maximintegrated.com
2
TP2
1UF
+10V
0.1UF
IN
GPIO1
1UF
C89
+10V
J26
C94
0.1UF
9
7
5
3
1
10
8
6
4
2
ADC_REFN
DAC_OUTAMPEXTPBC05DAAN
2
4
6
8
10
J27
C123
-10V
PBC05DAAN
1UF
C120
1
3
5
7
9
0.1UF
C113
EXT+
AMP+
DAC_OUT+
ADC_REFP
ADC_REF/2
C117
-10V
C104
1UF
10
RB43
10
RB47
C101
0.1UF
OUT
OUT
IN
ADC_REF/2
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
10K
R87
R86
10K
C133
1000PF
TP
G3
REVA OF MAX11270EVKIT
DOES NOT HAVE R86 AND R87
AND J27.9 IS ASSIGNED
TO GND, NOT ADC_REF/2
ADC_INN
ADC_INP
ADC_REFN
ADC_REFP
EXT_REFP
EXT_REFN
AVDD
AVSS
DAC_OUT+
DAC_OUT-
AGND
-10V
+10V
MAX1127X Family Evaluation Kit
Evaluates: MAX11270
Figure 10e. MAX11270 EV Kit Schematic (Sheet 5 of 6)
Maxim Integrated │ 23
+12V_FPGA
J16
USB+5V
IN
KLDX-0202-B
J12
IN
MBR0520L
D2
3
2
3
2
1
1
1
2
C 1
A
J15
D1
+5V
+5V
MBR0520L
C
MBR0520L
DB1
+12V
PCC02SAAN
+12V
TP
OSTTA020161
2
C
A
1UF
C36
1UF
C34
1UF
C55
A
0.47UF
C6
3
1
3
1
0.1UF
C56
1
2
IN
IN
U7
4
FB
NC
SHDN
GND
6
OUT
MAX8842ELT+
U9
NC
6
4
FB
5
6
OUT
MAX8842ELT+
IN
OUT
G N D E P NC
SHDN
GND
IN
1
OUT
MAX15006AATT+
U14
USB POWER
10UF
CB1
J46
237K
R16
453K
R13
237K
R17
453K
1
1K
R6
R14
10UF
C57
2
VDDIO
CLK
ITH
3
5
TP
G5
6.04K
R10
6.04K
R11
PCC02SAAN
J20
EN
U3
4
RB1
1K
1
2
8
ST2
1UF
C27
1UF
C25
TP
A3.6V
TP
D3.6V
OUT
OUT
OUT
ISOLATED
DS1
A3.6V
D3.6V
+3V3_USB
VDDIO
10
ST1
OUT
6
FAULT
MAX13256ATB+
1K
R7
A
K
7
2
4
4
5
6
3
3
2
T1
TGM-H240V8LF
8
1 1
C74
+5V
+5V
0.1UF
-10V
+15V
5
6
7
8
1UF
C35
1UF
C53
1UF
C37
~
D2
~
0.1UF
C33
4
3
5
2
3
1
3
1
1
2
~
D2
~
U4
BAS4002A-RPP
BAS4002A-RPP
U1
D1
D3
IN
IN
G N D E P NC
GND
NC
4
7
1
6
-
6
4
FB
NC
6
OUT
SHDN
GND
IN
+
5
6
D4
FB
-
D4
+
OUT
MAX8842ELT+
U8
SHDN
GND
U13
MAX8842ELT+
VSET
VOUT2
VOUT1
MAX664ESA
U19
VINSHDN1
SHDN2
SENSE
IN
OUT
OUT
MAX15006BATT+
U6
D1
D3
237K
R15
R12
150K
237K
R26
R28
105K
100K
R38
39K
R45
10UF
C28
1
1UF
C8
1
1
1UF
C1
1
1UF
C70
0
R9
R32
2
2
1
3
5
1UF
C26
1UF
C60
0.1UF
C73
TP
+5V
1
3
5
-1.8V
OUT
2
2
-15VEXT
TP
TP
0
+5V
L4
600
600
L5
L1
600
L2
600
J3
PBC03SABN
TP
+2.0V
TP
+1.8V
J17
2
4
6
OUT
OUT
R39
2
100
2
4
6
TP
+15VEXT
1
3
G6
4
2
2
2
GND1
7
VDD1
GND2
9
4
4
VDD2
EP
11
+15V
OUT
+2.0V
+1.8V
1UF
-1.8V
C43
0.1UF
C41
180PF
C12
0.1UF
C11
C10
1UF
180PF
C4
0.1UF
C3
1UF
C2
+15V
1
2
1
2
IN
G N D E P NC
IN
IN
G N D E P NC
IN
FB
OUT
MAX15006CATT+
U5
FB
OUT
G N D E P NC
U11
6
5
6
5
6
5
100K
100K
0.1UF
715K
2
4
6
169K
J18
2
4
6
100K
R18
R5
C9
R8
1
3
5
2
0.1UF
715K
R20
TP
+3.3V
1
3
5
R3
C5
TP
+10VEXT
R4
J2
PBC03SABN
-10VEXT
TP
FB
OUT
U2
MAX15006CATT+
IN
MAX15006CATT+
IN
1
2
7
3
1
3
TERMINAL BLOCK
TP
7
3
5
5
4
10UF
C40
+10V
1K RB2
TP
-10V
-10V
OUT
G1
TP
OUT
10UF
C13
10UF
C7
TP
+10V
+3.3V
DS2
3
2
3
2
1
5
0
4
4
1
7
3
8
2
2
RB29
4
7
3
7
3
A
K
www.maximintegrated.com
5
OUT
OUT
OUT
5V_FPGA
AGND
GND
OUT
MAX1127X Family Evaluation Kit
Evaluates: MAX11270
Figure 10f. MAX11270 EV Kit Schematic (Sheet 6 of 6)
Maxim Integrated │ 24
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 11. MAX11270 EV Kit Component Placement Guide—Top Side
www.maximintegrated.com
Maxim Integrated │ 25
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 12. MAX11270 EV Kit PCB Layout—Layer 1
www.maximintegrated.com
Maxim Integrated │ 26
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 13. MAX11270 EV Kit PCB Layout—Layer 2
www.maximintegrated.com
Maxim Integrated │ 27
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 14. MAX11270 EV Kit PCB Layout—Layer 3
www.maximintegrated.com
Maxim Integrated │ 28
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 15. MAX11270 EV Kit PCB Layout—Layer 4
www.maximintegrated.com
Maxim Integrated │ 29
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 16. MAX11270 EV Kit PCB Layout—Layer 5
www.maximintegrated.com
Maxim Integrated │ 30
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 17. MAX11270 EV Kit PCB Layout—Layer 6
www.maximintegrated.com
Maxim Integrated │ 31
Evaluates: MAX11270
1”
MAX1127X Family Evaluation Kit
Figure 18. MAX11270 EV Kit Component Placement Guide—Bottom Side
www.maximintegrated.com
Maxim Integrated │ 32
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Component List
Refer to file “evkit_bom_max11270_evkit_b.csv”
attached to this data sheet for component information.
www.maximintegrated.com
Ordering Information
PART
TYPE
MAX11270EVKIT#
#Denotes RoHS compliant.
EVKIT
Maxim Integrated │ 33
Evaluates: MAX11270
MAX1127X Family Evaluation Kit
Revision History
REVISION
NUMBER
REVISION
DATE
0
4/15
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2015 Maxim Integrated Products, Inc. │ 34
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