19-2736; Rev 0; 1/03
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
The MAX1156/MAX1158/MAX1174 are ideal for highperformance, battery-powered, data-acquisition applications. Excellent AC performance (THD = -100dB) and
DC accuracy (±1LSB INL) make the MAX1156/
MAX1158/MAX1174 ideal for industrial process control,
instrumentation, and medical applications.
The MAX1156/MAX1158/MAX1174 are available in a
20-pin TSSOP package and are fully specified over the
-40°C to +85°C extended temperature range and the
0°C to +70°C commercial temperature range.
Features
♦ Byte-Wide Parallel Interface
♦ Analog Input Voltage Range: ±10V, ±5V, 0 to 10V
♦ Single +4.75V to +5.25V Analog Supply Voltage
♦ Interface with +2.7V to +5.25V Digital Logic
♦ ±1LSB INL (max)
♦ ±1LSB DNL (max)
♦ Low Supply Current (max)
2.9mA (External Reference)
3.8mA (Internal Reference)
5µA AutoShutdown Mode
♦ Small Footprint
♦ 20-Pin TSSOP Package
Ordering Information
PART
INPUT
PINVOLTAGE
PACKAGE
RANGE
TEMP RANGE
0°C to +70°C
20 TSSOP
0 to +10V
MAX1156BCUP
0°C to +70°C
20 TSSOP
0 to +10V
MAX1156AEUP
-40°C to +85°C
20 TSSOP
0 to +10V
MAX1156BEUP
-40°C to +85°C
20 TSSOP
0 to +10V
MAX1156ACUP
Ordering Information continued at end of data sheet.
Applications
Typical Operating Circuit
Temperature Sensing and Monitoring
+5V ANALOG
Industrial Process Control
I/O Modules
+5V DIGITAL
0.1µF
0.1µF
Data-Acquisition Systems
µP DATA
D0–D7 BUS
OR
D8–D13
DVDD
AVDD
Precision Instrumentation
ANALOG INPUT
AIN
R/C
CS
MAX1156
MAX1158
MAX1174
EOC
REF
REFADJ
HBEN
Pin Configuration appears at end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
HIGH
BYTE
AGND DGND
0.1µF
10µF
LOW
BYTE
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1156/MAX1158/MAX1174
General Description
The MAX1156/MAX1158/MAX1174 14-bit, low-power,
successive-approximation analog-to-digital converters
(ADCs) feature automatic power-down, a factorytrimmed internal clock, and a byte-wide parallel interface. The devices operate from a single +4.75V to
+5.25V analog supply and feature a separate digital
supply input for direct interface with +2.7V to +5.25V
digital logic.
The MAX1156 accepts a 0 to +10V analog input voltage range. The MAX1158 accepts a ±10V bipolar analog input voltage range, while the MAX1174 accepts a
±5V bipolar analog input voltage range. All devices
consume no more than 26.5mW at a sampling rate of
135ksps when using an external reference, and 31mW
when using the internal +4.096V reference.
AutoShutdown™ reduces supply current to 0.4mA (typ)
at 10ksps.
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND .....................................................-16.5V to +16.5V
REF, REFADJ to AGND............................-0.3V to (AVDD + 0.3V)
CS, R/C, HBEN to DGND .........................................-0.3V to +6V
D_, EOC to DGND ...................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current into any Pin.........................50mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW
Operating Temperature Range
MAX11_ _ _CUP..................................................0°C to +70°C
MAX11_ _ _EUP ...............................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LSB
DC ACCURACY
Resolution
RES
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Transition Noise
14
Bits
No missing codes over temperature
-1
+1
MAX11_ _A
-1
+1
MAX11_ _B
-2
+2
RMS noise, external reference
0.32
Internal reference
0.34
Offset Error
-10
LSB
LSBRMS
0
+10
mV
Gain Error
0
±0.2
%FSR
Offset Drift
16
µV/°C
Gain Drift
±1
ppm/°C
85
dB
AC ACCURACY (fIN = 1kHz, VAIN = full range, 135ksps)
Signal-to-Noise Plus Distortion
SINAD
81
Signal-to-Noise Ratio
SNR
82
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
85
-100
87
dB
-86
103
dB
dB
ANALOG INPUT
Input Range
VAIN
MAX1156
0
+10
MAX1158
-10
+10
MAX1174
Input Resistance
RAIN
Normal operation
5.3
MAX1156
Shutdown mode
5.3
MAX1174
Shutdown mode
3.0
Normal operation
7.8
Shutdown mode
6.0
MAX1158
2
-5
MAX1156/MAX1174
V
+5
6.9
9.2
10
13.0
kΩ
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MAX1156, 0 ≤ VAIN ≤ +10V
Input Current
IAIN
Input Current Step at Power-Up
Input Capacitance
IPU
MIN
TYP
MAX
-0.1
+2.0
MAX1158,
-10V ≤ VAIN ≤ +10V
Normal operation
-1.8
+1.2
Shutdown mode
-1.8
+1.8
MAX1174,
-5V ≤ VAIN ≤ +5V
Normal operation
-1.8
+0.4
Shutdown mode
-1.8
+1.8
MAX1158, VAIN = +10V, shutdown mode to
operating mode
0.5
0.7
MAX1174, VAIN = +5V, shutdown mode to
operating mode
1
1.4
UNITS
mA
mA
CIN
10
pF
INTERNAL REFERENCE
REF Output Voltage
VREF
4.056
REF Output Tempco
REF Short-Circuit Current
IREF-SC
4.096
4.136
V
±35
ppm/°C
±10
mA
EXTERNAL REFERENCE
REF and REFADJ Input Voltage
Range
REFADJ Buffer Disable Threshold
REF Input Current
IREF
REFADJ Input Current
IREFADJ
3.8
4.2
V
AVDD 0.4
AVDD 0.1
V
Normal mode, fSAMPLE = 135ksps
Shutdown mode (Note 1)
REFADJ = AVDD
60
100
±0.1
±10
16
µA
µA
DIGITAL INPUTS/OUTPUTS
Output High Voltage
VOH
ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Output Low Voltage
VOL
ISINK = 1.6mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
Input Hysteresis
DVDD 0.4
V
0.4
0.7 ×
DVDD
Digital input = DVDD or 0V
V
V
-1
0.3 ×
DVDD
V
+1
µA
VHYST
0.2
V
Input Capacitance
CIN
15
pF
Three-State Output Leakage
IOZ
Three-State Output Capacitance
COZ
±10
15
µA
pF
_______________________________________________________________________________________
3
MAX1156/MAX1158/MAX1174
ELECTRICAL CHARACTERISTICS (continued)
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.70
5.25
V
External reference,
135ksps
Analog Supply Current
IAVDD
Shutdown Supply Current
ISHDN
Digital Supply Current
IDVDD
Power-Supply Rejection
Internal reference,
135ksps
MAX1156
2.9
MAX1158/MAX1174
4
MAX1156
5.3
3.8
MAX1158/MAX1174
mA
5.2
6.2
Shutdown mode (Note 1), digital input =
DVDD or 0V
0.5
5
µA
Standby mode
3.7
0.75
mA
AVDD = DVDD = +4.75V to +5.25V
mA
1
LSB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V ±5%, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ =
AVDD, CLOAD = 20pF, TA = TMIN to TMAX.)
PARAMETER
Maximum Sampling Rate
SYMBOL
CONDITIONS
Acquisition Time
tACQ
Conversion Time
tCONV
TYP
tCSH
(Note 2)
CS Pulse Width Low
tCSL
(Note 2)
R/C to CS Fall Setup Time
tDS
R/C to CS Fall Hold Time
tDH
CS to Output Data Valid
tDO
EOC Fall to CS Fall
tDV
CS Rise to EOC Rise
tEOC
Bus Relinquish Time
tBR
tDO1
UNITS
135
ksps
4.7
µs
µs
40
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
60
ns
ns
0
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
60
ns
ns
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
80
0
40
DVDD = +2.7V to +5.25V
80
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
80
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
80
_______________________________________________________________________________________
ns
ns
DVDD = +4.75V to +5.25V
Note 1: Maximum specification is limited by automated test equipment.
Note 2: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
4
MAX
2
CS Pulse Width High
HBEN Transition to Output Data
Valid
MIN
fSAMPLE-MAX
ns
ns
ns
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
MAX1156/58/74 toc02
1.0
1.5
0.6
1.0
0.4
0.5
0
-0.5
-1.0
0.2
0
-0.2
-1.5
-0.6
-2.0
-0.8
2000 4000 6000 8000 10000 12000 14000 16000
0
SHUTDOWN MODE
0.001
VAIN = 0V
0.0001
10
100
3.5
3.0
2.5
2.0
1.5
0
-0.05
-0.10
-0.15
-0.20
40
TEMPERATURE (°C)
60
80
MAX1174
2
0
-2
MAX1158
MAX1156
-4
-8
-10
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FFT AT 1kHz
0
MAX1156/58/74 toc08
4.136
4.126
4.116
4.106
4.096
4.086
fSAMPLE = 131ksps
-20
-40
-60
-80
-100
-120
4.076
-140
4.066
-160
-180
4.056
20
4
0
MAGNITUDE (dB)
0.05
6
-6
-40
INTERNAL REFERENCE (V)
MAX1156/58/74 toc07
0.10
80
60
8
0.5
INTERNAL REFERENCE
vs. TEMPERATURE
0.15
40
10
1.0
1000
20
MAX1156/58/74 toc06
4.0
GAIN ERROR vs. TEMPERATURE
0
0
OFFSET ERROR vs. TEMPERATURE
MAX1156/58/74 toc05
NO CONVERSIONS
4.5
TEMPERATURE (°C)
-20
-20
TEMPERATURE (°C)
SAMPLE RATE (ksps)
0.20
-40
fSAMPLE = 135ksps
SHUTDOWN MODE
BETWEEN CONVERSIONS
-40
OFFSET ERROR (mV)
0.1
1
4.75V
4.40
2000 4000 6000 8000 10000 12000 14000 16000
5.0
SHUTDOWN SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
MAX1156/58/74 toc04
STANDBY MODE
0.1
4.55
SHUTDOWN CURRENT (AVDD + DVDD)
vs. TEMPERATURE
10
0.01
4.60
CODE
SUPPLY CURRENT (AVDD + DVDD)
vs. SAMPLE RATE
0.01
5.0V
4.65
4.45
CODE
1
4.70
4.50
-1.0
0
5.25V
4.75
-0.4
-2.5
GAIN ERROR (%FSR)
4.80
MAX1156/58/74 toc09
0.8
SUPPLY CURRENT (mA)
2.0
DNL (LSB)
INL (LSB)
2.5
SUPPLY CURRENT (AVDD + DVDD)
vs. TEMPERATURE
DNL vs. CODE
MAX1156/58/74 toc01
MAX1156/58/74 toc03
INL vs. CODE
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
0
10
20
30
40
50
60
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX1156/MAX1158/MAX1174
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Typical Application Circuit)
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Typical Application Circuit)
SFDR vs. FREQUENCY
80
70
0
MAX1156/58/74 toc11
MAX1156/58/74 toc10
90
THD vs. FREQUENCY
120
100
-10
-20
-30
SFDR (dB)
50
40
THD (dB)
80
60
60
-40
-50
-60
-70
40
30
MAX1156/58/74 toc12
SINAD vs. FREQUENCY
100
SINAD (dB)
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
-80
20
-90
20
10
fSAMPLE = 131ksps
fSAMPLE = 131ksps
0
-100
0
1
10
100
fSAMPLE = 131ksps
-110
1
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
10
1
100
FREQUENCY (kHz)
Pin Description
PIN
NAME
1
D4/D12
2
D5/D13
3
D6/0
Three-State Digital Data Output
4
D7/0
Three-State Digital Data Output
R/C
Read/Convert Input. Power up and put the MAX1156/MAX1158/MAX1174 in acquisition mode by
holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on
R/C determines whether the reference and reference buffer power down or remain on after
conversion. Set R/C high during the second falling edge of CS to power down the reference and
buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third
falling edge of CS to put valid data on the bus.
6
EOC
End of Conversion. EOC drives low when conversion is complete.
7
AVDD
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
8
AGND
Analog Ground. Primary analog ground (star ground).
5
6
FUNCTION
Three-State Digital Data Output
Three-State Digital Data Output. D13 is the MSB.
9
AIN
10
AGND
Analog Input
11
REFADJ
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal reference
mode. Connect REFADJ to AVDD to select external reference mode.
12
REF
Reference Input/Output. Bypass REF with a 10µF capacitor to AGND for internal reference mode.
External reference input when in external reference mode.
Analog Ground. Connect pin 10 to pin 8.
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
PIN
NAME
FUNCTION
13
HBEN
14
CS
15
DGND
Digital Ground
16
DVDD
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
17
D0/D8
Three-State Digital Data Output. D0 is the LSB.
18
D1/D9
Three-State Digital Data Output
19
D2/D10
Three-State Digital Data Output
20
D3/D11
Three-State Digital Data Output
High-Byte Enable Input. Used to multiplex the 14-bit conversion result.
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C
is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result
onto the bus when R/C is high.
Analog Input
DVDD
1mA
DO–D13
DO–D13
CLOAD = 20pF
CLOAD = 20pF
1mA
DGND
DGND
a) HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
b) HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Figure 1. Load Circuits
Detailed Description
Converter Operation
The MAX1156/MAX1158/MAX1174 use a successiveapproximation (SAR) conversion technique with an
inherent track-and-hold (T/H) stage to convert an analog input into a 14-bit digital output. Parallel outputs
provide a high-speed interface to microprocessors
(µPs). The Functional Diagram shows a simplified internal architecture of the MAX1156/MAX1158/MAX1174.
Figure 3 shows a typical application circuit for the
MAX1156/MAX1158/MAX1174.
Input Scaler
The MAX1156/MAX1158/MAX1174 have an input
scaler, which allows conversion of true bipolar input
voltages and input voltages greater than the power
supply, while operating from a single +5V analog supply. The input scaler attenuates and shifts the analog
input to match the input range of the internal DAC. The
MAX1156 has a unipolar input voltage range of 0 to
+10V. The MAX1158 input voltage range is ±10V while
the MAX1174 input voltage range is ±5V. Figure 4
shows the equivalent input circuit of the MAX1156/
MAX1158/MAX1174. This circuit limits the current going
into or out of AIN to less than 1.8mA.
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
(AIN) charges capacitor CHOLD. The acquisition ends
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on CHOLD represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of 14-bit resolution. Force CS low to put valid
data on the bus after conversion is complete.
_______________________________________________________________________________________
7
MAX1156/MAX1158/MAX1174
Pin Description (continued)
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
tCSH
tCSL
CS
tACQ
REF POWERDOWN CONTROL
R/C
tDH
tDS
tEOC
tDV
EOC
tCONV
tDO
HBEN
tBR
tDO1
tDO
HIGH-Z
HIGH-Z
D7/D15–D0/D8
HIGH/LOW
BYTE VALID
HIGH/LOW
BYTE VALID
Figure 2. MAX1156/MAX1158/MAX1174 Timing Diagram
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1156/MAX1158/MAX1174 automatically enter
either standby mode (reference and buffer on) or shutdown (reference and buffer off) after each conversion,
depending on the status of R/C during the second
falling edge of CS.
Internal Clock
The MAX1156/MAX1158/MAX1174 generate an internal
conversion clock to free the microprocessor from the
burden of running the SAR conversion clock. Total conversion time (tCONV) after entering hold mode (second
falling edge of CS) to end of conversion (EOC) falling is
4.7µs (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1156/MAX1158/MAX1174 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start is ignored
if R/C is high. The MAX1156/MAX1158/MAX1174 need
at least 12ms (CREFADJ = 0.1µF, CREF = 10µF) for the
internal reference to wake up and settle before starting
the conversion, if powering up from shutdown.
8
+5V ANALOG
+5V DIGITAL
0.1µF
0.1µF
DVDD
AVDD
ANALOG INPUT
µP DATA
D0–D7 BUS
OR
D8–D13
AIN
R/C
CS
MAX1156
MAX1158
MAX1174
EOC
REF
REFADJ
HBEN
HIGH
BYTE
AGND DGND
0.1µF
10µF
LOW
BYTE
Figure 3. Typical Application Circuit for the MAX1156/MAX1158/
MAX1174
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
MAX1156
R2
MAX1158/MAX1174
R1
3.4kΩ
161Ω
AIN
TRACK
S1
CHOLD
30pF
R2
R1
3.4kΩ
161Ω
TRACK
S1
AIN
CHOLD
30pF
T/H OUT
R3
T/H OUT
R3
HOLD
TRACK
HOLD
S2
HOLD
S3
POWERDOWN
TRACK
HOLD
S2
R2 = 7.85kΩ (MAX1158)
OR 3.92kΩ (MAX1156/MAX1174)
S1, S2 = T/H SWITCH
S3 = POWER-DOWN
(MAX1158/MAX1174 ONLY)
R3 = 5.45kΩ (MAX1158)
OR 17.79kΩ (MAX1156/MAX1174)
Figure 4. Equivalent Input Circuit
Selecting Standby or Shutdown Mode
The MAX1156/MAX1158/MAX1174 have a selectable
standby or low-power shutdown mode. In standby
mode, the ADC’s internal reference and reference
buffer do not power down between conversions, eliminating the need to wait for the reference to power up
before performing the next conversion. Shutdown mode
powers down the reference and reference buffer after
completing a conversion. The reference and reference
buffer require a minimum of 12ms (CREFADJ = 0.1µF,
CREF = 10µF) to power up and settle from shutdown.
The state of R/C at the second falling edge of CS
selects which power-down mode the MAX1156/
MAX1158/MAX1174 enter upon conversion completion.
Holding R/C low causes the MAX1156/MAX1158/
MAX1174 to enter standby mode. The reference and
buffer are left on after the conversion completes. R/C
high causes the MAX1156/MAX1158/MAX1174 to enter
shutdown mode and power down the reference and
buffer after conversion (see Figures 5 and 6). Set the
voltage at R/C high during the second falling edge of
CS to realize the lowest current operation.
Standby Mode
While in standby mode, the supply current is less than
3.7mA (typ). The next falling edge of CS with R/C low
causes the MAX1156/MAX1158/MAX1174 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time.
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The next falling edge of CS with R/C
low causes the reference and buffer to wake up and
enter acquisition mode. To achieve 14-bit accuracy,
allow 12ms (CREFADJ = 0.1µF, CREF = 10µF) for the
internal reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1156/MAX1158/
MAX1174 is internally buffered to provide +4.096V output at REF. Bypass REF to AGND and REFADJ to
AGND with 10µF and 0.1µF, respectively. Sink or
source current at REFADJ to make fine adjustments to
the internal reference. The input impedance of REFADJ
is nominally 5kΩ. Use the circuit of Figure 7 to adjust
the internal reference to ±1.5%.
_______________________________________________________________________________________
9
MAX1156/MAX1158/MAX1174
REF
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ACQUISITION
CONVERSION
DATA
OUT
ACQUISITION
CS
CS
R/C
R/C
EOC
EOC
REF AND
BUFFER
POWER
REF AND
BUFFER
POWER
CONVERSION
DATA
OUT
Figure 5. Selecting Standby Mode
Figure 6. Selecting Shutdown Mode
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1156/
MAX1158/MAX1174’s internal buffer amplifier. Using
the buffered REFADJ input makes buffering the external reference unnecessary. The input impedance of
REFADJ is typically 5kΩ. The internal buffer output
must be bypassed at REF with a 10µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external 3.8V to 4.2V reference. During conversion, the external reference must
be able to drive 100µA of DC load current and have an
output impedance of 10Ω or less.
HBEN toggles the output between the high/low byte.
The low byte is loaded onto the output bus when HBEN
is low and the high byte is on the bus when HBEN is
high. The two MSBs of the high byte are always zero.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10µF capacitor.
Consider the MAX1156/MAX1158/MAX1174’s equivalent input noise (0.32LSB) when choosing a reference.
Reading the Conversion Result
EOC is provided to flag the microprocessor when a
conversion is complete. The falling edge of EOC signals that the data is valid and ready to be output to the
bus. D0–D13 are the parallel outputs of the
MAX1156/MAX1158/MAX1174. These three-state outputs allow for direct connection to a microcontroller I/O
bus. The outputs remain high-impedance during acquisition and conversion. Data is loaded onto the output
bus with the third falling edge of CS with R/C high (after
tDO). Bringing CS high forces the output bus back to
high impedance. The MAX1156/MAX1158/MAX1174
then wait for the next falling edge of CS to start the next
conversion cycle (see Figure 2).
10
Transfer Function
Figures 8, 9, and 10 show the MAX1156/MAX1158/
MAX1174 output transfer functions. The MAX1158 and
MAX1174 outputs are coded in offset binary, while the
MAX1156 is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy and prevent loading the
source. Switch the channels immediately after acquisition, rather than near the end of or after a conversion,
when the input signal is multiplexed. This allows more
time for the input buffer amplifier to respond to a large
step-change in input signal. The input amplifier must
have a high enough slew rate to complete the required
output voltage change before the beginning of the
acquisition time. Figure 11 shows an example of this
circuit using the MAX427.
Figures 12a and 12b show how the MAX1158 and
MAX1174 analog input current varies depending on
whether the chip is operating or powered down. The
part is fully powered down between conversions if the
voltage at R/C is set high during the second falling
edge of CS. The input current abruptly steps to the
powered up value at the start of acquisition. This step
in the input current can disrupt the ADC input, depending on the driving circuit’s output impedance at high
frequencies. If the driving circuit cannot fully settle by
______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
FULL-SCALE
TRANSITION
11 1111 1111 1111
MAX1156
MAX1158
MAX1174
+5V
MAX1156/MAX1158/MAX1174
MAX1156
INPUT RANGE = 0 TO +10V
OUTPUT CODE
11 1111 1111 1110
11 1111 1111 1101
68kΩ
100kΩ
REFADJ
FULL-SCALE RANGE
(FSR) = +10V
0.1µF
150kΩ
1LSB =
00 0000 0000 0011
FSR x VREF
16384 x 4.096
00 0000 0000 0010
00 0000 0000 0001
00 0000 0000 0000
0
1
2
3
16383
16382 16384
INPUT VOLTAGE (LSB)
Figure 7. MAX1156/MAX1158/MAX1174 Reference Adjust
Circuit
OUTPUT CODE
11 1111 1111 1111
MAX1158
INPUT RANGE = -10V TO +10V
FULL-SCALE
TRANSITION
Figure 8. MAX1156 Transfer Function
OUTPUT CODE
11 1111 1111 1111
11 1111 1111 1110
11 1111 1111 1110
11 1111 1111 1101
11 1111 1111 1101
10 0000 0000 0001
10 0000 0000 0000
FULL-SCALE RANGE
(FSR) = +20V
01 1111 1111 1111
1LSB =
00 0000 0000 0011
00 0000 0000 0010
FSR x VREF
16384 x 4.096
MAX1174
INPUT RANGE = -5V TO +5V
FULL-SCALE
TRANSITION
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0011
00 0000 0000 0010
FULL-SCALE RANGE
(FSR) = +10V
1LSB =
FSR x VREF
16384 x 4.096
00 0000 0000 0001
00 0000 0000 0001
00 0000 0000 0000
0
+8190 +8192
-8192 -8190
-1
+1
-8191 -8189
+8191
INPUT VOLTAGE (LSB)
00 0000 0000 0000
0
+8190 +8192
-8192 -8190
-1
+1
-8191 -8189
+8191
INPUT VOLTAGE (LSB)
Figure 9. MAX1158 Transfer Function
Figure 10. MAX1174 Transfer Function
the end of acquisition, the accuracy of the system can
be compromised. To avoid this situation, increase the
acquisition time, use a driving circuit that can settle
within tACQ, or leave the MAX1158/MAX1174 powered
up by setting the voltage at R/C low during the second
falling edge of CS.
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, isolate the digital and analog
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not layout digital signal paths underneath the
______________________________________________________________________________________
11
MAX1174
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
REF
1.5
MAX1156
MAX1158
MAX1174
MAX427
*
AIN
ANALOG INPUT CURRENT (mA)
ANALOG
INPUT
**
1.0
0.5
SHUTDOWN
MODE
0
-0.5
STANDBY
MODE
-1.0
*MAX1156 ONLY.
**MAX1158/MAX1174 ONLY.
-1.5
-5.0
-2.5
0
2.5
5.0
ANALOG INPUT VOLTAGE (V)
Figure 11. MAX1156/MAX1158/MAX1174 Fast-Settling Input
Buffer
Figure 12a. MAX1174 Analog Input Current
supply by connecting them with a low value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AV DD supply. Bypass AV DD to AGND with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capacitor
with the smallest capacitor closest to the device. Keep
capacitor leads short to minimize stray inductance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1156/MAX1158/
MAX1174 are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
12
MAX1158
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
1.5
ANALOG INPUT CURRENT (mA)
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
1.0
0.5
SHUTDOWN
MODE
0
STANDBY
MODE
-0.5
-1.0
-1.5
-10
-5
0
5
ANALOG INPUT VOLTAGE (V)
Figure 12b. MAX1158 Analog Input Current
______________________________________________________________________________________
10
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
SNR = (6.02 × N + 1.76) dB
where N = 14 bits.
In reality, there are other noise sources besides quantization noise; thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
SignalRMS
SINAD(dB) = 20 × log
(Noise + Distortion)RMS
zation noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB =
SINAD −1.76
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
V22 + V32 + V4 2 + V52
THD = 20 × log
V1
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
______________________________________________________________________________________
13
MAX1156/MAX1158/MAX1174
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N bits):
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
MAX1156/MAX1158/MAX1174
Functional Diagram
REFADJ
HBEN
AVDD AGND DVDD DGND
5kΩ
REFERENCE
OUTPUT
REGISTERS
8 BITS
8 BITS
D0–D7
OR
D8–D13
REF
AIN
INPUT
SCALER
CAPACITIVE
DAC
MAX1156
MAX1158
MAX1174
AGND
SUCCESSIVEAPPROXIMATION
REGISTER AND
CONTROL LOGIC
CLOCK
CS
EOC
R/C
Pin Configuration
Ordering Information (continued)
TOP VIEW
D4/D12 1
20 D3/D11
D5/D13 2
19 D2/D10
D6/0 3
18 D1/D9
D7/0 4
R/C 5
EOC 6
17 D0/D8
MAX1156
MAX1158
MAX1174
16 DVDD
15 DGND
AVDD 7
14 CS
AGND 8
13 HBEN
AIN 9
12 REF
AGND 10
PART
TEMP RANGE
PINPACKAGE
MAX1158ACUP
0°C to +70°C
20 TSSOP
±10V
MAX1158BCUP
0°C to +70°C
20 TSSOP
±10V
MAX1158AEUP
-40°C to +85°C
20 TSSOP
±10V
MAX1158BEUP
-40°C to +85°C
20 TSSOP
±10V
MAX1174ACUP
0°C to +70°C
20 TSSOP
±5V
MAX1174BCUP
0°C to +70°C
20 TSSOP
±5V
MAX1174AEUP
-40°C to +85°C
20 TSSOP
±5V
MAX1174BEUP
-40°C to +85°C
20 TSSOP
±5V
11 REFADJ
TSSOP
Chip Information
TRANSISTOR COUNT: 15,383
PROCESS: BiCMOS
14
INPUT
VOLTAGE
RANGE
______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
TSSOP4.40mm.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1156/MAX1158/MAX1174
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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