19-2653; Rev 1; 1/03
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Features
♦ Analog Input Voltage Range ±10V, ±5V, or 0 to 10V
♦ 14-Bit Wide Parallel Interface
♦ Single +4.75V to +5.25V Analog Supply Voltage
♦ Interfaces with +2.7V to +5.25V Digital Logic
♦ ±1LSB INL (max)
♦ ±1LSB DNL (max)
♦ Low Supply Current (MAX1159)
5.3mA (External Reference)
6.2mA (Internal Reference)
5µA AutoShutdown Mode
♦ Small Footprint
28-Pin TSSOP Package
Pin Configuration
TOP VIEW
D6 1
28 D5
D7 2
27 D4
D8 3
26 D3
D9 4
25 D2
D10 5
Applications
Temperature Sensing and Monitoring
D11 6
D12 7
24 D1
MAX1157
MAX1159
MAX1175
23 D0
22 N.C.
D13 8
21 N.C.
Industrial Process Control
R/C 9
20 DVDD
I/O Modules
EOC 10
19 DGND
Data-Acquisition Systems
AVDD 11
18 CS
Precision Instrumentation
AGND 12
17 RESET
AIN 13
16 REF
AGND 14
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
15 REFADJ
TSSOP
Ordering Information
PIN-PACKAGE
INPUT VOLTAGE
RANGE
PART
TEMP RANGE
INL (LSB)
MAX1157ACUI
0°C to +70°C
28 TSSOP
0 to +10V
±1
MAX1157BCUI
0°C to +70°C
28 TSSOP
0 to +10V
±2
Ordering Information continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1157/MAX1159/MAX1175
General Description
The MAX1157/MAX1159/MAX1175 14-bit, low-power,
successive-approximation analog-to-digital converters
(ADCs) feature automatic power-down, a factory-trimmed
internal clock, and a 14-bit wide parallel interface. The
devices operate from a single +4.75V to +5.25V analog
supply and feature a separate digital supply input for
direct interface with +2.7V to +5.25V digital logic.
The MAX1157 accepts an analog input voltage range
from 0 to +10V while the MAX1159 accepts a bipolar
analog input voltage range of ±10V. The MAX1175
accepts a bipolar analog input voltage range of ±5V.
All devices consume only 23mW at a sampling rate
of 135ksps when using an external reference and
29mW when using the internal +4.096V reference.
AutoShutdown™ reduces supply current to 0.4mA at
10ksps. The MAX1157/MAX1159/MAX1175 are ideal for
high-performance, battery-powered data-acquisition
applications. Excellent AC performance (THD = -100dB)
and DC accuracy (±1LSB INL) make the MAX1157/
MAX1159/MAX1175 ideal for industrial process control,
instrumentation, and medical applications.
The MAX1157/MAX1159/MAX1175 are available in a
28-pin TSSOP package and are fully specified over the
-40°C to +85°C extended temperature range and the
0°C to +70°C commercial temperature range.
MAX1157/MAX1159/MAX1175
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND .....................................................-16.5V to +16.5V
REF, REFADJ to AGND............................-0.3V to (AVDD + 0.3V)
CS, R/C, RESET to DGND ........................................-0.3V to +6V
D_, EOC to DGND ...................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current Into Any Pin ........................50mA
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Operating Temperature Range
MAX11_ _ _CUI ...................................................0°C to +70°C
MAX11_ _ _EUI ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
RES
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Transition Noise
Offset Error
14
Bits
No missing codes over temperature
-1
+1
MAX11_ _A
-1
+1
MAX11_ _B
-2
+2
RMS noise, external reference
0.32
Internal reference
0.34
MAX1159
-10
MAX1157/MAX1175
-10
0
LSB
LSB
LSBRMS
+10
+10
±0.2
mV
Gain Error
0
Offset Drift
16
%FSR
µV/°C
Gain Drift
±1
ppm/°C
85
dB
AC ACCURACY (fIN = 1kHz, VAIN = full range, 135ksps)
Signal-to-Noise Plus Distortion
SINAD
81
Signal-to-Noise Ratio
SNR
82
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
85
-100
87
dB
-86
103
dB
dB
ANALOG INPUT
Input Range
Input Resistance
VAIN
RAIN
MAX1157
0
+10
MAX1159
-10
+10
MAX1175
-5
+5
MAX1157/MAX1175
Normal operation
5.3
MAX1175
Shutdown mode
3
MAX1157
Shutdown mode
5.3
Normal operation
7.8
Shutdown mode
6
MAX1159
2
6.9
V
9.2
kΩ
10
_______________________________________________________________________________________
13.0
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Input Current
SYMBOL
IAIN
CONDITIONS
Input Capacitance
IPU
TYP
MAX
MAX1157,
0 ≤ VAIN ≤ +10V
Normal/shutdown
mode
-0.1
+2.0
MAX1159,
-10V ≤ VAIN ≤ +10V
Normal operation
-1.8
+1.2
Shutdown mode
-1.8
+1.8
Normal operation
-1.8
+0.4
Shutdown mode
-1.8
+1.8
MAX1175,
-5V ≤ VAIN ≤ +5V
Input Current Step at Power-Up
MIN
MAX1159, VAIN = +10V, shutdown mode to
operating mode
0.5
0.7
MAX1175, VAIN = +5V, shutdown mode to
operating mode
1
1.4
UNITS
mA
mA
CIN
10
pF
INTERNAL REFERENCE
REF Output Voltage
VREF
4.056
REF Output Tempco
REF Short-Circuit Current
IREF-SC
4.096
4.136
V
±35
ppm/°C
±10
mA
EXTERNAL REFERENCE
REF and REFADJ Input Voltage
Range
REFADJ Buffer Disable Threshold
REF Input Current
IREF
REFADJ Input Current
IREFADJ
3.8
4.2
V
AVDD 0.4
AVDD 0.1
V
Normal mode, fSAMPLE = 135ksps
Shutdown mode (Note 1)
REFADJ = AVDD
60
100
±0.1
±10
16
µA
µA
DIGITAL INPUTS/OUTPUTS
Output High Voltage
VOH
ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V, DVDD AVDD = +5.25V
0.4
Output Low Voltage
VOL
ISINK = 1.6mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
Input Hysteresis
V
0.4
0.7 ×
DVDD
Digital input = DVDD or 0V
V
V
-1
0.3 ×
DVDD
V
+1
µA
VHYST
0.2
V
Input Capacitance
CIN
15
pF
Three-State Output Leakage
IOZ
Three-State Output Capacitance
COZ
±10
15
µA
pF
_______________________________________________________________________________________
3
MAX1157/MAX1159/MAX1175
ELECTRICAL CHARACTERISTICS (continued)
MAX1157/MAX1159/MAX1175
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.75
5.25
V
2.70
5.25
V
POWER SUPPLIES
Analog Supply Voltage
AVDD
Digital Supply Voltage
DVDD
External reference,
135ksps
Analog Supply Current
IAVDD
Shutdown Supply Current
ISHDN
Digital Supply Current
IDVDD
Power-Supply Rejection
Internal reference,
135ksps
MAX1157
2.9
MAX1159/MAX1175
4.0
MAX1157
5.3
3.8
MAX1159/MAX1175
mA
5.2
6.2
Shutdown mode (Note 1), digital input =
DVDD or 0V
0.5
5
µA
Standby mode
3.7
0.75
mA
AVDD = DVDD = +4.75V to +5.25V
mA
1
LSB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD,
CLOAD = 20pF, TA = TMIN to TMAX.)
PARAMETER
Maximum Sampling Rate
SYMBOL
Acquisition Time
tACQ
Conversion Time
tCONV
CS Pulse Width High
CONDITIONS
MIN
TYP
fSAMPLE-MAX
tCSH
CS Pulse Width Low
tCSL
R/C to CS Fall Setup Time
tDS
R/C to CS Fall Hold Time
tDH
CS to Output Data Valid
tDO
EOC Fall to CS Fall
tDV
CS Rise to EOC Rise
tEOC
Bus Relinquish Time
tBR
UNITS
135
ksps
2
µs
4.7
(Note 2)
(Note 2)
40
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
60
40
DVDD = +2.7V to +5.25V
60
ns
ns
ns
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
80
0
ns
ns
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
80
DVDD = +4.75V to +5.25V
40
DVDD = +2.7V to +5.25V
80
_______________________________________________________________________________________
µs
ns
0
DVDD = +4.75V to +5.25V
Note 1: Maximum specification is limited by automated test equipment.
Note 2: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
4
MAX
ns
ns
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
0.8
0.6
0
-0.5
-0.2
-1.0
-0.4
-1.5
-0.6
-2.0
-0.8
-2.5
4096
8192
12288
0.001
VAIN = 0V
0.0001
0.1
1
10
100
4.0
3.5
3.0
2.5
2.0
1.5
-20
0
20
40
60
-0.10
-4
80
-40
MAX1157 toc08
4.126
MAGNITUDE (dB)
4.106
4.096
4.086
4.076
-100
-120
-140
-160
40
60
80
fSAMPLE = 135ksps
-80
-180
20
80
60
-60
4.056
0
40
-40
4.116
-0.20
TEMPERATURE (°C)
20
-20
4.066
-20
0
FFT AT 1kHz
0
-0.15
-40
-20
TEMPERATURE (°C)
4.136
INTERNAL REFERENCE (V)
-0.05
0
-2
-8
-40
MAX1157 toc07
0
2
-10
INTERNAL REFERENCE
vs. TEMPERATURE
0.05
80
4
0
GAIN ERROR vs. TEMPERATURE
0.10
60
-6
TEMPERATURE (°C)
0.15
40
6
0.5
SAMPLE RATE (ksps)
0.20
20
MAX1159
8
1.0
1000
0
OFFSET ERROR vs. TEMPERATURE
10
MAX1157 toc05
NO CONVERSIONS
4.5
-20
TEMPERATURE (°C)
OFFSET ERROR (mV)
0.01
SHUTDOWN SUPPLY CURRENT (mA)
SHUTDOWN
MODE
5.0
-40
16384
SHUTDOWN CURRENT (AVDD + DVDD)
vs. TEMPERATURE
0.1
0.01
12288
SUPPLY CURRENT (AVDD + DVDD)
vs. SAMPLE RATE
MAX1157 toc04
1
8192
CODE
STANDBY
MODE
fSAMPLE = 135ksps
SHUTDOWN MODE BETWEEN
CONVERSIONS
4.40
4096
CODE
10
4.55
4.45
0
16384
4.75V
4.60
4.50
-1.0
0
SUPPLY CURRENT (mA)
0
4.65
MAX1157 toc06
0.2
5.25V
5.0V
4.70
MAX 1157 toc09
0.4
0.5
DNL (LSB)
1.0
4.75
SUPPLY CURRENT (mA)
1.5
4.80
MAX1157 toc02
2.0
INL (LSB)
1.0
MAX1157 toc01
2.5
GAIN ERROR (%FSR)
SUPPLY CURRENT (AVDD + DVDD)
vs. TEMPERATURE
DNL vs. CODE
MAX1157 toc03
INL vs. CODE
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
0
20
40
60
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX1157/MAX1159/MAX1175
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Typical Application Circuit)
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Typical Application Circuit)
SPURIOUS-FREE DYNAMIC RANGE
vs. FREQUENCY
90
80
100
70
0
MAX1157 toc11
120
MAX1157 toc10
100
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
-10
-20
-30
80
50
40
-40
THD (dB)
SFDR (dB)
60
60
-50
-60
-70
40
30
MAX1157 toc12
SINAD vs. FREQUENCY
SINAD (dB)
MAX1157/MAX1159/MAX1175
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
-80
20
-90
20
10
-100
0
0
1
10
100
-110
1
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
10
1
100
FREQUENCY (kHz)
Pin Description
6
PIN
NAME
FUNCTION
1
D6
Three-State Digital Data Output
2
D7
Three-State Digital Data Output
3
D8
Three-State Digital Data Output
4
D9
Three-State Digital Data Output
5
D10
Three-State Digital Data Output
6
D11
Three-State Digital Data Output
7
D12
Three-State Digital Data Output
8
D13
Three-State Digital Data Output (MSB)
9
R/C
Read/Convert Input. Power up and place the MAX1157/MAX1159/MAX1175 in acquisition mode by
holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on
R/C determines whether the reference and reference buffer power down or remain on after
conversion. Set R/C high during the second falling edge of CS to power down the reference and
buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third
falling edge of CS to put valid data on the bus.
10
EOC
End of Conversion. EOC drives low when conversion is complete.
11
AVDD
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
12
AGND
Analog Ground. Primary analog ground (star ground).
13
AIN
14
AGND
Analog Input
Analog Ground. Connect pin 14 to pin 12.
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
PIN
NAME
FUNCTION
15
REFADJ
16
REF
17
RESET
18
CS
19
DGND
Digital Ground
20
DVDD
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
21, 22
N.C.
No Connection. Make no connection to these pins.
23
D0
Three-State Digital Data Output (LSB)
24
D1
Three-State Digital Data Output
25
D2
Three-State Digital Data Output
26
D3
Three-State Digital Data Output
27
D4
Three-State Digital Data Output
28
D5
Three-State Digital Data Output
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal reference
mode. Connect REFADJ to AVDD to select external reference mode.
Reference Input/Output. Bypass REF with a 10µF capacitor to AGND. REF is the external reference
input when in external reference mode.
Reset Input. Logic high resets the device.
Convert Start. The first falling edge of CS powers up the device and enables acquisition when R/C
is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result
onto the bus when R/C is high.
Detailed Description
DVDD
Converter Operation
The MAX1157/MAX1159/MAX1175 use a successiveapproximation (SAR) conversion technique with an
inherent track-and-hold (T/H) stage to convert an analog
input into a 14-bit digital output. Parallel outputs provide
a high-speed interface to microprocessors (µPs). The
Functional Diagram at the end of the data sheet shows a
simplified internal architecture of the MAX1157/
MAX1159/MAX1175. Figure 3 shows a typical application circuit for the MAX1157/MAX1159/MAX1175.
1mA
D0–D13
D0–D13
CLOAD = 20pF
CLOAD = 20pF
1mA
DGND
DGND
A)
HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
B)
HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Analog Input
Input Scaler
The MAX1157/MAX1159/MAX1175 have an input scaler
which allows conversion of true bipolar input voltages
and input voltages greater than the power supply, while
operating from a single +5V analog supply. The input
scaler attenuates and shifts the analog input to match
the input range of the internal DAC. The MAX1157 has
a unipolar input voltage range of 0 to +10V. The
Figure 1. Load Circuits
MAX1175 input voltage range is ±5V while the
MAX1159 input voltage range is ±10V. Figure 4 shows
the equivalent input circuit of the MAX1157/
MAX1159/MAX1175. This circuit limits the current going
into or out of AIN to less than 1.8mA.
_______________________________________________________________________________________
7
MAX1157/MAX1159/MAX1175
Pin Description (continued)
MAX1157/MAX1159/MAX1175
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
tCSL
tCSH
CS
tACQ
REF POWERDOWN CONTROL
tDS
R/C
tDH
tEOC
tDV
EOC
tCONV
HIGH-Z
D0–D13
tBR
tDO
HIGH-Z
DATA VALID
Figure 2. MAX1157/MAX1159/MAX1175 Timing Diagram
+5V ANALOG
0.1µF
Select standby mode or shutdown mode with R/C during
the second falling edge of CS (see Selecting Standby or
Shutdown Mode section). The MAX1157/MAX1159/
MAX1175 automatically enter either standby mode (reference and buffer on), or shutdown (reference and buffer
off) after each conversion depending on the status of
R/C during the second falling edge of CS.
0.1µF
DVDD
AVDD
ANALOG
INPUT
Power-Down Modes
+5V DIGITAL
D0–D13
AIN
R/C
CS
RESET
MAX1157
MAX1159
MAX1175
µP DATA
BUS
14-BIT
WIDE
Internal Clock
EOC
REF
REFADJ
AGND DGND
0.1µF
10µF
The MAX1157/MAX1159/MAX1175 generate an internal
conversion clock to free the microprocessor from the burden of running the SAR conversion clock. Total conversion time after entering hold mode (second falling edge
of CS) to end-of-conversion (EOC) falling is 4.7µs (max).
Applications Information
Starting a Conversion
Figure 3. Typical Application Circuit for the MAX1157/MAX1159/
MAX1175
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
(AIN) charges capacitor CHOLD. The acquisition ends
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on CHOLD represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of 14-bit resolution. Force CS low to put valid
data on the bus after conversion is complete.
8
CS and R/C control acquisition and conversion in the
MAX1157/MAX1159/MAX1175 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start CS is
ignored if R/C is high. The MAX1157/MAX1159/
MAX1175 need at least 6ms (CREFADJ = 0.1µF, CREF =
10µF) for the internal reference to wake up and settle
before starting the conversion if powering up from shutdown. Reset the MAX1157/MAX1159/MAX1175 by toggling RESET with CS high. The next falling edge of CS
begins acquisition.
Selecting Standby or Shutdown Mode
The MAX1157/MAX1159/MAX1175 have a selectable
standby or low-power shutdown mode. In standby
mode, the ADC’s internal reference and reference
buffer do not power down between conversions, eliminating the need to wait for the reference to power up
before performing the next conversion. Shutdown mode
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
MAX1157/MAX1159/MAX1175
REF
MAX1157
R2
161Ω
MAX1159/MAX1175
3.4kΩ
3.4kΩ
AIN
TRACK
S1
CHOLD
30pF
161Ω
AIN
HOLD
R3
S2
S1, S2 = T/H SWITCH
S3 = POWER-DOWN
(MAX1159/MAX1175
ONLY)
TRACK
S1
T/H OUT
HOLD TRACK
R3
R2
S3
POWERDOWN
CHOLD
30pF
HOLD TRACK
T/H OUT
HOLD
S2
R2 = 7.85kΩ (MAX1159)
OR 3.92kΩ (MAX1157/MAX1175)
R3 = 5.45kΩ (MAX1159)
OR 17.79kΩ (MAX1157/MAX1175)
Figure 4. Equivalent Input Circuit
ACQUISITION
CONVERSION
DATA
OUT
CS
R/C
EOC
REF AND
BUFFER
POWER
Figure 5. Selecting Standby Mode
powers down the reference and reference buffer after
completing a conversion. The reference and reference
buffer require a minimum of 12ms (CREFADJ = 0.1µF,
CREF = 10µF) to power up and settle from shutdown.
The state of R/C during the second falling edge of CS
selects which power-down mode the MAX1157/
MAX1159/MAX1175 enters upon conversion completion. Holding R/C low causes the MAX1157/MAX1159/
MAX1175 to enter standby mode. The reference and
buffer are left on after the conversion completes. R/C
high causes the MAX1157/MAX1159/MAX1175 to enter
shutdown mode and power down the reference and
buffer after conversion (see Figures 5 and 6). Set the
voltage at REF high during the second falling edge of
CS to realize the lowest current operation.
Standby Mode
While in standby mode, the supply current is less than
3.7mA (typ). The next falling edge of CS with R/C low
causes the MAX1157/MAX1159/MAX1175 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time.
_______________________________________________________________________________________
9
MAX1157/MAX1159/MAX1175
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ACQUISITION
CONVERSION
DATA
OUT
CS
R/C
EOC
REF AND
BUFFER
POWER
Figure 6. Selecting Shutdown Mode
MAX1157
MAX1159
MAX1175
+5V
100kΩ
68kΩ
REFADJ
0.1µF
150kΩ
Figure 7. MAX1157/MAX1159/MAX1175 Reference Adjust
Circuit
Shutdown Mode
In shutdown mode, the reference and reference buffer
shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The next falling edge of CS with R/C
low causes the reference and buffer to wake up and
enter acquisition mode. To achieve 14-bit accuracy,
allow 12ms (CREFADJ = 0.1µF, CREF = 10µF) for the
internal reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1157/MAX1159/
MAX1175 is internally buffered to provide +4.096V output at REF. Bypass REF to AGND and REFADJ to
AGND with 10µF and 0.1µF, respectively.
Sink or source current at REFADJ to make fine adjustments to the internal reference. The input impedance of
REFADJ is nominally 5kΩ. Use the circuit of Figure 7 to
adjust the internal reference to ±1.5%.
10
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1157/
MAX1159/MAX1175’s internal buffer amplifier. Using
the buffered REFADJ input makes buffering the external
reference unnecessary. The input impedance of
REFADJ is typically 5kΩ. The internal buffer output
must be bypassed at REF with a 10µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external 3.8V to 4.2V reference. During conversion, the external reference must
be able to drive 100µA of DC load current and have an
output impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10µF capacitor.
Consider the MAX1157/MAX1159/MAX1175’s equivalent
input noise (0.6LSB) when choosing a reference.
Reading the Conversion Result
EOC flags the microprocessor when a conversion is
complete. The falling edge of EOC signals that the data
is valid and ready to be output to the bus. D0–D13 are
the parallel outputs of the MAX1157/MAX1159/
MAX1175. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conversion. Data is loaded onto the bus with the third falling
edge of CS with R/C high (after tDO). Bringing CS high
forces the output bus back to high impedance. The
MAX1157/MAX1159/MAX1175 then wait for the next
falling edge of CS to start the next conversion cycle
(see Figure 2).
______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
11 . . . 1111
11 . . . 1110
11 . . . 1101
FULL-SCALE RANGE
(FSR) = +10V
1LSB =
00 . . . 011
FSR x VREF
16384 x 4.096
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
16382 16384
16383
3
Figure 8. MAX1157 Transfer Function
INPUT RANGE = -5V TO +5V
10 . . . 0001
10 . . . 0000
01 . . . 1111
FULL-SCALE RANGE
(FSR) = +10V
1LSB =
00 . . . 0011
00 . . . 0010
00 . . . 0001
00 . . . 0000
-8192 -8190
-8191 -8189
-1
0
10 . . . 0001
10 . . . 0000
01 . . . 1111
FULL-SCALE RANGE
(FSR) = +20V
1LSB =
00 . . . 0011
00 . . . 0010
00 . . . 0001
00 . . . 0000
-8192 -8190
-8191 -8189
-1
0
+1
FSR x VREF
16384 x 4.096
+8190 +8192
+8191
Figure 9. MAX1159 Transfer Function
FULL-SCALE
TRANSITION
11 . . . 1111
11 . . . 1110
11 . . . 1101
FULL-SCALE
TRANSITION
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
OUTPUT CODE
INPUT RANGE = -10V TO +10V
FSR x VREF
16384 x 4.096
+8190 +8192
+8191
+1
INPUT VOLTAGE (LSB)
Figure 10. MAX1175 Transfer Function
Transfer Function
Figures 8, 9, and 10 show the MAX1157/MAX1159/
MAX1175’s output transfer functions. The MAX1159
and MAX1175 outputs are coded in offset binary, while
the MAX1157 is coded on standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy and prevent loading the
source. Switch the channels immediately after acquisition, rather than near the end of or after a conversion
when the input signal is multiplexed. This allows more
time for the input buffer amplifier to respond to a large
step-change in input signal. The input amplifier must
have a high enough slew rate to complete the required
output voltage change before the beginning of the
acquisition time. Figure 11 shows an example of this
circuit using the MAX427.
Figures 12a and 12b show how the MAX1175 and
MAX1159 analog input current varies depending on
whether the chip is operating or powered down. The
part is fully powered down between conversions if the
voltage at R/C is set high during the second falling
edge of CS. The input current abruptly steps to the
powered up value at the start of acquisition. This step
in the input current can disrupt the ADC input, depending on the driving circuit’s output impedance at high
frequencies. If the driving circuit cannot fully settle by
the end of acquisition time, the accuracy of the system
can be compromised. To avoid this situation, increase
the acquisition time, use a driving circuit that can settle
within tACQ, or leave the MAX1175/MAX1159 powered
up by setting the voltage at R/C low during the second
falling edge of CS.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Do not run analog and digital lines parallel to each
other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground planes with only one point connecting the
two ground systems (analog and digital) as close to the
device as possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
______________________________________________________________________________________
11
MAX1157/MAX1159/MAX1175
INPUT RANGE = 0 TO +10V
OUTPUT CODE
Definitions
Integral Nonlinearity
REF
MAX1157
MAX1159
MAX1175
**
MAX427
AIN
ANALOG
INPUT
*
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1157/MAX1159/
MAX1175 are measured using the endpoint method.
Differential Nonlinearity
*MAX1157 ONLY.
**MAX1159/MAX1175 ONLY.
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Figure 11. MAX1157/MAX1159/MAX1175 Fast-Settling Input
Buffer
onto the analog lines. If the analog and digital sections
share the same supply, isolate the digital and analog
supply by connecting them with a low value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AV DD supply. Bypass AV DD to AGND with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capacitor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N bits):
SNR = ((6.02 ✕ N) + 1.76)dB
where N = 14 bits.
MAX1175
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
MAX1159
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
2.0
1.5
ANALOG INPUT CURRENT (mA)
1.5
ANALOG INPUT CURRENT (mA)
MAX1157/MAX1159/MAX1175
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
1.0
0.5
SHUTDOWN MODE
0
-0.5
STANDBY MODE
-1.0
0.5
SHUTDOWN MODE
0
STANDBY MODE
-0.5
-1.0
-1.5
-2.0
-1.5
-5.0
-2.5
0
2.5
ANALOG INPUT VOLTAGE (V)
Figure 12a. MAX1175 Analog Input Current
12
1.0
5.0
-10
-5
0
5
ANALOG INPUT VOLTAGE (V)
Figure 12b. MAX1159 Analog Input Current
______________________________________________________________________________________
10
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
2
2
2
2
V2 + V3 + V4 + V5
THD = 20 × log
V1
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
SignalRMS
SINAD(db) = 20 × log
(
+
)
Noise
Distortion
RMS
Spurious-Free Dynamic Range
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
SINAD - 1.76
ENOB =
6.02
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
Chip Information
TRANSISTOR COUNT: 15,383
PROCESS: BiCMOS
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
INPUT VOLTAGE
RANGE
INL (LSB)
MAX1157AEUI
-40°C to +85°C
28 TSSOP
0 to +10V
±1
MAX1157BEUI
-40°C to +85°C
28 TSSOP
0 to +10V
±2
MAX1159ACUI
0°C to +70°C
28 TSSOP
±10V
±1
MAX1159BCUI
0°C to +70°C
28 TSSOP
±10V
±2
MAX1159AEUI*
-40°C to +85°C
28 TSSOP
±10V
±1
MAX1159BEUI*
-40°C to +85°C
28 TSSOP
±10V
±2
MAX1175ACUI
0°C to +70°C
28 TSSOP
±5V
±1
MAX1175BCUI
0°C to +70°C
28 TSSOP
±5V
±2
MAX1175AEUI
-40°C to +85°C
28 TSSOP
±5V
±1
MAX1175BEUI
-40°C to +85°C
28 TSSOP
±5V
±2
*Future product—contact factory for availability.
______________________________________________________________________________________
13
MAX1157/MAX1159/MAX1175
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
MAX1157/MAX1159/MAX1175
Functional Diagram
REFADJ
AVDD AGND DVDD DGND
5kΩ
REFERENCE
OUTPUT
REGISTERS
14 BITS
14 BITS
D0–D13
REF
AIN
INPUT
SCALER
MAX1157
MAX1159
MAX1175
CAPACITIVE
DAC
AGND
RESET
CLOCK
CS
SUCCESSIVEAPPROXIMATION
REGISTER AND
CONTROL LOGIC
EOC
R/C
14
______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
TSSOP4.40mm.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1157/MAX1159/MAX1175
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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