19-2525; Rev 1; 4/10
KIT
ATION
EVALU
E
L
B
AVAILA
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Features
The MAX1162 low-power, 16-bit analog-to-digital converter (ADC) features a successive-approximation ADC,
automatic power-down, fast 1.1µs wakeup, and a highspeed SPI™/QSPI™/MICROWIRE™-compatible interface. The MAX1162 operates with a single +5V analog
supply and features a separate digital supply, allowing
direct interfacing with +2.7V to +5.25V digital logic.
o 16-Bit Resolution, No Missing Codes
At the maximum sampling rate of 200ksps, the
MAX1162 consumes typically 2.75mA. Power consumption is typically 13.75mA (AVDD = DVDD = +5V) at
a 200ksps (max) sampling rate. AutoShutdown™
reduces supply current to 140µA at 10ksps and to less
than 10µA at reduced sampling rates.
Excellent dynamic performance and low power, combined with ease of use and small package size (10-pin
µMAX® and 10-pin DFN) make the MAX1162 ideal for
battery-powered and data-acquisition applications or
for other circuits with demanding power consumption
and space requirements.
o SPI/QSPI/MICROWIRE-Compatible Serial Interface
o +5V Single-Supply Operation
o Adjustable Logic Level (+2.7V to +5.25V)
o Input-Voltage Range: 0 to VREF
o Internal Track/Hold, 4MHz Input Bandwidth
o Small 10-Pin µMAX or 10-Pin DFN Package
o Low Power
2.75mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
Ordering Information
TEMP
RANGE
PART
Applications
PINPACKAGE
INL
(LSB)
MAX1162BCUB+
0°C to +70°C
10 µMAX
±2
Motor Control
MAX1162BC_B*
0°C to +70°C
10 DFN
±2
Industrial Process Control
MAX1162CCUB+
0°C to +70°C
10 µMAX
±4
MAX1162CC_B*
0°C to +70°C
10 DFN
MAX1162BEUB+
-40°C to +85°C
10 µMAX
±2.5
MAX1162BE_B*
-40°C to +85°C
10 DFN
±2.5
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
±4
MAX1162CEUB+
-40°C to +85°C
10 µMAX
±4
Accelerometer Measurements
MAX1162CE_B*
-40°C to +85°C
10 DFN
±4
Portable- and Battery-Powered Equipment
*Future product—contact factory for DFN package availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
Functional Diagram appears at end of data sheet.
TOP VIEW
REF 1
AVDD
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
10 AIN
2
MAX1162
9
AGND
8
DVDD
AGND
3
CS
4
7
DGND
SCLK
5
6
DOUT
µMAX/DFN
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1162
General Description
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AIN, REF to AGND ...................................-0.3V to (AVDD + 0.3V)
SCLK, CS to DGND ..................................................-0.3V to +6V
DOUT to DGND .......................................-0.3V to (DVDD + 0.3V)
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ..........444mW
Operating Temperature Ranges
MAX1162_CUB .................................................0°C to +70°C
MAX1162_EUB ..............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7µF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
16
TA = -40°C
MAX1162B
Relative Accuracy (Note 2)
INL
MAX1162C
MAX1162B
Differential Nonlinearity
DNL
MAX1162C
Transition Noise
RMS noise
Offset Error
Gain Error
(Note 3)
Offset Drift
Gain Drift
(Note 3)
Bits
-2.5
+2.5
TA = 0°C
-2
+2
TA = +85°C
-2
+2
TA = -40°C
-4
+4
TA = 0°C
-4
+4
TA = +85°C
-4
+4
TA = -40°C
NMC*
2
TA = 0°C
NMC*
1.75
TA = +85°C
NMC*
1.75
TA = -40°C
-2
+2
TA = 0°C
-2
+2
TA = +85°C
-2
+2
±0.65
LSB
LSBRMS
0.1
1
mV
±0.002
±0.01
%FSR
0.4
ppm/oC
0.2
ppm/oC
*NMC = No missing code.
2
LSB
_______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7µF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINAD
86
89.5
dB
SNR
87
90
dB
92
103
dB
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VPSignal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
-90
dB
Full-Power Bandwidth
-3dB point
4
MHz
Full-Linear Bandwidth
SINAD > 86dB
10
kHz
CONVERSION RATE
Conversion Time
tCONV
Serial Clock Frequency
fSCLK
(Note 4)
5
0.1
240
µs
4.8
MHz
Aperture Delay
tAD
15
ns
Aperture Jitter
tAJ
4MHz) that can
drive the ADC’s input capacitance and settle quickly.
_______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
1mA
1mA
DOUT
DOUT
DOUT
1mA
CLOAD = 50pF
CLOAD = 50pF
CLOAD = 50pF
DGND
DGND
a) VOL TO VOH
DOUT
1mA
CLOAD = 50pF
DGND
MAX1162
VDD
VDD
DGND
a) VOH TO HIGH-Z
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
b) VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
CS
tCSW
tCSS
tCH
tCL
tCSH
SCLK
tCP
tDV
tDO
tTR
DOUT
TIMING NOT TO SCALE.
Figure 3. Detailed Serial Interface Timing
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
AIN
VREF
AIN
CS
REF
SCLK
DOUT
CS
SCLK
DOUT
4.7µF
AVDD
+5V
MAX1162
0.1µF
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD or AGND, allow the input to swing from
AGND - 0.3V to AVDD + 0.3V, without damaging the
device.
If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
+5V
DVDD
0.1µF
AGND
DGND
GND
Figure 4. Typical Operating Circuit
_______________________________________________________________________________________
9
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Digital Interface
Initialization after Power-Up and
Starting a Conversion
REF
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1162 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1162 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
TRACK
AIN
CAPACITIVE DAC
ZERO
CSWITCH
3pF
CDAC 32pF
HOLD
RIN
800Ω
GND
TRACK
HOLD
AUTO-ZERO
RAIL
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure that the minimum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Figure 5. Equivalent Input Circuit
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros and 16 data bits. Extra clock pulses occurring
after the conversion result has been clocked out, and
prior to the rising edge of CS, produce trailing zeros at
DOUT and have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX1162 in
shutdown. For maximum throughput, force CS low
again to initiate the next conversion immediately after
the specified minimum time (tCSW).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX1162 in shutdown.
Note: Coupling between SCLK and the analog
inputs (AIN and REF) may result in an offset.
Variations in frequency, duty cycle, or other aspects
of the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
CS
SCLK
DOUT
tDV
1
4
tCSS
tCL
6
8
16
24
20
tCSH
tCH
tACQ
12
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
tDO
Figure 6. External Timing Diagram
10
D0
______________________________________________________________________________________
tTR
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX1162
COMPLETE CONVERSION SEQUENCE
CS
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED DOWN
POWERED UP
TIMING NOT TO SCALE.
Figure 7. Shutdown Sequence
Output Coding and
Transfer Function
The data output from the MAX1162 is binary and Figure
8 depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(VREF = 4.096V and 1LSB = 63µV or 4.096V/65536).
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
Applications Information
External Reference
The MAX1162 requires an external reference with a
+3.8V and AVDD voltage range. Connect the external
reference directly to REF. Bypass REF to AGND (pin 3)
with a 4.7µF capacitor. When not using a low-ESR
bypass capacitor, use a 0.1µF ceramic capacitor in
parallel with the 4.7µF capacitor. Noise on the reference degrades conversion accuracy.
The input impedance at REF is 40kΩ for DC currents.
During a conversion the external reference at REF must
deliver 100µA of DC load current and have an output
impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX1162’s equivalent input noise (38µV RMS) when
choosing a reference.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multiplexed, switch the input channel immediately after acquisition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/µs to complete the required output-voltage
change before the beginning of the acquisition time.
FS = VREF
VREF
65536
1LSB =
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
INPUT VOLTAGE (LSB)
FS
FS - 3/2LSB
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conversion clock (SCLK) and other digital signals active during input acquisition contribute noise to the conversion
result. Noise signals synchronous with the sampling
interval result in an effective input offset. Asynchronous
signals produce random noise on the input, whose
high-frequency components can be aliased into the fre-
______________________________________________________________________________________
11
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
IN1
IN2
A0
A1
4-TO-1
MUX
MAX1162
IN3
AIN
OUT
IN4
CS
CLK
ACQUISITION
CONVERSION
CS
A0
A1
TIMING NOT TO SCALE.
CHANGE MUX INPUT HERE
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
quency band of interest. Minimize noise by presenting
a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN
to AGND, or buffering the input with an amplifier that
has a small-signal bandwidth of several MHz, or preferably both. AIN has 4MHz (typ) of bandwidth.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1162’s offset (1mV (max) for +5V
supply), or whose offset can be trimmed while maintaining stability over the required temperature range.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX1162’s
total harmonic distortion (THD = -102dB at 1kHz) at frequencies of interest. If the chosen amplifier has insufficient common-mode rejection, which results in degraded
THD performance, use the inverting configuration (positive input grounded) to eliminate errors from this source.
Low temperature-coefficient, gain-setting resistors reduce
linearity errors caused by resistance changes due to selfheating. To reduce linearity errors due to finite amplifier
gain, use amplifier circuits with sufficient loop gain at the
frequencies of interest.
The MAX1162’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
12
Serial Interfaces
If a serial interface is available, establish the CPU’s serial interface as master, so that the CPU generates the
serial clock for the MAX1162. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull
CS low.
2) Activate SCLK for a minimum of 24 clock cycles.
The serial data stream of eight leading zeros followed by the MSB of the conversion result begins at
the falling edge of CS. DOUT transitions on SCLK’s
falling edge and the output is available in MSB-first
______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
I/O
SCK
MISO
When using the SPI (Figure 10a) or MICROWIRE
(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.
Conversion begins with a falling edge on CS (Figure
10c). Three consecutive 8-bit readings are necessary
to obtain the entire 16-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge. The
first 8-bit data stream contains all leading zeros. The
second 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1162 supports a maximum
fSCLK of 4.8MHz. Figure 11a shows the MAX1162 connected to a QSPI master and Figure 11b shows the
associated interface timing.
CS
I/O
CS
SCLK
SK
SCLK
DOUT
SI
DOUT
MICROWIRE
VDD
SPI
MAX1162
MAX1162
SS
Figure 10a. SPI Connections
Figure 10b. MICROWIRE Connections
1ST BYTE READ
1
SCLK
2ND BYTE READ
4
6
12
8
16
CS
0
DOUT*
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
TIMING NOT TO SCALE.
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
______________________________________________________________________________________
13
MAX1162
SPI and MICROWIRE Interfaces
format. Observe the SCLK to DOUT valid timing
characteristic. Clock data into the µP on SCLK’s rising edge.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
4) With CS high, wait at least 50ns (tCSW) before starting a new conversion by pulling CS low. A conversion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
Data can be output in three 8-bit sequences or continuously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the LSB (D0) and
CS has been kept low, DOUT sends trailing zeros.
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
CS
CS
SCK
QSPI
SCLK
MISO
DOUT
VDD
MAX1162
SS
Figure 11a. QSPI Connections
1
SCLK
CS
4
6
8
END OF
ACQUISITION
DOUT*
12
D15
D14
D13
D12
16
D11
D10
D9
D8
24
20
D7
D6
D5
D4
D3
D2
D1
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
D0
HIGH-Z
LSB
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
PIC16 with SSP Module and
PIC17 Interface
VDD
VDD
SCLK
SCK
DOUT
SDI
CS
I/O
PIC16/17
MAX1162
GND
Figure 12a. SPI Interface Connection for a PIC16/PIC17
The MAX1162 is compatible with a PIC16/PIC17 microcontroller (µC) using the synchronous serial-port (SSP)
module.
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µC allows 8 bits of data
to be synchronously transmitted and received simulta-
Table 1. Detailed SSPCON Register Contents
CONTROL BIT
MAX1162
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detect Bit
SSPEN
BIT5
1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
CKP
BIT4
0
SSPM3
BIT3
0
SSPM2
BIT2
0
SSPM1
BIT1
0
SSPM0
BIT0
1
14
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
MAX1162
Table 2. Detailed SSPSTAT Register Contents
MAX1162
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP
BIT7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE
BIT6
1
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A
BIT5
X
Data Address Bit
P
BIT4
X
Stop Bit
S
BIT3
X
Start Bit
R/W
BIT2
X
Read/Write Bit Information
UA
BIT1
X
Update Address
BF
BIT0
X
Buffer Full Status Bit
X = Don’t care.
1ST BYTE READ
2ND BYTE READ
12
SCLK
16
CS
0
DOUT*
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
TIMING NOT TO SCALE.
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
neously. Three consecutive 8-bit readings (Figure 12b)
are necessary to obtain the entire 16-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains all zeros. The second 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains bits D7 through D0.
Definitions
tion, once offset and gain errors have been nulled. The
static linearity parameters for the MAX1162 are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Integral Nonlinearity
Aperture Definitions
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-fit straight line fit or a
line drawn between the endpoints of the transfer func-
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
______________________________________________________________________________________
15
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ENOB = (SINAD - 1.76) / 6.02
ENOB vs. INPUT FREQUENCY
Figure 13 shows the effective number of bits as a function of the MAX1162’s input frequency.
16
14
Total Harmonic Distortion
EFFECTIVE BITS
12
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
10
8
6
⎡
V22 + V32 + V4 2 + V52
THD = 20 × log⎢⎢
V1
⎢⎣
4
2
0
0.1
1
10
100
INPUT FREQUENCY (kHz)
Figure 13. Effective Number of Bits vs. Input Frequency
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADCs resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
⎤
⎥
⎥
⎥⎦
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
Supplies, Layout, Grounding,
and Bypassing
Use PC boards with separate analog and digital
ground planes. Do not use wire-wrap boards. Connect
the two ground planes together at the MAX1162 (pin 3).
Isolate the digital supply from the analog with a lowvalue resistor (10Ω) or ferrite bead when the analog
and digital supplies come from the same source
(Figure 14).
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals,
excluding the DC offset.
⎡
⎤
SignalRMS
⎥
SINAD(dB) = 20 × log ⎢
⎢ (Noise + Distortion)
⎥
RMS ⎦
⎣
Effective Number of Bits
Effective number of bits (ENOB) indicate the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
16
AIN
VREF
AIN
CS
REF
SCLK
DOUT
CS
SCLK
DOUT
4.7µF
AVDD
+5V
MAX1162
10Ω
0.1µF
DVDD
AGND
DGND
0.1µF
GND
Figure 14. Powering AVDD and DVDD from a Single Supply
______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
• Apply AGND before DGND.
• Apply AIN and REF after AVDD and AGND
are present.
• DVDD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV, 4LSB error with a +4V fullscale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and
digital (especially the SCLK and DOUT) lines parallel to
one another. If one must cross another, do so at right
angles.
The ADCs high-speed comparator is sensitive to highfrequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
AVDD
REF
AIN
AGND
TRACK AND
HOLD
SCLK
16-BIT SAR
ADC
OUTPUT
BUFFER
DOUT
CONTROL
CS
MAX1162
DGND
Package Information
Chip Information
PROCESS: BiCMOS
DVDD
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
10 µMAX
U10-2
21-0061
______________________________________________________________________________________
17
MAX1162
Functional Diagram
Constraints on sequencing the power supplies and
inputs are as follows:
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/02
Initial release
1
4/10
Changed analog supply current and added lead-free information
DESCRIPTION
PAGES
CHANGED
—
1, 3, 5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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