19-2956; Rev 1; 10/09
KIT
ATION
EVALU
LE
B
A
IL
A
AV
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
The MAX1167/MAX1168 low-power, multichannel, 16bit analog-to-digital converters (ADCs) feature a successive-approximation ADC, integrated +4.096V
reference, a reference buffer, an internal oscillator,
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The
MAX1167/MAX1168 operate with a single +5V analog
supply and feature a separate digital supply, allowing
direct interfacing with +2.7V to +5.5V digital logic.
The MAX1167/MAX1168 consume only 3.6mA (AVDD =
DVDD = +5V) at 200ksps when using an external reference.
AutoShutdown™ reduces the supply current to 185µA at
10ksps and to less than 10µA at reduced sampling rates.
The MAX1167 includes a 4-channel input multiplexer, and
the MAX1168 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated conversions are simplified with the DSP frame-sync input and
output featured in the MAX1168. The MAX1168 includes
a data-bit transfer input to select between 8-bit-wide or
16-bit-wide data-transfer modes. Both devices feature a
scan mode that converts each channel sequentially or
one channel continuously.
Excellent dynamic performance and low power, combined with ease of use and an integrated reference, make
the MAX1167/MAX1168 ideal for control and data-acquisition operations or for other applications with demanding
power consumption and space requirements. The
MAX1167 is available in a 16-pin QSOP package and the
MAX1168 is available in a 24-pin QSOP package. Both
devices are guaranteed over the commercial (0°C to
+70°C) and extended (-40°C to +85°C) temperature
ranges. Use the MAX1168 evaluation kit to evaluate the
MAX1168.
Features
♦ 16-Bit Resolution, No Missing Codes
♦ +5V Single-Supply Operation
♦ Adjustable Logic Level (+2.7V to +5.25V)
♦ Input Voltage Range: 0 to VREF
♦ Internal (+4.096V) or External (+3.8V to AVDD)
Reference
♦ Internal Track/Hold, 4MHz Input Bandwidth
♦ Internal or External Clock
♦ SPI/QSPI/MICROWIRE-Compatible Serial
Interface, MAX1168 Performs DSP-Initiated
Conversions
♦ 8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode
(MAX1168 Only)
♦ 4-Channel (MAX1167) or 8-Channel (MAX1168)
Input Mux
Scan Mode Sequentially Converts Multiple
Channels or One Channel Continuously
♦ Low Power
3.6mA at 200ksps
1.85mA at 100ksps
185µA at 10ksps
0.6µA in Full Power-Down Mode
♦ Small Package Size
16-Pin QSOP (MAX1167)
24-Pin QSOP (MAX1168)
Ordering Information
Applications
Motor Control
PART
TEMP RANGE
PINPACKAGE
INL
(LSB)
Industrial Process Control
MAX1167BCEE
0°C to +70°C
16 QSOP
±3
Industrial I/O Modules
MAX1167BEEE
-40°C to +85°C
16 QSOP
±3
Data-Acquisition Systems
MAX1168BCEG
0°C to +70°C
24 QSOP
±3
Thermocouple Measurements
MAX1168BEEG
-40°C to +85°C
24 QSOP
±3
Accelerometer Measurements
Pin Configurations appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1167/MAX1168
General Description
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AIN_, REF, REFCAP to AGND..................-0.3V to (AVDD + 0.3V)
SCLK, CS, DSEL, DSPR, DIN to DGND ...................-0.3V to +6V
DOUT, DSPX, EOC to DGND...................-0.3V to (DVDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Operating Temperature Ranges
MAX116_ _ CE_ ..................................................0°C to +70°C
MAX116_ _ EE_ ...............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1.8
±3
LSB
+0.7
+1.75
LSB
DC ACCURACY (Note 1)
Resolution
16
Relative Accuracy (Note 2)
INL
MAX116_B
Differential Nonlinearity
DNL
MAX116_B
(16 bit, no missing codes over temperature)
RMS
noise
Transition Noise
16-bit
NMC
External reference
0.7
Internal reference
0.8
Offset Error
Gain Error
(Note 3)
Offset Drift
Gain Drift
Bits
(Note 3)
LSBRMS
±0.1
±10
mV
±0.01
±0.2
%FSR
1
ppm/°C
±1.2
ppm/°C
88.5
dB
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 1)
Signal-to-Noise Plus Distortion
SINAD
85
Signal-to-Noise Ratio
SNR
86
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
88.5
-100
88
dB
-88
dB
101
dB
Full-Power Bandwidth
-3dB point
4
MHz
Full-Linear Bandwidth
SINAD > 85dB
10
kHz
Channel-to-Channel Isolation
(Note 4)
96
dB
CONVERSION RATE
Conversion Time
tCONV
Acquisition Time
tACQ
Serial Clock Frequency
f SCLK
2
Internal clock, no data transfer,
single conversion (Note 5)
5.52
External clock
3.75
(Note 6)
729
External clock, data transfer and conversion
0.1
External clock, data transfer only
_______________________________________________________________________________________
7.07
μs
ns
4.8
9
MHz
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Internal Clock Frequency
SYMBOL
f INTCLK
Aperture Delay
tAD
Aperture Jitter
tAJ
Sample Rate (Note 7)
fS
CONDITIONS
Internal clock
MIN
TYP
MAX
3.2
4.0
MHz
15
ns
10MHz) that can drive the ADC’s input capacitance
and settle quickly.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz smallsignal bandwidth, making possible the digitization of
high-speed transient events and the measurement of
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted, high-frequency signals into
the frequency band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD or AGND, allow the input to swing from
(AGND - 0.3V) to (AVDD + 0.3V) without damaging the
device. If the analog input exceeds 300mV beyond the
supplies, limit the input current to 10mA.
______________________________________________________________________________________
13
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
AIN0
AIN1
AIN2
AIN3
ANALOG
INPUTS
DIN
CS
SCLK
DOUT
EOC
SCLK
DOUT
EOC
CS
AIN0
AIN1
AIN2
AIN3
ANALOG
INPUTS
AIN4
AIN5
AIN6
DIN
CS
SCLK
DSPX
SCLK
DSPX
DOUT
DOUT
EOC
EOC
AIN7
MAX1167
REF
DIN
16
8
1μF
AGND
AGND
DGND
AVDD
+5V
0.1μF
DVDD
+5V
DIN
MAX1168
DSEL
DSPR
REF
1μF
AGND
AGND
DGND
AVDD
+5V
REFCAP
0.1μF
0.1μF
0.1μF
DVDD
+5V
REFCAP
0.1μF
0.1μF
GND
GND
Figure 5. MAX1167 Typical Operating Circuit
In addition to the standard 3-wire serial interface modes,
the MAX1168 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode and
a DSEL input to determine 8-bit-wide or 16-bit-wide datatransfer mode. When not using the MAX1168 in the DSP
interface mode, connect DSPR to DVDD and leave DSPX
unconnected.
REF
MUX
RDSON
Figure 6. MAX1168 T ypical Operating Circuit
TRACK
AIN_
CAPACITIVE
DAC
ZERO
CMUX
HOLD
CSWITCH
CDAC
RIN
AGND
HOLD
Command/Configuration/Control Register
TRACK
Table 1 shows the contents of the command/configuration/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configuration
of the device for each bit. Cycling the power supplies
resets the command/configuration/control register to the
power-on-reset default state.
AUTOZERO
RAIL
Figure 7. Equivalent Input Circuit
Digital Interface
The MAX1167/MAX1168 feature an SPI/QSPI/
MICROWIRE-compatible, 3-wire serial interface. The
MAX1167 digital interface consists of digital inputs CS,
SCLK, and DIN and outputs DOUT and EOC. The
MAX1167 operates in the following modes:
• SPI interface with external clock
• SPI interface with internal clock
• SPI interface with internal clock and scan mode
Initialization After Power-Up
A logic high on CS places the MAX1167/MAX1168 in
the shutdown mode chosen by the power-down bits,
and places DOUT in a high-impedance state. Drive CS
low to power up and enable the MAX1167/MAX1168
before starting a conversion. In internal reference
mode, allow 5ms for the shutdown internal reference
and/or buffer to wake and stabilize before starting a
conversion. In external reference mode (or if the internal reference is already on), no reference settling time
is needed after power-up.
Table 1. Command/Configuration/Control Register
COMMAND
POWER-UP
STATE
14
BIT7 (MSB)
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0 (LSB)
CH SEL2
CH SEL1
CH SEL0
SCAN1
SCAN0
REF/PD_SEL1
REF/PD SEL0
INT/EXT CLK
0
0
0
0
0
1
1
0
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
BIT7
BIT6
BIT5
CH SEL2
CH SEL1
CH SEL0
CHANNEL
AIN_
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
1
1
1
1
Table 3. MAX1167 Scan Mode, Internal
Clock Only
BIT4
BIT3
SCAN1
SCAN0
Single channel, no scan
0
0
Sequentially scan channels 0 through N
(N ≤ 3)
0
1
5
Sequentially scan channels 2 through N
(2 ≤ N ≤ 3)
1
0
0
6
Scan channel N four times
1
1
1
7
ACTION
Table 4. MAX1168 Scan Mode, Internal
Clock Only (Not for DSP Mode)
ACTION
BIT4
BIT3
SCAN1
SCAN0
Single channel, no scan
0
0
Sequentially scan channels 0 through N
(N ≤ 7)
0
1
Sequentially scan channels 4 through N
(4 ≤ N ≤ 7)
1
0
Scan channel N eight times
1
1
Table 5. Power-Down Modes
BIT2
BIT1
REF/PD_
SEL1
REF/PD
SEL0
REFERENCE
0
0
Internal
0
1
1
1
TYPICAL
SUPPLY
CURRENT
TYPICAL WAKEUP TIME
(CREF = 1µF)
Internal reference and reference buffer on
between conversions
1mA
NA
Internal
Internal reference and reference buffer off
between conversions
0.6µA
5ms
0
Internal
Internal reference on, reference buffer off
between conversions
0.43mA
5ms
1
External
Internal reference and buffer always off
0.6µA
NA
REFERENCE MODE
(INTERNAL REFERENCE)
Table 6. Clock Modes
BIT0
INT/EXT
CLK
CLOCK MODE
0
External clock
1
Internal clock
______________________________________________________________________________________
15
MAX1167/MAX1168
Table 2. Channel Select
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
tCSW
CS
tCSS
tCP
tCL
tCSH
tCH
•••
SCLK
tDS
tDH
DIN
tDO
tTR
tDV
DOUT
Figure 8. Detailed SPI Interface Timing
when in SPI/QSPI/MICROWIRE mode and on the falling
edge of DSPR when in DSP mode. Allow 5ms for the
internal reference to rise and settle when powering up
from a complete shutdown (VREF = 0, CREF = 1µF).
CS
COMPLETE CONVERSION SEQUENCE
DOUT
CONVERSION 0
CONVERSION 1
POWERED UP POWERED DOWN
POWERED UP
Figure 9. Shutdown Sequence
Power-Down Modes
Table 5 shows the MAX1167/MAX1168 power-down
modes. Three internal reference modes and one external reference mode are available. Select power-down
modes by writing to bits 2 and 1 in the command/configuration/control register. The MAX1167/MAX1168
enter the selected power-down mode on the rising
edge of CS.
The internal reference stays on when CS is pulled high,
if bits 2 and 1 are set to zero. This mode allows for the
fastest turn-on time.
Setting bit 2 = 0 and bit 1 = 1 turns both the reference
and reference buffer off when CS is brought high. This
mode achieves the lowest supply current. The reference and buffer wake up on the falling edge of CS
16
The internal reference stays on and the buffer is shut off
on the rising edge of CS when bit 2 = 1 and bit 1 = 0.
The MAX1167/MAX1168 enter this mode on the rising
edge of CS. The buffer wakes up on the falling edge of
CS when in SPI/QSPI/MICROWIRE mode and on the rising edge of DSPR when in DSP mode. Allow 5ms for
VREF to settle when powering up from a complete shutdown (VREF = 0, CREF = 1µF). VREFCAP is always equal
to +4.096V in this mode.
Set both bit 2 and bit 1 to 1 to turn off the reference and
reference buffer to allow connection of an external reference. Using an external reference requires no extra
wake-up time.
Operating Modes
External Clock 8-Bit-Wide Data-Transfer Mode
(MAX1167 and MAX1168)
Force DSPR high and DSEL low (MAX1168) for SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data. Ensure the duty cycle on SCLK is between 45%
and 55% when operating at 4.8MHz (the maximum
clock frequency). For lower clock frequencies, ensure
the minimum high and low times are at least 93ns.
External-clock-mode conversions with
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168
CS
1
16
8
24
SCLK
MSB
LSB
DIN
0
MSB
LSB
DOUT
DSPR*
DSEL*
ADC
STATE
tACQ
tCONV
IDLE
*MAX1168 ONLY
Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
SCLK rates less than 125kHz can reduce accuracy due
to leakage of the sampling capacitor. DOUT changes
from high-Z to logic low after CS is brought low. Input
data latches on the rising edge of SCLK. The first SCLK
rising edge begins loading data into the command/configuration/control register from DIN. The devices select
the proper channel for conversion on the rising edge of
the 3rd SCLK cycle. Acquisition begins immediately
thereafter and ends on the falling edge of the 6th clock
cycle. The MAX1167/MAX1168 sample the input and
begin conversion on the falling edge of the 6th clock
cycle.
Setup
and
configuration
of
the
MAX1167/MAX1168 complete on the rising edge of the
8th clock cycle. The conversion result is available (MSB
first) at DOUT on the falling edge of the 8th SCLK cycle.
To read the entire conversion result, 16 SCLK cycles are
needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising
edge of CS, cause zeros to be clocked out of DOUT.
The MAX1167/ MAX1168 external clock 8-bit-wide datatransfer mode requires 24 SCLK cycles for completion
(Figure 10).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1167/MAX1168 in shutdown.
External Clock 16-Bit-Wide Data-Transfer Mode
(MAX1168 Only)
Force DSPR high and DSEL high for SPI/QSPI/
MICROWIRE interface mode. Logic high at DSEL allows
the MAX1168 to transfer data in 16-bit-wide words. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data. Ensure the duty cycle on SCLK is between 45%
and 55% when operating at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that the
minimum high and low times are at least 93ns. Externalclock-mode conversions with SCLK rates less than
125kHz can reduce accuracy due to leakage of the sampling capacitor. DOUT changes from high-Z to logic low
after CS is brought low. Input data latches on the rising
edge of SCLK. The first SCLK rising edge begins loading
data into the command/configuration/control register from
DIN. The devices select the proper channel for conversion and begin acquisition on the rising edge of the 3rd
SCLK cycle. Setup and configuration of the MAX1168
completes on the rising edge of the 8th clock cycle.
Acquisition ends on the falling edge of the 14th SCLK
cycle. The MAX1168 samples the input and begins conversion on the falling edge of the 14th clock cycle. The
conversion result is available (MSB first) at DOUT on the
falling edge of the 16th SCLK cycle. To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occurring after the conversion result has
been clocked out and prior to the rising edge of CS,
cause zeros to be clocked out of DOUT.
______________________________________________________________________________________________________
17
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
1
16
8
24
32
SCLK
MSB
LSB
0 X
DIN
X
X
X
X
X
X
X
MSB
LSB
DOUT
DSPR
DSEL
ADC
STATE
tACQ
,
X = DON T CARE
IDLE
tCONV
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS
1
9
8
16
24
SCLK
2
INTERNAL
CLK
MSB
DIN
6
25
LSB
1
LSB
MSB
DOUT
X
EOC
ADC
STATE
,
X = DON T CARE
DSPR = DVDD, DSEL = GND (MAX1168 ONLY)
tACQ
tCONV
IDLE
POWER-DOWN
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
The MAX1168 external clock 16-bit-wide data-transfer
mode requires 32 SCLK cycles for completion (Figure 11).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and
Scan Mode (MAX1167 and MAX1168)
Force DSPR high and DSEL low (MAX1168) for the SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data (Figure 12). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the ris18
ing edge of SCLK. The command/configuration/control
register begins reading DIN on the first SCLK rising edge
and ends on the rising edge of the 8th SCLK cycle. The
MAX1167/MAX1168 select the proper channel for conversion on the rising edge of the 3rd SCLK cycle. The
internal oscillator activates 125ns after the rising edge of
the 8th SCLK cycle. Turn off the external clock while the
internal clock is on. Turning off SCLK ensures the lowest
noise performance during acquisition. Acquisition begins
on the 2nd rising edge of the internal clock and ends on
the falling edge of the 6th internal clock cycle. Each bit
of the conversion result shifts into memory as it becomes
available. The conversion result is available (MSB first) at
DOUT on the falling edge of EOC. The internal oscillator
and analog circuitry are shut down on the high-to-low
EOC transition. Use the EOC high-to-low transition as the
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168
CS
1
8
9
16
17
24
32
SCLK
2
13
32
INTERNAL
CLK
DIN
DATA
XXXXXXXX
LSB
MSB
DOUT
X
EOC
ADC
STATE
CONFIGURATION
,
X = DON T CARE
DSPR = DSEL = DVDD
tACQ
tCONV
POWER-DOWN
Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS
1
8
9
40
SCLK
2
INTERNAL
CLK
MSB
DIN
24
6
26
30
48
LSB
1
MSB
LSB
DOUT
X
EOC
ADC
STATE
CONFIGURATION
,
X = DON T CARE
DSPR = DVDD, DSEL = GND (MAX1168 ONLY)
tACQ
tCONV
tACQ
tCONV
POWER-DOWN
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
signal to restart the external clock (SCLK). To read the
entire conversion result, 16 SCLK cycles are needed.
Extra clock pulses, occurring after the conversion result
has been clocked out and prior to the rising edge of
CS, cause the conversion result to be shifted out again.
The MAX1167/MAX1168 internal clock 8-bit-wide datatransfer mode requires 24 external clock cycles and 25
internal clock cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1167/MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1167/MAX1168 in the internal clock mode. Enable
scanning by setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4). In scan
mode, conversion results are stored in memory until the
completion of the last conversion in the sequence.
Upon completion of the last conversion in the
sequence, EOC transitions from high to low to indicate
the end of the conversion and shuts down the internal
oscillator. Use the EOC high-to-low transition as the signal to restart the external clock (SCLK). DOUT provides
the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of EOC (Figure 14).
______________________________________________________________________________________
19
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
1
8
9
48
17
16
SCLK
32
13
2
34
45
64
INTERNAL
CLK
DIN
DATA
XXXXXXXX
LSB
MSB
DOUT
X
EOC
ADC
STATE
tACQ
,
X = DON T CARE
tACQ
tCONV
tCONV
POWER-DOWN
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)
tCSW
...
CS
tDF
tFSS
...
DSPR
tFSH
tCSS
tCL
tCSH
tCH
...
SCLK
tCP
tDS
tDH
...
DIN
tDO
tDV
DOUT
tTR
...
Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)
Internal Clock 16-Bit-Wide Data-Transfer and Scan
Mode (MAX1168 Only)
Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the
rising edge of SCLK. The command/configuration/control register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1168 selects the proper channel for
20
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external clock
while the internal clock is on. Turning off SCLK ensures
lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the internal clock and ends on the falling edge of the 18th internal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuitry
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168
CS
DSPR
16
1
8
MSB
LSB
24
SCLK
DIN
0
MSB
LSB
DOUT
DSPX
ADC
STATE
tACQ
IDLE
tCONV
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS
DSPR
1
8
MSB
LSB
0 X
16
24
32
SCLK
DIN
X
X
X
X
X
X
X
LSB
MSB
DOUT
DSPX
ADC
STATE
,
X = DON T CARE
tACQ
tCONV
IDLE
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conversion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
the conversion result to be shifted out again. The
MAX1168 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1168 in internal clock mode. Enable scanning by
______________________________________________________________________________________
21
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
OUTPUT CODE
FULL-SCALE
TRANSITION
1111...111
1111...110
1111...101
FS = VREF
V
1 LSB = REF
65,536
0000...011
0000...010
0000...001
0000...000
0
1
2
3
INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 19. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4). In scan mode, conversion results are stored in memory until the completion of
the last conversion in the sequence. Upon completion of
the last conversion in the sequence, EOC transitions
from high to low to indicate the end of the conversion
and shuts down the internal oscillator. Use the EOC
high-to-low transition as the signal to restart the external
clock (SCLK). DOUT provides the conversion results in
the same order as the channel conversion process. The
MSB of the first conversion is available at DOUT on the
falling edge of EOC. Figure 15 shows the timing
diagram for 16-bit-wide data transfer in scan mode.
DSP 8-Bit-Wide Data-Transfer Mode (External Clock
Mode, MAX1168 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of CS enables
DSP interface mode. After the MAX1168 enters DSP
mode, CS can remain low for the duration of the conversion process and each subsequent conversion. Drive
DSEL low to select the 8-bit data-transfer mode. A sync
pulse from the DSP at DSPR wakes the analog circuitry
and allows SCLK to clock in data (Figure 17). The frame
sync pulse alerts the MAX1168 that incoming data is
about to be sent to DIN. Ensure the duty cycle on SCLK
is between 45% and 55% when operating at 4.8MHz
(the maximum clock frequency). For lower clock frequencies, ensure the minimum high and low times are at
least 93ns. External clock mode conversions with SCLK
22
rates less than 125kHz can reduce accuracy due to
leakage of the sampling capacitor. The input data
latches on the falling edge of SCLK. The command/
configuration/control register starts reading data in on
the falling edge of the first SCLK cycle immediately following the falling edge of the frame sync pulse and
ends on the falling edge of the 8th SCLK cycle. The
MAX1168 selects the proper channel for conversion on
the falling edge of the 3rd clock cycle and begins
acquisition. Acquisition continues until the rising edge
of the 7th clock cycle. The MAX1168 samples the input
on the rising edge of the 7th clock cycle. On the rising
edge of the 8th clock cycle, the MAX1168 outputs a
frame sync pulse at DSPX. The frame sync pulse alerts
the DSP that the conversion results are about to be output at DOUT (MSB first) starting on the rising edge of
the 9th clock pulse. To read the entire conversion
result, 16 SCLK cycles are needed. Extra clock pulses,
occurring after the conversion result has been clocked
out and prior to the next rising edge of DSPR, cause
zeros to be clocked out of DOUT. The MAX1168 external clock, DSP 8-bit-wide data-transfer mode requires
24 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a conversion immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1168 in shutdown.
DSP 16-Bit-Wide Data-Transfer Mode (External
Clock Mode, MAX1168 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of CS enables
DSP interface mode. After the MAX1168 enters DSP
mode, CS can remain low for the duration of the conversion process and each subsequent conversion. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. Drive DSEL high
to select the 16-bit-wide data-transfer mode. A sync
pulse from the DSP at DSPR wakes the analog circuitry
and allows SCLK to clock in data (Figure 18). The
frame sync pulse also alerts the MAX1168 that incoming data is about to be sent to DIN. Ensure the duty
cycle on SCLK is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For
lower clock frequencies, ensure the minimum high and
low times are at least 93ns. External-clock-mode conversions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
I/O
CS
SCLK
SK
SCLK
MISO
DOUT
SI
DOUT
I/O
VDD
SPI
MICROWIRE
MAX1167
MAX1168
SS
MAX1167
MAX1168
Figure 20a. SPI Connections
Figure 20b. MICROWIRE Connections
1ST BYTE READ
1
SCLK
MAX1167/MAX1168
CS
SCK
2ND BYTE READ
4
6
12
8
16
CS
DOUT*
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 20c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle immediately following the falling edge of the frame sync pulse
and ends on the falling edge of the 16th SCLK cycle. The
MAX1168 selects the proper channel for conversion on
the falling edge of the 3rd clock cycle and begins acquisition. Acquisition continues until the rising edge of the
15th clock cycle. The MAX1168 samples the input on the
rising edge of the 15th clock cycle. On the rising edge of
the 16th clock cycle, the MAX1168 outputs a frame sync
pulse at DSPX. The frame sync pulse alerts the DSP that
the conversion results are about to be output at DOUT
(MSB first) starting on the rising edge of the 17th clock
pulse. To read the entire conversion result, 16 SCLK
cycles are needed. Extra clock pulses, occurring after the
conversion result has been clocked out and prior to the
next rising edge of DSPR, cause zeros to be clocked out
of DOUT. The MAX1168 external clock, DSP 16-bit-wide
data-transfer mode requires 32 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a conversion immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1168 in shutdown.
Output Coding and Transfer Function
The data output from the MAX1167/MAX1168 is straight
binary. Figure 19 shows the nominal transfer function.
Code transitions occur halfway between successive
integer LSB values (V REF = +4.096V, and 1 LSB =
+62.5µV or 4.096V / 65,536V).
______________________________________________________________________________________
23
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Table 7. Detailed SSPCON Register Contents
CONTROL BIT
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detection Bit
1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial
port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPEN
BIT5
CKP
BIT4
0
SSPM3
BIT3
0
SSPM2
BIT2
0
SSPM1
BIT1
0
SSPM0
BIT0
1
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and
selects fCLK = fOSC / 16.
X = Don’t care.
Applications Information
Internal Reference
The internal bandgap reference provides a buffered
+4.096V. Bypass REFCAP with a 0.1µF capacitor to
AGND and REF with a 1µF capacitor to AGND. For best
results, use low-ESR, X5R/X7R ceramic capacitors.
Allow 5ms for the reference and buffer to wake up from
full power-down (see Table 5).
External Reference
The MAX1167/MAX1168 accept an external reference
with a voltage range between +3.8V and AVDD. Connect
the external reference directly to REF. Bypass REF to
AGND with a 10µF capacitor. When not using a low-ESR
bypass capacitor, use a 0.1µF ceramic capacitor in parallel with the 10µF capacitor. Noise on the reference
degrades conversion accuracy.
The input impedance at REF is 37kΩ for DC currents.
During a conversion, the external reference at REF
must deliver 118µA of DC load current and have an output impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
equivalent input noise (40µV RMS ) of the MAX1167/
MAX1168 when choosing a reference.
When using the internal clock mode, the internal oscillator controls the acquisition and conversion processes,
while the external oscillator shifts data in and out of the
MAX1167/MAX1168. Turn off the external clock (SCLK)
when the internal clock is on to realize lowest noise performance. The internal clock remains off in external
clock mode.
Input Buffer
Most applications require an input-buffer amplifier to
achieve 16-bit accuracy. The input amplifier must have
a slew rate of at least 2V/µs and a unity-gain bandwidth
of at least 10MHz to complete the required output-voltage change before the end of the acquisition time.
At the beginning of the acquisition, the internal sampling capacitor array connects to AIN_ (the amplifier
input), causing some disturbance on the output of the
buffer. Ensure the sampled voltage has settled before
the end of the acquisition time.
CS
QSPI
24
SCLK
MISO
DOUT
VDD
MAX1167
MAX1168
Internal/External Oscillator
Select either an external (0.1MHz to 4.8MHz) or the
internal 4MHz (typ) clock to perform conversions
(Table 6). The external clock shifts data in and out of
the MAX1167/MAX1168 in either clock mode.
CS
SCK
SS
Figure 21a. QSPI Connections
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CONTROL BIT
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP
BIT7
0
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
CKE
BIT6
1
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
D/A
BIT5
X
Data Address Bit
P
BIT4
X
Stop Bit
Start Bit
S
BIT3
X
R/W
BIT2
X
Read/Write Bit Information
UA
BIT1
X
Update Address
BF
BIT0
X
Buffer-Full Status Bit
X = Don’t care.
SCLK
CS
1
4
6
DOUT*
8
12
D15
SAMPLING INSTANT
D14
D13
D12
16
D11
D10
D9
D8
24
20
D7
D6
D5
D4
D3
D2
MSB
D1
D0
HIGH-Z
LSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
Digital Noise
Digital noise can couple to AIN_ and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result.
Noise signals, synchronous with the sampling interval,
result in an effective input offset. Asynchronous signals
produce random noise on the input, whose high-frequency components can be aliased into the frequency band
of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at
the inputs. This requires bypassing AIN_ to AGND, or
buffering the input with an amplifier that has a small-signal bandwidth of several megahertz (doing both is preferable). AIN has a typical bandwidth of 4MHz.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the total harmonic distortion of the MAX1167/MAX1168 at the frequencies of interest (THD = -100dB at 1kHz). If the
chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use
the inverting configuration (positive input grounded) to
eliminate errors from this source. Low-temperaturecoefficient, gain-setting resistors reduce linearity errors
caused by resistance changes due to self-heating. To
reduce linearity errors due to finite amplifier gain, use
amplifier circuits with sufficient loop gain at the frequencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1167/MAX1168s’ offset (±10mV
max for +5V supply), or whose offset can be trimmed
while maintaining stability over the required temperature
range.
VDD
VDD
SCLK
SCK
DOUT
SDI
CS
I/O
PIC16/17
MAX1167
MAX1168
GND
Figure 22a. SPI-Interface Connection for a PIC16/PIC17
______________________________________________________________________________________
25
MAX1167/MAX1168
Table 8. Detailed SSPSTAT Register Contents
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
1ST BYTE READ
1
SCLK
2ND BYTE READ
4
6
8
12
16
CS
DOUT*
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
24
20
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX1167/MAX1168 support a maximum
f SCLK of 4.8MHz. Figure 21a shows the MAX1167/
MAX1168 connected to a QSPI master, and Figure 21b
shows the associated interface timing.
EXTERNAL
CLOCK
DSP
SCLK
SCLK
TFS
DSPR
RFS
DSPX
DT
DIN
DR
DOUT
FL1
CS
MAX1168
Figure 23. DSP Interface Connection
Serial Interfaces
SPI and MICROWIRE Interfaces
When using the SPI (Figure 20a) or MICROWIRE (Figure
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS
low to power on the MAX1167/MAX1168 before starting a
conversion (Figure 20c). Three consecutive 8-bit-wide
readings are necessary to obtain the entire 16-bit result
from the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all
leading zeros. The 2nd 8-bit-wide data stream contains
the MSB through D6. The 3rd 8-bit-wide data stream contains D5 through D0 followed by S1 and S0.
26
PIC16 with SSP Module and PIC17
Interface
The MAX1167/MAX1168 are compatible with a
PIC16/PIC17 controller (µC), using the synchronous serial-port (SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
be synchronously transmitted and received simultaneously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 16-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the µC on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
AIN_
SCLK
DOUT
REF
12
EFFECTIVE BITS
CS
AIN_
14
1μF
AVDD
+5V
10
0.1μF
8
MAX1167
MAX1168
10Ω
6
DVDD
4
0.1μF
2
CS
SCLK
DOUT
AGND
AGND
DGND
fSAMPLE = 200ksps
0
0.1
1
10
100
FREQUENCY (kHz)
GND
Figure 25. Powering AVDD and DVDD from a Single Supply
Figure 24. Effective Bits vs. Frequency
DSP Interface
Aperture Definitions
The DSP mode of the MAX1168 only operates in external clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1168. Use the same oscillator as
the DSP to provide the clock signal for the MAX1168.
The DSP provides the falling edge at CS to wake the
MAX1168. The MAX1168 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1168 in DSP mode. After the MAX1168
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1168 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1168 does not operate in scan mode when using DSP mode.
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1167/MAX1168
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of ±1 LSB. A
DNL error specification of ±1 LSB guarantees no missing codes and a monotonic transfer function.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N bits):
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 ✕ log [SignalRMS / (Noise +
Distortion)RMS]
______________________________________________________________________________________
27
MAX1167/MAX1168
EFFECTIVE NUMBER OF BITS (ENOB)
16
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Figure 24 shows the ENOB as a function of the
MAX1167/MAX1168s’ input frequency.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
⎡
THD = 20 × log ⎢
⎢
⎢⎣
(V22 + V32 + V42 + V52 ) ⎤⎥
V1
⎥
⎥⎦
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest frequency component.
28
Supplies, Layout, Grounding, and
Bypassing
Use printed circuit (PC) boards with separate analog
and digital ground planes. Do not use wire-wrap
boards. Connect the two ground planes together at the
MAX1167/MAX1168 AGND terminal. Isolate the digital
supply from the analog with a low-value resistor (10Ω)
or ferrite bead when the analog and digital supplies
come from the same source (Figure 25).
Constraints on sequencing the power supplies and
inputs are as follows:
• Apply AGND before DGND.
• Apply AIN_ and REF after AV DD and AGND are
present.
• DVDD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV and a 4 LSB error with a +4.096V
full-scale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and digital lines (especially the SCLK and DOUT) parallel to one
another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to highfrequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
______________________________________________________________________________________
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TOP VIEW
DOUT 1
16 DVDD
DSPR 1
24 N.C.
SCLK 2
15 DGND
DSEL 2
23 DSPX
14 CS
DOUT 3
22 DVDD
13 AVDD
SCLK 4
21 DGND
AIN0 5
12 AGND
DIN 5
AIN1 6
11 AGND
EOC 6
19 AVDD
AIN2 7
10 REFCAP
AIN0 7
18 AGND
AIN3 8
9
AIN1 8
17 AGND
AIN2 9
16 REFCAP
AIN3 10
15 REF
AIN4 11
14 AIN7
AIN5 12
13 AIN6
DIN 3
EOC 4
MAX1167
REF
QSOP
MAX1168
20 CS
QSOP
Package Information
Chip Information
TRANSISTOR COUNT: 20,760
PROCESS: BiCMOS
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
16 QSOP
E16-1
24 QSOP
E24-1
DOCUMENT NO.
21-0055
______________________________________________________________________________________
29
MAX1167/MAX1168
Pin Configurations
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Revision History
REVISION
NUMBER
REVISION
DATE
0
8/03
1
10/09
DESCRIPTION
PAGES
CHANGED
Initial release.
—
Changed 2.9mA at 200ksps to 3.6mA at 200ksps, 1.45mA at 100ksps to 1.85mA at
100ksps, and 145μA at 10ksps to 185μA to 10ksps in the General Description and
Features sections.
1
Removed the ±1.2 INL LSB and ±2 INL LSB packages from the Ordering Information
table.
1, 29
Updated the Electrical Characteristics table to include the reference buffer and GBD
at -40°C.
2–6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
