19-2755; Rev 1; 8/03
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
The MAX1178/MAX1188 are ideal for high-performance, battery-powered, data-acquisition applications.
Excellent AC performance (THD = -100dB) and DC
accuracy (±2 LSB INL) make the MAX1178/MAX1188
ideal for industrial process control, instrumentation, and
medical applications.
The MAX1178/MAX1188 are available in a 20-pin
TSSOP package and are fully specified over the -40°C
to +85°C extended temperature range and the 0°C to
+70°C commercial temperature range.
Features
♦ Byte-Wide Parallel Interface
♦ Analog Input Voltage Range: ±10V, ±5V
♦ Single +4.75V to +5.25V Analog Supply Voltage
♦ Interface with +2.7V to +5.25V Digital Logic
♦ ±2 LSB INL
♦ ±1 LSB DNL
♦ Low Supply Current (max)
2.9mA (External Reference)
3.8mA (Internal Reference)
5µA AutoShutdown Mode
♦ Small Footprint
♦ 20-Pin TSSOP Package
Ordering Information
INPUT
PINVOLTAGE
PACKAGE
RANGE (V)
PART
TEMP RANGE
MAX1178ACUP
0°C to +70°C
20 TSSOP
±5
MAX1178BCUP
0°C to +70°C
20 TSSOP
±5
MAX1178CCUP
0°C to +70°C
20 TSSOP
±5
MAX1178AEUP
-40°C to +85°C
20 TSSOP
±5
MAX1178BEUP
-40°C to +85°C
20 TSSOP
±5
MAX1178CEUP
-40°C to +85°C
20 TSSOP
±5
Ordering Information continued at end of data sheet.
Typical Operating Circuit
Applications
Temperature Sensing and Monitoring
+5V ANALOG +5V DIGITAL
Industrial Process Control
I/O Modules
0.1µF
0.1µF
Data-Acquisition Systems
AVDD
Precision Instrumentation
ANALOG INPUT
µP DATA
D0–D7 BUS
OR
D8–D15
DVDD
AIN
MAX1178
MAX1188
EOC
R/C
REF
CS
REFADJ
HBEN
Pin Configuration and Functional Diagram appear at end of
data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
HIGH
BYTE
AGND DGND
0.1µF
10µF
LOW
BYTE
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1178/MAX1188
General Description
The MAX1178/MAX1188 16-bit, low-power, successiveapproximation analog-to-digital converters (ADCs) feature automatic power-down, a factory-trimmed internal
clock, and a byte-wide parallel interface. The devices
operate from a single +4.75V to +5.25V analog supply
and feature a separate digital supply input for direct
interface with a +2.7V to +5.25V digital logic.
The MAX1188 accepts a bipolar analog input voltage
range of ±10V, while the MAX1178 accepts a bipolar
analog input voltage range of ±5V. All devices consume
no more than 26.5mW at a sampling rate of 135ksps
when using an external reference, and 31mW when using
the internal +4.096V reference. AutoShutdown™ reduces
supply current to 0.4mA at 10ksps.
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND .....................................................-16.5V to +16.5V
REF, REFADJ to AGND............................-0.3V to (AVDD + 0.3V)
CS, R/C, HBEN to DGND .........................................-0.3V to +6V
D_, EOC to DGND ...................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current into Any Pin ........................50mA
Continuous Power Dissipation (TA = +70°C)
TSSOP (derate 10.9mW/°C above +70°C) ..................879mW
Operating Temperature Ranges
MAX11_ _ _CUP..................................................0°C to +70°C
MAX11_ _ _EUP ...............................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
Differential Nonlinearity
RES
DNL
16
No missing codes
over temperature
-1
+1
MAX11_ _B
-1.0
+1.5
MAX11_ _C
Integral Nonlinearity
INL
Transition Noise
Bits
MAX11_ _A
-1
+2
MAX11_ _A
-2
+2
MAX11_ _B
-2
+2
MAX11_ _C
-4
+4
RMS noise, external reference
0.6
Internal reference
0.75
Offset Error
-10
Gain Error
LSB
LSB
LSBRMS
0
+10
mV
0
±0.2
%FSR
Offset Drift
16
µV/°C
Gain Drift
±1
ppm/°C
90
dB
AC ACCURACY (fIN = 1kHz, VAIN = full range, 135ksps)
Signal-to-Noise Plus Distortion
SINAD
86
Signal-to-Noise Ratio
SNR
87
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
91
-100
92
dB
-92
103
dB
dB
ANALOG INPUT
Input Range
VAIN
MAX1178
-5
+5
MAX1188
-10
+10
MAX1178
Input Resistance
RAIN
MAX1188
2
Normal operation
5.3
Shutdown mode
3.0
Normal operation
7.8
Shutdown mode
6.0
6.9
9.2
10
13.0
_______________________________________________________________________________________
V
kΩ
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Input Current
SYMBOL
IAIN
Input Current Step at Power-Up
Input Capacitance
IPU
CONDITIONS
MIN
TYP
MAX
MAX1178,
-5V ≤ VAIN ≤ +5V
Normal operation
-1.8
+0.4
Shutdown mode
-1.8
+1.8
MAX1188,
-10V ≤ VAIN ≤ +10V
Normal operation
-1.8
+1.2
Shutdown mode
-1.8
+1.8
MAX1178, VAIN = +5V, shutdown mode to
operating mode
1
1.4
MAX1188, VAIN = +10V, shutdown mode to
operating mode
0.5
0.7
UNITS
mA
mA
CIN
10
pF
INTERNAL REFERENCE
REF Output Voltage
VREF
4.056
REF Output Tempco
REF Short-Circuit Current
IREF-SC
4.096
4.136
V
±35
ppm/°C
±10
mA
EXTERNAL REFERENCE
REF and REFADJ Input-Voltage
Range
REFADJ Buffer-Disable Threshold
REF Input Current
IREF
REFADJ Input Current
IREFADJ
3.8
4.2
V
AVDD 0.4
AVDD 0.1
V
Normal mode, fSAMPLE = 135ksps
Shutdown mode (Note 1)
REFADJ = AVDD
60
100
±0.1
±10
16
µA
µA
DIGITAL INPUTS/OUTPUTS
Output High Voltage
VOH
ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Output Low Voltage
VOL
ISINK = 1.6mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
Input Hysteresis
Input Capacitance
DVDD 0.4
V
0.4
0.7 ×
DVDD
Digital input = DVDD or 0V
V
V
-1
0.3 ×
DVDD
V
+1
µA
VHYST
0.2
V
CIN
15
pF
Tri-State Output Leakage
IOZ
Tri-State Output Capacitance
COZ
±10
15
µA
pF
_______________________________________________________________________________________
3
MAX1178/MAX1188
ELECTRICAL CHARACTERISTICS (continued)
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.70
5.25
V
Analog Supply Current
IAVDD
Shutdown Supply Current
ISHDN
Digital Supply Current
IDVDD
Power-Supply Rejection
External reference, 135ksps
4
5.3
Internal reference, 135ksps
5.2
6.2
Shutdown mode (Note 1), digital input =
DVDD or 0V
0.5
5
µA
Standby mode
3.7
0.75
mA
AVDD = DVDD = 4.75V to 5.25V
mA
mA
3.5
LSB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD,
CLOAD = 20pF, TA = TMIN to TMAX.)
PARAMETER
Maximum Sampling Rate
SYMBOL
Acquisition Time
tACQ
Conversion Time
tCONV
CS Pulse-Width High
tCSH
CS Pulse-Width Low (Note 2)
tCSL
R/C to CS Fall Setup Time
tDS
R/C to CS Fall Hold Time
tDH
CS to Output Data Valid
tDO
EOC Fall to CS Fall
tDV
CS Rise to EOC Rise
tEOC
Bus Relinquish Time
tBR
HBEN Transition to Output Data
Valid
CONDITIONS
MIN
TYP
fSAMPLE-MAX
tDO1
UNITS
135
ksps
2
µs
4.7
(Note 2)
40
DVDD = 4.75V to 5.25V
40
DVDD = 2.7V to 5.25V
60
DVDD = 4.75V to 5.25V
40
DVDD = 2.7V to 5.25V
60
ns
ns
ns
DVDD = 4.75V to 5.25V
40
DVDD = 2.7V to 5.25V
80
0
ns
ns
DVDD = 4.75V to 5.25V
40
DVDD = 2.7V to 5.25V
80
DVDD = 4.75V to 5.25V
40
DVDD = 2.7V to 5.25V
80
DVDD = 4.75V to 5.25V
40
DVDD = 2.7V to 5.25V
80
_______________________________________________________________________________________
µs
ns
0
Note 1: Maximum specification is limited by automated test equipment.
Note 2: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
4
MAX
ns
ns
ns
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
1.5
1.0
1.0
0
0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
-2.0
-2.5
SUPPLY CURRENT (AVDD + DVDD)
vs. SAMPLE RATE
SHUTDOWN CURRENT (AVDD + DVDD)
vs. TEMPERATURE
SHUTDOWN MODE
0.01
0.001
VAIN = 0V
0.0001
0.1
1
10
100
4.0
3.0
2.5
2.0
1.5
-0.10
20
40
TEMPERATURE (°C)
60
80
MAX1188
MAX1178
-4
-8
-40
-20
0
20
40
60
-40
80
-20
0
20
40
60
80
TEMPERATURE (°C)
FFT AT 1kHz
4.136
4.126
4.116
4.106
4.096
4.086
4.076
4.056
0
0
-2
-10
-0.20
-20
2
0
4.066
80
60
4
0.5
-0.15
40
6
0
fSAMPLE = 131ksps
-20
-40
MAGNITUDE (dB)
-0.05
20
8
MAX1178/88 toc08
MAX1178/88 toc07
0
0
-6
INTERNAL REFERENCE
vs. TEMPERATURE
0.05
-20
10
1.0
GAIN ERROR vs. TEMPERATURE
0.10
fSAMPLE = 135ksps
SHUTDOWN MODE
BETWEEN CONVERSIONS
OFFSET ERROR vs. TEMPERATURE
3.5
TEMPERATURE (°C)
0.15
-40
NO CONVERSIONS
4.5
1000
0.20
4.75V
TEMPERATURE (°C)
SAMPLE RATE (ksps)
INTERNAL REFERENCE (V)
0.01
4.55
-40
OFFSET ERROR (mV)
0.1
5.0
SHUTDOWN SUPPLY CURRENT (µA)
MAX1178/88 toc04
STANDBY MODE
4.60
4.40
0 10,000 20,000 30,000 40,000 50,000 60,000
CODE
1
5.0V
4.65
4.45
CODE
10
4.70
4.50
-2.5
0 10,000 20,000 30,000 40,000 50,000 60,000
SUPPLY CURRENT (mA)
0.5
MAX1178/88 toc05
0.5
5.25V
4.75
MAX1178/88 toc06
1.5
4.80
MAX1178/88 toc09
2.0
SUPPLY CURRENT (mA)
2.0
-0.5
GAIN ERROR (%FSR)
MAX1178/88 toc02
2.5
DNL (LSB)
INL (LSB)
2.5
SUPPLY CURRENT (AVDD + DVDD)
vs. TEMPERATURE
DNL vs. CODE
MAX1178/88 toc01
MAX1178/88 toc03
INL vs. CODE
-60
-80
-100
-120
-140
-160
-180
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
0
10
20
30
40
50
60
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX1178/MAX1188
Typical Operating Characteristics
(Typical Operating Circuit, AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD,
CLOAD = 20pF. Typical values are at TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD,
CLOAD = 20pF. Typical values are at TA = +25°C, unless otherwise noted.)
SFDR vs. FREQUENCY
90
80
THD vs. FREQUENCY
0
MAX1178/88 toc11
MAX1178/88 toc10
120
100
MAX1178/88 toc12
SINAD vs. FREQUENCY
100
-10
-20
-30
70
60
50
40
THD (dB)
80
SFDR (dB)
SINAD (dB)
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
60
-50
-60
-70
40
30
-40
-80
20
-90
20
10
fSAMPLE = 131ksps
fSAMPLE = 131ksps
0
0
1
10
100
fSAMPLE = 131ksps
-100
-110
1
100
10
FREQUENCY (kHz)
FREQUENCY (kHz)
1
10
100
FREQUENCY (kHz)
Pin Description
PIN
NAME
1
D4/D12
Tri-State Digital-Data Output
2
D5/D13
Tri-State Digital-Data Output
3
D6/D14
Tri-State Digital-Data Output
4
D7/D15
Tri-State Digital-Data Output. D15 is the MSB.
R/C
Read/Convert Input. Power up and put the MAX1178/MAX1188 in acquisition mode by holding R/C
low during the first falling edge of CS. During the second falling edge of CS, the level on R/C
determines whether the reference and reference buffer power down or remain on after conversion.
Set R/C high during the second falling edge of CS to power down the reference and buffer, or set R/C
low to leave the reference and buffer powered up. Set R/C high during the third falling edge of CS to
put valid data on the bus.
6
EOC
End of Conversion. EOC drives low when conversion is complete.
7
AVDD
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
8
AGND
9
AIN
10
AGND
11
REFADJ
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal reference
mode. Connect REFADJ to AVDD to select external reference mode.
12
REF
Reference Input/Output. Bypass REF with a 10µF capacitor to AGND for internal reference mode.
External reference input when in external reference mode.
5
6
FUNCTION
Analog Ground. Primary analog ground (star ground).
Analog Input
Analog Ground. Connect pin 10 to pin 8.
_______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
PIN
NAME
FUNCTION
13
HBEN
14
CS
15
DGND
Digital Ground
16
DVDD
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
17
D0/D8
Tri-State Digital-Data Output. D0 is the LSB.
18
D1/D9
Tri-State Digital-Data Output
19
D2/D10
Tri-State Digital-Data Output
20
D3/D11
Tri-State Digital-Data Output
High-Byte Enable Input. Used to multiplex the 16-bit conversion result.
1: MSB available on the data bus.
0: LSB available on the data bus.
Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C
is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result
onto the bus when R/C is high.
Analog Input
DVDD
1mA
DO–D15
DO–D15
CLOAD = 20pF
CLOAD = 20pF
1mA
DGND
DGND
a) HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
b) HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Input Scaler
The MAX1178/MAX1188 have an input scaler, which
allows conversion of true bipolar input voltages and
input voltages greater than the power supply, while
operating from a single +5V analog supply. The input
scaler attenuates and shifts the analog input to match
the input range of the internal digital-to-analog converter
(DAC). The MAX1178 input voltage range is ±5V, while
the MAX1188 input voltage range is ±10V. Figure 4
shows the equivalent input circuit of the MAX1178/
MAX1188. This circuit limits the current going into or
out of AIN to less than 1.8mA.
Figure 1. Load Circuits
Detailed Description
Converter Operation
The MAX1178/MAX1188 use a successive-approximation (SAR) conversion technique with an inherent trackand-hold (T/H) stage to convert an analog input into a
16-bit digital output. Parallel outputs provide a highspeed interface to microprocessors (µPs). The Functional Diagram shows a simplified internal architecture of
the MAX1178/MAX1188. Figure 3 shows a typical operating circuit for the MAX1178/MAX1188.
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (Figure 4). In hold mode, the T/H switches open and the capacitive DAC samples the analog
input. During the acquisition, the analog input (AIN)
charges capacitor CHOLD. The acquisition ends on the
second falling edge of CS. At this instant, the T/H
switches open. The retained charge on CHOLD represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion
time to restore node T/H OUT to zero within the limits of
16-bit resolution. Force CS low to put valid data on the
bus after conversion is complete.
_______________________________________________________________________________________
7
MAX1178/MAX1188
Pin Description (continued)
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
tCSH
tCSL
CS
tACQ
REF POWERDOWN CONTROL
R/C
tDH
tDS
tEOC
tDV
EOC
tCONV
tDO
HBEN
tBR
tDO1
tDO
HIGH-Z
HIGH-Z
D7/D15–D0/D8
HIGH/LOW
BYTE VALID
HIGH/LOW
BYTE VALID
Figure 2. MAX1178/MAX1188 Timing Diagram
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1178/MAX1188 automatically enter either standby
mode (reference and buffer on) or shutdown (reference
and buffer off) after each conversion, depending on the
status of R/C during the second falling edge of CS.
+5V ANALOG
0.1µF
0.1µF
ANALOG INPUT
AIN
R/C
CS
Starting a Conversion
8
µP DATA
D0–D7 BUS
OR
D8–D15
MAX1178
MAX1188
Applications Information
CS and R/C control acquisition and conversion in the
MAX1178/MAX1188 (Figure 2). The first falling edge of
CS powers up the device and puts it in acquire mode if
R/C is low. The convert start is ignored if R/C is high.
The MAX1178/MAX1188 need at least 12ms for the
internal reference to wake up and settle before starting
the conversion (C REFADJ = 0.1µF, C REF = 10µF), if
powering up from shutdown.
DVDD
AVDD
Internal Clock
The MAX1178/MAX1188 generate an internal conversion clock to free the µP from the burden of running the
SAR conversion clock. Total conversion time (tCONV)
after entering hold mode (second falling edge of CS) to
end-of-conversion (EOC) falling is 4.7µs (max).
+5V DIGITAL
EOC
REF
REFADJ
HBEN
HIGH
BYTE
0.1µF
10µF
AGND DGND
LOW
BYTE
Figure 3. Typical Operating Circuit for the MAX1178/MAX1188
_______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Standby Mode
While in standby mode, the supply current is less than
3.7mA (typ). The next falling edge of CS with R/C low
causes the MAX1178/MAX1188 to exit standby mode
and begin acquisition. The reference and reference
buffer remain active to allow quick turn-on time.
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The next falling edge of CS with R/C low
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 16-bit accuracy, allow
12ms for the internal reference to wake up (CREFADJ =
0.1µF, CREF = 10µF).
MAX1178/MAX1188
Selecting Standby or Shutdown Mode
The MAX1178/MAX1188 have a selectable standby or
low-power shutdown mode. In standby mode, the ADC’s
internal reference and reference buffer do not power
down between conversions, eliminating the need to wait
for the reference to power up before performing the next
conversion. Shutdown mode powers down the reference
and reference buffer after completing a conversion. The
reference and reference buffer require a minimum of
12ms to power up and settle from shutdown (CREFADJ =
0.1µF, CREF = 10µF).
The state of R/C at the second falling edge of CS
selects which power-down mode the MAX1178/
MAX1188 enter upon conversion completion. Holding
R/C low causes the MAX1178/MAX1188 to enter standby mode. The reference and buffer are left on after the
conversion completes. R/C high causes the
MAX1178/MAX1188 to enter shutdown mode and
power-down the reference and buffer after conversion
(Figures 5 and 6). Set the voltage at R/C high during
the second falling edge of CS to realize the lowest current operation.
REF
MAX1178/MAX1188
R2
R1
3.4kΩ
161Ω
TRACK
S1
AIN
CHOLD
30pF
T/H OUT
R3
HOLD
TRACK
S3
POWERDOWN
HOLD
S2
R2 = 7.85kΩ (MAX1188) OR 3.92kΩ (MAX1178)
S1, S2 = T/H SWITCH
R3 = 5.45kΩ (MAX1188) OR 17.79kΩ (MAX1178)
S3 = POWER-DOWN
Figure 4. Equivalent Input Circuit
ACQUISITION
CONVERSION
DATA
OUT
CS
R/C
EOC
REF AND
BUFFER
POWER
Figure 5. Selecting Standby Mode
ACQUISITION
CONVERSION
DATA
OUT
Internal and External Reference
Internal Reference
The internal reference of the MAX1178/MAX1188 is
internally buffered to provide +4.096V output at REF.
Bypass REF to AGND and REFADJ to AGND with 10µF
and 0.1µF, respectively. Sink or source current at
REFADJ to make fine adjustments to the internal reference. The input impedance of REFADJ is nominally
5kΩ. Use the circuit in Figure 7 to adjust the internal
reference to ±1.5%.
CS
R/C
EOC
REF AND
BUFFER
POWER
Figure 6. Selecting Shutdown Mode
_______________________________________________________________________________________
9
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
OUTPUT CODE
MAX1178
MAX1188
+5V
11 1111 1111 1111
MAX1178
INPUT RANGE = -5V TO +5V
FULL-SCALE
TRANSITION
11 1111 1111 1110
68kΩ
11 1111 1111 1101
100kΩ
REFADJ
150kΩ
0.1µF
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
FULL-SCALE RANGE (FSR) = +1V
00 0000 0000 0011
00 0000 0000 0010
Figure 7. MAX1178/MAX1188 Reference-Adjust Circuit
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1178/
MAX1188s’ internal buffer amplifier. Using the buffered
REFADJ input makes buffering the external reference
unnecessary. The input impedance of REFADJ is typically 5kΩ. The internal buffer output must be bypassed
at REF with a 10µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external 3.8V to 4.2V reference. During conversion, the external reference must
be able to drive 100µA of DC load current and have an
output impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10µF capacitor.
Consider the MAX1178/MAX1188s’ equivalent input
noise (0.6 LSB) when choosing a reference.
Reading the Conversion Result
EOC is provided to flag the µP when a conversion is
complete. The falling edge of EOC signals that the data
is valid and ready to be output to the bus. D0–D15 are
the parallel outputs of the MAX1178/MAX1188. These
tri-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high impedance
during acquisition and conversion. Data is loaded onto
the output bus with the third falling edge of CS with R/C
high (after tDO). Bringing CS high forces the output bus
back to high impedance. The MAX1178/MAX1188 then
wait for the next falling edge of CS to start the next conversion cycle (Figure 2).
HBEN toggles the output between the high/low byte. The
low byte is loaded onto the output bus when HBEN is
low, and the high byte is on the bus when HBEN is high.
10
1 LSB =
00 0000 0000 0001
FSR x VREF
65,536 x 4.096
00 0000 0000 0000
-32,768 -32,766
0
+32,766 +32,768
+1
-32,767 -32,765 -1
+32,767
INPUT VOLTAGE (LSB)
Figure 8. MAX1178 Transfer Function
OUTPUT CODE
1111 1111 1111 1111
MAX1188
INPUT RANGE = -10V TO +10V
FULL-SCALE
TRANSITION
1111 1111 1111 1110
1111 1111 1111 1101
1000 0000 0000 0001
1000 0000 0000 0000
0001 1111 1111 1111
0000 0000 0000 0011
0000 0000 0000 0010
FULL-SCALE RANGE (FSR) = +20V
1 LSB =
0000 0000 0000 0001
FSR x VREF
65,536 x 4.096
0000 0000 0000 0000
0
+32,766 +32,768
-32,68 -32,766
+1
-32,767 -32,765 -1
+32,767
INPUT VOLTAGE (LSB)
Figure 9. MAX1188 Transfer Function
Transfer Function
Figures 8 and 9 show the MAX1178/MAX1188 output
transfer functions. The MAX1178 and MAX1188 outputs
are coded in offset binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy and prevent loading the
source. When the input signal is multiplexed, switch the
channels immediately after acquisition, rather than near
the end of, or after, a conversion. This allows more time
for the input buffer amplifier to respond to a large step
______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
REF
ANALOG
INPUT
MAX427
1.5
ANALOG INPUT CURRENT (mA)
AIN
MAX1178/MAX1188
MAX1178
MAX1188
MAX1178
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
1.0
0.5
SHUTDOWN
MODE
0
-0.5
STANDBY
MODE
-1.0
-1.5
-5.0
-2.5
0
2.5
5.0
ANALOG INPUT VOLTAGE (V)
Figure 10. MAX1178/MAX1188 Fast-Settling Input Buffer
Figure 11. MAX1178 Analog Input Current
change in input signal. The input amplifier must have a
high enough slew rate to complete the required output
voltage change before the beginning of the acquisition
time. Figure 10 shows an example of this circuit using
the MAX427.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not
run analog and digital lines parallel to each other, and do
not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground planes with
only one point connecting the two ground systems (analog and digital) as close to the device as possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
1.5
ANALOG INPUT CURRENT (mA)
Figures 11 and 12 show how the MAX1178/MAX1188
analog input current varies depending on whether the
chip is operating or powered down. The part is fully
powered down between conversions if the voltage at
R/C is set high during the second falling edge of CS.
The input current abruptly steps to the powered-up
value at the start of acquisition. This step in the input
current can disrupt the ADC input, depending on the
driving circuit’s output impedance at high frequencies. If
the driving circuit cannot fully settle by the end of acquisition, the accuracy of the system can be compromised.
To avoid this situation, increase the acquisition time, use
a driving circuit that can settle within tACQ, or leave the
MAX1178/MAX1188 powered up by setting the voltage
at R/C low during the second falling edge of CS.
MAX1188
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
1.0
0.5
SHUTDOWN
MODE
0
STANDBY
MODE
-0.5
-1.0
-1.5
-10
-5
0
5
10
ANALOG INPUT VOLTAGE (V)
Figure 12. MAX1188 Analog Input Current
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, isolate the digital and analog
supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AV DD supply. Bypass AV DD to AGND with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capacitor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
______________________________________________________________________________________
11
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static linearity parameters for the MAX1178/MAX1188 are
measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB guarantees no missing
codes and a monotonic transfer function.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N bits):
SNR = (6.02 × N + 1.76)dB
where N = 16 bits.
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. The SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five
harmonics, and the DC offset.
12
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SignalRMS
SINAD(dB) = 20 × log
(
+
)
Noise
Distortion
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB =
SINAD − 1.76
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
V22 + V32 + V4 2 + V52
THD = 20 × log
V1
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest frequency component.
______________________________________________________________________________________
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
REFADJ
HBEN
AVDD AGND DVDD DGND
5kΩ
REFERENCE
OUTPUT
REGISTERS
8 BITS
8 BITS
D0–D7
OR
D8–D15
REF
AIN
INPUT
SCALER
CAPACITIVE
DAC
MAX1178
MAX1188
AGND
SUCCESSIVEAPPROXIMATION
REGISTER AND
CONTROL LOGIC
CLOCK
CS
EOC
R/C
Pin Configuration
TOP VIEW
Ordering Information (continued)
PART
TEMP RANGE
INPUT
PINVOLTAGE
PACKAGE
RANGE (V)
D4/D12 1
20 D3/D11
D5/D13 2
19 D2/D10
MAX1188ACUP
0°C to +70°C
20 TSSOP
±10
D6/D14 3
18 D1/D9
MAX1188BCUP
0°C to +70°C
20 TSSOP
±10
D7/D15 4
17 D0/D8
MAX1188CCUP
0°C to +70°C
20 TSSOP
±10
MAX1188AEUP
-40°C to +85°C
20 TSSOP
±10
MAX1188BEUP
-40°C to +85°C
20 TSSOP
±10
MAX1188CEUP
-40°C to +85°C
20 TSSOP
±10
R/C 5
EOC 6
MAX1178
MAX1188
16 DVDD
15 DGND
AVDD 7
14 CS
AGND 8
13 HBEN
AIN 9
12 REF
AGND 10
11 REFADJ
TSSOP
Chip Information
TRANSISTOR COUNT: 15,383
PROCESS: BiCMOS
______________________________________________________________________________________
13
MAX1178/MAX1188
Functional Diagram
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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