EVALUATION KIT AVAILABLE
MAX1202/MAX1203
General Description
The MAX1202/MAX1203 are 12-bit data-acquisition systems specifically designed for use in applications with
mixed +5V (analog) and +3V (digital) supply voltages.
They operate with a single +5V analog supply or dual ±5V
analog supplies, and combine an 8-channel multiplexer,
high-bandwidth track/hold, and serial interface with high
conversion speed and low power consumption.
A 4-wire serial interface connects directly to SPI/
MICROWIRE® devices without external logic, and a serial
strobe output allows direct connection to TMS320-family
digital signal processors. The MAX1202/MAX1203 use
either the internal clock or an external serial-interface clock
to perform successive approximation analog-to-digital conversions. The serial interface operates at up to 2MHz.
The MAX1202 features an internal 4.096V reference,
while the MAX1203 requires an external reference. Both
parts have a reference-buffer amplifier that simplifies gain
trim. They also have a VL pin that is the power supply for
the digital outputs. Output logic levels (3V, 3.3V, or 5V) are
determined by the value of the voltage applied to this pin.
These devices provide a hard-wired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the devices. A
quick turn-on time enables the MAX1202/MAX1203 to
be shut down between conversions, allowing the user
to optimize supply currents. By customizing power-down
between conversions, supply current can drop below
10μA at reduced sampling rates.
The MAX1202/MAX1203 are available in 20-pin SSOP
and PDIP packages, and are specified for the commercial
and extended temperature ranges.
Applications
●●
●●
●●
●●
●●
5V/3V Mixed-Supply Systems
Data Acquisition
High-Accuracy Process Control
Battery-Powered Instruments
Medical Instruments
Typical Operating Circuit appears at end of data sheet.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
19-1173; Rev 3; 3/12
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Features
●● 8-Channel Single-Ended or 4-Channel Differential
Inputs
●● Operates from Single +5V or Dual ±5V Supplies
●● User-Adjustable Output Logic Levels
(2.7V to 5.25V)
●● Low Power: 1.5mA (Operating Mode)
2μA (Power-Down Mode)
●● Internal Track/Hold, 133kHz Sampling Rate
●● Internal 4.096V Reference (MAX1202)
●● SPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
●● Software-Configurable Unipolar/Bipolar Inputs
●● 20-Pin PDIP/SSOP
Ordering Information
PART
TEMP RANGE
MAX1202ACPP+
0ºC to +70ºC
PINPACKAGE
20 PDIP
MAX1202BCPP+
0ºC to +70ºC
20 PDIP
±1
MAX1202ACAP+
0ºC to +70ºC
20 SSOP
±1/2
MAX1202BCAP+
0ºC to +70ºC
20 SSOP
±1
Ordering Information continued at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
+
20 VDD
CH0
1
CH1
2
CH2
3
CH3
4
CH4
5
CH5
6
15 DOUT
CH6
7
14 VL
CH7
8
13 GND
VSS
9
12 REFADJ
19 SCLK
MAX1202
MAX1203
18 CS
17 DIN
16 SSTRB
11 REF
SHDN 10
PDIP/SSOP
INL
(LSB)
±1/2
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Absolute Maximum Ratings
VDD to GND.............................................................-0.3V to +6V
VL.............................................................. -0.3V to (VDD + 0.3V)
VSS to GND..............................................................+0.3V to -6V
VDD to VSS.............................................................-0.3V to +12V
CH0–CH7 to GND.......................... (VSS - 0.3V) to (VDD + 0.3V)
CH0–CH7 Total Input Current...........................................±20mA
REF to GND.............................................. -0.3V to (VDD + 0.3V)
REFADJ to GND........................................ -0.3V to (VDD + 0.3V)
Digital Inputs to GND................................ -0.3V to (VDD + 0.3V)
Digital Outputs to GND................................. -0.3V to (VL + 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 11.11mW/°C above +70°C).....................889mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
Operating Temperature Ranges
MAX1202_C_P/MAX1203_C_P...........................0°C to +70°C
MAX1202_E_P/MAX1203_E_P....................... -40°C to +85°C
Storage Temperature Range............................. -60°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
RES
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
12
Bits
MAX1202A/MAX1203A
±0.5
MAX1202B/MAX1203B
±1.0
no missing codes over temperature
±1.0
LSB
±3.0
LSB
Offset Error
MAX1202 (all grades)
Gain Error (Note 3)
External reference,
4.096V
Gain Temperature Coefficient
LSB
±3
MAX1203A
±1.5
MAX1203B
±3
External reference, 4.096V
Channel-to-Channel Offset Matching
LSB
±0.8
ppm/°C
±0.1
LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar-input mode)
Signal-to-Noise Plus Distortion Ratio
SINAD
Total Harmonic Distortion (up to the
5th Harmonic)
THD
Spurious-Free Dynamic Range
70
dB
-80
SFDR
80
dB
dB
Channel-to-Channel Crosstalk
VIN = 4.096VP-P, 65kHz (Note 4)
-85
dB
Small-Signal Bandwidth
-3dB rolloff
4.5
MHz
800
kHz
Full-Power Bandwidth
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Maxim Integrated │ 2
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
tCONV
Internal clock
External clock, 2MHz, 12 clocks/conversion
tACQ
5.5
10
6
1.5
µs
µs
Aperture Delay
10
ns
Aperture Jitter
< 50
ps
Internal Clock Frequency
External Clock Frequency Range
1.7
MHz
External compensation mode, 4.7µF
0.1
2.0
Internal compensation mode (Note 6)
0.1
0.4
0
2.0
Used for data transfer only
MHz
ANALOG INPUT
Input Voltage Range, Single-Ended
and Differential (Note 7)
Unipolar, VSS = 0V
VREF
Bipolar, VSS = -5V
±VREF/2
Multiplexer Leakage Current
On/off-leakage current, VCH_ = ±5V
±0.01
Input Capacitance
(Note 6)
16
±1
V
µA
pF
INTERNAL REFERENCE (MAX1202 only, reference-buffer enabled)
REF Output Voltage
TA = +25°C
4.076
4.096
4.116
V
30
mA
MAX1202AC
±30
±50
MAX1202AE
±30
±60
MAX1202B
±30
0 to 0.5mA output load
2.5
REF Short-Circuit Current
VREF Temperature Coefficien
Load Regulation (Note 8)
Capacitive Bypass at REF
Internal compensation mode
0
External compensation mode
4.7
Capacitive Bypass at REFADJ
mV
µF
0.01
REFADJ Adjustment Range
ppm/°C
µF
%
±1.5
EXTERNAL REFERENCE AT REF (Reference buffer disabled, VREF = 4.096V)
Input Voltage Range
2.50
Input Current
200
Input Resistance
REF Input Current in Shutdown
REFADJ Buffer Disable Threshold
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12
VSHDN = 0V
V
350
µA
20
1.5
VDD 50mV
VDD +
50mV
kΩ
10
µA
V
Maxim Integrated │ 3
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at REF
Reference-Buffer Gain
REFADJ Input Current
Internal compensation mode
0
External compensation mode
4.7
µF
MAX1202
1.68
MAX1203
1.64
V/V
MAX1202
±50
MAX1203
±5
µA
POWER REQUIREMENTS
Positive Supply Voltage
VDD
5 ±5%
V
Negative Supply Voltage
VSS
0 or 5
±5%
V
Positive Supply Current
IDD
Operating mode
1.5
2.5
Fast power-down (Note 9)
30
70
Full power-down (Note 9)
2
10
Operating mode and fast power-down
50
Full power-down
10
Negative Supply Current
ISS
Logic Supply Voltage
VL
Logic Supply Current (Notes 6, 10)
IL
Positive Supply Rejection (Note 11)
PSR
VDD = 5V ±5%; external reference, 4.096V;
full-scale input
Negative Supply Rejection (Note 11)
PSR
Logic Supply Rejection (Note 12)
PSR
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2.70
mA
µA
µA
5.25
V
10
µA
±0.06
±0.5
mV
VSS = -5V ±5%; external reference, 4.096V;
full-scale input
±0.01
±0.5
mV
External reference, 4.096V; full-scale input
±0.06
±0.5
mV
VL = VDD = 5V
Maxim Integrated │ 4
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
DIGITAL INPUTS—DIN, SCLK, CS, SHDN
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
VIH
MIN
TYP
2.0
0.8
0.15
IIN
VIN = 0V or VDD
DIN, SCLK, CS Input Capacitance
CIN
(Note 6)
SHDN Input High Voltage
VSH
VSM
SHDN Voltage, Unconnected
VFLT
1.5
SHDN Input Low Voltage
VSL
SHDN Input Current, High
ISH
SHDN = VDD
SHDN Input Current, Low
ISL
VSHDN = 0V
-4.0
SHDN = open
-100
SHDN = open
V
V
±1
µA
15
pF
VDD - 0.5
SHDN Input Mid Voltage
UNITS
V
VIL
VHYST
SHDN Maximum Allowed Leakage,
Mid-Input
MAX
V
VDD - 1.5
2.75
V
V
0.5
V
4.0
µA
µA
+100
nA
DIGITAL OUTPUTS—DOUT, SSTR (VL = 2.7V to 3.6V)
ISINK = 3mA
0.4
Output Voltage Low
VOL
Output Voltage High
VOH
ISOURCE = 1mA
Three-State Leakage Current
ILEAK
CS = VL
±10
µA
Three-State Output Capacitance
COUT
CS = VL (Note 6)
15
pF
ISINK = 6mA
0.3
VL - 0.5
V
V
DIGITAL OUTPUTS—DOUT, SSTR (VL = 4.75V to 5.25V)
Output Voltage Low
VOL
ISINK = 5mA
0.4
ISINK = 8mA
0.3
Output Voltage High
VOH
ISOURCE = 1mA
Three-State Leakage Current
ILEAK
VCS = 5V
±10
µA
Three-State Output Capacitance
COUT
VCS = 5V (Note 6)
15
pF
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4
V
V
Maxim Integrated │ 5
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
Acquisition Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tACQ
1.5
µs
DIN to SCLK Setup
tDS
100
ns
DIN to SCLK Hold
tDH
SCLK Fall to Output Data Valid
tDO
CLOAD = 100pF
CS Fall to Output Enable
tDV
CLOAD = 100pF
tTR
CLOAD = 100pF
CS Rise to Output Disable
20
0
ns
240
ns
240
ns
240
ns
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0
ns
SCLK Pulse Width High
tCH
200
ns
SCLK Pulse Width Low
tCL
200
ns
SCLK Fall to SSTRB
CLOAD = 100pF
tSSTRB
CS Fall to SSTRB Output Enable
(Note 6)
tSDV
CS Rise to SSTRB Output Disable
(Note 6)
tSTR
SSTRB Rise to SCLK Rise
(Note 6)
tSCK
External-clock mode only, CLOAD = 100pF
0
240
ns
240
ns
240
ns
ns
Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar-input mode.
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 3: MAX1202—internal reference, offset nulled; MAX1203—external reference (VREF = 4.096V), offset nulled.
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not production tested.
Note 7: Common-mode range for analog inputs is from VSS to VDD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
REFADJ = GND. Shutdown supply current is also dependent on VIH (Figure 12c).
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.
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Maxim Integrated │ 6
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Typical Operating Characteristics
(VDD = 5V ±5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = +25°C, unless otherwise noted.)
1.6
MAX1202
1.4
1.2
4.7
4.9
5.1
2.0
MAX1202
1.5
MAX1203
1.0
0.5
5.3
0
5.5
-60
-20
20
60
100
5
3
2
1
-60
-20
60
20
TEMPERATURE (°C)
TEMPERATURE (ºC)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
1.5
0.5
0.4
0.3
0.2
1.0
0.5
0
-0.5
-1.0
2
0
-1
-4
-5
140
-60
-20
20
60
2
1
0
-1
-2
5
-20
60
20
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
4
GAIN-ERROR MATCHING (LSB)
MAX1202 TOC07
OFFSET-ERROR MATCHING (LSB)
-60
TEMPERATURE (ºC)
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
-3
140
100
TEMPERATURE (ºC)
MAX1202 toc08
TEMPERATURE (ºC)
3
140
-3
-2.0
100
SINGLE-ENDED
-2
0
60
DIFFERENTIAL
1
-1.5
20
100
3
0.1
-20
140
4
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
0.6
5
100
MAX1202 toc06
2.0
MAX1202 toc05
0.7
-60
REFADJ = GND
FULL POWER-DOWN
4
0
140
MAX1202 toc03
6
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY VOLTAGE (V)
MAX1202 toc04
0.8
INL (LSB)
2.5
MAX1203
4.5
MAX1202 toc02
MAX1202 toc01
1.8
1.0
3.0
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.0
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
3
2
1
0
-1
-2
-3
-4
-60
-20
20
60
TEMPERATURE (ºC)
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100
140
-5
-60
-20
20
60
100
140
TEMPERATURE (ºC)
Maxim Integrated │ 7
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Typical Operating Characteristics (continued)
(VDD = 5V ±5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL
0.8
0.6
AMPLITUDE (dB)
INL (LSB)
0.4
0.2
0
-0.2
-0.4
-20
-40
-60
-80
-0.6
-100
-0.8
-1.0
VSS = -5V
0
MAX1202 toc10
FFT PLOT
20
MAX1202 toc09
1.0
0
750
1500
2250
3000
3750
-120
4500
0
DIGITAL CODE
33.25
66.50
FREQUENCY (kHz)
Pin Description
PIN
NAME
1–8
CH0–CH7
9
VSS
FUNCTION
Sampling Analog Inputs
Negative Supply Voltage. Tie VSS to -5V ±5% or to GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to VDD puts
the reference-buffer amplifier in internal compensation mode. Leaving SHDN unconnected puts the
reference-buffer amplifier in external compensation mode.
10
SHDN
11
REF
12
REFADJ
13
GND
14
VL
15
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
16
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
the analog-to-digital conversion, and goes high when the conversion is finished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is
high (external clock mode).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
19
SCLK
20
VDD
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Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the
reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external
reference mode, disable the internal buffer by pulling REFADJ to VDD.
Input to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier.
Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB). 2.7V ≤ VL ≤ 5.25V.
Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed (Duty cycle must be 40% to 60% in external clock mode).
Positive Supply Voltage, +5V ±5%
Maxim Integrated │ 8
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
+3.3V
3kΩ
DOUT
DOUT
3kΩ
CLOAD
CLOAD
GND
GND
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
+3.3V
DOUT
DOUT
3kΩ
CLOAD
GND
a. VOH to High-Z
3kΩ
CLOAD
CS
SCLK
18
19
DIN
17
SHDN
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
GND
13
REFADJ
12
REF
11
INPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
15
16
DOUT
SSTRB
T/H
CLOCK
IN 12-BIT
SAR
ADC OUT
MAX1202
MAX1203
REF
+2.44V
REFERENCE 20kΩ
(MAX1202)
A ª 1.68
20
14
9
VDD
VL
VSS
+4.096V
GND
b. VOL to High-Z
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
Detailed Description
to GND during a conversion. To do this, connect a 0.1μF
capacitor from IN- (of the selected analog input) to GND.
The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to 3V microprocessors
(μPs). Figure 3 is the MAX1202/MAX1203 block diagram.
Pseudo-Differential Input
Figure 4 shows the ADC’s analog comparator’s sampling
architecture. In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to GND. In
differential mode, IN+ and IN- are selected from pairs of
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels using Tables 3 and 4.
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudodifferential such that only the signal at IN+ is sampled.
The return side (IN-) must remain stable (typically within
±0.5 LSB, within ±0.1 LSB for best results) with respect
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During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends on
the falling SCLK edge after the input control word’s last bit
is entered. The T/H switch opens at the end of the acquisition interval, retaining charge on CHOLD as a sample of
the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply GND.
This unbalances node ZERO at the comparator’s input.
The capacitive DAC adjusts during the remainder of the
conversion cycle to restore node ZERO to 0V within the
limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x [(VIN+) - (VIN-)] from CHOLD to
the binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal.
Maxim Integrated │ 9
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Track/Hold
The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is connected
to GND if the converter is set up for single-ended inputs,
and the converter samples the “+” input. IN- connects to
the “-” input if the converter is set up for differential inputs,
and the difference of |N+ - IN-| is sampled. The positive
input connects back to IN+, at the end of the conversion,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, acquisition
time increases and more time must be allowed between
conversions. The acquisition time, tACQ, is the maximum
time the device takes to acquire the signal, and is also the
minimum time needed for the signal to be acquired. It is
calculated by the following:
tACQ = 9 x (RS + RIN) x 16pF
where RIN = 9kΩ, RS = the source impedance of the input
signal, and tACQ is never less than 1.5μs. Source impedances below 1kΩ do not significantly affect the ADC’s AC
+3V
0.1µF
VL
performance. Higher source impedances can be used if
an input capacitor is connected to the analog inputs, as
shown in Figure 5. Note that the input capacitor forms
an RC filter with the input source impedance, limiting the
ADC’s signal bandwidth.
12-BIT CAPACITIVE DAC
REF
CH0
CH1
INPUT
MUX
–
CH4
CH5
CH6
CH7
CSWITCH
9kΩ
RIN
HOLD
TRACK
T/H
SWITCH
GND
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
Figure 4. Equivalent Input Circuit
VDD
OSCILLOSCOPE
+5V
0.1µF
ZERO
16pF
CH2
CH3
COMPARATOR
CHOLD
+
4.7µF
GND
0 TO
4.096V
ANALOG 0.01µF
INPUT
CH7
SCLK
VSS
MAX1202
MAX1203
SSTRB
CS
DOUT*
SCLK
+3V
DIN
2MHz
OSCILLATOR
CH1
CH2
CH3
CH4
SSTRB
C2
0.01µF
C1
4.7µF
REFADJ
DOUT
REF
SHDN
+2.5V
N.C.***
**
+2.5V
REFERENCE
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX).
**REQUIRED FOR MAX1203 ONLY.
***NO CONNECTION
Figure 5. Quick-Look Circuit
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Maxim Integrated │ 10
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Table 1a. Unipolar Full Scale and Zero
Scale
ZERO
SCALE
FULL SCALE
0V
+4.096V
at REFADJ
0V
at REF
0V
VREFADJ x A*
REFERENCE
Internal
External
VREF
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
Table 1b. Bipolar Full Scale, Zero Scale,
and Negative Full Scale
REFERENCE
Internal
at
External REFADJ
at REF
NEGATIVE
FULL SCALE
ZERO
SCALE
FULL SCALE
+4.096V/2
0V
+4.096V/2
-1/2 VREFADJ
x A*
0V
+1/2 VREFADJ
x A*
+1/2 VREF
0V
+1/2 VREF
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz smallsignal bandwidth. Therefore it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog inputs
to VDD and VSS, allow the analog input pins to swing from
(VSS - 0.3V) to (VDD + 0.3V) without damage. However,
for accurate conversions near full scale, the inputs must
not exceed VDD by more than 50mV, or be lower than
VSS by 50mV.
If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of
off-channels more than 2mA.
The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick Look
Use the circuit of Figure 5 to quickly evaluate the MAX1202/
MAX1203’s analog performance. The MAX1202/MAX1203
require a control byte to be written to DIN before each conversion. Tying DIN to +3V feeds in control byte $FF hex,
www.maximintegrated.com
which triggers single-ended unipolar conversions on CH7
in external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for one clock period before the most significant bit of the 12-bit conversion result shifts out of DOUT.
Varying the analog input to CH7 alters the sequence of
bits from DOUT. A total of 15 clock cycles per conversion
is required. All SSTRB and DOUT output transitions occur
on SCLK’s falling edge.
How to Start a Conversion
Clocking a control byte into DIN starts conversion on the
MAX1202/MAX1203. With CS low, each rising edge on
SCLK clocks a bit from DIN into the MAX1202/MAX1203’s
internal shift register. After CS falls, the first logic “1” bit
defines the control byte’s MSB. Until this first “start” bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 2 shows the control-byte format.
The MAX1202/MAX1203 are fully compatible with SPI/
MICROWIRE devices. For SPI, select the correct clock
polarity and sampling edge in the SPI control registers:
set CPOL = 0 and CPHA = 0. MICROWIRE and SPI both
transmit and receive a byte at the same time. Using the
Typical Operating Circuit, the simplest software interface
requires only three 8-bit transfers to perform a conversion
(one 8-bit transfer to configure the ADC, and two more
8-bit transfers to clock out the 12-bit conversion result).
Maxim Integrated │ 11
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Table 2. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT1
BIT 0 (LSB)
START
SEL 2
SEL 1
SEL 0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
7 (MSB)
START
The first logic 1 bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog
input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2
to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended
mode, input signal voltages are referred to GND. In differential mode, the voltage difference
between two channels is measured. (Tables 3 and 4).
1
0 (LSB)
DESCRIPTION
Selects clock and power-down modes.
PD1 PD0 Mode
0
0
Full power-down (IDD = 2µA, internal reference)
0
1
Fast power-down (IDD = 30µA, internal reference)
1
0
Internal clock mode
1
1
External clock mode
PD1
PD0
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
0
0
0
+
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
-
+
+
+
+
+
+
+
-
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
0
0
0
+
-
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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-
CH2
CH3
+
-
CH4
CH5
+
-
CH6
CH7
+
-
-
+
+
-
+
-
+
Maxim Integrated │ 12
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Simple Software Interface
Digital Output
Make sure the CPU’s serial interface runs in master mode
so the CPU generates the serial clock. Choose a clock
frequency from 100kHz to 2MHz.
In unipolar-input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s complement (Figure 16). Data is clocked out at SCLK’s falling
edge in MSB-first format. The digital output logic level is
adjusted with the VL pin. This allows DOUT and SSTRB
to interface with 3V logic without the risk of overdrive. The
MAX1202/MAX1203’s digital inputs are designed to be
compatible with 5V CMOS logic as well as 3V logic.
1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull CS
on the MAX1202/MAX1203 low.
Internal and External Clock Modes
The MAX1202/MAX1203 can use either an external serial
clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1202/
MAX1203. The T/H acquires the input signal as the last
three bits of the control byte are clocked into DIN. Bits
PD1 and PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common to
both modes.
3) Transmit TB1 and simultaneously receive a byte and
call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simultaneously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simultaneously receive byte RB3.
6) Pull CS on the MAX1202/MAX1203 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded with
one leading zero and three trailing zeros. The total conversion time is a function of the serial-clock frequency and
the amount of idle time between 8-bit transfers. To avoid
excessive T/H droop, make sure that the total conversion
time does not exceed 120μs.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and DOUT
go into a high-impedance state when CS goes high; after
CS
tACQ
SCLK
1
DIN
SSTRB
4
SEL2 SEL1 SEL0
8
UNI/ SGL/
BIP DIF PD1
16
20
24
PD0
START
RB1
B11
MSB
DOUT
ADC STATE
12
IDLE
ACQUISITION
1.5µs
(SCLK = 2MHz)
RB3
RB2
B10
B9
B8
B7
B6
B5
B4
CONVERSION
B3
B2
B1
B0
LSB
FILLED WITH
ZEROS
IDLE
Figure 6. 24-Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible)
www.maximintegrated.com
Maxim Integrated │ 13
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
•••
CS
tCSH
tCSS
tCL
tCH
SCLK
tCSH
•••
tDS
tDH
DIN
•••
tDV
tDO
DOUT
tTR
•••
Figure 7. Detailed Serial-Interface Timing
CS
•••
•••
tSTR
tSDV
SSTRB
•••
•••
tSSTRB
SCLK
•••
tSSTRB
•••
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
the next CS falling edge, SSTRB outputs a logic low.
Figure 8 shows SSTRB timing in external clock mode.
The conversion must complete in some minimum time or
droop on the sample-and-hold capacitors might degrade
conversion results. Use internal clock mode if the clock
period exceeds 10μs or if serial-clock interruptions could
cause the conversion interval to exceed 120μs.
Internal Clock
In internal clock mode, the MAX1202/MAX1203 generate
their own conversion clock. This frees the μP from run-
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ning the SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum
of 10μs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling clock
edge produces the MSB of the conversion at DOUT, fol-
Maxim Integrated │ 14
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CS
SCLK
1
DIN
2
3
4
SEL2 SEL1 SEL0
7
8
UNI/ SGL/
BIP DIF PD1
PD0
5
6
9
10
11
12
18
19
20
21
22
23
24
START
SSTRB
tCONV
B11
MSB B10
DOUT
ADC STATE
ACQUISITION CONVERSION
1.5s
10s MAX
(SCLK = 2MHz)
IDLE
B9
B2
B1
FILLED WITH
B0
LSB ZEROS
IDLE
Figure 9. Internal Clock Mode Timing
CS • • •
tCONV
tCSH
tCSS
tSCK
SSTRB • • •
tSSTRB
SCLK • • •
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
lowed by the remaining bits in MSB-first format (Figure
9). CS does not need to be held low once a conversion is
started. Pulling CS high prevents data from being clocked
into the MAX1202/MAX1203 and three-states DOUT, but
it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance state
when CS goes high.
Figure 10 shows SSTRB timing in internal clock mode.
Data can be shifted in and out of the MAX1202/MAX1203
at clock rates up to 2.0MHz, if tACQ is kept above 1.5μs.
Data Framing
CS’s falling edge does not start a conversion on the
MAX1202/MAX1203. The first logic high clocked into
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DIN is interpreted as a start bit and defines the first bit
of the control byte. A conversion starts on SCLK’s falling
edge after the eighth bit of the control byte (the PD0 bit)
is clocked into DIN. The start bit is defined as one of the
following:
The first high bit clocked into DIN with CS low anytime
the converter is idle (e.g., after VDD is applied).
or
The first high bit clocked into DIN after bit 5 (B5) of a
conversion in progress appears at DOUT.
If a falling edge on CS forces a start bit before B5
becomes available, the current conversion is terminated
and a new one started. Thus, the fastest the MAX1202/
MAX1203 can run is 15 clocks/conversion.
Maxim Integrated │ 15
MAX1202/MAX1203
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (μCs) require that data transfers
occur in multiples of eight clock cycles; 16 clocks per
conversion is typically the fastest that a μC can drive
the MAX1202/MAX1203. Figure 11b shows the serialinterface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled low,
internal power-on reset circuitry activates the MAX1202/
MAX1203 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies are stabilized, the
internal reset time is 100μs. No conversions should be performed during this phase. SSTRB is high on power-up, and
if CS is low, the first logical 1 on DIN is interpreted as a start
bit. Until a conversion takes place, DOUT shifts out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.
Leave SHDN unconnected to select external compensation. The Typical Operating Circuit uses a 4.7μF capacitor
at REF. A value of 4.7μF or greater ensures stability and
allows converter operation at the 2MHz full clock speed.
External compensation increases power-up time (see the
section Choosing Power-Down Mode, and Table 5).
Internal compensation requires no external capacitor
at REF, and is selected by pulling SHDN high. Internal
compensation allows for the shortest power-up times, but
the external clock must be limited to 400kHz during the
conversion.
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full
power-down or fast power-down mode via bits 1 and 0
of the DIN control byte with SHDN high or unconnected
(Tables 2 and 6). Pull SHDN low at any time to shut down
the converter completely. SHDN overrides bits 1 and 0 of
the control byte.
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5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Full power-down mode turns off all chip functions that draw
quiescent current, reducing IDD and ISS typically to 2μA.
For the MAX1202, fast power-down mode turns off all
circuitry except the bandgap reference. With fast powerdown mode, the supply current is 30μA. Power-up time
can be shortened to 5μs in internal compensation mode.
Since the MAX1203 does not have an internal reference,
power-up times coming out of full or fast power-down are
identical.
IDD shutdown current can increase if any digital input
(DIN, SCLK, CS) is held high in either power-down mode.
The actual shutdown current depends on the state of the
digital inputs, the voltage applied to the digital inputs (VIH),
the supply voltage (VDD), and the operating temperature.
Figure 12c shows the maximum IDD increase for each
digital input held high in power-down mode for different
operating conditions. This current is cumulative, so if all
three digital inputs are held high, the additional shutdown
current is three times the value shown in Figure 12c.
In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer compensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7μF compensation capacitor (200ms with a 33μF capacitor) when the
capacitor is initially fully discharged. From fast powerdown, start-up time can be eliminated by using lowleakage capacitors that do not discharge more than 1/2
LSB while shut down. In power-down, the capacitor has
to supply the current into the reference (typically 1.5μA)
and the transient currents at power-up.
Figures 12a and 12b show the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software powerdown is asserted, the ADC continues to operate in the
last specified clock mode until the conversion is complete.
The ADC then powers down into a low quiescent-current
state. In internal clock mode, the interface remains active
and conversion results can be clocked out even though
the MAX1202/MAX1203 have already entered software
power-down.
The first logical 1 on DIN is interpreted as a start bit and
powers up the MAX1202/MAX1203. Following the start
bit, the control byte also determines clock and power-
Maxim Integrated │ 16
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CS
1
8
1
8
1
SCLK
DIN
S
S
CONTROL BYTE 0
DOUT
B11 B10 B9 B8
S
CONTROL BYTE 1
B7 B6 B5 B4 B3
B2
B1 B0
B11 B10 B9
B8 B7 B6
CONTROL BYTE 2
B5 B4 B3 B2
B1
B0
CONVERSION RESULT 1
CONVERSION RESULT 0
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
•••
SCLK
•••
DIN
S
S
CONTROL BYTE 0
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
•••
CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5
•••
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
down modes. For example, if the DIN word contains PD1
= 1, the chip remains powered up. If PD1 = 0, power-down
resumes after one conversion.
Hardware Power-Down
The SHDN pin places the converter into full power-down
mode. Unlike the software power-down modes, conversion
is not completed; it stops coincidentally with SHDN being
brought low. There is no power-up delay if an external reference, which is not shut down, is used. SHDN also selects
internal or external reference compensation (Table 7).
Power-Down Sequencing
The MAX1202/MAX1203’s automatic power-down modes
can save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.
this example) are required for the reference buffer to settle. When exiting FULLPD, waiting this 2ms in FASTPD
mode (instead of just exiting FULLPD mode and returning
to normal operating mode) reduces power consumption
by a factor of 10 or more (Figure 13).
Lowest Power at Higher Throughputs
Figure 14b shows power consumption with external reference compensation in fast power-down, with one and
eight channels converted. The external 4.7μF compensation requires a 50μs wait after power-up. This circuit
combines fast multichannel conversion with the lowest
power consumption possible. Full power-down mode
can increase power savings in applications where the
MAX1202/MAX1203 are inactive for long periods of time,
but where intermittent bursts of high-speed conversion
are required.
Lowest Power at up to
500 Conversions per Channel per Second
Figure 14a depicts MAX1202 power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01μF bypass
capacitor at REFADJ forms an RC filter with the internal
20kΩ reference resistor, with a 0.2ms time constant. To
achieve full 12-bit accuracy, 10 time constants (or 2ms in
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Maxim Integrated │ 17
MAX1202/MAX1203
CLOCK
MODE
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
SETS EXTERNAL
CLOCK MODE
SX X XX X 0 1
DOUT
DATA VALID
(12 DATA BITS)
MODE
POWERED UP
S XX XXX 1 1
DATA VALID
(12 DATA BITS)
DATA
INVALID
FAST
POWER-DOWN
FULL
POWERDOWN
POWERED UP
POWERED
UP
Figure 12a. Timing Diagram for Power-Down Modes, External Clock
Table 5. Typical Power-Up Delay Times
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION MODE
REF
CAPACITOR
(µF)
POWER-DOWN
MODE
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
Enabled
Internal
—
Enabled
Internal
—
Fast
5
26
Full
300
Enabled
External
26
4.7
Fast/Full
See Figure 14c
133
Disabled
Disabled
—
—
Fast
2
133
—
—
Full
2
133
Table 6. Software Shutdown
and Clock Mode
PD1
PD0
DEVICE MODE
0
0
Full power-down mode
0
1
Fast power-down mode
1
0
Internal clock mode
1
1
External clock mode
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Table 7. Hard-Wired Shutdown
and Compensation Mode
SHDN
STATE
DEVICE
MODE
REFERENCE-BUFFER
COMPENSATION
VDD
Enabled
Internal compensation
Unconnected
Enabled
External compensation
GND
Full
power-down
N/A
Maxim Integrated │ 18
MAX1202/MAX1203
CLOCK
MODE
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
SX X XX X 0 0
DOUT
S
DATA VALID
DATA VALID
CONVERSION
SSTRB
CONVERSION
FULL
POWER-DOWN
POWERED UP
MODE
POWERED
UP
Figure 12b. Timing Diagram for Power-Down Modes, Internal Clock
External and Internal References
40
The MAX1202 can be used with an internal or external
reference, whereas an external reference is required for
the MAX1203. An external reference can be connected
directly at the REF terminal, or at the REFADJ pin.
SUPPLY CURRENT PER INPUT (mA)
35
(VDD - VIH) = 2.55V
30
25
An internal buffer is designed to provide 4.096V at REF
for both the MAX1202 and the MAX1203. The MAX1202’s
internally trimmed 2.44V reference is buffered with a gain
of 1.68. The MAX1203’s REFADJ pin is buffered with
a gain of 1.64, to scale an external 2.5V reference at
REFADJ to 4.096V at REF.
20
15
(VDD - VIH) = 2.25V
10
(VDD - VIH) = 1.95V
5
MAX1202 Internal Reference
0
-60
-20
20
60
100
140
TEMPERATURE (°C)
Figure 12c. Additional IDD Shutdown Supply Current vs. VIH for
Each Digital Input at a Logic 1
The MAX1202’s full-scale range using the internal reference is 4.096V with unipolar inputs and ±2.048V with
bipolar inputs. The internal reference voltage is adjustable
to ±1.5% with the circuit of Figure 17.
COMPLETE CONVERSION SEQUENCE
DIN
1
00
FULLPD
REFADJ
(ZEROS)
2ms WAIT
1
01
FASTPD
CH1
1
(ZEROS)
CH7
11
NOPD
1
00
FULLPD
1
01
FASTPD
2.5V
0V
REF
4V
t = RC = 20kW x CREFADJ
0V
tBUFFEN ª 15µs
Figure 13. MAX1202 FULLPD/FASTPD Power-Up Sequence
www.maximintegrated.com
Maxim Integrated │ 19
MAX1202/MAX1203
MAX1202/MAX1203
FAST POWER-DOWN
8 CHANNELS
100
1 CHANNEL
10
1
0
50
100 150 200 250 300 350 400 450 500
10,000
AVERAGE SUPPLY CURRENT (µA)
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
MAX186-14A
FULL POWER-DOWN
1000
AVERAGE SUPPLY CURRENT (µA)
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
8 CHANNELS
1000
100
10
CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. MAX1202 Supply Current vs. Sample Rate/
Second, FULLPD, 400kHz Clock
1 CHANNEL
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
0
2k
4k
6k
8k
10k
12k
14k
16k
18k
CONVERSIONS PER CHANNEL PER SECOND
Figure 14b. MAX1202/MAX1203 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock
External Reference
Using the buffered REFADJ input makes buffering of the
external reference unnecessary. When connecting an
external reference directly at REF, disable the internal
buffer by tying REFADJ to VDD. In power-down, the input
bias current to REFADJ can be as much as 25μA with
REFADJ tied to VDD (MAX1202 only). Pull REFADJ to
GND to minimize the input bias current in power-down.
Transfer Function and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 16 shows the bipolar I/O
transfer function. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary
with 1 LSB = 1.00mV (4.096V/4096) for unipolar operation, and 1 LSB = 1.00mV [(4.096V/2 - -4.096V/2)/4096]
for bipolar operation.
Figure 17 shows how to adjust the ADC gain in applications that use the internal reference. The circuit provides
±1.5% (±65 LSBs) of gain adjustment range.
www.maximintegrated.com
3.0
2.5
POWER-UP DELAY (ms)
With both the MAX1202 and MAX1203, an external reference can be placed at either the input (REFADJ) or the
output (REF) of the internal reference-buffer amplifier.
The REFADJ input impedance is typically 20kΩ for the
MAX1202, and higher than 100kΩ for the MAX1203,
where the internal reference is omitted. At REF, the DC
input resistance is a minimum of 12kΩ. During conversion,
an external reference at REF must deliver up to 350μA DC
load current and have an output impedance of 10Ω or less.
If the reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7μF capacitor.
2.0
1.5
1.0
0.5
0
0.0001
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines underneath the ADC package.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
Maxim Integrated │ 20
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
011 . . . 111
11 . . . 110
FS = +2.048V
011 . . . 110
1LSB = +4.096V
4096
11 . . . 101
000 . . . 010
000 . . . 001
FS = +4.096V
1LSB = + 4.096V
4096
111 . . . 111
111 . . . 110
111 . . . 101
00 . . . 011
00 . . . 010
100 . . . 001
00 . . . 001
00 . . . 000
000 . . . 000
100 . . . 000
0
1
2
3
INPUT VOLTAGE (LSBs)
FS
(“star” ground point) at GND. Connect all other analog
grounds to this ground. No other digital system ground
should be connected to this single-point analog ground.
The ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the power supplies can affect the
ADC’s high-speed comparator. Bypass these supplies
to the single-point analog ground with 0.1μF and 4.7μF
bypass capacitors close to the MAX1202/MAX1203.
Minimize capacitor lead lengths for best supply-noise
rejection. If the +5V power supply is very noisy, a 10Ω
resistor can be connected as a lowpass filter, as shown
in Figure 18.
+FS - 1LSB
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
www.maximintegrated.com
0V
-FS
Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale
+5V
MAX1202
510kΩ
100kΩ
12
24kΩ
REFADJ
0.01µF
Figure 17. MAX1202 Reference-Adjust Circuit
Maxim Integrated │ 21
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TMS320CL3x to MAX1202/
MAX1203 Interface
3) Write an 8-bit word (1XXXXX11) to the MAX1202/
MAX1203 to initiate a conversion and place the device
into external clock mode. Refer to Table 2 to select the
proper XXXXX bit values for your specific application.
Figure 19 shows an application circuit to interface the
MAX1202/MAX1203 to the TMS320 in external clock
mode. Figure 20 shows the timing diagram for this interface circuit.
4) The MAX1202/MAX1203’s SSTRB output is monitored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1202/MAX1203.
Use the following steps to initiate a conversion in the
MAX1202/MAX1203 and to read the results:
1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1202/MAX1203’s SCLK input.
5) The TMS320 reads in one data bit on each of the next
16 rising edges of SCLK. These data bits represent the
12-bit conversion result followed by four trailing bits,
which should be ignored.
6) Pull CS high to disable the MAX1202/MAX1203 until
the next conversion is initiated.
2) The MAX1202/MAX1203’s CS is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX1202/MAX1203’s DIN.
SUPPLIES
+5V
-5V
+3V
GND
XF
CS
CLKX
R* = 10Ω
VDD
SCLK
TMS320LC3x
MAX1202
MAX1203
CLKR
GND
VSS
VL
MAX1202
MAX1203
+3V
DGND
DIGITAL
CIRCUITRY
DX
DIN
DR
DOUT
FSR
SSTRB
*OPTIONAL
Figure 18. Power-Supply Grounding Connection
Figure 19. MAX1202/MAX1203-to-TMS320 Serial Interface
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
DOUT
MSB
B10
B1
LSB
HIGH
IMPEDANCE
Figure 20. TMS320 Serial-Interface Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 22
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Chip Information
Ordering Information (continued)
INL
(LSB)
±1/2
PROCESS: BiCMOS
PART
TEMP RANGE
MAX1202AEPP+
-40ºC to +85ºC
PINPACKAGE
20 PDIP
MAX1202BEPP+
-40ºC to +85ºC
20 PDIP
±1
MAX1202AEAP+
-40ºC to +85ºC
20 SSOP
±1/2
MAX1202BEAP+
-40ºC to +85ºC
20 SSOP
±1
MAX1203ACPP+
0ºC to +70ºC
20 PDIP
±1/2
MAX1203BCPP+
0ºC to +70ºC
20 PDIP
±1
MAX1203ACAP+
0ºC to +70ºC
20 SSOP
±1/2
PACKAGE
TYPE
PACKAGE
CODE
MAX1203BCAP+
0ºC to +70ºC
20 SSOP
±1
20 SSOP
A20+2
21-0056
90-0094
MAX1203AEPP+
-40ºC to +85ºC
20 PDIP
±1/2
20 PDIP
P20+3
21-0043
—
MAX1203BEPP+
-40ºC to +85ºC
20 PDIP
±1
MAX1203AEAP+
-40ºC to +85ºC
20 SSOP
±1/2
MAX1203BEAP+
-40ºC to +85ºC
20 SSOP
±1
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
DOCUMENT
LAND
NO.
PATTERN NO.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit
+5V
CH0
0 to
4.096V
ANALOG
INPUTS
MAX1202
REF
SCLK
DIN
DOUT
REFADJ
C3
0.1µF
C4
4.7µF
C5
0.1µF
CPU
GND
VSS
CS
C2
0.01µF
VDD
VL
CH7
C1
4.7µF
+3V
VDD
SSTRB
SHDN
www.maximintegrated.com
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
Maxim Integrated │ 23
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Package Information
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
1/97
Initial release
1
3/97
Added MAX1203 to the data sheet
1–24
2
5/98
Corrected gain error limit
2, 20
3
3/12
Removed military grade packages and updated style throughout data sheet
DESCRIPTION
—
1–10, 13, 16, 18,
22, 23
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2012 Maxim Integrated Products, Inc. │ 24
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