MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
General Description
The MAX120/MAX122 complete, BiCMOS, sampling 12-bit
analog-to-digital converters (ADCs) combine an on-chip
track/hold (T/H) and a low-drift voltage reference with fast
conversion speeds and low-power consumption. The T/H’s
350ns acquisition time combined with the MAX120’s 1.6µs
conversion time results in throughput rates as high as 500k
samples per second (ksps). Throughput rates of 333ksps
are possible with the 2.6µs conversion time of the MAX122.
The MAX120/MAX122 accept analog input voltages from
-5V to +5V. The only external components needed are
decoupling capacitors for the power-supply and reference voltages. The MAX120 operates with clocks in the
0.1MHz to 8MHz frequency range. The MAX122 accepts
0.1MHz to 5MHz clock frequencies.
The MAX120/MAX122 employ a standard microprocessor
(µP) interface. Three-state data outputs are configured
to operate with 12-bit data buses. Data-access and busrelease timing specifications are compatible with most
popular µPs without resorting to wait states. In addition,
the MAX120/MAX122 can interface directly to a first-in,
first-out (FIFO) buffer, virtually eliminating µP interrupt
overhead. All logic inputs and outputs are TTL/CMOS
compatible. For applications requiring a serial interface,
refer to the MAX121.
Applications
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Digital-Signal Processing
Audio and Telecom Processing
Speech Recognition and Synthesis
High-Speed Data Acquisition
Spectrum Analysis
Data Logging Systems
Pin Configuration
TOP VIEW
1
+
MODE
RD
24
2
VSS MAX122 CS
23
3
VDD
INT/BUSY
22
4
AIN
CLKIN
21
5
VREF
CONVST
20
6
AGND
D0
19
7
D11
D1
18
8
D10
D2
17
9
D9
D3
16
10
D8
D4
15
11
D7
D5
14
12
DGND
D6
13
MAX120
PDIP/SO/SSOP
19-0030; Rev 1; 3/12
Features
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12-Bit Resolution
No Missing Codes Over Temperature
20ppm/°C -5V Internal Reference
1.6µs Conversion Time/500ksps Throughput
(MAX120)
2.6µs Conversion Time/333ksps Throughput
(MAX122)
Low Noise and Distortion:
• 70dB (min) SINAD
• -77dB (max) THD (MAX122)
Low Power Dissipation: 210mW
Separate Track/Hold Control Input
Continuous-Conversion Mode Available
±5V Input Range, Overvoltage Tolerant to ±15V
24-Pin Narrow DIP, Wide SO, and SSOP Packages
Ordering Information
PART
TEMP RANGE
PINPACKAGE
INL
(LSB)
MAX120CNG+
0°C to +70°C
24 PDIP
±1
MAX120CWG+
0°C to +70°C
24 Wide SO
±1
MAX120CAG+
0°C to +70°C
24 SSOP
±1
MAX120ENG+
-40°C to +85°C
24 PDIP
±1
MAX120EWG+
-40°C to +85°C
24 Wide SO
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagram
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Absolute Maximum Ratings
VDD to DGND...........................................................-0.3V to +6V
VSS to DGND.........................................................+0.3V to -17V
AIN to AGND........................................................................±15V
AGND to DGND..................................................................±0.3V
Digital Inputs/Outputs to DGND.....................-0.3V to (V + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Narrow PDIP (derate 13.33mW/°C above +70°C).....1067mW
SO (derate 11.76mW/°C above +70°C).......................941mW
SSOP (derate 8.00mW/°C above +70°C)....................640mW
Narrow CDIP (derate 12.50mW/°C above +70°C).....1000mW
Operating Temperature Ranges
MAX12_C............................................................0°C to +70°C
MAX12_E_ ..................................................... -40°C to +85°C
MAX12_MRG ............................................... -55°C to +125°C
Storage Temperature Range...............................-65°C to+160°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +4.75V to +5.25V, VSS = -10.8V to -15.75V, fCLK = 8MHz for MAX120 and 5MHz for MAX122, TA = TMIN to TMAX, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
Differential Nonlinearity (Note 1)
Integral Nonlinearity
(Note 1)
RES
DNL
12
12-bit no missing
codes over
temperature range
11-bit no missing
codes over
temperature range
INL
±3/4
MAX120C/E,
MAX122BC/BE
±1
MAX120M
±2
LSB
MAX122AC/AE
±3/4
MAX120C/E,
MAX122BC/BE
±1
Code 00..00 to 00..01 transition,
near VAIN = 0V
Bipolar Zero Error (Note 1)
±3
Temperature drift
Full-Scale Error (Notes 1, 2)
Including reference; adjusted for bipolar
zero error; TA = +25°C
Full-Scale Temperature Drift
Excluding reference
Power-Supply Rejection Ratio
(Change in FS)
(Note 3)
Bits
MAX122AC/AE
PSRR
±0.005
LSB
LSB
LSB/”C
±8
±1
LSB
ppm/”C
VDD only, 5V ±5%
±1/4
±3/4
VSS only, -12V ±10%
±1/4
±1
VSS only, -15V ±5%
±1/4
±1
LSB
ANALOG INPUT
Input Range
Input Current
-5
VAIN = +5V (approximately 6kΩ to REF)
Input Capacitance (Note 4)
Full-Power Input Bandwidth
+5
V
2.5
mA
10
pF
1.5
MHz
REFERENCE
Output Voltage
No external load, VAIN = 5V, TA = +25°C
External Load Regulation
0mA < ISINK < 5mA, VAIN = 0V
5
Temperature Drift (Note 5)
MAX12_C/E
±25
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-5 02
-4.98
V
mV
ppm/°C
Maxim Integrated │ 2
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Electrical Characteristics (continued)
(VDD = +4.75V to +5.25V, VSS = -10.8V to -15.75V, fCLK = 8MHz for MAX120 and 5MHz for MAX122, TA = TMIN to TMAX, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (MAX120: fS = 500kHz, VAIN = ±5VP-P, 100kHz: MAX122: fS = 333kHz, VAIN = ±5VP-P, 50kHz
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
(First Five Harmonics)
SINAD
TA = +25°C
TA = +25°C
THD
TA = +25°C
Spurious-Free Dynamic Range
SFDR
MAX120, MAX122
70
MAX122AC/AE
70
MAX122BC/BE
69
72
dB
MAX120
-82
-77
MAX122
-85
-78
MAX122AC/AE
-77
MAX122BC/BE
-75
MAX120
77
82
MAX122
78
85
MAX122AC/AE
77
MAX122BC/BE
75
dB
dB
CONVERSION TIME
Synchronous
Clock Frequency
tCONV
13tCLK
fCLK
MAX120
1.63
MAX122
2.60
MAX120
0.1
8
MAX122
0.1
5
µs
MHz
DIGITAL INPUTS (CLKIN, CONVST, RD, CS)
Input High Voltage
VIH
Input Low Voltage
VIL
2.4
V
0.8
V
10
pF
VIN = 0V or VDD
±5
µA
0.4
V
Input Capacitance (Note 4)
Input Current
DIGITAL OUTPUTS (INT/BUSY, D11–D0)
Output Low Voltage
VOL
ISINK = 1.6mA
Output High Voltage
VOH
ISOURCE = 1mA
Leakage Current
ILKG
VIN = 0V or VDD, D11–D0
VDD - 0.5
V
Output Capacitance (Note 4)
±5
µA
10
pF
POWER REQUIREMENTS
Positive Supply Voltage
VDD
Guaranteed by supply rejection test
4.75
5.25
V
Negative Supply Voltage
VSS
Guaranteed by supply rejection test
-10.80
-15.75
V
Positive Supply Current (Note 6)
IDD
VDD = 5.25V, VSS = -15.75V, VAIN = 0V
9
15
mA
Negative Supply Current (Note 6)
ISS
VDD = 5.25V, VSS = -15.75V, VAIN = 0V
14
20
mA
VDD = 5V, VSS = -12V, VAIN = 0V
210
315
mW
Power Dissipation (Note 6)
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Maxim Integrated │ 3
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Timing Characteristics
(VDD = +5V, VSS = -12V to -15V, 100% tested, TA = TMIN to TMAX, unless otherwise noted.) (Note 7)
PARAMETER
SYMBOL
CONDITIONS
TA = +25°C
MIN
TYP
MAX12_C/E
MAX
MIN
TYP
MAX
UNITS
CS to RD Setup Time
tCS
0
0
ns
CS to RD Hold Time
tCH
0
0
ns
CONVST Pulse Width
tCW
30
30
ns
RD Pulse Width
tRW
tDA
tDA
ns
Data-Access Time
tDA
Bus-Relinquish Time
tDH
RD or CONVST to BUSY
tB0
CL = 50pF
CLKIN to BUSY or INT
tB1
CL = 50pF
CLKIN to BUSY Low
tB2
RD to INT High
40
75
100
ns
30
50
65
ns
30
75
100
ns
70
110
150
ns
In mode 5
45
90
120
ns
tIH
CL = 50pF
30
50
75
ns
BUSY or INT to Data Valid
tBD
CL (Data) = 100pF,
CL (INT, BUSY) = 50pF
20
30
ns
Acquisition Time (Note 8)
tACQ
Aperture Delay (Note 8)
CL = 100pF
350
350
tAP
Aperture Jitter (Note 8)
ns
10
ns
30
ps
Note 1: These tests are performed at VDD = 5V, VSS = -15V. Operation over supply is guaranteed by supply rejection tests.
Note 2: Ideal full-scale transition is at +5V - 3/2 LSB = +4.9963V, adjusted for offset error.
Note 3: Supply rejection defined as change in full-scale transition voltage with the specified change in supply voltage = (FS at nominal supply)- (FS at nominal supply ± tolerance), expressed in LSBs.
Note 4: For design guidance only, not tested.
Note 5: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as TC = ΔVREF/
VREF/(ΔT).
Note 6: VCS = VRD = VCONVST = 0V, VMODE = 5V.
Note 7: Control inputs specified with tr = tf = 5ns ( 10% to 90% of +5V) and timed from a 1.6V voltage level. Output delays are
measured to +0.8V if going low, or +2.4V if going high. For bus-relinquish time, a change of 0.5V is measured. See Figures
1 and 2 for load circuits.
Note 8: For design guidance only, not tested.
Pin Description
PIN
1
NAME
MODE
FUNCTION
Mode Input. Hardwire to set operational mode.
VDD: Single conversion, INT Output
OPEN: Single conversion, BUSY Output
DGND: Continuous conversions, BUSY Output
2
VSS
Negative Power Supply, -12V or -15V
3
VDD
Positive Power Supply, +5V
4
AIN
Sampling Analog Input, ±5V bipolar input range
5
VREF
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-5V Reference Output. Bypass to AGND with 22µF || 0.1µF.
Maxim Integrated │ 4
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Pin Description (continued)
PIN
NAME
FUNCTION
6
AGND
7–11, 13–19
D11–D0
Analog Ground
12
DGND
20
CONVST
21
CLKIN
22
INT/BUSY
23
CS
Chip-Select Input, Active-Low. When RD is low, enables the three-state outputs. If CONVST and
RD are low, a conversion is initiated on the falling edge of CS.
24
RD
Read Input, Active-Low. When CS is low, RD enables the three-state outputs. If CONVST and CS
are low, conversion is initiated on the falling egde of RD.
Three-State Data Outputs D11 (MSB) to D0 (LSB)
Digital Ground
Convert Start Input. Initiates conversions on its falling edge.
Clock Input. Drive with TTL-compatible clock from 0.1MHz to 8MHz (MAX120), 0.1MHz to 5MHz
(MAX122)
Interrupt or Busy Output. Indicates converter status. If MODE is connected to VDD, configure
for an INT output. If MODE is open or connected to DGND, configure for a BUSY output. See
operational diagrams.
Detailed Description
ADC Operation
The MAX120/MAX122 use successive approximation and
input T/H circuitry to convert an analog signal to a series
of 12-bit digital-output codes. The control logic interfaces
easily to most µPs, requiring only a few passive components tor most applications. The T/H does not require an
external capacitor. Figure 3 shows the MAX120/MAX122
in the simplest operational configuration.
Analog Input Track/Hold
Figure 4 shows the equivalent input circuit, illustrating the
sampling architecture of the ADC’s analog comparator.
An internal buffer charges the hold capacitor to minimize
the required acquisition time between conversions. The
analog input appears as a 6kΩ resistor in parallel with a
10pF capacitor.
Figure 1. Load Circuits for Access Time
Between conversions, the buffer input is connected to AIN
through the input resistance. When a conversion starts,
the buffer input disconnects from AIN, thus sampling the
input. At the end of the conversion, the buffer input reconnects to AIN, and the hold capacitor once again charges
to the input voltage.
The T/H is in tracking mode whenever a conversion is
NOT in progress. Hold mode starts approximately 10ns
after a conversion is initiated. Variation in this delay from
one conversion to the next (aperture jitter) is typically
30ps. Figures 7 through 11 detail the T/H mode and interface timing for the various interface modes.
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Figure 2. Load Circuits for Bus-Relinquish Time
Maxim Integrated │ 5
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 3. MAX120/MAX122 in the Simplest Operational Mode
(Continuous Conversion)
Figure 4. Equivalent Input Circuit
Internal Reference
Digital Interlace
The MAX120/MAX122 -5.00V buried-zener reference
biases the internal DAC. The reference output is available
at the VREF pin and must be bypassed to the AGND pin
with a 0.1µF ceramic capacitor in parallel with a 22µF or
greater electrolytic capacitor. The electrolytic capacitor’s
equivalent series resistance (ESR) must be 100mΩ or
less to properly compensate the reference output buffer.
Sanyo’s organic semiconductor works well.
Sanyo Video Components (USA)
Phone: (619) 661-6835
FAX: (619) 661-1055
Sanyo Electric Company, LTD. (Japan)
Phone: 0720-70-1005
FAX: 0720-70-1174
Sanyo Fisher Vertriebs GmbH (Germany)
Phone: 06102-27041, ext. 44 FAX: 06102-27045
Proper bypassing minimizes reference noise and maintains a low impedance at high frequencies. The internal
reference output buffer can sink up to a 5mA external load.
An external reference voltage can be used to overdrive
the MAX120/MAX122’s internal reference if it ranges from
-5.05V to -5.10V and is capable of sinking a minimum
of 5mA. The external VREF bypass capacitors are still
required.
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External Clock
The MAX120/MAX122 require a TTL-compatible clock
for proper operation. The MAX120 accepts clocks in
the 0.1MHz to 8MHz frequency range when operating
in modes 1–4 (see the Operating Modes section). The
maximum clock frequency is limited to 6MHz when operating in mode 5. The MAX122 requires a 0.1MHz to 5MHz
clock for operation in all five modes. The minimum clock
frequency for both the MAX120 and MAX122 is limited to
0.1MHz, due to the T/H’s droop rate.
Clock and Control Synchronization
The clock and convert start inputs (CONVST or RD and
CS, see the Operating Modes section) are not synchronized, the conversion time can vary from 13 to 14 clock
cycles. The successive approximation register (SAR)
always changes state on the CLKIN input’s rising edge.
To ensure a fixed conversion time, see Figure 5 and the
following guidelines.
For a conversion time of 13 clock cycles, the convert start
input(s) should go low at least 50ns before CLKIN’s next
rising edge. For a conversion time of 14 clock cycles,
the convert start input(s) should go low within 10ns of
CLKIN’s next rising edge. If the convert start input(s) go
low from 10ns to 50ns before CLKIN’s next rising edge,
the number of clock cycles required is undefined and can
be either 13 or 14. For best analog performance, synchronize the convert start inputs with the clock input.
Maxim Integrated │ 6
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 5. Clock and Control Synchronization
Figure 7. Full-Control Mode (Mode 1)
or for µP-based systems where the ADC and the µP are
linked through first-in, first-out (FIFO) buffers or direct
memory access (DMA) ports. Slow-memory mode (mode
3) is intended for µPs that can be forced into a wait state
during the ADC’s conversion time. ROM mode (mode 4) is
for µPs that cannot be forced into a wait state.
Figure 6. Data-Access and Bus-Relinquish Timing
Output Data Format
The conversion result is output on a 12-bit data bus with
a 75ns data-access time. The output data format is twoscomplement. Three input control signals (CS, RD, and
CONVST), the INT/BUSY converter status output, and the
12 bits of output data can interface directly to a 16-bit data
bus. See Figure 6 for data-access timing.
Timing and Control
The MAX120/MAX122 have five operational modes as
outlined in Figures 7 to 11 and discussed in the Operating
Modes section.
Full-control mode (mode 1) provides maximum control to
the user for convert start and data-read operations.
Full-control mode is for µPs with or without wait-state
capability. Stand-alone mode (mode 2) and continuousconversion mode (mode 5) are for systems without µPs,
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In all five operating modes, the start of a conversion is
controlled by one of three digital inputs: CONVST, RD, or
CS. Figure 12 shows the logic equivalent for the conversion circuitry. In any operating mode, CONVST must be
low for a conversion to occur. Once the conversion is in
progress, it cannot be restarted.
Read operations are controlled by RD and CS. Both of
these digital inputs must be low to read output data. The
INT/BUSY output indicates the converter’s status and
determines when the data from the most recent conversion is available. The MODE input configures the INT/
BUSY output as follows:
If MODE = VDD, INT/BUSY functions as an
INTERRUPT output. In this configuration, INT/BUSY
goes low when the conversion is complete and returns
high after the conversion data has been read.
If MODE is left open or tied to DGND, INT/BUSY
functions as a BUSY output. In this case, INT/BUSY
goes low at the start of a conversion and remains low
until the conversion is complete and the data is available at D0–D11.
Maxim Integrated │ 7
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 8. Stand-Alone Mode (Mode 2)
Figure 9. Slow-Memory Mode (Mode 3)
Initialization After Power-Up
When the conversion is complete, the data can be read
without initiating a new conversion by pulling RD and CS
low and leaving CONVST high. To start a new conversion
without reading data, RD and CS should remain high
while CONVST is driven low. To simultaneous read data
and initiate a new conversion, CONVST, RD, and CS
should all be pulled low. Note: Allow at least 350ns for
T/H acquisition time between the end of one conversion
and the beginning of the next.
On power-up, the first MAX120/MAX122 conversion is
valid if the following conditions are met:
1) Allow 14 clock cycles for the internal T/H to enter the
track mode, plus a minimum of 350ns in the track
mode for the data-acquisition time.
2) Make sure the reference voltage has settled. Allow
0.5ms for each 1µF of reference bypass capacitance
(11ms for a 22µF capacitor).
Operating Modes
Mode 1: (Full-Control Mode)
Figure 7 shows the timing diagram for full-control mode
(mode 1). In this mode, the µP controls the conversion
start and data-read operations independently.
A falling edge on CONVST places the T/H into hold mode
and starts a conversion in the SAR. The conversion is
complete in 13 or 14 clock cycles as discussed in the
Clock and Control Synchronization section. A change in
the INT/BUSY output state signals the end of a conversion as follows:
If MODE = VDD, the end of conversion is signaled by the
INT/BUSY output falling edge.
If MODE = OPEN or DGND, the INT/BUSY output goes
low while the conversion is in progress and returns high
when the conversion is complete.
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Mode 2: Stand-Alone Operation
(MODE= OPEN, RD = CS = DGND)
For systems that do not use or require full-bus interfacing, the MAX120/MAX122 can be operated in stand-alone
mode directly linked to memory through DMA ports or a
FIFO buffer. In stand-alone mode, a conversion is initiated by a falling edge on CONVST. The data outputs are
always enabled; data changes at the end of a conversion
as indicated by a rising edge on INT/BUSY. See Figure 8
for stand-alone mode timing.
Mode 3: Slow-Memory Mode
(CONVST = GND, MODE= OPEN)
Taking RD and CS lo laces the T/H into hold mode and
starts a conversion. INT/BUSY remains low while the
conversion is in progress and can be used as a wait input
to the µP. Data from the previous conversion appears on
the data bus until the conversion end is indicated by INT/
BUSY. See Figure 9 for slow-memory mode timing.
Maxim Integrated │ 8
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 12. Conversion-Control Logic
Figure 10. ROM Mode (Mode 4)
continuously at the rate of one conversion for every 14
clock cycles, which includes 2 clock cycles for the T/H
acquisition time. To satisfy the 350ns minimum acquisition time requirement within 2 clock cycles, the MAX120’s
maximum clock frequency is 6MHz when operating in
mode 5.
The data outputs are always enabled and “new” disappears on the output bus at the end of a conversion as
indicated by the INT/BUSY output rising edge. The MODE
input should be hard-wired to GND. Pulling CS, RD,
or CONVST high stops conversions. See Figure 11 for
continuous-conversion mode timing.
Applications Information
Using FIFO Buffers
Figure 11. Continuous-Conversion Mode (Mode 5)
Mode 4: ROM Mode
(MODE = OPEN, CONVST = GND)
In ROM mode, the MAX120/MAX122 behave like a fast
access memory location avoid placing the µP into a wait
state. Pulling RD and CS low places the T/H in hold mode,
starts a conversion, and reads data from the previous
conversion. Data from the first read in a sequence is often
disregarded when this interface mode is used. A second
read operation accesses the first conversion’s result and
also starts a new conversion. The time between successive read operations must be longer than the sum of the
T/H acquisition time and the MAX120/MAX122 conversion time. See Figure 10 for ROM-mode timing.
Mode 5: Continuous-Conversion Mode
(CONVST = RD = CS = MODE = GND)
For systems that do not use or require full-bus interfacing,
the MAX120/MAX122 can operate in continuous-conversion mode, directly linked to memory through DMA ports
or a FIFO buffer. In this mode, conversions are performed
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Using FIFO memory to buffer blocks of data from the
MAX120 reduces µP interrupt overhead time by enabling
the µP to process data while the MAX120, unassisted,
writes conversion results to the FIFO. To retrieve a block
of data, the µP reads from the FIFO via a read-interrupt
cycle. Read and write operations for the FIFO are completely asynchronous. Figure 13 shows the MAX120
operating in continuous-conversion mode (mode 5),writing data directly into the two IDT7200 256 x 9 FIFO buffers at the rate of 428ksps. The µP is interrupted to read
the accumulated data by the FIFO’s half-full (HF) flag
approximately three times per millisecond. For operation
at 500ksps, use an 8MHz clock, and pulse CONVST at
500kHz. The full flag (FF) indicates that the FIFO is full.
If this flag is ignored, data may be lost. If necessary, conversions can be inhibited by pulling CS, RD, or CONVST
high. The FIFO’s read cycle times are as fast as 15ns,
satisfying most system speed requirements. The RESET
input resets all data in the FIFO to zero.
For synchronous operation, the CONVST pin may be
used to initiate conversions, as described in the Operating
Modes section (Mode 2: Stand-Alone Operation).
Maxim Integrated │ 9
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 13. Using MAX120 with FIFO Memory
Digital-Bus Noise
If the ADC’s data bus is active during a conversion,
coupling from the data pins to the ADC comparator can
cause errors. Using slow-memory mode (mode 3) avoids
this problem by placing the µP in a wait state during the
conversion. If the data bus is active during the conversion
in either mode 1 or 4, use three-state drivers to isolate the
bus from the ADC.
In ROM mode (mode 4), considerable digital noise is
generated in the ADC when RD or CS go high, disabling
the output buffers after a conversion is started. This noise
can cause errors if it occurs at the same instant the SAR
latches a comparator decision. To avoid this problem, RD
and CS should be active for less than 1 clock cycle. If
this is not possible, RD or CS should go high coinciding
with CLKIN’s falling edge, since the comparator output is
always latched at CLKIN’s rising edge
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Layout, Grounding, and Bypassing
For best system performance, use PCBs with separate
analog and digital ground planes. Wirewrap boards are
not recommended. The two ground planes should be tied
together at the low-impedance power-supply source, as
shown in Figure 14.
The board layout should ensure that digital and analog
signal lines are kept separate from each other as much as
possible. Do not run analog and digital (especially clock)
lines parallel to one another.
The ADC’s high-speed comparator is sensitive to high
frequency noise in the VDD and VSS power supplies.
Bypass these supplies to the analog ground plane with
0.1µF and 10µF bypass capacitors. Minimize capacitor
lead lengths for best noise rejection. If the +5V power
supply is very noisy, connect a 5Ω resistor, as shown in
Figure 14. Figure 15 shows the negative power-supply
(VSS) rejection vs. frequency. Figure 16 shows the positive power-supply (VDD) rejection vs. frequency, with and
without the optional 5Ω resistor.
Maxim Integrated │ 10
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 16. VDD Power-Supply Rejection vs. Frequency
Figure 14. Power-Supply Grounding
To adjust bipolar offset with Figure 19’s circuit, apply +1/2
LSB (0.61mV) to the noninverting amplifier input and
adjust R4 for output-code flicker between 0000 and 0000
0000 0001. For full scale, apply FS - the output code flickers between 0111 1111 1110 and 0111 1111 1111. There
may be some interaction between these adjustments. The
MAX120/MAX122 transfer function used in conjunction
with Figure 19’s circuit is the same as Figure 17, except
the full-scale range is reduced to 2.5V.
To adjust bipolar offset with Figure 20’s circuit, apply
-1/2 LSB (-1.22mV) at VIN and adjust R5 for output-code
flicker between 0000 0000 0000 and 0000 0000 0001. For
gain adjustment, apply -FS + ½ LSB (-4.9951V) at VIN
and adjust R1 so the output code flickers between 0111
1111 1110 and 0111 1111 1111. As with Figure 20’s circuit,
the offset and gain adjustments may interact. Figure 21
plots the transfer function for Figure 20’s circuit.
Figure 15. VSS Power-Supply Rejection vs. Frequency
Gain and Offset Adjustment
Figure 17 plots the bipolar input/output transfer function for the MAX120/MAX122. Code transitions occur
halfway between successive integer LSB values. Output
coding is two’s-complement binary with 1 LSB = 2.44mV
(10V/4096).
In applications where gain (full-scale range) adjustment
is required, Figure 18’s circuit can be used. If both offset
and gain (full-scale range) need adjustment, either of the
circuits in Figures 19 and 20 can be used. Offset should
be adjusted before gain for either of these circuits.
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Dynamic Performance
High-speed sampling capability and 500ksps throughput
(333ksps for the MAX122) make the MAX120/MAX122
ideal for wideband-signal processing. To support these
and other related applications, fast fourier transform (FFT)
test techniques are used to guarantee the ADC’s dynamic
frequency response, distortion, and noise at the rated
throughput. Specifically, this involves applying a lowdistortion sine wave to the ADC input and recording the
digital conversion results for a specified time. The data is
then analyzed using an FFT algorithm, which determines
its spectral content.
Maxim Integrated │ 11
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 17. Bipolar Transfer Function
Figure 19. Offset and Gain Adjustment (Noninverting)
Figure 18. Trim Circuit for Gain Only
Figure 19. Offset and Gain Adjustment (Noninverting)
ADCs have traditionally been evaluated by specifications
such as zero and full-scale error, integral nonlinearity
(INL), and differential nonlinearity (DNL). Such parame
ters are widely accepted for specifying performance with
DC and slowly varying signals, but are less useful in
signal processing applications where the ADC’s impact
on the system transfer function is the main concern. The
significance of various DC errors does not translate well
to the dynamic case, so different tests are required.
The theoretical minimum ADC noise is caused by quantization error and is a direct result of the ADC’s resolution:
SNR = (6.02N + 1.76)dB, where N is the number of bits
of resolution. A perfect 12-bit ADC can, therefore, do no
better than 74dB. An FFT plot shows the output level in
various spectral bands. Figure 22 shows the result of
sampling a pure 100kHz sinusoid at a 500ksps rate with
the MAX120.
Signal-to-Noise Ratio and
Effective Number of Bits
The signal-to-noise plus distortion ratio (SINAD) is the
ratio of the fundamental input frequency’s RMS amplitude
to the RMS amplitude of all other ADC output signals. The
output band is limited to frequencies above DC and below
one-half the ADC sample rate.
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By transposing the equation that converts resolution to
SNR, we can, from the measured SINAD, determine the
effective resolution (or effective number of bits) the ADC
provides: N = (SINAD - 1.76)/6.02. Figure 22 shows the
effective number of bits as a function of the input frequency for the MAX120. The MAX122 performs similarly.
Maxim Integrated │ 12
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 21. Inverting Bipolar Transfer Function
Figure 23. Effective Bits vs. Input Frequency
where V1 is the fundamental RMS amplitude, and V2 to
VN are the amplitudes of the 2nd through Nth harmonics.
The THD specification in the Electrical Characteristics
table includes the 2nd through 5th harmonics.
lntermodulation Distortion
If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearities
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency
Figure 22. MAX120 FFT Plot
Total Harmonic Distortion
If a pure sine wave is sampled by an ADC at greater than
the Nyquist frequency, the nonlinearities in the ADC’s
transfer function create harmonics of the input frequency
in the sampled output data.
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics (in the frequency band above DC
and below one-half the sample rate, but not including the
DC component) to the RMS amplitude of the fundamental
frequency. This is expressed as follows:
THD = 20log
If two pure sine waves of frequency fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
THD includes those distortion products with m or n equal
to zero. lntermodulation distortion consists of all distortion products for which neither m nor n equal zero. For
example, the 2nd-order IMD terms include (fa + fb) and
(fa - fb) while the 3rd-order IMD terms include (2fa + fb),
(2fa - fb) , (fa + 2fb), and (fa - 2fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd-order IMD products can be
expressed by the following formula:
amplitude at (fa ± fb)
IMD (fa ± fb) =
20log
amplitude at fa
V 2 2 + V3 2 + V 4 2 ... + VN 2
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V1
Maxim Integrated │ 13
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Spurious-Free Dynamic Range
Spurious-free dynamic range is the ratio of the fundamental RMS amplitude to the amplitude of the next largest
spectral component (in the frequency band above DC and
below one-half the sample rate). Usually the next largest
spectral component occurs at some harmonic of the input
frequency. However, if the ADC is exceptionally linear, it
may occur only at a random peak in the ADC’s noise floor.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
Ordering Information (continued)
TEMP RANGE
PINPACKAGE
-40°C to +85°C
24 SSOP
±1
MAX122ACNG+
0°C to +70°C
24 PDIP
±3/4
MAX122BCNG+
0°C to +70°C
24 PDIP
MAX122ACWG+
0°C to +70°C
24 Wide SO
MAX122BCWG+
0°C to +70°C
24 Wide SO
MAX122ACAG+
0°C to +70°C
24 SSOP
±3/4
MAX122BCAG+
0°C to +70°C
24 SSOP
±1
MAX122AENG+
-40°C to +85°C
24 PDIP
±3/4
MAX122BENG+
-40°C to +85°C
24 PDIP
±1
MAX122AEWG+
-40°C to +85°C
24 Wide SO
±3/4
MAX122BEWG+
-40°C to +85°C
24 Wide SO
±1
MAX122AEAG+
-40°C to +85°C
24 SSOP
±3/4
MAX122BEAG+
-40°C to +85°C
24 SSOP
±1
MAX122BMRG-
-55°C to +125°C 24 CERDIP
PART
MAX120EAG+
INL
(LSB)
±1
±3/4
±1
±1
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 CDIP
R24-4
21-0045
—
+Denotes a lead(Pb)-free/RoHS-compliant package.
24 PDIP
N24+3
21-0043
—
†MAX120 EV kit can be used to evaluate the MAX122; when
24 SO
W24+2
21-0042
90-0182
24 SSOP
A24+2
21-0056
90-0110
www.maximintegrated.com
MAX120EVKIT-DIP†
0°C to +70°C
PDIP – Through Hole
ordering the EV kit, ask for a free sample of the MAX122.
-Denotes a package containing lead(Pb).
Maxim Integrated │ 14
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
9/92
Initial release
1
3/12
Removed PDIP, CERDIP packages from Ordering Information. Updated style
throughout data sheet.
DESCRIPTION
—
1–16
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2012 Maxim Integrated Products, Inc. │ 15