MAX1243BESA

MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 __________________General Description ________________________________Features The MAX1242/MAX1243 are low-power, 10-bit analogto-digital converters (ADCs) available in 8-pin packages. They operate with a single +2.7V to +5.25V supply and feature a 7.5µs successive-approximation ADC, a fast track/hold (1.5µs), an on-chip clock, and a high-speed, 3-wire serial interface. Power consumption is only 3mW (V DD = 3V) at the 73ksps maximum sampling speed. A 2µA shutdown mode reduces power at slower throughput rates. The MAX1242 has an internal 2.5V reference, while the MAX1243 requires an external reference. The MAX1243 accepts signals from 0V to VREF, and the reference input range includes the positive supply rail. An external clock accesses data from the 3-wire interface, which connects directly to standard microcontroller I/O ports. The interface is compatible with SPI, QSPI™, and MICROWIRE®. Excellent AC characteristics and very low power combined with ease of use and small package size make these converters ideal for remote-sensor and dataacquisition applications, or for other circuits with demanding power consumption and space requirements. The MAX1242/MAX1243 are available in 8-pin PDIP and SO packages. o +2.7V to +5.25V Single-Supply Operation Applications Portable Data Logging Process Control Monitoring Test Equipment Temperature Measurement o 10-Bit Resolution o Internal 2.5V Reference (MAX1242) o Small Footprint: 8-Pin DIP and SO Packages o Low Power: 3.7mW (73ksps, MAX1242) 3mW (73ksps, MAX1243) 66µW (1ksps, MAX1243) 5µW (Power-Down Mode) o Internal Track/Hold o SPI/QSPI™/MICROWIRE® 3-Wire Serial Interface o Pin-Compatible 12-Bit Upgrades: MAX1240/MAX1241 _________________Ordering Information PART TEMP PIN- INL RANGE PACKAGE (LSB) MAX1242ACPA+ 0°C to +70°C 8 PDIP ±1/2 MAX1242BCPA+ 0°C to +70°C 8 PDIP ±1 MAX1242ACSA+ 0°C to +70°C 8 SO ±1/2 MAX1242BCSA+ 0°C to +70°C 8 SO ±1 MAX1242AEPA+ -40°C to +85°C 8 PDIP ±1/2 Ordering Information continued at end of data sheet. Note: Order the MAX1242A in place of the MAX1242C. Order the MAX1242B in place of the MAX1242D. +Denotes a lead(Pb)-free/RoHS-compliant package. Isolated Data Acquisition ________________Functional Diagram Pin Configuration VDD 1 CS SCLK TOP VIEW SHDN 7 8 3 CONTROL LOGIC INT CLOCK + VDD 1 AIN 2 SHDN 3 MAX1242 MAX1243 REF 4 PDIP/SO 8 SCLK 7 CS 6 DOUT 5 GND AIN 2 T/H 4 6 DOUT 10-BIT SAR 2.5V REFERENCE REF OUTPUT SHIFT REGISTER MAX1242 MAX1243 MAX1242 ONLY 5 GND QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-1156; Rev 3; 1/12 MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 ABSOLUTE MAXIMUM RATINGS VDD to GND .............................................................-0.3V to +6V AIN to GND................................................-0.3V to (VDD + 0.3V) REF to GND ...............................................-0.3V to (VDD + 0.3V) Digital Inputs to GND...............................................-0.3V to +6V DOUT to GND............................................-0.3V to (VDD + 0.3V) DOUT Current ..................................................................±25mA Continuous Power Dissipation (TA = +70°C) PDIP (derate 9.09mW/°C above +70°C).....................727mW SO (derate 5.88mW/°C above +70°C)........................471mW Operating Temperature Ranges MAX1242/MAX1243_C_A ..................................0°C to +70°C MAX1242/MAX1243_E_ A ..............................-40°C to +85°C Storage Temperature Range............................-60°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Soldering Temperature (reflow) ......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.25V; 73ksps; fSCLK = 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external reference; VREF = 2.5V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note1) (Note 1) Resolution 10 Relative Accuracy (Note 2) Differential Nonlinearity DNL Offset Error Gain Error (Note 3) Bits MAX124_A ±0.5 MAX124_B ±1.0 No missing codes over temperature ±1 MAX124_A ±1 MAX124_B ±2 MAX124_A ±1 MAX124_B ±2 Gain Temperature Coefficient LSB LSB LSB LSB ±0.25 ppm/°C 66 dB -70 dB 70 dB 2.25 MHz 1.0 MHz DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5V 2.5Vp-p, 73ksps, ffSCLK = 2.1MHz) P-P, 73ksps, SCLK =2.1MHz) Signal-to-Noise Plus Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Small-Signal Bandwidth Up to the 5th harmonic -3dB rolloff Full-Power Bandwidth CONVERSION RATE Conversion Time tCONV Track/Hold Acquisition Time tACQ Throughput Rate Aperture Delay 5.5 7.5 fSCLK = 2.1MHz tAP Figure 9 Aperture Jitter µs 1.5 µs 73 ksps 30 ns 3.6V 2.0 3.0 VHYST VIN = 0V or VDD SCLK, CS Input Capacitance CIN (Note 6) SHDN Input High Voltage VSH SHDN Input Low Voltage VSL ±0.01 VSM SHDN Voltage, Open VFLT SHDN Max Allowed Leakage, Mid Input V ±1 µA 15 pF V VDD - 0.4 V VSHDN = 0V or VDD SHDN Input Mid Voltage 0.8 0.2 IIN SHDN Input Current V 1.1 SHDN = open 0.4 V ±4.0 µA VDD - 1.1 VDD / 2 SHDN = open V V ±100 nA 0.4 0.8 V DIGITAL OUTPUT: DOUT Output Voltage Low VOL Output Voltage High Three-State Leakage Current VOH IL Three-State Output Capacitance COUT ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA VDD - 0.5 CS = VDD ±0.01 CS = VDD (Note 6) ±10 V µA 15 pF 5.25 V POWER REQUIREMENTS Supply Voltage VDD 2.7 Operating mode (MAX1242) Operating mode (MAX1242) Supply Current Power-Supply Rejection (Note 7) Maxim Integrated IDD PSR VDD = 3.6V VDD = 5.25V VDD = 3.6V Operating mode (MAX1243) VDD = 5.25V VDD = 3.6V Power-down VDD = 5.25V VDD = VDD(min) to VDD(max), full-scale input 1.4 1.8 0.9 1.6 1.9 3.5 ±0.3 2.0 3.0 1.5 2.5 10 15 mA µA mV 3 MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 TIMING CHARACTERISTICS (VDD = +2.7V to +5.25V, circuit of Figure 9, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL MIN CONDITIONS tACQ CS = VDD (Note 8) SCLK Fall to Output Data Valid tDO Figure 1, CLOAD = 50pF CS Fall to Output Enable tDV CS Rise to Output Disable tTR Acquisition Time TYP MAX 1.5 UNITS µs 20 200 ns Figure 1, CLOAD = 50pF 240 ns Figure 2, CLOAD = 50pF 240 ns 2.1 MHz MAX124_ _C/E SCLK Clock Frequency fSCLK 0 SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low tCL 200 ns SCLK Low to CS Fall Setup Time tCS0 50 ns DOUT Rise to SCLK Rise (Note 6) tSTR 0 ns CS Pulse Width tCS 240 ns Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: Offset nulled. Note 4: Sample tested to 0.1% AQL. Note 5: External load should not change during conversion for specified accuracy. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Measured as [VFS (VDD(min)) - VFS (VDD(max))]. Note 8: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. +2.7V 6kΩ DOUT DOUT 6kΩ CLOAD = 50pF CLOAD = 50pF DGND DGND a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL Figure 1. Load Circuits for DOUT Enable Time +2.7V 6kΩ DOUT DOUT 6kΩ CLOAD = 50pF CLOAD = 50pF DGND DGND a) VOH to High-Z b) VOLto High-Z Figure 2. Load Circuits for DOUT Disable Time 4 Maxim Integrated MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 __________________________________________Typical Operating Characteristics (VDD = +3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.50 CLOAD = 50pF MAX1242 1.25 CLOAD = 50pF MAX1243 1.00 CLOAD = 20pF 0.75 RL = ∞ CODE = 1010101000 0.50 2.25 2.75 3.25 3.75 4.25 4.75 2.5 2.0 1.5 1.0 0.5 0 2.25 5.25 2.75 3.25 3.75 4.25 4.75 2.5000 2.4995 2.4990 2.75 3.25 3.75 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 0.25 0.20 INL (LSB) 1.0 0.15 MAX1242 0.10 MAX1243 0.9 0.05 RLOAD = ∞ CODE = 1010101000 -20 MAX1242 MAX1243 0 20 60 100 140 2.500 VDD = 3.6V VDD = 5V 2.499 VDD = 2.7V 2.498 2.497 2.496 2.495 2.494 2.25 2.75 3.25 3.75 4.25 4.75 -60 -40 -20 0 5.25 20 40 60 80 100 120 140 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. CODE 0.30 MAX1242/43-07 0.30 0.25 VDD = 2.7V 0.15 0.25 0.10 0.20 0.15 0.15 0.10 MAX1242 0.10 0.05 INL (LSB) INL (LSB) 0.20 MAX1242/43-09 -60 2.501 INTERNAL REFERENCE VOLTAGE (V) MAX1242/43-07 0.30 MAX1242/43-04 MAX1242 1.1 0.8 2.5005 2.4985 2.25 5.25 MAX1242/43-03 MAX1242/43-02 3.0 MAX1242 2.5010 SUPPLY VOLTAGE (V) 1.2 SUPPLY CURRENT (mA) MAX1242/MAX1243 SUPPLY VOLTAGE (V) 1.3 INL (LSB) 3.5 MAX1242/43-06 CLOAD = 20pF 2.5015 MAX1242/43-08 SUPPLY CURRENT (mA) 1.75 4.0 SHUTDOWN SUPPLY CURRENT (μA) MAX1242/43-01 2.00 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE 0 -0.05 MAX1242 0.05 0.05 -0.10 MAX1243 MAX1243 0 0 2.25 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) Maxim Integrated 4.75 5.25 -0.15 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0 256 512 CODE 768 1024 5 MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 ______________________________________________________________Pin Description PIN NAME 1 VDD Positive Supply Voltage: +2.7V to +5.25V FUNCTION 2 AIN Sampling Analog Input, 0V to VREF range 3 SHDN Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1242/MAX1243 down to 15µA (max) supply current. Both MAX1242 and MAX1243 are fully operational with either SHDN high or open. For the MAX1242, pulling SHDN high enables the internal reference, and letting SHDN open disables the internal reference and allows for the use of an external reference. 4 REF Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1242; bypass with a 4.7µF capacitor. External reference voltage input for MAX1243, or for MAX1242 with the internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference. 5 GND Analog and Digital Ground 6 DOUT Serial-Data Output. Data changes state at SCLK’s falling edge. High impedance when CS is high. 7 CS Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high impedance. 8 SCLK Serial-Clock Input. SCLK clocks data out at rates up to 2.1MHz. _______________Detailed Description Converter Operation The MAX1242/MAX1243 use an input track/hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 10-bit output. Figure 3 shows the MAX1242/MAX1243 in their simplest configuration. The MAX1242/MAX1243 convert input signals in the 0V to VREF range in 9µs, including T/H acquisition time. The MAX1242’s internal reference is trimmed to 2.5V, while the MAX1243 requires an external reference. Both devices accept external reference voltages from 1.0V to VDD. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (μPs). The MAX1242/MAX1243 have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current below 10µA (VDD ≤ 3.6V), while pulling SHDN high or leaving it open puts the devices into operational mode. A conversion is initiated by pulling CS low. The conversion result is available at DOUT in unipolar serial format. The serial-data stream consists of a high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first). Analog Input Figure 4 illustrates the sampling architecture of the analog-to-digital converter’s (ADC’s) comparator. The fullscale input voltage is set by the voltage at REF. 6 Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H switch opens and maintains a constant input to the ADC’s SAR section. During acquisition, the analog input AIN charges capacitor CHOLD. Bringing CS low ends the acquisition interval. At this instant, the T/H switches the input side of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO at the comparator’s input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10bit resolution. This action is equivalent to transferring a charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion’s end, the input side of C HOLD switches back to AIN, and C HOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. Acquisition time is calculated by: tACQ = 7(RS + RIN) x 16pF Maxim Integrated MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 +2.7V to +5.25V CAPACITIVE DAC 4.7μF 0.1μF REF 1 2 ANALOG INPUT 0V TO VREF VDD SCLK AIN CS 8 7 MAX1242 MAX1243 SHUTDOWN INPUT 3 REFERENCE INPUT 4 SHDN REF AIN SERIAL INTERFACE HOLD DOUT GND ZERO - + 16pF CSWITCH 6 COMPARATOR TRACK INPUT CHOLD 9kΩ RIN HOLD TRACK 5 C* MAX1243 AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. GND *4.7μF, MAX1242 0.1μF, MAX1243 Figure 3. Operational Diagram where RIN = 9kΩ, RS = the input signal’s source impedance, and tACQ is never less than 1.5µs. Source impedances below 4kΩ do not significantly affect the ADC’s AC performance. Higher source impedances can be used if a 0.01µF capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s input signal bandwidth. Input Bandwidth The ADC’s input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and GND, allow the input to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA. Maxim Integrated Figure 4. Equivalent Input Circuit Internal Reference (MAX1242) The MAX1242 has an on-chip voltage reference trimmed to 2.5V. The internal reference output is connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to 400µA. Bypass REF with a 4.7µF capacitor. Larger capacitors increase wake-up time when exiting shutdown (see Using SHDN to Reduce Supply Current). The internal reference is enabled by pulling the SHDN pin high. Letting SHDN open disables the internal reference, which allows the use of an external reference, as described in the External Reference section. External Reference The MAX1242/MAX1243 operate with an external reference at the REF pin. To use the MAX1242 with an external reference, disable the internal reference by letting SHDN open. Stay within the voltage range 1.0V to VDD to achieve specified accuracy. The minimum input impedance is 18kΩ for DC currents. During conversion, the external reference must be able to deliver up to 250µA of DC load current and have an output impedance of 10Ω or less. The recommended minimum value for the bypass capacitor is 0.1µF. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor. 7 MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 Using SHDN to Reduce Supply Current Serial Interface Initialization after Power-Up and Starting a Conversion When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7µF reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the internal reset time is 10µs after the power supplies have stabilized. No conversions should be performed during these times. To start a conversion, pull CS low. At CS’s falling edge, the T/H enters its hold mode and a conversion is initiated. After an internally timed conversion period, the end of conversion is signaled by DOUT pulling high. Data can then be shifted out serially with the external clock. Power consumption can be reduced significantly by shutting down the MAX1242/MAX1243 between conversions. Figure 6 shows a plot of average supply current vs. conversion rate. Because the MAX1243 uses an external reference voltage (assumed to be present continuously), it “wakes up” from shutdown more quickly, providing lower average supply currents. The wakeup time, tWAKE, is the time from SHDN deasserted to the time when a conversion may be initiated (Figure 5). For the MAX1242, this time depends on the time in shutdown (Figure 7) because the external 4.7µF reference bypass capacitor loses charge slowly during shutdown. The MAX1243’s wake-up time is largely dependent on the external reference’s power-up time. If the external reference is not shut down, the wake-up time is approximately 4µs. COMPLETE CONVERSION SEQUENCE CS tWAKE SHDN DOUT CONVERSION 0 CONVERSION 1 POWERED UP POWERED DOWN POWERED UP Figure 5. Shutdown Sequence MAX1243-fig06 1000 0.8 CODE = 0101010100 MAX1242 VDD = 5V 100 MAX1242 VDD = 3V 10 1 1 10 100 1k 10k 100k CONVERSIONS/SEC Figure 6. Average Supply Current vs. Conversion Rate 8 0.6 0.4 0.2 MAX1243 VDD = 3V 0.1 1.0 POWER-UP DELAY (ms) SUPPLY CURRENT (μA) VDD = VREF RLOAD = ∞, CLOAD = 50pF MAX1242/43-07 10,000 0.0 0.001 0.01 0.1 1 10 TIME IN SHUTDOWN (sec) Figure 7. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown Maxim Integrated MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243 CS 1 4 8 12 16 SCLK DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 EOC INTERFACE IDLE CONVERSION IN PROGRESS TRACK/HOLD TRACK STATE HOLD SUB BITS CLOCK OUT SERIAL DATA EOC TRAILING ZEROS IDLE TRACK 7.5μs (tCONV) HOLD 12.5 × 0.476μs = 5.95μs 0μs CYCLE TIME 0.24μs 0μs (tCS) TOTAL = 13.7μs Figure 8a. Interface Timing Sequence CS 1 4 8 SCLK DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 EOC INTERFACE IDLE CONVERSION IN PROGRESS TRACK/HOLD TRACK STATE HOLD 7.5μs (tCONV) CLOCK OUT SERIAL DATA EOC IDLE TRACK HOLD 0.24μs 10.5 × 0.476μs = 5μs 0μs CYCLE TIME (tCS) TOTAL = 12.74μs Figure 8b. Interface Timing Sequence—Minimum Cycle Time tCS CS … tCS0 SCLK tDO tDV tCONV … DOUT tAP INTERNAL T/H tCH … (TRACK/ACQUIRE) tCL B0 tTR S1 S0 tSTR (HOLD) … (TRACK/ACQUIRE) Figure 9. Detailed Serial-Interface Timing Maxim Integrated 9 MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 External Clock The actual conversion does not require the external clock. This allows the conversion result to be read back at the µP’s convenience at any clock rate up to 2.1MHz. The clock duty cycle is unrestricted if each clock phase is at least 200ns. Do not run the clock while a conversion is in progress. OUTPUT CODE FULL-SCALE TRANSITION 11…111 11…110 11…101 Timing and Control Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface operation. A CS falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic low. SCLK must be kept low during the conversion. An internal register stores the data when the conversion is in progress. EOC is signaled by DOUT going high. DOUT’s rising edge can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on SCLK’s falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 10 data bits, two sub-bits, and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros at DOUT and have no effect on converter operation. For minimum cycle time, use DOUT’s rising edge as the EOC signal and then clock out the data with 10.5 clock cycles at full speed (Figure 8b). Pull CS high after reading the conversion’s LSB. After the specified minimum time, tCS, pull CS low again to initiate the next conversion. FS = VREF - 1LSB 1LSB = VREF 1024 00…011 00…010 00…001 00…000 0 1 I/O CS SCK SCLK MISO DOUT +3V MAX1242 MAX1243 SS a) SPI CS CS SCK SCLK MISO DOUT +3V MAX1242 MAX1243 SS b) QSPI __________Applications Information I/O CS SK SCLK SI DOUT MAX1242 MAX1243 Connection to Standard Interfaces The MAX1242/MAX1243 serial interface is fully compatible with SPI, QSPI, and Microwire standard serial interfaces (Figure 11). FS FS - 3/2LSB Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF - 1LSB, Zero Scale (ZS) = GND Output Coding and Transfer Function The data output from the MAX1242/MAX1243 is binary. Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successive-integer LSB values. If VREF = 2.5V, then 1LSB = 2.44mV or 2.5V / 1024. 2 3 INPUT VOLTAGE (LSB) c) MICROWIRE Figure 11. Common Serial-Interface Connections to the MAX1242/MAX1243 10 Maxim Integrated MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 1ST BYTE READ 2ND BYTE READ SCLK CS tCONV HIGH-Z D9 DOUT D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 S1 S0 S1 S0 LSB EOC Figure 12. SPI/Microwire Serial-Interface Timing (CPOL = CPHA = 0) SCLK CS tCONV HIGH-Z DOUT D9 D8 D7 D6 MSB D5 D4 D3 D2 D1 D0 LSB EOC Figure 13. QSPI Serial-Interface Timing (CPOL = CPHA = 0) If a serial interface is available, set the CPU’s serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.1MHz. 1) Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2) Wait the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT rising edge to determine the end of conversion. 3) Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the DOUT conversion. DOUT output data transitions on SCLK’s falling edge and is available in MSB-first format. Observe the SCLK-to-DOUT valid timing characteristic. Data can be clocked into the µP on SCLK’s rising edge. 4) Pull CS high at or after the 11th falling clock edge. If CS remains low, the two sub-bits and trailing zeros are clocked out after the LSB. 5) With CS = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CS low. If a conversion is aborted by pulling CS high before the conversion’s end, wait the minimum acquisition time, tACQ, before starting a new conversion. Data can be output in two bytes or continuously, as shown in Figures 8a and 8b. The bytes contain the result of the conversion padded with one leading 1, two sub-bits, and trailing 0s if SCLK is still active with CS kept low. Maxim Integrated SPI and Microwire When using SPI or QSPI, set CPOL = 0 and CPHA = 0. Conversion begins with a CS falling edge. DOUT goes low, indicating a conversion is in progress. Wait until DOUT goes high or until the maximum specified 7.5µs conversion time elapses. Two consecutive 1-byte reads are required to get the full 10+2 bits from the ADC. DOUT output data transitions on SCLK’s falling edge and is clocked into the µP on SCLK’s rising edge. The first byte contains a leading 1, and seven bits of conversion result. The second byte contains the remaining three bits, two sub-bits, and three trailing zeros. See Figure 11 for connections and Figure 12 for timing. QSPI Set CPOL = CPHA = 0. Unlike SPI, which requires two 1-byte reads to acquire the 10 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1242/MAX1243 require 11 clock cycles from the µP to clock out the 10 bits of data. Additional clock cycles clock out the two sub-bits followed by trailing zeros (Figure 13). The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz. Layout and Grounding For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. 11 MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 Ordering Information (continued) PART TEMP PIN- INL RANGE PACKAGE (LSB) MAX1242BEPA+ -40°C to +85°C 8 PDIP MAX1242AESA+ -40°C to +85°C 8 SO ±1/2 MAX1242BESA+ -40°C to +85°C 8 SO ±1 MAX1243ACPA+ 0°C to +70°C 8 PDIP ±1/2 MAX1243BCPA+ 0°C to +70°C 8 PDIP ±1 MAX1243ACSA+ 0°C to +70°C 8 SO ±1/2 MAX1243BCSA+ 0°C to +70°C 8 SO ±1 MAX1243AEPA+ -40°C to +85°C 8 PDIP ±1/2 MAX1243BEPA+ -40°C to +85°C 8 PDIP ±1 ___________________Chip Information SUBSTRATE CONNECTED TO GND PROCESS: BiCMOS ±1 MAX1243AESA+ -40°C to +85°C 8 SO ±1/2 MAX1243BESA+ -40°C to +85°C 8 SO ±1 Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. LAND PATTERN NO. PACKAGE TYPE PACKAGE CODE OUTLINE NO. 8 PDIP P8+2 21-0043 — 8 SO S8+5 21-0041 90-0096 Note: Order the MAX1242A in place of the MAX1242C. Order the MAX1242B in place of the MAX1242D. +Denotes a lead(Pb)-free/RoHS-compliant package. 12 Maxim Integrated MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 Revision History REVISION NUMBER REVISION DATE 0 11/96 Initial release 2 6/98 Extended temperature parts available 3 1/12 Removed military grades and added stylistic changes. DESCRIPTION PAGES CHANGED — — 1–7, 12 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 13 © 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.