19-3659; Rev 1; 10/06
MAX12553/MAX12554/MAX12555
Evaluation Kits
The MAX12553/MAX12554/MAX12555 evaluation kits (EV
kits) are fully assembled and tested PCBs that contain all
the components necessary to evaluate the performance
of this family of 14-bit, analog-to-digital converters
(ADCs). These ADCs accept differential or single-ended
analog inputs, however, the EV kits allow for evaluation
with either type of signal from one single-ended analogsignal source. The digital outputs produced by the ADCs
are captured easily with a user-provided high-speed logic
analyzer or data-acquisition system. The EV kits operate
from a 1.8V and a 3.3V power supply and include circuitry that generates a low-jitter clock signal from an AC
signal provided by the user.
Features
95Msps Sampling Rate with the MAX12555
80Msps Sampling Rate with the MAX12554
65Msps Sampling Rate with the MAX12553
Low-Voltage and Low-Power Operation
Fully Differential or Single-Ended Signal-Input
Configuration
Differential or Single-Ended Clock Configuration
On-Board Clock-Shaping Circuit with Adjustable
Duty Cycle
Fully Assembled and Tested
Part Selection Table
Ordering Information
PART NUMBER
SPEED (Msps)
APPLICATION
PART
TEMP RANGE
IC PACKAGE
0°C to +70°C
40 Thin QFN-EP*
95
IF/Baseband
Sampling
MAX12555EVKIT+
MAX12555ETL+
MAX12554EVKIT+
0°C to +70°C
40 Thin QFN-EP*
0°C to +70°C
40 Thin QFN-EP*
80
IF/Baseband
Sampling
MAX12553EVKIT+
MAX12554ETL+
MAX12553ETL+
65
IF/Baseband
Sampling
+ Denotes a lead-free and RoHS-compliant EV kit.
*EP = Exposed paddle.
Component List
DESIGNATION
QTY
C1, C2, C7, C33
4
C3, C4, C6,
C8–C12, C17,
C21, C27, C34,
C43, C45
14
C5, C14, C16,
C18, C19, C20,
C38, C44, C49,
C50
0
Not installed, capacitors (0402)
8
C13, C15,
C22–C26, C42
C28
1
DESCRIPTION
DESIGNATION
QTY
DESCRIPTION
22µF ±20%, 10V tantalum
capacitors (B-case)
AVX TAJB226M010
C29, C40, C41,
C48, C51, C52
0
Not installed, capacitors (0603)
1.0µF ±10%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105K
KEMET C0402C105K9PAC
C30, C31, C32,
C35, C36, C37
6
2.2µF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J225M
Panasonic ECJ1VB0J225K
C39
1
4.7µF ±10%, 6.3V X5R ceramic
capacitor (0603)
TDK C1608X5R0J475K
Panasonic ECJ1VB0J475K
0.1µF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
KEMET C0402C104K8PAC
C46, C47
2
15pF ±5%, 50V C0G ceramic
capacitors (0402)
Murata GRM1555C1H150J
CLOCK4
0
Not installed, SMA vertical
connector (SMA)
10µF ±20%, 6.3V X5R ceramic
capacitor (0805)
TDK C2012X5R0J106M
KEMET C0805C106K9PAC
CLOCK, AINP,
AINN
3
SMA vertical PC mount
connectors (SMA)
Component List continued on next page.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
Evaluate: MAX12553/MAX12554/MAX12555
General Description
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Component List (continued)
DESIGNATION
QTY
DESCRIPTION
1
Dual Schottky diode (SOT23)
Central Semiconductor
CMPD6263S, lead free
(Top Mark: D96)
Vishay BAS70-04 (Top Mark: 74)
Diodes Inc. BAS70-04-7-F
(Top Mark: K74 or K7D)
D1
D2
0
Not installed, diode (SOT23)
J1
1
Dual-row, 2 x 20, 40-pin header
JU1, JU9, JU10
0
Not installed, 2-pin headers
JU2–JU8
7
3-pin headers
4
EMI filters
Murata NFM41PC204F1H3B
L1–L4
DESIGNATION
QTY
DESCRIPTION
T1, T2
2
1:1 RF transformers
Mini-Circuits ADT1-1WT
T3
1
4:1 RF transformer
Mini-Circuits ADT4-6WT
T4
0
Not installed, transformer
TP1–TP4
4
Miniature PC test points (red)
Keystone Electronics 5000
TP5, TP6
2
Miniature PC test points (black)
Keystone Electronics 5001
U1
1
See the EV Kit-Specific
Component List
U2
1
Low-voltage, 16-bit register
(48-pin TSSOP)
Texas Instruments
SN74AVC16374DGGR
U3
0
Not installed (SC70-5)
U4
1
TinyLogic UHS buffer (SC70-5)
Fairchild NC7SZ125P5
R1, R8, R11,
R15–R28, R31
0
Not installed, resistors (0603)
R2, R12, R13,
R14
0
Not installed, resistors (0402)
R3, R4
2
75Ω ±0.5% resistors (0603)
R5, R6
2
1.0kΩ ±5% resistors (0402)
R7, R9
2
100Ω ±1% resistors (0603)
U5
0
Not installed (8-pin SO)
R10
1
10kΩ potentiometer, 12-turn,
1/4in
U6
1
R29, R30
2
110Ω ±0.5% resistors (0603)
TinyLogic dual UHS inverter
(SC70-6)
Fairchild NC7WZ04P6
RA1–RA4
4
220Ω ±5% resistor arrays
Panasonic EXB-2HV-221J
—
7
Shunts (JU2–JU8)
—
1
MAX12553/MAX12554/
MAX12555EVKIT+ PCB
EV Kit-Specific Component List
EV KIT PART NUMBER
REFERENCE DESIGNATOR
MAX12555EVKIT+
MAX12554EVKIT+
MAX12553EVKIT+
DESCRIPTION
MAX12555ETL+ (40-pin, 6mm x 6mm x 0.8mm Thin QFN with EP)
U1
MAX12554ETL+ (40-pin, 6mm x 6mm x 0.8mm Thin QFN with EP)
MAX12553ETL+ (40-pin, 6mm x 6mm x 0.8mm Thin QFN with EP)
Component Suppliers
SUPPLIER
PHONE
WEBSITE
AVX Corp.
843-946-0238
www.avxcorp.com
Central Semiconductor
631-435-1110
www.centralsemi.com
Fairchild Semiconductor
888-522-5372
www.fairchildsemi.com
Murata Mfg. Co., Ltd.
770-436-1300
www.murata.com
Panasonic Corp.
714-373-7366
www.panasonic.com
TDK Corp.
847-803-6100
www.component.tdk.com
Note: Indicate that you are using the MAX12553, MAX12554, or MAX12555 when contacting these component suppliers.
2
_______________________________________________________________________________________
MAX12553/MAX12554/MAX12555
Evaluation Kits
Recommended Equipment
•
DC power supplies:
Digital (VLDUT) 1.8V, 100mA
Logic (VL) 1.8V, 100mA
Analog (VDUT) 3.3V, 250mA
•
Signal generator with low phase noise and low jitter
for clock input (e.g., HP/Agilent 8644B)
•
Signal generator for analog-signal input (e.g.,
HP/Agilent 8644B)
•
Logic analyzer or data-acquisition system (e.g.,
HP/Agilent 16500C)
•
Analog bandpass filters (e.g., K&L Microwave) for
input and clock signals
•
Digital voltmeter
Procedure
Each EV kit is a fully assembled and tested surfacemount PCB. Follow the steps below to verify board operation. Caution: Do not turn on power supplies or enable
signal generators until all connections are completed.
1) Verify that shunts are installed across pins 2-3 of
jumpers JU2 (ADC enabled) and JU3 (two’s-complement digital-output format).
2) Verify that shunts are installed across pins 1-2 of
jumpers JU4 (internal duty-cycle equalizer enabled)
and JU5 (differential clock configuration).
3) Verify that shunts are installed across pins 2-3 of
jumper JU6 and across pins 1-2 of jumpers JU7
and JU8.
4) Connect the clock generator output to the clock
bandpass filter input.
5) Connect the output of the clock bandpass filter to
the CLOCK SMA connector.
6) Connect the output of the analog-signal generator
to the input of the signal bandpass filter. Keep the
cable connection between the signal generators, filters, and EV kit board as short as possible for optimum dynamic performance.
7) Connect the output of the signal bandpass filter to
the AINP SMA connector. Note: It is recommended that a 3dB or 6dB attenuation pad be used to
reduce reflections and distortion from the bandpass filter.
8) Connect the logic analyzer to the square pin header
(J1). See the Digital Output section for bit locations
and J1 header designations. The system clock is
available on pin 3 of J1.
9) Connect a 3.3V, 250mA power supply to VDUT.
Connect the ground terminal of this supply to the
corresponding GND pad.
10) Connect a 1.8V, 100mA power supply to VL.
Connect the ground terminal of this supply to the
GND pad.
11) Connect a 1.8V, 100mA power supply to VLDUT.
Connect the ground terminal of this supply to the
GND pad.
12) Turn on the 3.3V power supply.
13) Turn on the 1.8V power supplies.
14) Enable the signal generators.
15) Set the clock-signal generator to the desired clock
frequency. See the Part Selection Table for appropriate frequency settings for each EV kit. The amplitude
of the generator should be sufficient to produce a
16dBm signal at the SMA input of the EV kits.
16) Set the analog input-signal generators for an output
amplitude of less than or equal to 2VP-P and to the
desired test frequency.
17) Verify that the two signal generators are synchronized to each other. Adjust the output power level
of the signal generators to overcome cable, bandpass filter, and attenuation pad losses at the input.
18) Enable the logic analyzer.
19) Collect data using the logic analyzer.
Detailed Description
Each EV kit is a fully assembled and tested PCB that
contains all the components necessary to evaluate the
performance of the MAX12553, MAX12554, or MAX12555
IC. Data generated by the EV kits are captured on a
single 14-bit parallel bus. The EV kits accept differential
or single-ended analog inputs and single-ended clock
signals. With the proper board configuration, the ADC is
evaluated with both types of signals by supplying only
one single-ended analog signal to the EV kit.
The EV kits are designed as four-layer PCBs to optimize the performance of this family of ADCs. For simple
operation, the EV kits require 3.3V and 1.8V power
supplies, applied to analog and digital power planes,
respectively. However, the digital plane operates down
to 1.7V without compromising the ADC’s performance.
The logic analyzer’s threshold must be adjusted
accordingly.
_______________________________________________________________________________________
3
Evaluate: MAX12553/MAX12554/MAX12555
Quick Start
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Access to the digital outputs is provided through connector J1. The 40-pin connector easily interfaces with a
user-provided logic analyzer or data-acquisition system.
The DAV buffered output clock signal is available at pin
3 of J1 (CLKO) and is used to synchronize the output
data to the logic analyzer.
Table 2. Clock Drive Settings
JUMPER
SHUNT
POSITION
JU4
2-3
JU6
1-2
Power Supplies
JU7
2-3
The EV kits require separate analog and digital power
supplies for best performance. Separate 3.3V power
supplies are used to power the analog circuit blocks of
the converter (VDUT) and the clock-shaping circuit
(VCLK). To evaluate single-ended clock-signal operation, 3.3V must be supplied to VCLK. Separate 1.8V
power supplies are used to power the digital circuit
block of the converter (VLDUT) and the buffer/driver, U2
(VL). The digital circuit blocks of the EV kits operate with
voltage supplies as low as 1.7V and as high as 3.6V.
JU8
2-3
JU4
1-2*
JU6
2-3*
JU7
1-2*
JU8
1-2*
Clock Input
The MAX12553, MAX12554, and MAX12555 accept differential or single-ended clock input signals. However,
the EV kits only accept a single-ended clock signal.
The EV kits include circuitry that converts a singleended signal to a differential clock signal through a
transformer or a user-installed differential clock driver
IC (U5). The EV kits also include clock-shaping circuitry
for a single-ended clock-signal configuration. Jumper
JU5 must be configured for differential or single-ended
clock-signal operation. See Table 1 for jumper settings.
Table 1. Clock Input Settings (JU5)
SHUNT
POSITION
CLKTYP PIN
Single-Ended Clock
Mode—See the Clock-Shaping
Circuit with Variable Duty Cycle
section.
Differential Clock Mode—A
single-ended signal is converted
to a differential signal that drives
the ADC clock inputs.
*Default position.
Install a shunt across pins 1-2 of jumper JU5 for differential clock operation. Note: While in transformercoupled differential clock mode, power to VCLK
should not be applied unless R10 is turned to one
extreme to avoid unnecessary triggering of U6.
Unnecessary triggering could potentially disturb the
ground plane with unwanted spur energy.
Clock-Shaping Circuit with Variable Duty Cycle
An on-board variable duty-cycle, clock-shaping circuit
generates a single-ended clock signal from an AC-coupled sine wave applied to the CLOCK SMA connector.
Measure the clock signal at pin 2 of jumper JU7 and
adjust potentiometer R10 to obtain the desired duty
cycle. See Table 2 for shunt positions. A 3.3V voltage
source must be connected across VCLK and GND to
power the clock-circuit comparators.
CLOCK INPUT
CONFIGURATION
1-2*
Connected to VLDUT
Differential
2-3
Connected to GND
Single-Ended
*Default position.
Transformer-Coupled Differential Clock
A single-ended signal connected to the CLOCK SMA
connector is converted to a differential signal by transformer T3. In this mode, diode D1 limits the clock-signal
amplitude. Using this diode in the signal path allows the
clock signal to be increased significantly without violating the absolute maximum ratings of the converter
inputs, as the diode clips the input signal. Overdriving
the clock input to the board (CLOCK SMA) results in an
increased slew rate, which, in turn, compensates for the
negative effects that clock jitter imposes on parameters
such as signal-to-noise ratio (SNR) and signal-to-noise
plus distortion (SINAD). See Table 2 for jumper settings.
4
CLOCK MODE
Input Signal
The MAX12553, MAX12554, and MAX12555 accept differential or single-ended analog input signals. However,
the EV kits require only a single-ended analog input
signal. Because the amplitude of the received signal at
the ADC depends on the actual cable and bandpass
filter loss, account for these losses when configuring
the signal-input generator. In differential mode, onboard transformers T1 and T2 take the single-ended
analog input connected to the AINP SMA connector
and generate a differential analog signal at the ADC’s
input pins. For direct single-ended or differential inputsignal operation, the EV kit board circuit modifications
are listed in the Direct AC-Coupled Differential Input
and Direct AC-Coupled Single-Ended Input sections.
_______________________________________________________________________________________
MAX12553/MAX12554/MAX12555
Evaluation Kits
2) Remove the short across resistor R15.
3) Remove R3 and R4.
4) Install 0Ω resistors across R20 and R24.
5) Install 0.1µF ceramic capacitors across C51 and
C52.
6) Modify resistors R29 and R30 to match the source
impedance (e.g., 25Ω resistors for a 50Ω differential
source impedance).
Reference Voltage
The MAX12553, MAX12554, and MAX12555 require an
input-reference voltage at the converter’s REFIN pin to
set the full-scale analog-signal voltage input. The ADC
offers a stable on-chip reference voltage of 2.048V that
is accessed at the REFIN pad. The EV kits were
designed to use the on-chip reference voltage by shorting REFIN to REFOUT through resistor R12.
The user externally adjusts the reference level, hence
the full-scale range, by cutting open the PC trace shorting resistor R12 and installing the appropriate resistors
at locations R2 and R12 (located on the board’s component side). Calculate the resistor values using the following equation:
⎛V
⎞
R12 = R2 ⎜ REFOUT − 1⎟
⎝ VREFIN
⎠
7) Connect the positive input-signal source to the
AINP SMA connector.
8) Connect the negative input-signal source to the
AINN SMA connector.
Direct AC-Coupled Single-Ended Input
To evaluate the MAX12553/MAX12554/MAX12555 EV
kits with a single-ended input signal directly connected
to the ADC input terminal, modify the EV kits as follows:
1) Remove transformers T1 and T2.
2) Remove resistor R3.
3) Install 0Ω resistors across R20, R29, and R13.
4) Install a 0.1µF ceramic capacitor across C51.
5) Install a 1µF capacitor across C47.
6) Modify resistor R30 to match the source impedance
(e.g., a 50Ω resistor for a 50Ω source impedance).
7) Connect the positive input-signal source to the
AINP SMA connector.
Converter Power-Down
The MAX12553, MAX12554, and MAX12555 each feature an active-high global device power-down pin.
Jumper JU2 controls this feature. Other ICs on the EV
kits continue to draw quiescent current from the power
supplies. See Table 3 for power-down jumper settings.
Table 3. Power-Down Settings (JU2)
EV KIT
OPERATION
SHUNT
POSITION
PD PIN
1-2
Connected to VLDUT
Powered Down
2-3*
*Default position.
Connected to GND
Normal Operation
where:
R2 = 10kΩ ±1%
VREFOUT = 2.048V
V REFIN = desired REFIN voltage in the 0.7V to
2.2V range
Alternatively, resistors R12 and R2 can be left unpopulated and the ADC’s full-scale range set by applying a
stable, low-noise, external voltage reference directly at
the REFIN pad.
Shorting the REFIN pad to ground through resistor R2
disables the internal reference voltage. In this mode,
test points TP1 (REFP), TP2 (REFN), and TP3 (COM)
must be driven with stable reference voltages. Refer to
the Analog Inputs and Reference Configurations section in the MAX12553, MAX12554, and MAX12555 IC
data sheets for further details. Note: To drive test
point TP3 with an external reference voltage, add a
0Ω resistor across R27.
Output Coding
Set the digital output coding to either two’s-complement or Gray-code format by configuring jumper JU3.
See Table 4 for shunt positions.
Table 4. Output Code Settings (JU3)
SHUNT
POSITION
G/T PIN
DIGITAL OUTPUT
FORMAT
1-2
Connected to VLDUT
Gray Code
2-3*
Connected to GND
Two's Complement
*Default position.
_______________________________________________________________________________________
5
Evaluate: MAX12553/MAX12554/MAX12555
Direct AC-Coupled Differential Input
To evaluate the MAX12553/MAX12554/MAX12555 EV
kits with differential input signals directly connected to
the ADC input pins, modify the EV kits as follows:
1) Remove transformers T1 and T2.
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Digital Output
The MAX12553, MAX12554, and MAX12555 feature a
14-bit, parallel, CMOS-compatible output bus. The outputs of the ADC are applied to an output buffer (U2)
capable of driving large capacitive loads that may be
present at the logic analyzer connection. The digital
outputs are valid on the rising edge of the CLKO output
signal. The outputs of the buffer are connected to a
40-pin header (J1) located on the right side of the EV
kits, where the user connects a logic analyzer or dataacquisition system. See Table 5 for bit locations at
header J1. The signals are available on the J1 pins
closest to the edge of the EV kit boards.
Component Placement and
Board Layout Recommendations
Refer to the Schematic and Layout Guidelines for HighSpeed Data Converters application note, located at
www.maxim-ic.com/appnotes.cfm/an_pk/3491,
for a detailed discussion about component placement and PCB layout recommendations for the
MAX12553/MAX12554/MAX12555.
Table 5. Output Bit Locations (J1)
CLOCK
DOR
BIT
D13
J1-3
CLKO
J1-7
J1-11
6
BIT
D12
BIT
D11
J1-13 J1-15
BIT
D10
BIT
D9
BIT
D8
BIT
D7
BIT
D6
BIT
D5
BIT
D4
BIT
D3
BIT
D2
BIT
D1
BIT
D0
J1-17
J1-19
J1-21
J1-23
J1-25
J1-27
J1-29
J1-31
J1-33
J1-35
J1-37
_______________________________________________________________________________________
_______________________________________________________________________________________
VL
GND
VLDUT
GND
1
1
1
2
L3
2
L2
2
L1
3
3
3
COM
VCC
OVDD
1
2
3
C32
2.2µF
C17
1.0µF
TP2
TP1
1
2
3
CLKP
CLKN
INN
INP
C28
10µF
1
2
3
1
1
2
3
C21
1.0µF
TP6
10
9
6
5
3
2
1
8
11
40
JU2 37
OVDD
C45
1.0µF
JU3
OVDD
GND
JU5
OVDD
C12
1.0µF
C4
1.0µF
C3
1.0µF
JU4
OVDD
C7
22µF
10V
C2
22µF
10V
C1
22µF
10V
VCLK
14
15
36
35
16
7
GND GND
REFIN
REFOUT
DOR
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
33
4
MAX12553/
MAX12554/
MAX12555
U1
34
C34
1.0µF
OVDD OVDD DAV
17
OVDD
C33
22µF
10V
GND GND
CLKP
CLKN
INN
INP
COM
REFN
REFP
DCE
CLKTYP
G/T
PD
13
3
VDD VDD VDD VDD VDD
12
VDD
2
L4
VCK
Y
39
38
R2
OPEN
R12
SHORT
(PC TRACE)
C26
0.1µF
REFIN
C44
OPEN
9
10
7
19
8
11
6
20
18
12
5
21
13
14
3
23
4
15
2
24
22
16
1
9
8
26
25
10
7
11
6
28
27
12
5
29
13
4
15
16
C5
OPEN
30
RA2
220Ω
RA1
220Ω
4
5
14
2
1
CUT HERE
JU1
U3
OPEN
VCC
3
TP4
GND
A
OE
31
32
3
2
1
VCC
24
1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
TP5
A
OE
25
4
5
4
10
15
18
VCC
21
31
42
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
VCC VCC
28
34
45
39
GND GND GND GND
U2
SN74AVC16374
VCC
7
VCC
CLK0
C6
1.0µF
GND GND GND GND
2OE
1OE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1CLK 2CLK
48
Y
VCC
U4
NC7SZ125
GND
26
3
2
1
VCC
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
C35
2.2µF
CLK0
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
C23
0.1µF
N.C.
C30
2.2µF
C8
1.0µF
C36
2.2µF
N.C.
N.C.
N.C.
J1
C31
2.2µF
C10
1.0µF
C24
0.1µF
J1-1
J1-3
J1-9
J1-5
J1-7
J1-11
J1-13
J1-15
J1-17
J1-19
J1-21
J1-23
J1-25
J1-27
J1-29
J1-31
J1-33
J1-35
J1-37
J1-39
C13
0.1µF
C9
1.0µF
C25
0.1µF
J1-2
J1-4
J1-10
J1-6
J1-8
J1-12
J1-14
J1-16
J1-18
J1-20
J1-22
J1-24
J1-26
J1-28
J1-30
J1-32
J1-34
J1-36
J1-38
J1-40
C15
0.1µF
C11
1.0µF
C37
2.2µF
N.C.
N.C.
PLACE CAPACITORS IN THE FOLLOWING LOCATIONS OF U1:
C35 AND C23 NEXT TO PIN 36
C36 AND C24 NEXT TO PINS 12/13
C37 AND C25 NEXT TO PINS 14/15
VDD
RA4
220Ω
RA3
220Ω
OVDD
VCC
Evaluate: MAX12553/MAX12554/MAX12555
VDUT
VDD
MAX12553/MAX12554/MAX12555
Evaluation Kits
Figure 1a. MAX12553/MAX12554/MAX12555 EV Kits Schematic (Sheet 1 of 2)
7
8
R1
OPEN
CLOCK4
OPEN
3
2
1
T4
OPEN
AINN
AINP
4
5
6
C48
OPEN
R15
SHORT
(PC TRACE)
R23
SHORT
(PC TRACE)
R31
R19 OPEN
SHORT
(PC TRACE)
C29
OPEN
R24
OPEN
R4
75Ω
0.5%
C52
OPEN
4
3
R28
SHORT
(PC TRACE)
4
6
3
T2
C51
OPEN
5
VEE
U5
OPEN
2
1
RESET
CLK
VBB
CLK
VCC
5
6
1
3
4
2
8
2
T1
R3
75Ω
0.5%
R25
OPEN
C38
OPEN
R16
OPEN
R11
OPEN
Q
Q
6
7
C50
OPEN
C49
OPEN
VCK C18
OPEN
5
1
R20
OPEN
3
R21
C16 OPEN
OPEN
D2
1 OPEN
2
L
R
C14
OPEN
VCK
TP3
C39
4.7µF
JU9
OPEN
CLKP
R13
SHORT
(PC TRACE)
R29
110Ω
0.5%
R22
SHORT
(PC TRACE)
R30
110Ω
0.5%
R14
SHORT
(PC TRACE)
JU10
OPEN
CLKN
C20
OPEN
R27
OPEN
R17
OPEN
R26
OPEN
R18
OPEN
C19
OPEN
C46
15pF
C47
15pF
3
2 D1
R
COM
1
2 JU8
3
3
2 JU7
1
L
C41
SHORT
C40
SHORT
INN
INP
1
4
3
R9
100Ω
1%
R7
100Ω
1%
U6-B
C27
1.0µF
6
2
5
C43 VCK
1.0µF
C42
0.1µF
1
U6-A
6
5
4
T3
1
2
3
1
JU6 2
3
C22
0.1µF
VCK
R6
1.0kΩ
CLOCK
R8
OPEN
R10
10kΩ
R5
1.0kΩ
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Figure 1b. MAX12553/MAX12554/MAX12555 EV Kits Schematic (Sheet 2 of 2)
_______________________________________________________________________________________
MAX12553/MAX12554/MAX12555
Evaluation Kits
Evaluate: MAX12553/MAX12554/MAX12555
Figure 2. MAX12553/MAX12554/MAX12555 EV Kits Component Placement Guide—Component Side
_______________________________________________________________________________________
9
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Figure 3. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Component Side
10
______________________________________________________________________________________
MAX12553/MAX12554/MAX12555
Evaluation Kits
Evaluate: MAX12553/MAX12554/MAX12555
Figure 4. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Ground Planes
______________________________________________________________________________________
11
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Figure 5. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Power Planes
12
______________________________________________________________________________________
MAX12553/MAX12554/MAX12555
Evaluation Kits
Evaluate: MAX12553/MAX12554/MAX12555
Figure 6. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Solder Side
______________________________________________________________________________________
13
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
Figure 7. MAX12553/MAX12554/MAX12555 EV Kits Component Placement Guide—Solder Side
Revision History
Pages changed at Rev 1: Title change—all pages, 1–14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 14
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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