MAX12557EVKIT

Click here to ask about the production status of specific part numbers. MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits General Description The MAX12527/MAX12528/MAX12529/MAX12557/ MAX12558/MAX12559 evaluation kits (EV kits) are fully assembled and tested circuit boards that contain all the components necessary to evaluate the performance of this family of 12-bit and 14-bit, dual analog-to-digital converters (ADCs). These ADCs accept differential analog input signals. The EV kits generate these signals from user-provided single-ended input sources. The digital outputs produced by the ADCs can be easily sampled with a user-provided high-speed logic analyzer or dataacquisition system. The EV kits operate from 2.0V and 3.3V power supplies. Part Selection Table PART SAMPLING RATE (Msps) RESOLUTION (Bits) MAX12559ETK 96 14 MAX12558ETK 80 14 MAX12557ETK 65 14 MAX12529ETK 96 12 MAX12528ETK 80 12 MAX12527ETK 65 12 Evaluate: MAX12527/28/29/57/58/59 Features ●● Low-Voltage and Low-Power Operation ●● On-Board Clock-Shaping Circuitry Option ●● On-Board Output Drivers ●● Fully Assembled and Tested Ordering Information PART TEMP RANGE* IC PACKAGE MAX12527EVKIT# 0°C to +70°C 68 TQFN-EP** MAX12528EVKIT 0°C to +70°C 68 TQFN-EP** MAX12529EVKIT 0°C to +70°C 68 TQFN-EP** MAX12557EVKIT 0°C to +70°C 68 TQFN-EP** MAX12558EVKIT 0°C to +70°C 68 TQFN-EP** MAX12559EVKIT 0°C to +70°C 68 TQFN-EP** #Denotes ROHS compliant with exemption. *EV kit PC board temperature range only. **EP = Exposed paddle. Component List DESIGNATION QTY C1–C4 0 Not installed (0603) C5, C6, C11, C13, C14, C16, C17, C28–C32, C45, C46, C57–C60, C62–C65 22 0.1μF ±20%, 10V X5R ceramic capacitors (0402) TDK C1005X5R1A104M C7–C10 C12, C21–C27 C15, C18, C19, C20 19-3920; Rev 2; 3/21 4 8 4 DESCRIPTION 5.6pF ±0.5pF, 50V C0G ceramic capacitors (0402) TDK C1005C0G1H5R6D 4.7μF ±20%, 6.3V X5R ceramic capacitors (0603) TDK C1608X5R0J475M 0.1μF ±20%, 6.3V X5R ceramic capacitors (0201) TDK C0603X5R0J104M DESIGNATION QTY DESCRIPTION C33–C38, C47, C53 8 220μF ±20%, 6.3V tantalum capacitors (C case) AVX TPSC227M006R0250 C39, C40, C41, C55, C61, C66 6 10μF ±20%, 6.3V X5R ceramic capacitors (0805) TDK C2012X5R0J106M C42, C43, C44, C56 4 1.0μF ±20%, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A105M C51, C52 2 0.01μF ±5%, 25V C0G ceramic capacitors (0603) TDK C1608C0G1E103J C67 1 1.0μF ±20%, 6.3V X5R ceramic capacitor (0402) TDK C1005X5R0J105M MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Component List (continued) DESIGNATION QTY DESCRIPTION D1 1 Dual Schottky diode (SOT23) Central Semiconductor CMPD6263S Vishay BAS70-04 Diodes Inc. BAS70-04 J1, J2, J7 3 SMA PC mount connectors J3, J4, J8 3 2-pin headers J5, J6 2 Dual-row, 40-pin headers (2 x 20) JU1–JU6 6 3-pin headers L1–L4 4 EMI filters Murata NFM41PC155B1E3 R1–R8, R13–R16, R21–R32, R37, R40–R45 0 Not installed (0603) R9–R12 4 75Ω ±0.5% resistors (0603) R17–R20 4 110Ω ±0.5% resistors (0603) R33–R36 0 Not installed (0402) R38, R39 2 49.9Ω ±1% resistors (0603) R46, R47 2 100Ω ±1% resistors (0603) R48 1 10kΩ potentiometer R49–R52 4 24.9Ω ±0.5% resistors (0402) DESIGNATION QTY DESCRIPTION RA1–RA8 8 220Ω ±5% resistor arrays Panasonic EXB-2HV-221J T1–T4 4 1:1 RF transformers Mini-Circuits ADT1-1WT T5 1 1:2 RF transformer Coilcraft TTWB-2-B TP1–TP6 6 Test points U1 1 See the EV Kit Specific Component List U2, U3 2 Low-voltage 16-bit registers (48-pin TSSOP) Pericom PI74ALVTC16374 or Texas Instruments SN74ALVCH16374DGGR U4 1 TinyLogic ULP-A buffer (SC70-5) Fairchild NC7SV125P5 U5 1 TinyLogic ULP-A inverter (SC70-6) Fairchild NC7WV04P6 None 6 Shunts None 1 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 PC board EV Kit Specific Component List EV KIT PART NUMBER REFERENCE DESIGNATOR DESCRIPTION MAX12527EVKIT# Maxim MAX12527ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12528EVKIT Maxim MAX12528ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm MAX12529EVKIT MAX12557EVKIT U1 Maxim MAX12529ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) Maxim MAX12557ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12558EVKIT Maxim MAX12558ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) MAX12559EVKIT Maxim MAX12559ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm) www.maximintegrated.com Maxim Integrated │  2 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Component Suppliers SUPPLIER PHONE FAX WEBSITE AVX 843-946-0238 843-626-3123 www.avxcorp.com Central Semiconductor 631-435-1110 631-435-1824 www.centralsemi.com Coilcraft 847-639-6400 847-639-1469 www.coilcraft.com Diodes Inc. 805-446-4800 805-446-4850 www.diodes.com Fairchild 888-522-5372 — Murata 770-436-1300 770-436-3030 www.murata.com Panasonic 714-373-7366 714-737-7323 www.panasonic.com Pericom 800-435-2336 408-435-1100 www.pericom.com TDK 847-803-6100 847-390-4405 www.component.tdk.com Texas Instruments 972-644-5580 214-480-7800 www.ti.com www.fairchildsemi.com Note: Indicate that you are using the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 when contacting these component suppliers. Quick Start Recommended Equipment ●● DC power supplies: Analog (VDD) 3.3V, 500mA Digital (OVDD) 2.0V, 50mA Buffers (VLOGIC) 2.0V, 100mA ●● Signal generator with low phase noise and low jitter for clock input signal (e.g., HP/Agilent 8644B) ●● Two signal generators with low phase noise for analog signal inputs (e.g., HP/Agilent 8644B) ●● Logic analyzer or data-acquisition system (e.g., HP/ Agilent 16500C) ●● Narrow-band analog bandpass filters (e.g., Allen Avionics, K&L Microwave) for input signals and clock signal ●● Digital multimeter Procedure The EV kit is a fully assembled and tested printed circuit (PC) board. Follow the steps below to verify board operation. Do not turn on power supplies or enable signal generators until all connections are completed. 1) Verify that shunts are installed in the following locations: JU1 (2-3)  Independent reference mode JU2 (2-3)  ADC active (not in power-down mode) JU3 (2-3)  Outputs in two’s-complement format JU4 (1-2)  Differential clock input JU5 (2-3)  No clock division JU6 (2-3)  No clock division www.maximintegrated.com 2) Connect the clock signal generator to the input of the clock bandpass filter. 3) Connect the output of the clock bandpass filter to the SMA connector labeled J7. 4) Connect the analog input signal generators to the inputs of the desired analog bandpass filters. For best results, connect the bandpass filter directly to the SMA connector and forego any cables in between. 5) Connect the output of the analog bandpass filters to the SMA connectors labeled J1 and J2. The analog input signals can be monitored at J3 and J4. Eliminate cables between bandpass filter outputs and SMA connectors. If cables must be used, they should be as short as possible. Add a 3dB to 6dB attenuator between bandpass filter and SMA connectors to control undesired distortion components induced by the signal generator. 6) Connect the logic analyzer to headers J5 and J6 to collect digitized data from channels A and B. See the Output Bit Locations section in this document for header connections. 7) Connect a 3.3V, 500mA power supply to VDD and connect its ground terminal to the GND pad. 8) Connect a 2.0V, 50mA power supply to OVDD and connect its ground terminal to the GND pad. 9) Connect a 2.0V, 100mA power supply to VLOGIC and connect its ground terminal to the GND pad. 10) Short the VCLK pad to the corresponding GND pad. Note: The VCLK supply is only required when the data converter is operating in single-ended clock mode. See the Configuring the EV Kit for SingleEnded Clock Operation section in this document for further details. Maxim Integrated │  3 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits 11) Turn on all the power supplies. 12) Enable the signal generators. 13) Set the clock signal generator to the desired clock frequency. See the Part Selection Table for the appropriate frequency settings for each EV kit. The amplitude of the generator should be sufficient to produce a 16dBm signal at the SMA input of the EV kit. Insertion losses due to the series-connected filter (step 2) and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. 14) Set the analog input signal generators to output the desired test frequency. The amplitude of the generator should produce a signal that is no larger than 7.5dBm as measured at the SMA input of the EV kit. Insertion losses due to the series-connected filter (step 5) and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. Also account for the attenuation from the 3dB to 6dB attenuator. 15) All signal generators should be phase-locked to each other. 16) Enable the logic analyzer. Evaluate: MAX12527/28/29/57/58/59 Power Supplies For best performance, the EV kits require separate analog, digital, clock, and buffer power-supply sources. Individual 3.3V and 2.0V power supplies are recommended to power the analog (VDD) and digital (OVDD) portions of the converter. A separate 2.0V power supply (VLOGIC) is used to power the output buffers (U2, U3) of the EV kit. The on-board clock circuitry (VCLK) is powered by a 3.3V power supply. The VCLK supply is only required when the ADC is operating in single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section for further details. Converter Power-Down The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 each feature an active-high global device power-down pin. Jumper JU2 controls this feature. See Table 1 for shunt positions. Table 1. Power-Down Shunt Settings (JU2) SHUNT POSITION PD PIN 1-2 OVDD 2-3* GND DESCRIPTION ADC powered down ADC active (normal operation) 17) Collect data using the logic analyzer. *Default configuration: JU2 (2-3). Detailed Description Clock The EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, or MAX12559. Additionally, the data converter allows for either differential or single-ended signals to drive the clock inputs. The MAX12527/MAX12528/MAX12529/MAX12557/ MAX12558/MAX12559 EV kits support both methods. The ADCs accept differential input signals; however, onboard transformers (T1–T4) convert a readily available single-ended source output to the required differential signal. The input signals of the ADC can be measured using a differential oscilloscope probe at headers J3 and J4. In single-ended operation, the clock signal is applied to the ADC through a buffer (U5). In differential mode, an onboard transformer converts a user-provided single-ended analog input and generates a differential analog signal, which is then applied to the ADC’s input pins. Output drivers (U2 and U3) buffer the output signals of the data converter. The digital outputs of the EV kit are accessible at headers J5 and J6. Jumper JU4 controls the ADC clock input. See Table 2 for jumper configuration. The EV kits are designed as a four-layer PC board to optimize the performance of this family of ADCs. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals. 100Ω differential microstrip transmission lines are used for analog and clock inputs. 50Ω microstrip transmission lines are used for all digital outputs. The trace lengths of the 100Ω differential input lines are matched to within a few thousandths of an inch to minimize layout-dependent input-signal skew. www.maximintegrated.com Table 2. Clock Selection Shunt Settings (JU4) SHUNT POSITION DIFFCLK/ SECLK PIN 1-2* OVDD 2-3 GND DESCRIPTION Differential clock mode. Single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section for further details. *Default configuration: JU4 (1-2). Maxim Integrated │  4 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Configuring the EV Kits for Single-Ended Clock Operation To configure the MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 EV kits for singleended clock operation, the following modifications must be made to the clock circuit: 1) Cut the trace at locations R41, R43, and R44. 2) Install 0Ω resistors at locations R40, R42, and R45. 3) Install a 49.9Ω ±1% resistor at location R37. 4) Connect a 3.3V power supply to VCLK (needs to be capable of sourcing up to 10mA output current). Connect the ground terminal of this supply to GND. In single-ended clock configuration, potentiometer R48 can be utilized to control the duty cycle of the clock input signal. Measure the clock input at J8 and adjust R48 until the desired duty cycle is achieved. Clock-Divider Control The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 each feature internal divideby-2/divide-by-4 clock-divider circuitry (DIV2, DIV4). Jumpers JU5 and JU6 control this circuitry. Refer to the individual ADC data sheets for a detailed explanation of the internal clock divider. See Table 3 for jumper configuration. Table 3. Clock-Divider Shunt Settings (JU5, JU6) SHUNT POSITION PD PIN DESCRIPTION JU5 JU6 DIV2 DIV4 2-3* 2-3* GND GND Normal clock mode 1-2 2-3 OVDD GND Divide-by-2 clock mode (DIV2) 2-3 1-2 GND 1-2 1-2 OVDD Divide-by-4 clock mode (DIV4) OVDD OVDD INVALID *Default configuration: JU5 (2-3), JU6 (2-3). Input Signal Although this family of ADCs accepts differential analog input signals, the EV kit only requires single-ended analog input signals, with amplitudes less than 7.5dBm. Insertion losses due to a series-connected filter and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. On-board transformers (T1–T4) convert the single-ended analog input signals and generate the recommended differential analog signals at the ADCs’ differential input pins. www.maximintegrated.com Evaluate: MAX12527/28/29/57/58/59 Optimizing the Analog Input Network for Different Input Frequencies The EV kits are designed for excellent AC performance across a broad 3MHz to 400MHz input frequency range. The design can be further optimized by adjusting components C7–C10 and R49–R52. See Table 4 for the appropriate component values for specific input frequency ranges. Table 4. Component Selection for Optimized AC Performance INPUT FREQUENCY RANGE (MHz) C7–C10 COMPONENT VALUES (pF) R49–R52 COMPONENT VALUES (Ω) 3 to 400* 5.6 25 < 10 12 to 22 0 10 to 125 12 25 to 50 > 125 5.6 to 12 0 *Default EV kit configuration. Reference The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 feature numerous reference operation modes. The default EV kit configuration connects the ADC’s internal 2.048V reference output to the reference input. In this case, the converter generates the REFN, REFP, and COM voltages from this input (refer to the individual ADC’s data sheet for a more detailed explanation). To apply a user-supplied reference, cut the trace at location R33 and connect the desired external reference to the REFIN pad. Alternatively, the EV kit can be configured to use a divided internal reference value. If the desired reference voltage is less than 2.048V, cut the trace at location R33 and install resistors in locations R33 and R34. Calculate the resistor values from the equations below: = R 34 VREF VREFOUT ×RT R= 33 R T − R 34 where: VREF = desired reference voltage VREFOUT = ADC’s internal reference voltage of 2.048V RT = ADC’s minimum reference resistance ≈ 10kΩ Maxim Integrated │  5 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Shared Reference Mode To maximize isolation between the two input channels, the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 feature two independent references. To improve channel matching this family of ADCs provides a mode where both input channels share the same reference. Jumper JU1 controls this shared reference feature. See Table 5 for the desired jumper configuration. Table 5. Shared Reference Shunt Settings (JU1) SHUNT POSITION SHREF PIN DESCRIPTION 1-2 OVDD Shared reference mode. Install 0Ω resistors at locations R35 and R36. 2-3* GND Independent reference mode. Remove any component at locations R35 and R36. Evaluate: MAX12527/28/29/57/58/59 Table 6. Reference Test Point Connections TEST POINT CONNECTION DESCRIPTION TP1 COMA Common-mode voltage for channel A. TP2 COMB Common-mode voltage for channel B. TP3 REFPA Positive voltage reference terminal for channel A. TP4 REFNA Negative voltage reference terminal for channel A. TP5 REFPB Positive voltage reference terminal for channel B. TP6 REFNB Negative voltage reference terminal for channel B. Note: Refer to the respective ADC data sheet for REFP, REFN, and COM voltage ranges. Output Signal 1) Cut the trace at location R33. The MAX12527, MAX12528, and MAX12529 feature two 12-bit, parallel, CMOS-compatible digital outputs that transmit the converted analog input signals. The higherresolution MAX12557, MAX12558, and MAX12559 feature two 14-bit, parallel, CMOS-compatible digital outputs that transmit the converted analog input signals. Each set of 12-bit or 14-bit digital outputs also includes a clock (CLK) bit and overrange (DORA/B) bit to accommodate data synchronization and error detection. See the Output Bit Locations section for more details on how to configure these 12-bit and 14-bit converter outputs. 2) Remove resistor R34 (not installed by default). Output Format 3) Connect the REFIN pad to GND. Set the digital output coding to either two’s-complement or Gray code, by configuring jumper JU3. See Table 7 for the jumper configuration. *Default configuration: JU1 (2-3). Alternative Reference Mode The MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 derive their REFP, REFN, and COM voltages from the REFIN input. To override these derived voltages, follow the board modifications given below. 4) Apply the desired voltages to test points TP1–TP6. See Table 6 for a detailed description of test point connections. Table 7. Output Format Shunt Settings (JU3) SHUNT POSITION G/T Pin 1-2 OVDD 2-3* GND DESCRIPTION Gray code selected. Digital output format is Gray code. Two’s complement selected. Digital output format is two’s complement. *Default configuration: JU3 (2-3). www.maximintegrated.com Maxim Integrated │  6 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Output Bit Locations Two drivers (U2 and U3) buffer the digital outputs of the individual ADCs. These drivers can drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected to 40-pin headers J5 and J6. See Table 8 (14-bit ADCs) and Table 9 (12-bit ADCs) for bit locations of headers J5 and J6. Table 8. Output Bit Locations (MAX12557, MAX12558, MAX12559—14-Bit, Dual ADCs) SIGNAL CHANNEL Evaluate: MAX12527/28/29/57/58/59 Note: Silkscreen markings on the EV kit PC board indicate pin markings for the MAX12557, MAX12558, and MAX12559. These pin markings are not valid for the MAX12527, MAX12528, or MAX12529. Use the connections outlined in Table 9. Table 9. Output Bit Locations (MAX12527, MAX12528, MAX12529—12-Bit, Dual ADCs) DESCRIPTION SIGNAL A B D0 J5-37 J6-37 Data Bit 0 (LSB) D1 J5-35 J6-35 D2 J5-33 D3 CHANNEL DESCRIPTION A B N.C. J5-37 J6-37 N.C. Data Bit 1 N.C. J5-35 J6-35 N.C. J6-33 Data Bit 2 D0 J5-33 J6-33 Data Bit 0 (LSB) J5-31 J6-31 Data Bit 3 D1 J5-31 J6-31 Data Bit 1 D4 J5-29 J6-29 Data Bit 4 D2 J5-29 J6-29 Data Bit 2 D5 J5-27 J6-27 Data Bit 5 D3 J5-27 J6-27 Data Bit 3 D6 J5-25 J6-25 Data Bit 6 D4 J5-25 J6-25 Data Bit 4 D7 J5-23 J6-23 Data Bit 7 D5 J5-23 J6-23 Data Bit 5 D8 J5-21 J6-21 Data Bit 8 D6 J5-21 J6-21 Data Bit 6 D9 J5-19 J6-19 Data Bit 9 D7 J5-19 J6-19 Data Bit 7 D10 J5-17 J6-17 Data Bit 10 D8 J5-17 J6-17 Data Bit 8 D11 J5-15 J6-15 Data Bit 11 D9 J5-15 J6-15 Data Bit 9 D12 J5-13 J6-13 Data Bit 12 D10 J5-13 J6-13 Data Bit 10 D13 J5-11 J6-11 Data Bit 13 (MSB) D11 J5-11 J6-11 Data Bit 11 (MSB) DOR J5-9 J6-9 Over Range Bit DOR J5-9 J6-9 Over Range Bit CLK J5-3 J6-3 Clock Bit CLK J5-3 J6-3 Clock Bit Note: Pins 1, 2, 5, 6, 39, and 40 of J5 and pins 1, 2, 5, 6, 7, 39, and 40 of J6 are open. All other pins that are not listed in Table 8 are connected to GND. www.maximintegrated.com Note: Pins 1, 2, 5, 6, 39, and 40 of J5 and pins 1, 2, 5, 6, 7, 39, and 40 of J6 are open. All other pins that are not listed in Table 9 are connected to GND. Maxim Integrated │  7 J2 J1 R3 OPEN C2 SHORT (PC TRACE) R4 SHORT (PC TRACE) R2 SHORT (PC TRACE) R1 OPEN R8 OPEN 4 3 6 2 T2 5 1 R7 OPEN 4 3 R6 OPEN 2 6 5 1 T1 C4 OPEN C3 OPEN REFIN R12 75Ω 0.5% R11 75Ω 0.5% R10 75Ω 0.5% R9 75Ω 0.5% C12 4.7µF 4 3 6 4 2 6 2 R16 OPEN T4 R15 OPEN R14 OPEN T3 5 1 3 5 1 R36 OPEN R27 OPEN R25 OPEN C17 0.1µF C13 0.1µF R34 OPEN R20 110Ω 0.5% R19 110Ω 0.5% R18 110Ω 0.5% R17 110Ω 0.5% C6 0.1µF C16 0.1µF C14 0.1µF C22 4.7µF C21 4.7µF R28 SHORT (PC TRACE) R24 SHORT (PC TRACE) TP2 R23 SHORT (PC TRACE) R22 SHORT (PC TRACE) C5 0.1µF R26 TP1 SHORT (PC TRACE) R49 24.9Ω 0.5% R51 24.9Ω 0.5% C9 5.6pF JU2 OVDD 1 2 3 OVDD JU1 TP4 CLKP TP5 1 2 3 JU3 OVDD TP6 TP3 C11 0.1µF COMB COMA CLKN R35 OPEN 1 2 3 C18 0.1µF C15 0.1µF J4 R33 SHORT (PC TRACE) C10 R32 5.6pF SHORT R52 (PC TRACE) 24.9Ω 0.5% C20 0.1µF COMB J3 R31 SHORT (PC TRACE) C8 R30 5.6pF SHORT R50 (PC TRACE) 24.9Ω 0.5% C19 0.1µF COMA C7 5.6pF R29 SHORT (PC TRACE) 64 65 66 11 10 8 7 20 19 68 67 16 12 15 3 6 2 VDD VDD G/T PD SHREF REFPB REFNB REFNA REFPA CLKP CLKN REFIN REFOUT INBP COMB INBN INAN COMA INAP 1459 131417 OVDD DIV2 DIV4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DORB DAV DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DIFFCLK/SECLK MAX12557 MAX12558 MAX12559 U1 DA8 DA9 DA10 DA11 DA12 DA13 DORA OVDD 23 24 25 26 61 62 63 27 43 60 VDD GND R21 SHORT (PC TRACE) VDD GND R13 OPEN VDD GND R5 OPEN OVDD VDD GND C1 SHORT (PC TRACE) VDD VDD GND OVDD GND www.maximintegrated.com GND 18 21 22 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 JU4 1 2 3 OVDD 1 2 3 OVDD JU5 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DORB LATCH DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DORA JU6 1 2 3 OVDD MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 1. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 1 of 4) Maxim Integrated │  8 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA13 DA12 DORA GND VDD 11 10 6 7 8 9 13 12 4 5 14 15 3 2 16 9 8 1 10 7 RA2 220Ω 11 6 5 U2 PI74ALVTC16374 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1D6 1D5 1D4 1D3 1D2 1Q1 1Q8 1D7 2Q1 2Q2 2Q3 2Q4 2Q5 1D8 1D1 1 1OE 24 2OE 47 46 44 43 41 40 38 37 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 2Q6 13 12 2Q7 2Q8 2CLK C42 1.0µF 2D6 29 14 42 31 18 C39 10µF 7 VLOGIC C36 220µF 6.3V 2 3 2D7 27 15 3 4 2D8 1CLK 2 26 48 16 LATCH 2 3 1 RA1 220Ω C33 220µF 6.3V 1 L1 C34 220µF 6.3V VCC GND VCC 1 VCC OVDD L2 VCC GND GND GND GND GND GND www.maximintegrated.com 4 10 15 21 28 34 45 39 GND GND 2 3 5 6 8 11 9 12 13 14 16 11 10 6 7 9 12 8 13 5 14 15 16 9 10 11 12 4 3 2 1 8 7 6 5 13 17 14 4 15 16 CLK VDD C24 4.7µF C25 4.7µF 19 RA6 220Ω RA5 220Ω C23 4.7µF C43 1.0µF 3 2 1 C29 0.1µF LATCH C40 10µF 20 22 23 25 C28 0.1µF C37 220µF 6.3V C26 4.7µF C30 0.1µF J5-2 J5-39 J5-37 J5-35 J5-33 J5-31 J5-29 J5-27 J5-25 J5-23 J5-21 J5-19 J5-40 J5-38 J5-36 J5-34 J5-32 J5-30 J5-28 J5-26 J5-24 J5-22 J5-20 J5-18 J5-16 J5-17 J5-14 J5-15 J5-12 J5-10 J5-8 J5-6 J5-4 J5-11 J5-13 J5-7 J5-9 J5-5 J5-3 J5-1 J5 40-PIN HEADER C27 4.7µF C31 0.1µF C32 0.1µF OVDD MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 2. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 2 of 4) Maxim Integrated │  9 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB12 DB11 DORB DB13 9 7 8 13 12 11 10 9 6 7 8 5 14 4 15 3 2 16 10 1 11 6 RA4 220Ω 14 3 4 5 15 2 13 12 16 RA3 220Ω 1 C35 220µF 6.3V 2 LATCH 3 1CLK 7 18 VLOGIC C41 10µF 31 42 U3 PI74ALVTC16374 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 1D7 1D6 1D5 1D4 1D3 1D2 1D1 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 4 10 15 21 28 34 45 39 A 9 10 7 3 8 11 6 5 2 12 5 6 14 15 16 13 RA8 220Ω 9 10 11 12 14 13 15 16 4 3 2 1 8 6 7 RA7 220Ω Y 4 VCC 5 C60 0.1µF CLK C67 1.0µF VLOGIC C59 0.1µF 8 9 11 12 13 14 16 17 4 5 19 1 2 GND 3 3 C58 0.1µF U4 NC7SV125 1 OE 2 C57 0.1µF 20 22 23 25 C44 1.0µF 2CLK LATCH C66 10µF 1D8 1 1OE 24 2OE 47 46 44 43 41 40 38 37 26 2D8 27 2D7 29 2D6 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 48 C38 220µF 6.3V VCC GND 1 VCC VLOGIC VCC L3 VCC GND GND GND GND GND GND www.maximintegrated.com GND GND C61 10µF C63 0.1µF J6-8 J6-7 J6-20 J6-22 J6-24 J6-19 J6-21 J6-23 J6-39 J6-37 J6-35 J6-33 J6-31 J6-29 J6-27 J6-40 J6-38 J6-36 J6-34 J6-32 J6-30 J6-28 J6-26 J6-18 J6-17 J6-25 J6-14 J6-16 J6-13 J6-15 J6-10 J6-12 J6-5 J6-9 J6-11 J6-4 J6-6 J6-2 J6-3 J6-1 J6 40-PIN HEADER C62 0.1µF C64 0.1µF C65 0.1µF VLOGIC MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 3. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 3 of 4) Maxim Integrated │  10 J2 J1 R3 OPEN C2 SHORT (PC TRACE) R4 SHORT (PC TRACE) R2 SHORT (PC TRACE) R1 OPEN R8 OPEN 4 3 6 2 T2 5 1 R7 OPEN R6 OPEN 4 3 6 2 T1 5 1 C4 OPEN C3 OPEN REFIN R12 75Ω 0.5% R11 75Ω 0.5% R10 75Ω 0.5% R9 75Ω 0.5% C12 4.7µF 4 3 6 4 2 6 2 R16 OPEN T4 R15 OPEN R14 OPEN T3 5 1 3 5 1 R36 OPEN R27 OPEN R25 OPEN C17 0.1µF C13 0.1µF R34 OPEN R20 110Ω 0.5% R19 110Ω 0.5% R18 110Ω 0.5% R17 110Ω 0.5% C6 0.1µF C16 0.1µF C14 0.1µF C22 4.7µF C21 4.7µF R28 SHORT (PC TRACE) R24 SHORT (PC TRACE) TP2 R23 SHORT (PC TRACE) R22 SHORT (PC TRACE) C5 0.1µF R26 TP1 SHORT (PC TRACE) R21 SHORT (PC TRACE) R49 24.9Ω 0.5% R51 24.9Ω 0.5% C9 5.6pF JU3 1 2 3 JU2 1 2 3 1 2 3 JU1 OVDD TP5 TP3 OVDD TP6 R35 OPEN TP4 CLKP CLKN C11 0.1µF COMB COMA OVDD C18 0.1µF C15 0.1µF J4 R33 SHORT (PC TRACE) C10 R32 5.6pF SHORT R52 (PC TRACE) 24.9Ω 0.5% C20 0.1µF COMB J3 R31 SHORT (PC TRACE) C8 R30 5.6pF SHORT R50 (PC TRACE) 24.9Ω 0.5% C19 0.1µF COMA C7 5.6pF R29 SHORT (PC TRACE) 64 65 66 11 10 8 7 20 19 68 67 16 12 15 3 6 2 VDD VDD G/T PD SHREF REFPB REFNB REFNA REFPA CLKP CLKN REFIN 4 1 REFOUT INBP COMB INBN INAN COMA INAP U1 MAX12527 MAX12528 MAX12529 5 OVDD DIFFCLK/SECLK DIV2 DIV4 N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DORB DAV N.C. N.C. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DORA OVDD 23 24 25 26 61 62 63 27 43 60 VDD GND R13 OPEN VDD 9 13 14 17 GND R5 OPEN VDD GND C1 SHORT (PC TRACE) VDDOVDD VDD GND VDD GND OVDD GND www.maximintegrated.com GND 18 21 22 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 JU4 1 2 3 OVDD 1 2 3 OVDD JU5 N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DORB LATCH N.C. N.C. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DORA JU6 1 2 3 OVDD MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 4. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 1 of 4) Maxim Integrated │  11 N.C. N.C. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA11 DA10 DORA GND VDD 12 11 10 9 5 6 7 8 13 12 11 10 9 6 7 8 5 14 4 15 3 2 16 14 13 3 4 1 15 2 RA2 220Ω 16 1 RA1 220Ω C33 220µF 6.3V 1 2 L1 LATCH GND 2D8 1CLK U2 PI74ALVTC16374 42 31 18 C39 10µF 7 VLOGIC C36 220µF 6.3V C42 1.0µF 1Q6 1Q5 1Q4 1Q3 1D6 1D5 1D4 1D3 1D1 1Q1 1Q2 1Q7 1D2 1Q8 1D7 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2CLK 3 1D8 1 1OE 24 2OE 47 46 44 43 41 40 38 37 2D7 29 2D6 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 27 26 48 3 2 VCC 1 VCC C34 220µF 6.3V VCC OVDD L2 VCC GND GND GND GND GND GND www.maximintegrated.com 4 10 15 21 28 34 45 39 GND GND 12 11 10 5 6 7 8 6 5 3 2 9 13 14 15 16 9 10 11 4 3 2 1 8 7 6 12 8 9 11 12 13 14 16 5 13 17 14 4 15 16 CLK VDD C24 4.7µF C25 4.7µF 3 RA6 220Ω RA5 220Ω C23 4.7µF C43 1.0µF 19 2 1 C29 0.1µF LATCH C40 10µF 20 22 23 25 C28 0.1µF C37 220µF 6.3V C26 4.7µF C30 0.1µF J5-39 J5-37 J5-35 J5-33 J5-31 J5-29 J5-27 J5-25 J5-23 J5-21 J5-19 J5-17 J5-15 J5-11 J5-13 J5-7 J5-9 J5-5 J5-3 J5-1 J5-40 J5-38 J5-36 J5-34 J5-32 J5-30 J5-28 J5-26 J5-24 J5-22 J5-20 J5-18 J5-16 J5-14 J5-12 J5-10 J5-8 J5-6 J5-4 J5-2 J5 40-PIN HEADER C27 4.7µF C31 0.1µF C32 0.1µF OVDD MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 5. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 2 of 4) Maxim Integrated │  12 N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB10 DB9 DORB DB11 9 8 13 12 11 10 9 4 6 7 8 5 14 15 3 2 16 10 7 1 11 6 RA4 220Ω 14 3 4 5 15 2 13 12 16 RA3 220Ω 1 C35 220µF 6.3V 2 LATCH 3 2CLK 7 18 VLOGIC C41 10µF 31 42 U3 PI74ALVTC16374 1Q6 1Q5 1Q4 1Q3 1Q2 1D6 1D5 1D4 1D3 1D2 1Q1 1Q7 1D1 1Q8 1D7 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 4 10 15 21 28 34 45 39 VCC 5 10 7 3 9 11 6 5 8 12 2 13 5 14 15 16 4 RA8 220Ω 9 10 11 12 14 13 15 16 6 3 2 1 8 RA7 220Ω Y 4 C60 0.1µF CLK C67 1.0µF VLOGIC C59 0.1µF 8 9 11 12 13 14 16 6 7 4 5 17 3 1 2 GND 19 3 C58 0.1µF U4 NC7SV125P5 A 1 OE 2 C57 0.1µF 20 22 23 25 C44 1.0µF 2CLK LATCH C66 10µF 1D8 1 1OE 24 2OE 47 46 44 43 41 40 38 37 26 2D8 27 2D7 29 2D6 30 2D5 32 2D4 33 2D3 35 2D2 36 2D1 48 C38 220µF 6.3V VCC GND 1 VCC VLOGIC VCC L3 VCC GND GND GND GND GND GND www.maximintegrated.com GND GND C61 10µF C63 0.1µF J6-20 J6-22 J6-24 J6-19 J6-21 J6-23 J6-39 J6-37 J6-35 J6-33 J6-31 J6-29 J6-27 J6-40 J6-38 J6-36 J6-34 J6-32 J6-30 J6-28 J6-26 J6-18 J6-17 J6-25 J6-14 J6-16 J6-13 J6-15 J6-10 J6-12 J6-8 J6-7 J6-9 J6-11 J6-6 J6-5 J6-2 J6-4 J6-3 J6-1 J6 40-PIN HEADER C62 0.1µF C64 0.1µF C65 0.1µF VLOGIC MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Figure 6. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 3 of 4) Maxim Integrated │  13 Evaluate: MAX12527/28/29/57/58/59 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits R41 SHORT (PC TRACE) C45 0.1µF J7 R37 OPEN R43 SHORT (PC TRACE) C51 0.01µF CLKN 1 T5 R38 49.9Ω 1% 6 2 5 3 4 2 D1 R45 OPEN 1 J8 R39 49.9Ω 1% 3 CLKP VCLK R44 SHORT (PC TRACE) C52 0.01µF R46 100Ω 1% VCLK R48 10kΩ C46 R47 100Ω 1% 0.01µF 5 1 R40 OPEN U5–A U5–B 6 3 4 R42 OPEN 2 VCLK L4 VCLK GND 1 C53 220µF 6.3V 3 2 C47 220µF 6.3V C55 10µF C56 1µF Figure 7. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 4 of 4) www.maximintegrated.com Maxim Integrated │  14 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 www.maximintegrated.com 1.0” Figure 8. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit Component Placement Guide—Component Side www.maximintegrated.com Maxim Integrated │  15 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 1.0” Figure 9. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout—Component Side www.maximintegrated.com Maxim Integrated │  16 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 1.0” Figure 10. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout (Inner Layer 2)—Ground Planes www.maximintegrated.com Maxim Integrated │  17 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 1.0” Figure 11. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout (Inner Layer 3)—Power Planes www.maximintegrated.com Maxim Integrated │  18 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 1.0” Figure 12. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout—Solder Side www.maximintegrated.com Maxim Integrated │  19 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 1.0” Figure 13. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Component Placement Guide—Solder Side www.maximintegrated.com Maxim Integrated │  20 MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits Evaluate: MAX12527/28/29/57/58/59 Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 12/05 Initial Release 1 1/21 Updated Ordering Information, Component List, and EV Kit Specific Component List 1–19 2 3/21 Updated Ordering Information and Component List 1, 2 DESCRIPTION — For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2021 Maxim Integrated Products, Inc. │  21