KIT
ATION
EVALU
E
L
B
A
IL
AVA
19-0792; Rev 0; 4/07
1.62V to 3.6V Improved High-Speed LLT
Features
The MAX13042E–MAX13045E 4-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13042E–MAX13045E are ideally suited for level
translation in systems with four channels. Externally
applied voltages, VCC and VL, set the logic levels on
either side of the device. Logic signals present on the
VL side of the device appear as a high-voltage logic
signal on the VCC side of the device and vice-versa.
The MAX13042E–MAX13045E operate at full speed
with external drivers that source as little as 4mA output
current or larger. Each input/output (I/O) channel is
pulled up to V CC or V L by an internal 30µA current
source, allowing the MAX13042E–MAX13045E to be
driven by either push-pull or open-drain drivers.
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
part when VCC is less than VL. The state of I/O VCC_ and
I/O VL_ during shutdown is chosen by selecting the
appropriate part version. (See the Ordering Information/
Selector Guide).
The MAX13042E–MAX13045E operate with VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V
to +3.2V, making them ideal for data transfer between
low-voltage ASIC/PLDs and higher voltage systems.
The MAX13042E–MAX13045E are available in 12-bump
UCSP™ (1.54mm x 2.12mm) and 14-pin TDFN (3mm x
3mm) packages, and operate over the extended -40°C
to +85°C temperature range.
♦ Compatible with 4mA Input Drivers or Larger
♦ 100Mbps Guaranteed Data Rate
♦ Four Bidirectional Channels
♦ Enable Input
♦ ±15kV ESD Protection on I/O VCC_ Lines
♦ +1.62V ≤ VL ≤ +3.2V and +2.2V ≤ VCC ≤ +3.6V
Supply Voltage Range
♦ 12-Bump UCSP (1.54mm x 2.12mm) and
14-Pin TDFN (3mm x 3mm) Lead-Free Packages
Typical Operating Circuit
+3.3V
+1.8V
0.1μF
VL
+1.8V
SYSTEM
CONTROLLER
0.1μF
1μF
VCC
+3.3V
SYSTEM
MAX13042E–
MAX13045E
EN
I/O VL_
EN
DATA
I/O VCC_
4
GND
DATA
4
GND
GND
Applications
CMOS Logic-Level
Translation
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Portable POS Systems
Low-Voltage ASIC Level
Translation
Cell Phones
SPI™, MICROWIRE™
Level Translation
Portable Communication
Devices
Pin Configurations appear at end of data sheet.
GPS
Telecommunications
Equipment
Ordering Information/Selector Guide continued at end of
data sheet.
Ordering Information/Selector Guide
PART
PINPACKAGE
I/O VL_ STATE DURING
SHUTDOWN
I/O VCC_ STATE DURING
SHUTDOWN
TOP
MARK
MAX13042EEBC+T
12 UCSP-12
High Impedance
High Impedance
ADQ
B12-3
MAX13042EETD+T
14 TDFN-EP**
High Impedance
High Impedance
ADE
T1433-2
Note: All devices operate over the -40°C to +85°C temperature
range.
+Denotes a lead-free package.
PKG CODE
*Future product—contact factory for availability.
**EP = Exposed paddle.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX13042E–MAX13045E
General Description
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
VCC, VL .....................................................................-0.3V to +4V
I/O VCC_..................................................... -0.3V to (VCC + 0.3V)
I/O VL_ ...........................................................-0.3V to (VL + 0.3V)
EN.............................................................................-0.3V to +4V
Short-Circuit Duration I/O VL_, I/O VCC_ to GND .......Continuous
Continuous Power Dissipation (TA = +70°C)
12-Bump UCSP (derate 6.5mW/°C above +70°C) ......519mW
14-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
+3.3V, VL = +1.8V, and TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
VL Supply Range
VCC Supply Range
Supply Current from VCC
Supply Current from VL
VCC Shutdown Supply Current
VL
1.62
3.2
V
VCC
2.2
3.6
V
25
µA
10
µA
1
µA
IQVCC
I/O VCC_ = VCC, I/O VL_ = VL
IQVL
I/O VCC_ = VCC, I/O VL_ = VL
ISHDN-VCC
VL Shutdown-Mode Supply
Current
ISHDN-VL
I/O VCC_, I/O VL_ Tri-State
Leakage Current
ILEAK
EN Input Leakage Current
ILEAK_EN
TA = +25°C, EN = GND
0.1
TA = +25°C, EN = GND
0.1
1
TA = +25°C, EN = VL, VCC = GND
0.1
4
TA = +25°C, EN = GND
0.1
2
µA
1
µA
TA = +25°C
µA
VL - VCC Shutdown Threshold
High
VTH_H
VCC rising (Note 3)
0
0.1VL
0.8
V
VL - VCC Shutdown Threshold
Low
VTH_L
VCC falling (Note 3)
0
0.12VL
0.8
V
I/O VCC_ Pulldown Resistance
During Shutdown
RVCC_PD_SD
MAX13043E/MAX13045E
10
16.5
23
kΩ
RVL_PD_SD
MAX13044E/MAX13045E
10
16.5
23
kΩ
IVL_PU_
I/O VL_ = GND, I/O VCC_ = GND
20
65
µA
IVCC_PU_
I/O VCC_ = GND, I/O VL_ = GND
20
65
µA
I/O VL_ Pulldown Resistance
During Shutdown
I/O VL_ Pullup Current
I/O VCC_ Pullup Current
I/O VL_ to I/O VCC_ DC
Resistance
2
RIOVL_IOVCC (Note 4)
3
_______________________________________________________________________________________
kΩ
1.62V to 3.6V Improved High-Speed LLT
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
+3.3V, VL = +1.8V, and TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ESD PROTECTION
I/O VL_, EN
I/O VCC_
Human Body Model
±2
Human Body Model, CVCC = 1µF
±15
IEC 61000-4-2 Air-Gap Discharge,
CVCC = 1µF
±15
IEC 61000-4-2 Contact Discharge,
CVCC = 1µF
±8
kV
kV
LOGIC LEVELS
I/O VL_ Input-Voltage High
Threshold
VIHL
(Note 5)
I/O VL_ Input-Voltage Low
Threshold
VILL
(Note 5)
I/O VCC_ Input-Voltage High
Threshold
VIHC
(Note 5)
I/O VCC_ Input-Voltage Low
Threshold
VILC
(Note 5)
EN Input-Voltage-High
Threshold
VIH
EN Input-Voltage-Low
Threshold
VIL
I/O VL_ Output-Voltage High
VL - 0.2
V
0.15
VCC 0.4
V
0.2
VL - 0.4
I/O VL_ source current = 20µA
I/O VL_ Output-Voltage Low
VOLL
I/O VL_ sink current = 20µA, I/O VCC_ < 0.2V
I/O VCC_ Output-Voltage High
VOHC
I/O VCC_ source current = 20µA
I/O VCC_ Output-Voltage Low
VOLC
I/O VCC_ sink current = 20µA,
I/O VL_ < 0.15V
V
V
0.4
VOHL
V
2/3 VL
V
V
1/3 VL
2/3 VCC
V
V
1/3 VCC
V
RISE-/FALL-TIME ACCELERATOR STAGE
Accelerator Pulse Duration
On falling edge
3.5
On rising edge
3.5
VL Output Accelerator Source
Impedance
VL = 1.62V
24
VL = 3.2V
11
VCC Output Accelerator Source
Impedance
VCC = 2.2V
13
VCC = 3.6V
9
VL Output Accelerator Sink
Impedance
VL = 1.62V
14
VL = 3.2V
10
VCC Output Accelerator Sink
Impedance
VCC = 2.2V
11
VCC = 3.6V
9
ns
Ω
Ω
Ω
Ω
_______________________________________________________________________________________
3
MAX13042E–MAX13045E
ELECTRICAL CHARACTERISTICS (continued)
TIMING CHARACTERISTICS
(+2.2V ≤ VCC ≤ +3.6V, +1.62V ≤ VL ≤ +3.2V; CIOVL_ ≤ 15pF, CIOVCC_ ≤ 10pF; RSOURCE < 150Ω, rise/fall time < 3ns, EN = VL,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, and TA = +25°C.) (Notes 1, 2)
MAX
UNITS
I/O VCC_ Rise Time
PARAMETER
tRVCC
Figure 1
2.5
ns
I/O VCC_ Fall Time
tFVCC
Figure 1
2.5
ns
I/O VL_ Rise Time
tRVL
Figure 2
2.5
ns
I/O VL_ Fall Time
tFVL
Figure 2
2.5
ns
Propagation Delay
(Driving I/O VL_)
tPVL-VCC
Figure 1
6.5
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
Figure 2
6.5
ns
SYMBOL
tSKEW
(Note 4)
0.7
ns
tEN-VCC
Figure 3
5
µs
tEN-VL
Figure 3
5
µs
Channel-to-Channel Skew
Propagation Delay From I/O VL_
to I/O VCC_ after EN
Propagation Delay From I/O VCC_
to I/O VL_ after EN
Maximum Data Rate
CONDITIONS
MIN
Push-pull operation
TYP
100
Mbps
Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
correlation and design and not production tested.
Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 3: When VCC is below VL by more than the VL - VCC shutdown threshold, the device turns off its pullup generators and the I/Os
enter their respective shutdown states.
Note 4: Guaranteed by design.
Note 5: Input thresholds are referenced to the boost circuit.
Typical Operating Characteristics
(VCC = 3.3V, VL = 1.8V, CIOVCC_ = 10pF, CIOVL_ = 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA = +25°C,
unless otherwise noted.)
370
360
350
340
330
320
VCC = 3.6V
8
6
4
2
15
VCC SUPPLY CURRENT (mA)
380
10
MAX13042E toc02
390
VL SUPPLY CURRENT (mA)
MAX13042E toc01
400
VCC SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
VL SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING ONE I/O VCC_)
MAX13042E toc03
VL SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
VL SUPPLY CURRENT (μA)
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
12
9
6
3
310
300
2.2
2.4
2.6
2.8
3.0
3.2
VCC SUPPLY VOLTAGE (V)
4
3.4
3.6
0
0
1.6
2.0
2.4
2.8
VL SUPPLY VOLTAGE (V)
3.2
2.2
2.4
2.6
2.8
3.0
3.2
VL SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.4 3.6
1.62V to 3.6V Improved High-Speed LLT
6
4
5
IVCC
4
IVL
3
2
10
9
SUPPLY CURRENT (mA)
6
SUPPLY CURRENT (mA)
8
MAX13042E toc05
VCC = 3.6V
IVCC
6
5
4
IVL
3
1
0
0
3.2
-40
60
-40
85
3000
2000
1000
16
14
VCC SUPPLY CURRENT (mA)
MAX13042E toc07
4000
10
35
TEMPERATURE (°C)
VCC SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING ONE I/O VL_)
VL SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING ONE I/O VCC_)
5000
-15
12
10
8
6
1.4
1.2
20
25
30
CAPACITIVE LOAD (pF)
35
0.2
tRVL
1.5
tFVL
1.0
0.5
20
25
30
CAPACITIVE LOAD (pF)
35
5.0
4.5
PROPAGATION DELAY (ns)
2.0
15
40
4.0
3.5
3.0
tPLH
2.5
tPHL
2.0
15
20
25
30
CAPACITIVE LOAD (pF)
35
40
20
25
30
CAPACITIVE LOAD (pF)
35
40
5.0
4.5
4.0
3.5
tPHL
3.0
2.5
2.0
tPLH
1.5
1.0
0.5
0
1.0
10
15
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
1.5
0
10
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13042E toc10
2.5
0
10
40
tFVCC
0.6
0.4
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O VL_ (DRIVING I/O VCC_)
3.0
0.8
2
PROPAGATION DELAY (ns)
15
tRVCC
1.0
4
MAX13042E toc11
10
85
60
1.6
0
0
35
10
TEMPERATURE (°C)
-15
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O VCC_ (DRIVING I/O VL_)
RISE/FALL TIME (ns)
2.0
2.4
2.8
VL SUPPLY VOLTAGE (V)
MAX13042E toc08
1.6
MAX13042E toc09
0
VL SUPPLY CURRENT (μA)
7
2
2
1
RISE/FALL TIME (ns)
8
MAX13042E toc12
VCC SUPPLY CURRENT (mA)
7
MAX13042E toc04
10
SUPPLY CURRENT vs. TEMPERATURE
(DRIVING ONE I/O VL_)
SUPPLY CURRENT vs. TEMPERATURE
(DRIVING ONE I/O VCC_)
MAX13042E toc06
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE
(DRIVING ONE I/O VCC_)
10
15
20
25
30
CAPACITIVE LOAD (pF)
35
40
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
5
MAX13042E–MAX13045E
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, CIOVCC_ = 10pF, CIOVL_ = 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, CIOVCC_ = 10pF, CIOVL_ = 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA = +25°C,
unless otherwise noted.)
TYPICAL I/O VCC_ DRIVING
(FREQUENCY = 26MHz, CIOVL_ = 15pF)
MAX1342E toc14
TYPICAL I/O VL_ DRIVING
(FREQUENCY = 26MHz, CIOVCC_ = 40pF)
MAX1342E toc13
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
I/O VCC_
2V/div
I/O VL_
1V/div
I/O VCC_
2V/div
I/O VL_
1V/div
10ns/div
10ns/div
Pin Description
PIN
6
NAME
FUNCTION
UCSP
TDFN
A1
8
I/O VCC4
Input/Output 4. Referenced to VCC.
A2
10
I/O VCC3
Input/Output 3. Referenced to VCC.
A3
12
I/O VCC2
Input/Output 2. Referenced to VCC.
A4
14
I/O VCC1
Input/Output 1. Referenced to VCC.
B1
9
VCC
Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with a
0.1µF ceramic capacitor. For full ESD protection, connect an
additional 1µF ceramic capacitor from VCC to GND as close to the
VCC input as possible.
B2
6
VL
Logic Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with a
0.1µF ceramic capacitor placed as close to the device as possible.
B3
2
EN
Enable Input. Drive EN to GND for shutdown mode, or drive EN to
VL or VCC for normal operation.
B4
13
GND
C1
7
I/O VL4
Input/Output 4. Referenced to VL.
C2
5
I/O VL3
Input/Output 3. Referenced to VL.
C3
3
I/O VL2
Input/Output 2. Referenced to VL.
C4
1
I/O VL1
Input/Output 1. Referenced to VL.
—
4, 11
N.C.
—
EP
EP
Ground
No Connection. Leave N.C. unconnected.
Exposed Pad. Connect exposed pad to GND.
_______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
VL
tRVCC
VCC
90%
VCC
EN
VL
90%
I/O VL_
MAX13042E–MAX13045E
VL
tFVCC
50%
VCC
50%
50%
50%
I/O VCC_
I/O VL_
10%
I/O VCC_ 10%
150Ω
CIOVCC
tPLH
tPHL
tPVL-VCC = tPLH OR tPHL
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
VL
EN
VL
tFVL
tRVL
VCC
I/O VCC_
VCC
MAX13042E–MAX13045E
VL
VCC
90%
50%
I/O VL_
50%
I/O VCC_
150Ω
50%
50%
10%
10%
I/O VL_
CIOVL
tPLH
90%
tPHL
tPVCC-VL = tPLH OR tPHL
Figure 2. Push-Pull Driving I/O VCC_ Test Circuit and Timing
_______________________________________________________________________________________
7
MAX13042E–MAX13045E
Test Circuits/Timing Diagrams
1.62V to 3.6V Improved High-Speed LLT
MAX13042E–MAX13045E
Test Circuits/Timing Diagrams (continued)
VL
EN
VL MAX13042E–
EN
VCC
MAX13045E
t'EN-VCC
0V
I/O VCC_
SOURCE
VL
I/O VL_
I/O VL_
0V
RLOAD
VCC
CIOVCC
I/O VCC_
VL
VCC / 2
0V
VCC
VL
EN
VL MAX13042E–
VCC
RLOAD
EN
t"EN-VCC
0V
MAX13045E
SOURCE
VL
I/O VL_
I/O VL_
0V
I/O VCC_
VCC
I/O VCC_
VCC / 2
CIOVCC
0V
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
VL
EN
VL
EN
MAX13042E– VCC
MAX13045E
t'EN-VL
SOURCE
VCC
I/O VCC_
I/O VCC_
I/O VL_
RLOAD
CIOVL
0V
0V
VCC
VL
I/O VL_
VL / 2
0V
VL
EN
EN
VL
SOURCE
VL
MAX13042E– VCC
MAX13045E
t"EN-VL
VCC
I/O VCC_
0V
RLOAD
I/O VCC_
I/O VL_
0V
VL
I/O VL_
VL / 2
CIOVL
0V
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
Figure 3. Enable Test Circuit and Timing
8
_______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
VL
VCC
MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
part when VCC is less than VL. The state of I/O VCC_ and
I/O VL_ during shutdown is chosen by selecting the
appropriate part version (see the Ordering Information/
Selector Guide).
The MAX13042E–MAX13045E operate with VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V
to +3.2V.
Level Translation
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
For proper operation, ensure that +2.2V ≤ V CC
≤ +3.6V, +1.62V ≤ V L ≤ V CC - 0.2V. When power is
supplied to VL while VCC is missing or less than VL, the
MAX13042E–MAX13045E automatically enter a lowpower mode. The devices will also enter shutdown mode
when EN = 0V. This allows VCC to be disconnected and
still have a known state on I/O VL_. The maximum data
rate depends heavily on the load capacitance (see the
Rise/Fall Time vs. Capacitive Load graphs in the Typical
Operating Characteristics), output impedance of the
driver, and the operating voltage range.
Input Driver Requirements
I/O VCC4
I/O VL4
EN
GND
Detailed Description
The MAX13042E–MAX13045E 4-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13042E–MAX13045E are ideally suited for level
translation in systems with four channels. Externally
applied voltages, VCC and VL, set the logic levels on
either side of the device. Logic signals present on the
VL side of the device appear as a high-voltage logic
signal on the VCC side of the device and vice-versa.
The MAX13042E–MAX13045E operate at full speed
with external drivers that source as little as 4mA output
current. Each I/O channel is pulled up to VCC or VL by
an internal 30µA current source, allowing the
MAX13042E–MAX13045E to be driven by either pushpull or open-drain drivers.
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
The MAX13042E–MAX13045E architecture is based on
an nMOS pass gate and output accelerator stages
(Figure 6). The accelerators are active only when there
is a rising/falling edge on a given I/O. A short pulse is
then generated where the output accelerator stages
become active and charge/discharge the capacitances
at the I/Os. Due to its architecture, both input stages
become active during the one-shot pulse. This can lead
to current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
The MAX13042E–MAX13045E have internal current
sources capable of sourcing 30µA to pull up the I/O
lines. These internal-pullup current sources allow the
inputs to be driven with open-drain drivers as well as
push-pull drivers. It is not recommended to use external
pullup resistors on the I/O lines. The architecture of the
MAX13042E–MAX13045E permits either side to be driven with a minimum of 4mA drivers or larger.
Output Load Requirements
The MAX13042E–MAX13045E I/O are designed to drive
CMOS inputs. Do not load the I/O lines with a resistive
load less than 25kΩ and do not place an RC circuit at
the input of these devices to slow down the edges. If a
slower rise/fall time is required, refer to the MAX3000E/
MAX3001E logic-level translator data sheet.
_______________________________________________________________________________________
9
MAX13042E–MAX13045E
Functional Diagram
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
VCC
VL
ENABLE
ENABLE
late signals without inversion. These devices provide
the smallest solution (UCSP package) for unidirectional
level translation without inversion.
ESD Test Conditions
ENABLE
30μA
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
30μA
I/O VL_
I/O VCC_
VCC
VL
BOOST
CIRCUIT
VL
VCC
BOOST
CIRCUIT
NOTE: THE MAX13042E–MAX13045E ARE ENABLED WHEN
VL < VCC AND EN = VL.
Use with External Pullup/
Pulldown Resistors
Due to the architecture of the MAX13042E–MAX13045E,
it is not recommended to use external pullup or pulldown resistors on the bus. In certain applications, the
use of external pullup or pulldown resistors is desired to
have a known bus state when there is no active driver
on the bus. The MAX13042E–MAX13045E include internal pullup current sources that set the bus state when
the device is enabled. In shutdown mode, the state of
I/O VCC_ and I/O VL_ is dependent on the selected part
version (see the Ordering Information/Selector Guide).
Figure 4. Simplified Functional Diagram for One I/O Line
Shutdown Mode
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
part when VCC is unconnected or less than VL.
Applications Information
Layout Recommendations
Use standard high-speed layout practices when
laying out a board with the MAX13042E–MAX13045E.
For example, to minimize line coupling, place all other
signal lines not connected to the MAX13042E–
MAX13045E at least 1x the substrate height of the
PCB away from the input and output lines of the
MAX13042E–MAX13045E.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VL and VCC to ground with 0.1µF ceramic capacitors. Place all capacitors as close to the
power-supply inputs as possible. For full ESD protection, bypass VCC with a 1µF ceramic capacitor located
as close to the VCC input as possible.
Open-Drain Signaling
The MAX13042E–MAX13045E are designed to pass opendrain as well as CMOS push-pull signals. When used with
open-drain signaling, the rise time will be dominated by the
interaction of the internal pullup current source and the parasitic load capacitance. The MAX13042E–MAX13045E
include internal rise-time accelerators to speed up transitions, eliminating any need for external pullup resistors. For
applications such as I2C or 1-wire that require an external
pullup resistor, please consult the MAX3378E and
MAX3396E data sheets.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profiles, as well as the latest information on reliability testing
results, go to Maxim’s website at www.maxim-ic.com/ucsp
to find the Application Note: UCSP – A Wafer-Level ChipScale Package.
Chip Information
PROCESS: BiCMOS
Unidirectional vs. Bidirectional
Level Translator
The MAX13042E–MAX13045E bidirectional level translators can operate as a unidirectional device to trans-
10
______________________________________________________________________________________
1.62V to 3.6V Improved High-Speed LLT
TOP VIEW
TOP VIEW
(BUMPS ON BOTTOM)
1
+
2
+
I/O VL1
1
14
I/O VCC1
EN
2
13
GND
I/O VL2
3
12
I/O VCC2
N.C.
4
11
N.C.
I/O VL3
5
10
I/O VCC3
VL
6
9
VCC
I/O VL4
7
8
I/O VCC4
3
4
MAX13042E–MAX13045E
A
MAX13042E–MAX13045E
*EP
I/O VCC4
I/O VCC3
I/O VCC2
I/O VCC1
VCC
VL
EN
GND
I/O VL4
I/O VL3
I/O VL2
I/O VL1
B
C
UCSP
(1.54mm x 2.12mm)
TDFN
(3mm x 3mm)
*CONNECT EXPOSED PAD TO GROUND
Ordering Information/Selector Guide (continued)
PART
PINPACKAGE
I/O VL_ STATE DURING
SHUTDOWN
I/O VCC_ STATE DURING
SHUTDOWN
TOP
MARK
PKG CODE
MAX13043EEBC+T
12 UCSP-12
High Impedance
16.5kΩ to GND
ADR
B12-3
MAX13043EETD+T
14 TDFN-EP**
T1433-2
High Impedance
16.5kΩ to GND
ADF
MAX13044EEBC+T* 12 UCSP-12
16.5kΩ to GND
High Impedance
ADS
B12-3
MAX13044EETD+T*
16.5kΩto GND
High Impedance
ADG
T1433-2
MAX13045EEBC+T* 12 UCSP-12
16.5kΩ to GND
16.5kΩ to GND
ADT
B12-3
MAX13045EETD+T*
16.5kΩ to GND
16.5kΩ to GND
ADH
T1433-2
14 TDFN-EP**
14 TDFN-EP**
Note: All devices operate over the -40°C to +85°C temperature
range.
+Denotes a lead-free package.
*Future product—contact factory for availability.
**EP = Exposed paddle.
______________________________________________________________________________________
11
MAX13042E–MAX13045E
Pin Configurations
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12L, UCSP 4x3.EPS
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
PACKAGE OUTLINE, 4x3 UCSP
21-0104
12
______________________________________________________________________________________
F
1
1
1.62V to 3.6V Improved High-Speed LLT
6, 8, &10L, DFN THIN.EPS
______________________________________________________________________________________
13
MAX13042E–MAX13045E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
PACKAGE VARIATIONS
SYMBOL
MIN.
MAX.
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
A
0.70
0.80
T633-2
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
D
2.90
3.10
T833-2
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
E
2.90
3.10
T833-3
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
A1
0.00
0.05
T1033-1
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
L
0.20
0.40
T1033-2
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
k
0.25 MIN.
T1433-1
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
A2
0.20 REF.
T1433-2
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
Springer
is a registered trademark of Maxim Integrated Products, Inc.
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