19-3481; Rev 0; 10/04
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
The MAX1307/MAX1311/MAX1315 12-bit, analog-to-digital converters (ADCs) feature a 1075ksps sampling rate, a
20MHz input bandwidth, and three analog input ranges.
The MAX1307 provides a 0 to +5V input range, with ±6V
fault-tolerant inputs. The MAX1311 provides a ±5V input
range with ±16.5V fault-tolerant inputs. The MAX1315 provides a ±10V input range with ±16.5V fault-tolerant inputs.
The MAX1307/MAX1311/MAX1315 include an on-chip
2.5V reference. These devices also accept an external
+2V to +3V reference.
All devices operate from a +4.75 to +5.25V analog supply, and a +2.7V to +5.25V digital supply. The devices
consume 36mA total supply current when fully operational. A 0.62µA shutdown mode is available to save
power during idle periods.
A 20MHz, 12-bit, parallel data bus provides the conversion results. An internal 15MHz oscillator, or an externally
applied clock, drives conversions.
Each device is available in a 48-pin 7mm x 7mm
TQFP package and operates over the extended
(-40°C to +85°C) temperature range.
Applications
Features
♦ ±1 LSB INL, ±0.9 LSB DNL (max)
♦ 84dBc SFDR, -86dBc THD, 71dB SINAD,
fIN = 500kHz at -0.4dBFS
♦ Extended Input Ranges
0 to +5V (MAX1307)
-5V to +5V (MAX1311)
-10V to +10V (MAX1315)
♦ Fault-Tolerant Inputs
±6V (MAX1307)
±16.5V (MAX1311/MAX1315)
♦ Fast 0.72µs Conversion Time
♦ 12-Bit, 20MHz Parallel Interface
♦ Internal or External Clock
♦ +2.5V Internal Reference or +2.0V to +3.0V
External Reference
♦ +5V Analog Supply, +3V to +5V Digital Supply
36mA Analog Supply Current
1.3mA Digital Supply Current
Shutdown Mode
♦ 48-Pin TQFP Package (7mm x 7mm Footprint)
Industrial Process Control and Automation
Vibration and Waveform Analysis
Data-Acquisition Systems
DGND
DVDD
D11
39
37
38
EOLC
EOC
40
41
42
43
44
45
46
CHSHDN
SHDN
CLK
CONVST
CS
WR
RD
36
2
35
3
34
4
33
5
32
6
31
MAX1307
MAX1311
MAX1315
7
8
30
29
26
12
25
PIN-PACKAGE
-40°C to +85°C
48 TQFP
MAX1311ECM
-40°C to +85°C
48 TQFP
MAX1315ECM
-40°C to +85°C
48 TQFP
Selector Guide
±10
1
C48-6
23
MAX1315EC
22
C48-6
21
C48-6
1
20
1
±5
19
0 to +5
MAX1311EC
18
MAX1307EC
17
INPUT
RANGE (V)
16
PART
24
27
11
15
10
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
TEMP RANGE
MAX1307ECM
AGND
AVDD
REFMS
REF
REF+
COM
REFAGND
DGND
28
14
9
INTCLK/EXTCLK
AGND
AVDD
Ordering Information
PART
1
13
AVDD
AGND
AGND
AIN
I.C.
MSV
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
47
TOP VIEW
48
Pin Configuration
CHANNEL
COUNT
PKG
CODE
TQFP
________________________________________________________________ Maxim Integrated Products
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1307/MAX1311/MAX1315
General Description
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0, I.C. to AGND (MAX1307)..............................................±6V
CH0, I.C. to AGND (MAX1311) .............................................±16.5V
CH0, I.C. to AGND (MAX1315) .............................................±16.5V
D0–D11 to DGND ....................................-0.3V to (DVDD + 0.3V)
EOC, EOLC, RD, WR, CS to DGND .........-0.3V to (DVDD + 0.3V)
CONVST, CLK, SHDN, CHSHDN to DGND...-0.3V to (DVDD + 0.3V)
INTCLK/EXTCLK to AGND .......................-0.3V to (AVDD + 0.3V)
REFMS, REF, MSV to AGND.....................-0.3V to (AVDD + 0.3V)
REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)
Maximum Current into Any Pin Except AVDD,
DVDD, AGND, DGND....................................................±50mA
Continuous Power Dissipation (TA = +70°C)
TQFP (derate 22.7mW/°C above +70°C) ................1818.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (See Figures 3 and 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.5
±1.0
LSB
±0.3
±0.9
LSB
STATIC PERFORMANCE (Note 1)
Resolution
N
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Offset Error
Offset-Error Temperature Drift
12
No missing codes
Bits
Unipolar, 0x000 to 0x001
±3
±10
Bipolar, 0xFFF to 0x000
±3
±15
Unipolar, 0x000 to 0x001
7
Bipolar, 0xFFF to 0x000
7
Gain Error
±2
Gain-Error Temperature Drift
LSB
ppm/°C
±16
4
LSB
ppm/°C
DYNAMIC PERFORMANCE AT fIN = 500kHz, AIN = -0.4dBFS
Signal-to-Noise Ratio
Signal-to-Noise Plus Distortion
SNR
68
71
dB
SINAD
68
71
dB
Total Harmonic Distortion
THD
-86
Spurious-Free Dynamic Range
SFDR
84
-80
dBc
dBc
ANALOG INPUTS (AIN)
MAX1307
Input Voltage
VAIN
0
MAX1311
-5
+5
MAX1315
-10
+10
MAX1307
Input Resistance
(Note 2)
RAIN
IAIN
8.66
MAX1315
14.26
MAX1311
MAX1315
2
V
7.58
MAX1311
MAX1307
Input Current
(Note 2)
+5
VCH = +5V
VCH = 0V
0.54
-0.157
-0.12
-1.16
-0.87
VCH = +5V
VCH = -5V
0.29
VCH = +10V
VCH = -10V
0.56
-1.13
-0.85
_______________________________________________________________________________________
kΩ
0.72
0.39
0.74
mA
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (See Figures 3 and 4)
PARAMETER
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
CAIN
MAX
UNITS
15
pF
TRACK/HOLD
External-Clock Throughput Rate
fTH
(Note 3)
1075
ksps
Internal-Clock Throughput Rate
fTH
(Note 3)
983
ksps
20
MHz
20
MHz
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
tAD
8
ns
Aperture Jitter
tAJ
50
psRMS
INTERNAL REFERENCE
REF Output Voltage
VREF
2.475
2.500
Reference Output-Voltage
Temperature Drift
2.525
30
ppm/°C
REFMS Output Voltage
VREFMS
REF+ Output Voltage
VREF+
3.850
V
COM Output Voltage
VCOM
2.600
V
REF- Output Voltage
VREF-
1.350
V
VREF+ VREF-
2.500
V
Differential Reference Voltage
2.475
V
2.500
2.525
V
EXTERNAL REFERENCE (REF and REFMS are externally driven)
REF Input Voltage Range
VREF
REF Input Resistance
RREF
2.0
2.5
(Note 4)
REF Input Capacitance
REFMS Input Voltage Range
VREFMS
REFMS Input Resistance
RREFMS
2.0
3.0
5
kΩ
15
pF
2.5
(Note 5)
REFMS Input Capacitance
V
3.0
V
5
kΩ
15
pF
REF+ Output Voltage
VREF+
VREF = +2.5V
3.850
V
COM Output Voltage
VCOM
VREF = +2.5V
2.600
V
REF- Output Voltage
VREF-
VREF = +2.5V
1.350
V
VREF+ VREF-
VREF = +2.5V
2.500
V
Differential Reference Voltage
DIGITAL INPUTS (RD, WR, CS, CLK, SHDN, CHSHDN, CONVST)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input Hysteresis
0.7 x DVDD
V
0.3 x DVDD
20
V
mV
_______________________________________________________________________________________
3
MAX1307/MAX1311/MAX1315
ELECTRICAL CHARACTERISTICS (continued)
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (See Figures 3 and 4)
PARAMETER
SYMBOL
Input Capacitance
CIN
Input Current
IIN
CONDITIONS
MIN
TYP
MAX
15
VIN = 0 or DVDD
UNITS
pF
0.02
±1
µA
CLOCK-SELECT INPUT (INTCLK/EXTCLK)
Input-Voltage High
VIH
Input-Voltage Low
VIL
0.7 x AVDD
V
0.3 x AVDD
V
DIGITAL OUTPUTS (D0–D11, EOC, EOLC)
Output-Voltage High
VOH
ISOURCE = 0.8mA, Figure 1
Output-Voltage Low
VOL
ISINK = 1.6mA, Figure 1
DVDD - 0.6
V
D0–D11 Tri-State Leakage Current
RD = high or CS = high
0.06
D0–D11 Tri-State Output
Capacitance
RD = high or CS = high
15
0.4
V
1
µA
pF
POWER SUPPLIES
Analog Supply Voltage
AVDD
Digital Supply Voltage
DVDD
Analog Supply Current
Digital Supply Current
(CLOAD = 100pF) (Note 6)
IAVDD
IDVDD
4.75
2.70
5.25
V
5.25
V
MAX1307
36
39
MAX1311
34
36
MAX1315
34
36
MAX1307
1.3
2.6
MAX1311
1.3
2.6
MAX1315
1.3
2.6
Shutdown Current
(Note 7)
IAVDD
SHDN = DVDD, VCH = float
0.6
10
IDVDD
SHDN = DVDD, RD = WR = high
0.02
1
Power-Supply Rejection Ratio
PSRR
AVDD = +4.75V to +5.25V
50
Internal clock, Figure 6
800
mA
mA
µA
dB
TIMING CHARACTERISTICS (Figure 1)
900
ns
Time to Conversion Result
tCONV
CONVST Pulse-Width Low
(Acquisition Time)
tACQ
Figures 6, 7 (Note 8)
CS to RD
tCTR
Figures 6, 7
(Note 9)
ns
RD to CS
tRTC
Figures 6, 7
(Note 9)
ns
Data Access Time
(RD Low to Valid Data)
tACC
Figures 6, 7
tREQ
Figures 6, 7
Bus Relinquish Time (RD High)
External clock, Figure 7
CLK
cycles
12
0.1
1000.0
30
5
30
µs
ns
ns
CLK Rise to EOC Delay
tEOCD
Figure 7
20
ns
CLK Rise to EOLC Fall Delay
tEOLCD
Figure 7
20
ns
20
ns
CONVST Fall to EOLC Rise Delay
4
tCVEOLCD Figures 6, 7
_______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (See Figures 3 and 4)
PARAMETER
SYMBOL
CONDITIONS
Internal clock, Figure 6
EOC Pulse Width
tEOC
External CLK Period
tCLK
MIN
External clock, Figure 7
Figure 7
Logic sensitive to rising edges, Figure 7
External CLK Low Period
tCLKL
Logic sensitive to rising edges, Figure 7
20
External Clock Frequency
fCLK
(Note 10)
0.1
Internal Clock Frequency
fINT
CLK
cycles
10.00
µs
20
ns
ns
20.0
15
Figure 7
UNITS
ns
0.05
tCLKH
tCNTC
MAX
1
External CLK High Period
CONVST High to CLK Edge
TYP
50
MHz
MHz
20
ns
Note 1: For the MAX1307, VIN = 0 to +5V. For the MAX1311, VIN = -5V to +5V. For the MAX1315, VIN = -10V to +10V.
Note 2: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
IAIN =
VAIN − VBIAS
RAIN
for AIN within the input voltage range.
Note 3: Throughput rate is a function of clock frequency (fCLK). The external clock throughput rate is specified with fCLK =
16.67MHz and the internal clock throughput rate is specified with fCLK = 15MHz. See the Data Throughput section for more
information.
Note 4: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
IREF =
VREF − 2.5V
RREF
for VREF within the input voltage range.
Note 5: The REFMS input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMS input current using:
IREFMS =
VREFMS − 2.5V
RREFMS
for VREFMS within the input voltage range.
Note 6: The analog input is driven with a -0.4dBFS 500kHz sine wave.
Note 7: Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown-current specification is due to automated test equipment limitations.
Note 8: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 9: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 10: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
and the falling edge of EOLC to a maximum of 1ms.
_______________________________________________________________________________________
5
MAX1307/MAX1311/MAX1315
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C,
unless otherwise noted.) (Figures 3 and 4)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.6
0.8
0.6
0.4
DNL (LSB)
0.4
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
MAX1307/11/15 toc02
0.8
INL (LSB)
1.0
MAX1307/11/15 toc01
1.0
0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
OFFSET ERROR
vs. TEMPERATURE
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
0.6
12
8
OFFSET ERROR (LSB)
0.4
0.2
0
-0.2
-0.4
MAX1307/11/15 toc04
0.8
OFFSET ERROR (LSB)
16
MAX1307/11/15 toc03
1.0
4
0
-4
-8
-0.6
-12
-0.8
-16
-1.0
4.7
4.8
4.9
5.0
5.1
5.2
-40
5.3
-15
10
35
60
85
60
85
TEMPERATURE (°C)
AVDD (V)
GAIN ERROR
vs. TEMPERATURE
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
0
12
8
GAIN ERROR (LSB)
-1
-2
-3
MAX1307/11/15 toc06
16
MAX1307/11/15 toc05
1
GAIN ERROR (LSB)
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
4
0
-4
-8
-4
-12
-16
-5
4.7
4.8
4.9
5.0
AVDD (V)
6
5.1
5.2
5.3
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C,
unless otherwise noted.) (Figures 3 and 4)
SMALL-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
AIN = -20dBFS
0
AIN = -0.5dBFS
0
-2
GAIN (dB)
-4
-6
-4
-6
-8
-8
-10
-10
-12
-12
0.1
1
100
10
0.1
1
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(2048-POINT DATA RECORD)
fTH = 1.04167Msps
fIN = 500kHz
AIN = -0.05dBFS
SNR = 70.7dB
SINAD = 70.6dB
THD = -87.5dBc
SFDR = 87.1dBc
-20
-30
-40
-50
5497
5000
4000
COUNTS
-10
AMPLITUDE (dBFS)
OUTPUT HISTOGRAM (DC INPUT)
6000
MAX1307/11/15 toc09
0
-60
-70
3000
2000
-80
-90
1611
1084
1000
-100
0
-110
0
100
200
100
10
ANALOG INPUT FREQUENCY (MHz)
MAX1307/11/15 toc10
GAIN (dB)
-2
2
MAX1307/11/15 toc07
2
MAX1307/11/15 toc08
LARGE-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
300
FREQUENCY (kHz)
400
500
0
0
2044
2045
2046
2047
2048
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
7
MAX1307/MAX1311/MAX1315
Typical Operating Characteristics (continued)
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C,
unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCY
80
76
78
76
74
SINAD (dB)
74
72
70
68
MAX1307/11/15 toc12
78
SNR (dB)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCY
MAX1307/11/15 toc11
80
72
70
68
66
66
64
64
62
62
60
60
0
5
10
15
20
25
0
5
fCLK (MHz)
15
20
25
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
-65
-70
95
90
SFDR (dBc)
-75
-80
MAX1307/11/15 toc14
100
MAX1307/11/15 toc13
-60
85
80
-85
75
-90
70
-95
65
60
-100
0
5
10
15
fCLK (MHz)
8
10
fCLK (MHz)
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
THD (dBc)
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
20
25
0
5
10
15
20
fCLK (MHz)
_______________________________________________________________________________________
25
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C,
unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. REFERENCE VOLTAGE
SIGNAL-TO-NOISE RATIO
vs. REFERENCE VOLTAGE
73
74
73
72
SINAD (dB)
72
71
70
69
71
70
69
68
68
67
67
66
66
65
65
2.2
2.4
2.6
2.8
2.0
3.0
2.2
2.4
2.6
2.8
VREF (V)
VREF (V)
TOTAL HARMONIC DISTORTION
vs. REFERENCE VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE
vs. REFERENCE VOLTAGE
100
MAX1307/11/15 toc17
-70
-72
-74
-76
3.0
MAX1307/11/15 toc18
2.0
95
90
-78
SFDR (dBc)
THD (dBc)
MAX1307/11/15 toc16
74
SNR (dB)
75
MAX1307/11/15 toc15
75
-80
-82
85
80
-84
-86
75
-88
-90
2.0
2.2
2.4
2.6
VREF (V)
2.8
3.0
70
2.0
2.2
2.4
2.6
2.8
3.0
VREF (V)
_______________________________________________________________________________________
9
MAX1307/MAX1311/MAX1315
Typical Operating Characteristics (continued)
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C,
unless otherwise noted.) (Figures 3 and 4)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
40
1.0
0.8
IDVDD (mA)
38
IAVDD (mA)
MAX1307/11/15 toc20
1.2
MAX1307/11/15 toc19
42
36
0.6
34
0.4
32
0.2
0
30
4.7
4.8
4.9
5.0
5.1
5.2
2.5
5.3
3.0
3.5
4.5
5.0
5.5
DIGITAL SHUTDOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
680
660
640
MAX1307/11/15 toc22
22
MAX1307/11/15 toc21
700
20
18
620
IDVDD (nA)
IAVDD (nA)
4.0
DVDD (V)
AVDD (V)
600
580
16
14
560
540
12
520
10
500
4.7
4.8
4.9
5.0
5.1
5.2
2.5
5.3
3.0
3.5
4.0
4.5
5.0
5.5
DVDD (V)
AVDD (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
2.5003
2.503
2.502
VREF (V)
2.5002
2.5001
2.5000
MAX1307/11/15 toc24
2.504
MAX1307/11/15 toc23
2.5004
VREF (V)
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
2.501
2.500
2.499
2.4999
2.498
2.4998
2.497
2.4997
2.496
2.4996
-40
4.7
4.8
4.9
5.0
5.1
5.2
5.3
-15
10
35
60
TEMPERATURE (°C)
AVDD (V)
10
______________________________________________________________________________________
85
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar
devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C,
unless otherwise noted.) (Figures 3 and 4)
INTERNAL CLOCK CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGE
tCONV
800
tCONV
600
780
TIME (ns)
TIME (ns)
MAX1304 toc26
800
700
820
MAX1307/11/15 toc25
900
INTERNAL CLOCK CONVERSION TIME
vs. TEMPERATURE
500
400
300
760
740
200
720
100
0
700
4.8
4.9
5.0
5.1
5.3
5.2
-40
-15
AVDD (V)
0
-0.5
MAX1311
1.5
1.0
ICH_ (mA)
0.5
2.5
2.0
0.5
0
-0.5
-6
-4
-2
0
VCH_ (V)
2
4
6
1.0
0.5
0
-1.5
-2.5
-3.0
-2.0
MAX1315
-1.0
-2.0
-1.5
1.5
-0.5
-1.0
-1.5
-1.0
2.0
ICH_ (mA)
1.0
85
60
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
MAX1307/11/15 toc28
1.5
ICH_ (mA)
3.0
MAX1307/11/15 toc27
MAX1307
35
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
2.0
10
TEMPERATURE (°C)
MAX1307/11/15 toc29
4.7
-2.0
-20
-15
-10
-5
0
VCH_ (V)
5
10
15
20
-20
-15
-10
-5
0
5
10
15
20
VCH_ (V)
______________________________________________________________________________________
11
MAX1307/MAX1311/MAX1315
Typical Operating Characteristics (continued)
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description
PIN
NAME
1, 15, 17
AVDD
Analog Power Input. AVDD is the power input for the analog section of the converter. Apply +5V to AVDD.
Connect all AVDD pins together. See the Layout, Grounding, and Bypassing section for additional
information.
2, 3, 14,
16, 23
AGND
Analog Ground. AGND is the power return for AVDD. Connect all AGND pins together.
4
AIN
Analog Input
6
MSV
Midscale Voltage Bypass. For the unipolar MAX1307, connect a 2.2µF and a 0.1µF capacitor from MSV to
AGND. For the bipolar MAX1311/MAX1315, connect MSV to AGND.
13
INTCLK/ Clock-Mode Select Input. Connect INTCLK/EXTCLK to AVDD to select the internal clock. Connect
EXTCLK INTCLK/EXTCLK to AGND to use an external clock connected to CLK.
REFMS
Midscale Reference Bypass/Input. REFMS connects through a 5kΩ resistor to the internal +2.5V bandgap
reference buffer.
For the MAX1307 unipolar devices, VREFMS is the input to the unity-gain buffer that drives MSV. MSV sets the
midpoint of the input voltage range. For internal reference operation, bypass REFMS with a ≥0.01µF capacitor
to AGND. For external reference operation, drive REFMS with an external voltage from +2V to +3V.
For the MAX1311/MAX1315 bipolar devices, connect REFMS to REF. For internal reference operation, bypass
the REFMS/REF node with a ≥0.01µF capacitor to AGND. For external reference operation, drive the
REFMS/REF node with an external voltage from +2V to +3V.
19
REF
ADC Reference Bypass/Input. REF connects through a 5kΩ resistor to the internal +2.5V bandgap
reference buffer.
For internal reference operation, bypass REF with a ≥0.01µF capacitor.
For external reference operation with the MAX1307 unipolar devices, drive REF with an external voltage
from +2V to +3V.
For external reference operation with the MAX1311/MAX1315 bipolar devices, connect REFMS to REF and
drive the REFMS/REF node with an external voltage from +2V to +3V.
20
REF+
Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND. Also bypass REF+ to REF- with
a 2.2µF and a 0.1µF capacitor. VREF+ = VCOM + VREF / 2.
21
COM
Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF capacitor.
VCOM = 13 / 25 x AVDD.
22
REF-
Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND. Also bypass REF- to REF+ with
a 2.2µF and a 0.1µF capacitor.
VREF+ = VCOM - VREF / 2.
24, 39
DGND
Digital Ground. DGND is the power return for DVDD. Connect all DGND pins together.
25, 38
DVDD
Digital Power Input. DVDD powers the digital section of the converter, including the parallel interface. Apply
+2.7V to +5.25V to DVDD. Bypass DVDD to DGND with a 0.1µF capacitor. Connect all DVDD pins together.
26
D0
Digital Output 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
27
D1
Digital Output 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
28
D2
Digital Output 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
29
D3
Digital Output 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
30
D4
Digital Output 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
31
D5
Digital Output 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
18
12
FUNCTION
______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
PIN
NAME
32
D6
FUNCTION
Digital Output 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
33
D7
Digital Output 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
34
D8
Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
35
D9
Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
36
D10
Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
37
D11
Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
40
EOC
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. It returns high on the next rising
CLK edge or the falling CONVST edge.
41
EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. It returns high
when CONVST goes low for the next conversion sequence.
42
RD
Read Input. Pulling RD low initiates a read command of the parallel data bus.
43
WR
Write Input. WR is not implemented. Connect WR to RD, CS, DGND, or DVDD.
44
CS
Chip-Select Input. Pulling CS low activates the digital interface. Forcing CS high places D0–D11 in highimpedance mode.
45
CONVST
46
CLK
47
SHDN
48
5, 7–12
Conversion Start Input. Driving CONVST high initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST.
External Clock Input. For external clock operation, connect INTCLK/EXTCLK to DGND and drive CLK with
an external clock signal from 100kHz to 20MHz. For internal clock operation, connect INTCLK/EXTCLK to
DVDD and connect CLK to DGND.
Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN to DGND for normal
operation.
CHSHDN CHSHDN Is Not Implemented. Connect CHSHDN to DGND.
I.C.
Internally Connected. Connect I.C. to AGND.
______________________________________________________________________________________
13
MAX1307/MAX1311/MAX1315
Pin Description (continued)
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
Detailed Description
VDD
IOL = 1.6mA
1.6V
DEVICE PIN
100pF
The MAX1307/MAX1311/MAX1315 contain a 1075ksps 12bit ADC with track and hold (T/H). Input scaling on the
MAX1307/MAX1311/MAX1315 allows a 0 to +5V, ±5V, or
±10V analog input signal, respectively. Additionally, the
MAX1307 features ±6V fault-tolerant inputs, while the
MAX1311/MAX1315 feature ±16.5V fault-tolerant inputs.
The MAX1307/MAX1311/MAX1315 include an on-chip
+2.5V reference. These devices also accept an external
+2V to +3V reference.
The conversion results are available in 0.72µs with a
sampling rate of 1075ksps. Internal or external clock
capabilities offer greater flexibility. A high-speed, 20MHz
parallel interface outputs the conversion results.
IOH = 0.8mA
Figure 1. Digital Load Test Circuit
AVDD
MAX1307
MAX1311
MAX1315
12-BIT
ADC
T/H
AIN
DVDD
DATA
REGISTER
OUTPUT
DRIVERS
D11
D0
MSV
WR
*
CS
REF+
COM
REF-
INTERFACE
AND
CONTROL
RD
CONVST
SHDN
5kΩ
INTCLK/EXTCLK
REF
CLK
5kΩ
CHSHDN
REFMS
EOC
2.500V
EOLC
DGND
AGND
*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES
Figure 2. Functional Diagram
14
______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
DVDD
0.1µF
1
0.1µF
15
0.1µF
17
BIPOLAR
CONFIGURATION
18
0.01µF
19
AVDD
DGND
AVDD
CLK
REFMS
MAX1311
MAX1315
CONVST
CS
WR
0.1µF
20
REF+
0.1µF
2.2µF
RD
EOLC
22
REF0.1µF
SHDN
MSV
REF
EOC
24, 39
GND
48
47
46
45
44
43
DIGITAL
INTERFACE
AND
CONTROL
42
41
40
2.2µF
D11
21
0.1µF
GND
+2.7V TO +5.25V
0.1µF
AVDD
CHSHDN
6
25, 38
MAX1307/MAX1311/MAX1315
+5V
COM
D9
2, 3, 14, 16, 23
12
11
10
9
36
35
34
AGND
D8
I.C.
D7
I.C.
D6
I.C.
D5
I.C.
D4 30
8 I.C.
7 I.C.
BIPOLAR
ANALOG
INPUT
D10
37
5 I.C.
4 A
IN
13 INTCLK/EXTCLK
D3
D2
33
32
31
PARALLEL
DIGITAL
OUTPUT
29
28
D1 27
D0 26
Figure 3. Typical Bipolar Operating Circuit
______________________________________________________________________________________
15
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
+5V
0.1µF
1
0.1µF
15
0.1µF
17
DVDD
AVDD
25, 38
+2.7V TO +5.25V
0.1µF
AVDD
DGND
AVDD
24, 39
GND
2.2µF
6
0.1µF
MSV
SHDN
CLK
0.01µF
UNIPOLAR
CONFIGURATION
CHSHDN
18
0.01µF
19
REFMS
CONVST
MAX1307
REF
CS
WR
0.1µF
20
RD
REF+
0.1µF
2.2µF
EOLC
EOC
22
48
47
46
45
44
43
DIGITAL
INTERFACE
AND
CONTROL
42
41
40
REF0.1µF
2.2µF
D11
21
0.1µF
COM
D10
D9
GND
2, 3, 14, 16, 23
12
11
10
AGND
D8
I.C.
D7
I.C.
D6
I.C.
D5
9
I.C.
8 I.C.
7 I.C.
UNIPOLAR
ANALOG
INPUTS
5 I.C.
4 A
IN
13 INTCLK/EXTCLK
37
36
35
34
33
32
31
PARALLEL
DIGITAL
OUTPUT
D4 30
D3
D2
29
28
D1 27
D0 26
Figure 4. Typical Unipolar Operating Circuit
16
______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
CH_
ANALOG
SIGNAL
SOURCE
OVERVOLTAGE
PROTECTION
CLAMP
2.5pF
R1
UNDERVOLTAGE
PROTECTION
CLAMP
Selecting an Input Buffer
CHOLD
CSAMPLE
R2
VBIAS
*MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION.
PART
INPUT RANGE (V) R1 (kΩ) R2 (kΩ) VBIAS (V)
MAX1307
0 TO +5
3.33
5.00
0.90
MAX1311
±5
6.67
2.86
2.50
MAX1315
±10
13.33
2.35
2.06
R1 | | R2 = 2kΩ
Figure 5. Equivalent Analog Input T/H Circuit
Analog Input
Track and Hold (T/H)
The input T/H circuit is controlled by the CONVST input.
When CONVST is low, the T/H circuit tracks the analog
input. When CONVST is high, the T/H circuit holds the
analog input. The rising edge of CONVST is the analog
input sampling instant. There is an aperture delay (tAD)
of 8ns and a 50psRMS aperture jitter (tAJ).
To settle the charge on CSAMPLE to 12-bit accuracy,
use a minimum acquisition time (t ACQ ) of 100ns.
Therefore, CONVST must be low for at least 100ns.
Although longer acquisition times allow the analog input
to settle to its final value more accurately, the maximum
acquisition time must be limited to 1ms. Accuracy with
conversion times longer than 1ms cannot be guaranteed due to capacitor droop in the input circuitry.
To improve the input signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (15pF) and
settle quickly. For example, the MAX4431 or the
MAX4265 can be used for 0 to +5V unipolar devices, or
the MAX4350 can be used for ±5V bipolar inputs.
Most applications require an input buffer to achieve 12-bit
accuracy. Although slew rate and bandwidth are important, the most critical input buffer specification is settling
time. At the beginning of the acquisition, the ADC internal
sampling capacitor array connects to the analog inputs,
causing some disturbance. Ensure the amplifier is capable of settling to at least 12-bit accuracy during the acquisition time (t ACQ ). Use a low-noise, low-distortion,
wideband amplifier that settles quickly and is stable with
the ADC’s 15pF input capacitance.
Refer to the Maxim website at www.maxim-ic.com for
application notes on how to choose the optimum buffer
amplifier for your ADC application.
Input Bandwidth
The input-tracking circuitry has a 20MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Input Range and Protection
The MAX1307 provides a 0 to +5V input voltage range
with fault protection of ±6V. The MAX1311 provides a
±5V input voltage range with fault protection of ±16.5V.
The MAX1315 provides a ±10V input voltage range with
fault protection of ±16.5V. Figure 5 shows the equivalent analog input circuit.
______________________________________________________________________________________
17
MAX1307/MAX1311/MAX1315
MAX1307
MAX1311
MAX1315
AVDD
*RSOURCE
Due to the analog input resistive divider formed by R1
and R2 in Figure 5, any significant analog input source
resistance (R SOURCE) results in gain error. Furthermore, R SOURCE causes distortion due to nonlinear
analog input currents. Limit RSOURCE to a maximum
of 100Ω.
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
Data Throughput
Starting a Conversion
The data throughput (fTH) of the MAX1307/MAX1311/
MAX1315 is a function of the clock speed (fCLK). In
internal clock mode, fCLK = 15MHz (typ). In external
clock mode, these devices accept an fCLK between
100kHz and 20MHz. Figures 6 and 7 calculate fTH as
follows:
To start a conversion using internal clock mode, pull
CONVST low for the acquisition time (tACQ). The T/H
acquires the signal while CONVST is low, and conversion begins on the rising edge of CONVST. The end-ofconversion (EOC) signal and end-of-last-conversion
signal (EOLC) pulse low whenever a conversion result
is available for reading (Figure 6).
To start a conversion using external clock mode, pull
CONVST low for the acquisition time (tACQ). The T/H
acquires the signal while CONVST is low. The rising
edge of CONVST is the sampling instant. Apply an
external clock to CLK to start the conversion. To avoid
T/H droop degrading the sampled analog input signals,
the first CLK pulse must occur within 10µs from the
rising edge of CONVST. Additionally, the external clock
frequency must be greater than 100kHz to avoid T/H
droop degrading accuracy. The conversion result is
available for read when EOC or ELOC goes low on the
rising edge of the 13th clock cycle (Figure 7).
In both internal and external clock modes, hold
CONVST high until the conversion result is read. If
CONVST goes low in the middle of a conversion, the
current conversion is aborted and a new conversion is
initiated. Furthermore, there must be a period of bus
inactivity (tQUIET) for 50ns or longer before the falling
edge of CONVST for the specified ADC performance.
fTH =
1
tACQ + tQUIET +
13
fCLK
where tQUIET is the period of bus inactivity before the
rising edge of CONVST (≥50ns). See the Starting a
Conversion section for more information.
Clock Modes
The MAX1307/MAX1311/MAX1315 perform conversions
using either an internal clock or external clock. There are
13 clock periods per conversion.
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For internal clock operation, connect INTCLK/EXTCLK to AVDD
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AVDD, not DVDD.
External Clock
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AVDD, not
DV DD . The external clock frequency can be up to
20MHz. Linearity is not guaranteed with clock frequencies below 100kHz due to droop in the T/H circuits.
Applications Information
Digital Interface
Conversion results are available through the 12-bit digital
interface (D0–D11). The interface includes the following
control signals: chip select (CS), read (RD), end of conversion (EOC), end of last conversion (EOLC), conversion
start (CONVST), shutdown (SHDN), internal clock select
(INTCLK/EXTCLK), and external clock input (CLK).
Figures 6 and 7 and the Timing Characteristics show the
operation of the interface. D0–D11 go high impedance
when RD = 1 or CS = 1.
18
Reading a Conversion Result
Figures 6 and 7 show the interface signals to initiate a
read operation. CS can be low at all times, low during the
RD cycles, or the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC or EOLC to go low. In internal clock mode,
EOC or EOLC goes low within 900ns. In external clock
mode, EOC or EOLC goes low on the rising edge of the
13th CLK cycle. To read the conversion result, drive CS
and RD low to latch data to the parallel digital output
bus. Bring RD high to release the digital bus.
______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1307/MAX1311/MAX1315
NEXT SAMPLE
INSTANT
SAMPLE
INSTANT
tACQ
CONVST
HOLD
TRACK
TRACK
tCONV
EOC
tEOC
tCVEOLCD
EOLC
tQUIET ≥ 50ns
tRTC
CS*
tCTR
RD
tRDL
AIN
D0–D11
tACC
tREQ
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 6. Reading a Conversion—Internal Clock
Power-Up Reset
After applying power, allow a 1ms wake-up time to
elapse and then initiate a conversion and discard the
results. After the conversion is complete, accurate conversions can be obtained.
Shutdown Modes
During shutdown the internal reference and analog
circuits in the device shutdown and the analog supply
current drops to 0.6µA (typ). Set SHDN high to enter
shutdown mode.
EOC and EOLC are high when the MAX1307/MAX1311/
MAX1315 are shut down.
The state of the digital outputs D0–D11 is independent
of the state of SHDN. If CS and RD are low, the digital
outputs D0–D11 are active regardless of SHDN. The
digital outputs only go high impedance when CS or RD
is high. When the digital outputs are powered down,
the digital supply current drops to 20nA.
Exiting shutdown (falling edge of SHDN) starts a conversion in the same way as the rising edge of CONVST.
After coming out of shutdown, initiate a conversion and
discard the results. Allow a 1ms wake-up time to expire
before initiating the first accurate conversion.
______________________________________________________________________________________
19
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
SAMPLE
INSTANT
NEXT SAMPLE
INSTANT
tACQ
CONVST
HOLD
TRACK
tCLK
tCNTC
CLK
1
2
TRACK
tCLKH
3
8
9
tCLKL
10
12
14
13
tEOCD
15
16
tEOCD
EOC
tEOC
tEOLCD
tCVEOLCD
EOLC
tCONV
tQUIET = 50ns
tRTC
CS*
tCTR
RD
tRDL
D0–D11
AIN
tACC
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
tREQ
Figure 7. Reading a Conversion—External Clock
20
______________________________________________________________________________________
1
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
Midscale Voltage (MSV)
The voltage at MSV (VMSV) sets the midpoint of the ADC
transfer functions. For the 0 to +5V input range (unipolar
devices), the midpoint of the transfer function is +2.5V.
For the ±5V and ±10V input range devices, the midpoint
of the transfer function is zero.
As shown in Figure 2, there is a unity-gain buffer
between REFMS and MSV in the unipolar MAX1307. This
midscale buffer sets the midpoint of the unipolar transfer
functions to either the internal +2.5V reference or an
externally applied voltage at REF MS . V MSV follows
VREFMS within ±3mV.
The midscale buffer is not active for the bipolar
devices. For these devices, MSV must be connected to
AGND or externally driven. REFMS must be bypassed
with a 0.01µF capacitor to AGND.
See the Transfer Functions section for more information
about MSV.
External Reference
External reference operation is achieved by overriding
the internal reference voltage. Override the internal reference voltage by driving REF with a +2.0V to +3.0V
external reference. As shown in Figure 2, the REF input
impedance is 5kΩ. For more information about using
external references, see the Transfer Functions section.
Table 1. Reference Bypass Capacitors
INPUT VOLTAGE RANGE
LOCATION
UNIPOLAR (µF)
MSV Bypass Capacitor to AGND
BIPOLAR (µF)
2.2 || 0.1
N/A
REFMS Bypass Capacitor to AGND
0.01
0.01
REF Bypass Capacitor to AGND
0.01
0.01
REF+ Bypass Capacitor to AGND
0.1
0.1
2.2 || 0.1
2.2 || 0.1
REF+ to REF- Capacitor
REF- Bypass Capacitor to AGND
0.1
0.1
COM Bypass Capacitor to AGND
2.2 || 0.1
2.2 || 0.1
N/A = Not applicable. Connect MSV directly to AGND.
Table 2. Reference Voltages
PARAMETER
EQUATION
CALCULATED VALUE (V)
VREF = 2.000V,
AVDD = 5.0V
(
)
CALCULATED VALUE (V)
VREF = 2.500V,
AVDD = 5.0V
CALCULATED VALUE (V)
VREF = 3.000V,
AVDD = 5.0V
(
)
(
)
VCOM
VCOM = 13 / 25 x AVDD
2.600
2.600
2.600
VREF+
VREF+ = VCOM + VREF / 2
3.600
3.850
4.100
VREF-
VREF- = VCOM - VREF / 2
1.600
1.350
1.100
VREF+ - VREF-
VREF = VREF- - VREF+
2.000
2.500
3.000
______________________________________________________________________________________
21
MAX1307/MAX1311/MAX1315
Reference
Internal Reference
The internal reference circuits provide for analog input
voltages of 0 to +5V for the unipolar MAX1307, ±5V for
the bipolar MAX1311, or ±10V for the bipolar MAX1315.
Install external capacitors for reference stability, as indicated in Table 1 and shown in Figures 3 and 4.
As illustrated in Figure 2, the internal reference voltage
is 2.5V (VREF). This 2.5V is internally buffered to create
the voltages at REF+ and REF-. Table 2 shows the voltages at COM, REF+, and REF-.
Transfer Functions
Unipolar 0 to +5V Devices
Table 3 and Figure 8 show the offset binary transfer
function for the MAX1307 with a 0 to +5V input range.
The full-scale input range (FSR) is two times the voltage
at REF. The internal +2.5V reference gives a +5V FSR,
while an external +2V to +3V reference allows an FSR
of +4V to +6V, respectively. Calculate the LSB size
using:
1 LSB =
2 x VREF
212
The input range is centered about VMSV, internally set
to +2.5V. For a custom midscale voltage, drive REFMS
with an external voltage source and MSV will follow
REFMS. Noise present on MSV or REFMS directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV.
Determine the input voltage as a function of V REF ,
VMSV, and the output code in decimal using:
VCH_ = LSB x CODE10 + VMSV - 2.500V
which equals 1.22mV when using a 2.5V reference.
Table 3. 0 to 5V Unipolar Code Table
BINARY
DIGITAL
OUTPUT CODE
DECIMAL
EQUIVALENT
DIGITAL OUTPUT
CODE
(CODE10)
1111 1111 1111
= 0xFFF
4095
+4.9994 ± 0.5 LSB
1111 1111 1110
= 0xFFE
4094
+4.9982 ± 0.5 LSB
1000 0000 0001
= 0x801
2049
+2.5018 ± 0.5 LSB
1000 0000 0000
= 0x800
2048
+2.5006 ± 0.5 LSB
0111 1111 1111
= 0x7FF
2047
+2.4994 ± 0.5 LSB
0000 0000 0001
= 0x001
1
+0.0018 ± 0.5 LSB
0000 0000 0000
= 0x000
0
+0.0006 ± 0.5 LSB
INPUT VOLTAGE
(V)
VREF = +2.5V
VREFMS = +2.5V
(
2 x VREF
)
0xFFF
0xFFE
0xFFD
0xFFC
BINARY OUTPUT CODE
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
0x801
0x800
0x7FF
0x0003
0x0002
0x0001
0x0000
1 LSB =
0
1 2 3
2046
2048 2050
(MSV)
INPUT VOLTAGE (LSBs)
Figure 8. 0 to +5V Unipolar Transfer Function
22
______________________________________________________________________________________
2 x VREF
4093
212
4095
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
1 LSB =
4 x VREF
212
which equals 2.44mV when using a 2.5V reference.
The input range is centered about VMSV. Normally, MSV
= AGND, and the input is symmetrical about zero. For a
custom midscale voltage, drive MSV with an external
voltage source. Noise present on MSV directly couples
into the ADC result. Use a precision, low-drift voltage
reference with adequate bypassing to prevent MSV
from degrading ADC performance. For maximum FSR,
do not violate the absolute maximum voltage ratings of
the analog inputs when choosing MSV.
Determine the input voltage as a function of V REF ,
VMSV, and the output code in decimal using:
VCH_ = LSB x CODE10 + VMSV
Table 4. ±5V Bipolar Code Table
DECIMAL
EQUIVALENT
DIGITAL OUTPUT
CODE
(CODE10)
0111 1111 1111 =
0x7FF
+2047
+4.9988 ± 0.5 LSB
0111 1111 1110 =
0x7FE
+2046
+4.9963 ± 0.5 LSB
0000 0000 0001 =
0x001
+1
+0.0037 ± 0.5 LSB
0000 0000 0000 =
0x000
0
+0.0012 ± 0.5 LSB
INPUT VOLTAGE
(V)
VREF = +2.5V
VMSV = 0
(
)
1111 1111 1111 =
0xFFF
-1
-0.0012 ± 0.5 LSB
1000 0000 0001 =
0x801
-2047
-4.9963 ± 0.5 LSB
1000 0000 0000 =
0x800
-2048
-4.9988 ± 0.5 LSB
4 x VREF
TWO'S COMPLEMENT BINARY OUTPUT CODE
TWO’s
COMPLEMENT
DIGITAL OUTPUT
CODE
0x7FF
0x7FE
0x7FD
0x7FC
0x001
0x000
0xFFF
0x803
0x802
0x801
0x800
1 LSB =
-2048 -2046
-1 0 +1
(MSV)
4 x VREF
212
+2045 +2047
INPUT VOLTAGE (VCH_ - VMSV IN LSBs)
Figure 9. ±5V Bipolar Transfer Function
______________________________________________________________________________________
23
MAX1307/MAX1311/MAX1315
Bipolar ±5V Devices
Table 4 and Figure 9 show the two’s complement transfer function for the ±5V input range MAX1311. The FSR is
four times the voltage at REF. The internal +2.5V reference gives a +10V FSR, while an external +2V to +3V
reference allows an FSR of +8V to +12V respectively.
Calculate the LSB size using:
Bipolar ±10V Devices
Table 5 and Figure 10 show the two’s complement transfer function for the ±10V input range MAX1315. The FSR
is eight times the voltage at REF. The internal +2.5V reference gives a +20V FSR, while an external +2V to +3V reference allows an FSR of +16V to +24V, respectively.
Calculate the LSB size using:
1 LSB =
8 x VREF
212
which equals 4.88mV with a +2.5V internal reference.
The input range is centered about V MSV. Normally,
MSV = AGND, and the input is symmetrical about zero.
For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV.
Determine the input voltage as a function of V REF ,
VMSV, and the output code in decimal using:
VCH_ = LSB x CODE10 + VMSV
Table 5. ±10V Bipolar Code Table
TWO’s
COMPLEMENT
DIGITAL OUTPUT
CODE
DECIMAL
EQUIVALENT
DIGITAL OUTPUT
CODE
(CODE10)
INPUT VOLTAGE
(V)
VREF = +2.5V
VMSV = 0
0111 1111 1111 =
0x7FF
+2047
+9.9976 ± 0.5 LSB
0111 1111 1110 =
0x7FE
+2046
+9.9927 ± 0.5 LSB
0000 0000 0001 =
0x001
+1
+0.0073 ± 0.5 LSB
0000 0000 0000 =
0x000
0
0.0024 ± 0.5 LSB
(
)
1111 1111 1111 =
0xFFF
-1
-0.0024 ± 0.5 LSB
1000 0000 0001 =
0x801
-2047
-9.9927 ± 0.5 LSB
1000 0000 0000 =
0x800
-2048
-9.9976 ± 0.5 LSB
8 x VREF
TWO'S COMPLEMENT BINARY OUTPUT CODE
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
0x7FF
0x7FE
0x7FD
0x7FC
0x001
0x000
0xFFF
0x803
0x802
0x801
0x800
1 LSB =
-2048 -2046
-1 0 +1
(MSV)
24
______________________________________________________________________________________
212
+2045 +2047
INPUT VOLTAGE (VCH_ - VMSV IN LSBs)
Figure 10. ±10V Bipolar Transfer Function
8 x VREF
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
High-frequency noise in the power supplies degrades
the ADC’s performance. Bypass the analog power
plane to the analog ground plane with a 2.2µF capacitor within one inch of the device. Bypass each AVDD to
AGND pair of pins with a 0.1µF capacitor as close to
the device as possible. AVDD to AGND pairs are pin 1
to pin 2, pin 14 to pin 15, and pin 16 to pin 17.
Likewise, bypass the digital power plane to the digital
ground plane with a 2.2µF capacitor within one inch of
the device. Bypass each DVDD to DGND pair of pins
with a 0.1µF capacitor as close to the device as possible. DVDD to DGND pairs are pin 24 to pin 25, and pin
38 to pin 39. If a supply is very noisy use a ferrite bead
as a lowpass filter as shown in Figure 11.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is drawn between the end points of the
transfer function, once offset and gain errors have
been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worstcase value is reported in the Electrical Characteristics
table. A DNL error specification of less than ±1 LSB
guarantees no missing codes and a monotonic
transfer function.
ANALOG SUPPLY
+5V
RETURN
DIGITAL
GROUND
POINT
DIGITAL SUPPLY
RETURN +3V TO +5V
OPTIONAL ANALOG
GROUND
FERRITE
POINT
BEAD
AVDD
AGND
MAX1307
MAX1311
MAX1315
DGND
DGND
DVDD
DATA
DVDD
DIGITAL
CIRCUITRY
Figure 11. Power-Supply Grounding and Bypassing
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Typically, the point at which
offset error is specified is either at or near the zeroscale point of the transfer function or at or near the midscale point of the transfer function.
For the unipolar devices (MAX1307), the ideal zero-scale
transition from 0x000 to 0x001 occurs at 1 LSB above
AGND (Figure 8, Table 3). Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point.
For the bipolar devices (MAX1311/MAX1315), the ideal
midscale transition from 0xFFF to 0x000 occurs at MSV
(Figures 9 and 10, Tables 4 and 5). The bipolar offset
error is the amount of deviation between the measured
midscale transition point and the ideal midscale transition point.
______________________________________________________________________________________
25
MAX1307/MAX1311/MAX1315
Layout, Grounding, and Bypassing
For best performance use PC boards. Board layout must
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and do not run
digital lines underneath the ADC package.
Figure 11 shows the recommended system ground connections. Establish an analog ground point at AGND and
a digital ground point at DGND. Connect all analog
grounds to the analog ground point. Connect all digital
grounds to the digital ground point. For lowest-noise
operation, make the power-supply ground returns as low
impedance and as short as possible. Connect the analog
ground point to the digital ground point at one location.
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
Gain Error
Signal-to-Noise Plus Distortion (SINAD)
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1307/
MAX1311/MAX1315, the gain error is the difference of
the measured full-scale and zero-scale transition points
minus the difference of the ideal full-scale and zeroscale transition points.
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
For the unipolar devices (MAX1307), the full-scale transition point is from 0xFFE to 0xFFF and the zero-scale
transition point is from 0x000 to 0x001.
For the bipolar devices (MAX1311/MAX1315), the fullscale transition point is from 0x7FE to 0x7FF and the
zero-scale transition point is from 0x800 to 0x801.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02dB × N + 1.76dB
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter.
For these devices, SNR is computed by taking the ratio
of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
26
⎛
SignalRMS
SINAD(dB) = 20 x log ⎜
2
2
⎜ Noise
RMS + DistortionRMS
⎝
⎞
⎟
⎟
⎠
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed as:
ENOB =
SINAD − 1.76
6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmonics to the fundamental itself. This is expressed as:
⎛ V22 + V32 + V 2 + V52 + V62 ⎞
4
THD = 20 x log ⎜
⎟
⎜
⎟
V1
⎝
⎠
where V1 is the fundamental amplitude, and V2 through
V 6 are the amplitudes of the 2nd- through 6thorder harmonics.
______________________________________________________________________________________
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so that the signal’s slew rate does not limit the
ADC’s performance. The input frequency is then swept
up to the point where the amplitude of the digitized
conversion result has decreased by -3dB.
Aperture Delay
Aperture delay (tAD) is the time delay from the CONVST
rising edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
aperture delay.
Jitter is a concern when considering an ADC’s dynamic
performance, e.g., SNR. To reconstruct an analog input
from the ADC digital outputs, it is critical to know the
time at which each sample was taken. Typical applications use an accurate sampling clock signal that has
low jitter from sampling edge to sampling edge. For a
system with a perfect sampling clock signal, with no
clock jitter, the SNR performance of an ADC is limited
by the ADC’s internal aperture jitter as follows:
⎛
⎞
1
SNR = 20 x log ⎜
⎟
⎝ 2 x π x fIN x tAJ ⎠
Full-Power Bandwidth
A large, -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
DC Power-Supply Rejection (PSRR)
DC PSRR is defined as the change in the positive fullscale transfer-function point caused by a ±5% variation
in the analog power-supply voltage (AVDD).
Chip Information
TRANSISTOR COUNT: 50,000
PROCESS: 0.6µm BiCMOS
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
______________________________________________________________________________________
27
MAX1307/MAX1311/MAX1315
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the
next-largest spurious component, excluding DC offset.
SFDR is specified in decibels relative to the carrier (dBc).
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
MAX1307/MAX1311/MAX1315
1075ksps, 12-Bit, Parallel-Output ADCs with
±10V, ±5V, and 0 to +5V Analog Input Ranges
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
21-0054
E
1
2
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
21-0054
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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