19-3900; Rev 1; 8/11
KIT
ATION
EVALU
E
L
B
AVAILA
+5V Multiprotocol, Software-Selectable
Clock Transceiver
Features
The MAX13172E is a four-driver/four-receiver multiprotocol transceiver that operates from a single +5V supply in
conjunction with the MAX13170E and MAX13174E. The
MAX13172E, along with the MAX13170E and the
MAX13174E, form a complete software-selectable data
terminal equipment (DTE) or data communication equipment (DCE) interface port that supports the V.28 (RS-232),
V.10/V.11 (RS-449/V.36, EIA-530, EIA-530A, X.21, RS423), and V.35 protocols. The MAX13172E transceiver
carries serial-interface control signaling, while the
MAX13170E carries the high-speed clock and data signals. Typically, the MAX13170E is terminated using the
MAX13174E.
The MAX13172E is available in a 5.3mm x 10.2mm, 28pin SSOP package and operates over the 0°C to +70°C
commercial temperature range.
o The MAX13170E/MAX13172E/MAX13174E Chipset
is a Pin-for-Pin Upgrade to the MXL1544/MAX3175/
MXL1543/MXL1543B Chipset
o Chipset Operates from a Single +5V Supply
o Software-Selectable DCE/DTE Configurations
o Supports V.28 (RS-232), V.10/V.11 (RS-449/V.36,
EIA-530, EIA-530A, X.21, RS-423) Protocols
o Flowthrough Pin Configuration
o Fail-Safe Receivers While Maintaining V.11 and
V.35 Compatibility
o Extremely Low Maximum Shutdown Current
(No-Cable Mode)
o TUV-Certified NET1/NET2 and TBR1/TBR2
Compliant (Pending)
o Extended ESD Protection for All Transmitter
Outputs and Receivers Inputs to GND
±10kV Using the Human Body Model
±3kV Using the Contact Method Specified in
IEC 61000-4-2
±3kV Using the Air Gap Discharge Method
Specified in IEC 61000-4-2
Applications
Data Networking
CSU/DSU Devices
Data Routers
Switches
PCI Cards
Telecommunication Equipment
Ordering Information
PART
TEMP RANGE
MAX13172ECAI+
0°C to +70°C
PIN-PACKAGE
28 SSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
T4
LL
CTS
DSR
R4
R3
R2
DCD
R1
MAX13172E T3
DTR
RTS
T2
T1
RXD
RXC
R3
R2
TXC
R1
MAX13170E T3
SCTE TXD
T2
T1
MAX13174E
18
13 5 10 8
22 6
23 20 19 4
1
7
16 3
9 17
12 15 11 24 14 2
TXD A (103)
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SG (102)
SHIELD (101)
RTS A (105)
RTS B
DTR A (108)
DTR B
DCD A (107)
DCD B
DSR A (109)
DSR B
CTS A (106)
CTS B
LL A (141)
DB-25 CONNECTOR
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX13172E
General Description
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
ABSOLUTE MAXIMUM RATINGS
Receiver Inputs
R_IN_, T_OUT_/R_IN_ ........................................-15V to +15V
R_INA to R_INB, T3OUTA/R1INA to
T3OUT/R1INB.....................................................-15V to +15V
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP
Single-Layer Board (derate 9.5mW/°C above +70°C) ......762mW
Multi-Layer Board (derate 14.9mW/°C above +70°C)........1194mW
Operating Temperature Range ................................0°C to 70°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
(All voltages referenced to GND, unless otherwise noted.)
Supply Voltages
VCC .......................................................................-0.3V to +6V
VDD ....................................................................-0.3V to +7.1V
VEE.....................................................................+0.3V to -7.1V
VDD to VCC ............................................................+0.3 to +6V
Logic Input Voltages
M0, M1, M2, DCE/DTE, T_IN, INVERT..................-0.3V to +6V
Logic Output Voltages
R_OUT ....................................................-0.3V to (VCC + 0.3V)
Transmitter Outputs
T_OUT_, T_OUT_/R_IN_ (No-Cable Mode,
V.28 only).........................................................-15V to +15V
Short-Circuit Duration to GND...............................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
SSOP
Junction-to-Ambient Thermal Resistance (θJA)...............+67°C/W
Junction-to-Case Thermal Resistance (θJC)......................+25°C/W
Note 1: Package thermal resistances were obtained using the method described in JESD51-7, using a four-layer board. For detailed
information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, TA = TMIN to TMAX. Typical values are at VCC = 5V, and TA = +25°C, V.28 mode only: VDD = +5.6V to +7.1V and
VEE = -7.1V to -5.4V. Typical values are at VDD = +6.9V and VEE = -6.7V, no-cable mode: VDD = VCC and VEE = 0V, other modes:
VDD = +5.15V to +5.7V and VEE = -4.84V to -4.16V. Typical value are at VDD = +5.3V and VEE = -4.5V.) (Notes 2, 3)
PARAMETER
VCC Operating Range
SYMBOL
VCC
VDD Operating Range
VDD
VEE Operating Range
VEE
VCC Supply Current (DCE Mode)
(Digital Inputs = GND or VCC)
(Transmitter Outputs Static)
CONDITIONS
ICC
2
PD
TYP
MAX
UNITS
V
4.5
5.5
V.28 mode
5.6
7.1
V.10 or V.11 mode
5.15
5.7
V.28 mode
-7.1
-5.4
V.10 or V.11 mode
-4.84
-4.16
CH1, CH3 = V.11, CH2 = V.10, CH4 = V.10,
no load
5.5
CH1, CH3 = V.11, CH2 = V.10, CH4 = V.10,
full load
95
135
CH1, CH2, CH3 = V.11, CH4 = V.10, full load
138
180
V.28 mode
3.5
9
0
10
No cable mode; M0, M1, M2, DCE/DTE,
INVERT, open or at VCC (VDD = VCC and
VEE = GND)
Internal Power Dissipation
(DCE Mode)
MIN
CH1, CH3 = V.11, CH2, CH4 = V.10, no load
300
V.28 mode, full load
54
_______________________________________________________________________________________
V
V
mA
µA
mW
+5V Multiprotocol, Software-Selectable
Clock Transceiver
(VCC = 4.5V to 5.5V, TA = TMIN to TMAX. Typical values are at VCC = 5V, and TA = +25°C, V.28 mode only: VDD = +5.6V to +7.1V and
VEE = -7.1V to -5.4V. Typical values are at VDD = +6.9V and VEE = -6.7V, no-cable mode: VDD = VCC and VEE = 0V, other modes:
VDD = +5.15V to +5.7V and VEE = -4.84V to -4.16V. Typical value are at VDD = +5.3V and VEE = -4.5V.) (Notes 2, 3)
PARAMETER
VEE Supply Current
SYMBOL
IEE
VDD Supply Current
IDD
Thermal-Shutdown Protection
CONDITIONS
MIN
TYP
CH1, CH3 = V.11, CH2 = V.10 or V.11,
CH4 = V.10, no load
2.1
CH1, CH2, CH3 = V.11, CH4 = V.10,
full load (output low)
13
MAX
UNITS
30
mA
CH1, CH3 = V.11, CH2, CH4 = V.10,
full load (output low)
22
30
V.28 mode, no load
1
V.28 mode, full load (output low)
12
18
No cable mode
(VDD = VCC and VEE = GND)
0
10
CH1, CH3 = V.11, CH2 = V.10 or V.11,
CH4 = V.10, no load
0.6
CH1, CH2, CH3 = V.11, CH4 = V.10,
full load (output high)
11
30
CH1, CH3 = V.11, CH2, CH4 = V.10, full
load (output high)
22
30
V.28 mode, no load
2.5
V.28 mode, full load (output high)
12
10
No cable mode
(VDD = VCC and VEE = GND)
0
10
µA
mA
THSD
+145
µA
°C
LOGIC INPUTS (M0, M1, M2, DCE/DTE, INVERT, T1IN, T2IN, T3IN, T4IN)
Input High Voltage
VIH
Input Low Voltage
VIL
Logic-Input Current
IIN
Pullup Resistor
RPUIN
0.66 x VCC
V
0.33 x VCC
T1IN, T2IN, T3IN, T4IN
-1
M0, M1, M2, DCE/DTE, INVERT to VCC
50
100
V
+1
µA
166
kΩ
LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT, R4OUT)
Output High Voltage
VOH
ISOURCE = 4mA
Output Low Voltage
VOL
ISINK = 4mA
Output Pullup Resistor
Transmitter Output Leakage
Current
RPUY
IZ
0.66 x VCC
V
0.33 x VCC
No cable mode (to VCC)
71.4
-0.25V < VOUT < +0.25V, VCC = 0V or no
cable mode
±1
V
kΩ
±5
µA
+VCC
V
V.11 TRANSMITTER
Open-Circuit Differential Output
Voltage
VODO
Loaded Differential Output
Voltage (Note 4)
|VODL|
Change in Magnitude of Output
Differential Voltage
∆VOD
Open circuit, R = 1.95kΩ, Figure 1
R = 50Ω, Figure 1
R = 50Ω, Figure 1
R = 50Ω, Figure 1
- VCC
0.5 x VODO
V
2
0.2
V
_______________________________________________________________________________________
3
MAX13172E
ELECTRICAL CHARACTERISTICS (continued)
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.5V to 5.5V, TA = TMIN to TMAX. Typical values are at VCC = 5V, and TA = +25°C, V.28 mode only: VDD = +5.6V to +7.1V and
VEE = -7.1V to -5.4V. Typical values are at VDD = +6.9V and VEE = -6.7V, no-cable mode: VDD = VCC and VEE = 0V, other modes:
VDD = +5.15V to +5.7V and VEE = -4.84V to -4.16V. Typical value are at VDD = +5.3V and VEE = -4.5V.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Common-Mode Output Voltage
VOC
R = 50Ω, Figure 1
3.0
V
Change in Magnitude of
Common-Mode Output Voltage
∆VOC
R = 50Ω, Figure 1
0.2
V
150
mA
Short-Circuit Current
ISC
VOUT = VGND
Rise Time
tR
Figures 2, 5
4
10
ns
Fall Time
tF
Figures 2, 5
6
10
ns
Transmitter Input-to-Output Prop
Delay
tPHL, tPLH
Figures 2, 5
22
ns
Data Skew
|tPHL-tPLH|
Figures 2, 5 (Note 5)
3
ns
Figures 2, 5 (Notes 5, 6)
3
ns
-50
mV
Output-to-Output Skew
tSKEWT
V.11 RECEIVER
Differential Threshold Voltage
VTH
-7V ≤ VCM ≤ +7V
Input Hysteresis
∆VTH
-7V ≤ VCM ≤ +7V
-200
15
Receiver Input Current
IIN
-10V ≤ VA,B ≤ +10V
-0.66
Receiver Input Resistance
RIN
-10V ≤ VA,B ≤ +10V
15
Rise or Fall Time
mV
+0.66
mA
30
kΩ
ns
tR, tF
Figures 2, 6
3
Receiver Input-to-Output Delay
tPHL, tPLH
Figures 2, 6
16
Data Skew
|tPHL-tPLH|
Figures 2, 6 (Note 5)
3.5
ns
(Notes 5, 6)
3.5
ns
Output-to-Output Skew
tSKEWR
26
ns
V.10 TRANSMITTER
Open-Circuit Output Voltage
Swing (Figure 3)
VO
Output Voltage Swing (Figure 3)
VT
RL = 3.9kΩ (out high)
4
6
RL = 3.9kΩ (out low)
-6
-4
RL = 450Ω (out high)
3.6
RL = 450Ω (out low)
RL = 450Ω
Short-Circuit Current
Rise or Fall Time
Transmitter Input-to-Output Delay
ISC
VO = VGND
V
-3.6
V
+55
mA
0.9 x |VO|
-55
tR, tF
RL = 450Ω, CL =100pF (Figure 7)
2
µs
tPLH, tPHL
RL = 450Ω, CL =100pF (Figure 7)
1
µs
V.10 RECEIVER
Input Threshold Voltage
VTH
Input Hysteresis
∆VTH
Measured on inverting input (A)
50
250
25
Receiver Input Current
IIN
-10V ≤ VA ≤ +10V
-0.66
Receiver Input Impedance
RIN
-10V ≤ VA ≤ +10V
15
mV
mV
+0.66
mA
30
kΩ
Rise or Fall Time
tR, tF
Figures 4, 8
3
ns
Receiver Input-to-Output Delay
from Low to High
tPLH
Figures 4, 8
55
ns
Receiver Input-to-Output Delay
from High to Low
tPHL
Figures 4, 8
109
ns
|tPHL-tPLH|
Figures 4, 8
60
ns
Data Skew
4
_______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
(VCC = 4.5V to 5.5V, TA = TMIN to TMAX. Typical values are at VCC = 5V, and TA = +25°C, V.28 mode only: VDD = +5.6V to +7.1V and
VEE = -7.1V to -5.4V. Typical values are at VDD = +6.9V and VEE = -6.7V, no-cable mode: VDD = VCC and VEE = 0V, other modes:
VDD = +5.15V to +5.7V and VEE = -4.84V to -4.16V. Typical value are at VDD = +5.3V and VEE = -4.5V.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V.28 TRANSMITTER
Open circuit (output high)
Output-Voltage Swing
VOD
Open circuit (output low)
RL = 3kΩ
Short-Circuit Current
Output Slew Rate
Transmitter Input-to-Output
Propagation Delay
Output high
VDD
VEE
+5
Output low
-6.8
|ISC|
SRR/F
RL = 3kΩ, CL = 2500pF, Figures 3, 9
tPHL, tPLH
RL = 3kΩ, CL = 2500pF, Figures 3, 9
V
+6.8
4
1
-5
85
mA
30
V/µs
2
µs
2
V
7
kΩ
V.28 RECEIVER
Input Threshold Low
VIL
Input Threshold High
VIH
0.8
Input Hysteresis
VHyst
Input Resistance
RIN
Rise or Fall Time
tR, tF
Figures 4, 10
tPHL, tPLH
Figures 4, 10
Receiver Input-to-Output Delay
V
0.25
-15V ≤ VIN ≤ +15V
3
5
V
3
ns
150
ns
ESD PROTECTION (T_OUT_, T_OUT_/R_OUT_, R_IN_ to GND)
Contact Discharge IEC61000-4-2
ESD Protection
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
+3
Air Gap Discharge IEC61000-4-2
±3
Human Body Model
±10
kV
The MAX13172E is designed to operate with VDD and VEE supplied by the MAX13170E charge pump.
All devices are 100% production tested at TA = +25°C, and are guaranteed by design for TA = 0°C to +70°C as specified.
|VODL| is guaranteed at both 0.5 x VODO and 2V.
Guaranteed by design, not production tested.
Ouput-to-output skews are evaluated as a difference of propagation delays between different channels in the same condtion
and for the same polarity (LH or HL).
_______________________________________________________________________________________
5
MAX13172E
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
FULL LOAD, R = 50Ω
100
50
6
4
0
0
10
100
1,000 10,000 100,000
1
10
100
0.1
1,000 10,000 100,000
1
10
100
1,000 10,000 100,000
DATA RATE (kbps)
DATA RATE (kbps)
V.28 MODE SUPPLY CURRENT (ICC)
vs. DATA RATE
V.28 MODE SUPPLY CURRENT (IDD)
vs. DATA RATE
V.28 MODE SUPPLY CURRENT (IEE)
vs. DATA RATE
DCE MODE, INVERT = 0
ALL TRANSMITTERS OPERATING
AT THE SPECIFIED DATA RATE
16
20
MAX13172E toc05
20
MAX13172E toc06
DATA RATE (kbps)
DCE MODE, INVERT = 0
ALL TRANSMITTERS OPERATING
AT THE SPECIFIED DATA RATE
5
0.1
MAX13172E toc04
6
1
FULL LOAD, R = 50Ω
NO LOAD, R = 1.95kΩ
4
2
FULL LOAD, R = 50Ω
NO LOAD, R = 1.95kΩ
NO LOAD, R = 1.95kΩ
0.1
DCE MODE, INVERT = 0
ALL TRANSMITTERS OPERATING
AT THE SPECIFIED DATA RATE
8
6
2
0
10
MAX13172E toc03
8
IDD (mA)
ICC (mA)
150
DCE MODE, INVERT = 1
ALL TRANSMITTERS OPERATING
AT THE SPECIFIED DATA RATE
IEE (mA)
DCE MODE, INVERT = 1
ALL TRANSMITTERS OPERATING
AT THE SPECIFIED DATA RATE
200
10
MAX13172E toc01
250
V.11 MODE SUPPLY CURRENT (IEE)
vs. DATA RATE
V.11 MODE SUPPLY CURRENT (IDD)
vs. DATA RATE
MAX13172E toc02
V.11 MODE SUPPLY CURRENT (ICC)
vs. DATA RATE
DCE MODE, INVERT = 0
ALL TRANSMITTERS OPERATING
AT THE SPECIFIED DATA RATE
16
FULL LOAD (RL = 3kΩ, CL = 2500pF)
AND NO LOAD
12
IEE (mA)
3
IDD (mA)
ICC (mA)
4
FULL LOAD, RL = 3kΩ,
CL = 2500pF
8
12
FULL LOAD, RL = 3kΩ,
CL = 2500pF
8
2
0
0
0
0
50
100
150
200
250
150
200
50
100
150
200
250
V.10 RATIO OF LOADED/UNLOADED
OUTPUT VOLTAGE vs. TEMPERATURE
6
-2
-3
2
DCE MODE,
VDD = +5.3V,
VEE = -4.5V
0
-2
RL = 450Ω
VOUT-
-4
20
30
40
50
TEMPERATURE (°C)
60
70
VOUT-
0.90
0.88
0.84
0.82
0.80
-10
10
0.92
0.86
RL = 3.9kΩ
-8
-5
VOUT+
0.94
-6
VOUT-
-4
0.96
VOUT+
4
DCE MODE,
VDD = +5.3V,
VEE = -4.5V
0.98
RATIO (V/V)
OUTPUT VOLTAGE (V)
DCE MODE,
INVERT = 1,
R = 50Ω
RL = 3.9kΩ
8
1.00
MAX13172E toc08
MAX13172E toc07
10
MAX13172E toc09
V.10 OUTPUT VOLTAGE
vs. TEMPERATURE
2
0
0
250
V.11 LOADED DRIVER DIFFERENTIAL
OUTPUT VOLTAGE vs. TEMPERATURE
3
-1
100
DATA RATE (kbps)
VOUT+
0
50
DATA RATE (kbps)
4
1
0
DATA RATE (kbps)
5
6
4
4
1
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
0
10
20
30
40
50
TEMPERATURE (°C)
60
70
0
10
20
30
40
50
TEMPERATURE (°C)
_______________________________________________________________________________________
60
70
+5V Multiprotocol, Software-Selectable
Clock Transceiver
V.11 RECEIVER INPUT CURRENT
vs. INPUT VOLTAGE
DCE MODE,
R = 3kΩ,
VDD = +6.9V,
VEE = -6.7V
2
0
-2
-4
VOUT-
200
4
3
R1IN_
100
0
R2IN_, R3IN_
-100
-200
2
1
0
-1
-2
-300
-3
-8
-400
-4
-10
-500
-6
20
30
40
50
60
-5
0
5
10
-15
-10
-5
0
5
10
15
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
V.28 SLEW RATE
vs. LOAD CAPACITANCE
V.10 TEANSMITTER RISE/FALL TIME
vs. LOAD CAPACITANCE
LOOPBACK SCOPE SHOT PHOTO V.11
MODE (UNLOADED)
RL = 3kΩ
30
2.0
20
SRF
SRR
10
MAX13172E toc15
VDD = +5.3V,
VEE = -4.5V
1.6
RISE/FALL TIME (µs)
25
15
-5
-10
70
MAX13172E toc14
35
10
MAX13172E toc13
0
SLEW RATE (V/µs)
5
INPUT CURRENT (mA)
4
DTE MODE
300
INPUT CURRENT (µA)
OUTPUT VOLTAGE (V)
VOUT+
400
MAX13172E toc11
8
6
500
MAX13172E toc10
10
V.28 RECEIVER INPUT CURRENT
vs. INPUT VOLTAGE
MAX13172E toc12
V.28 LOADED OUTPUT VOLTAGE
vs. TEMPERATURE
TIN
5V/div
TOUT/RIN
5V/div
ROUT
5V/div
FALL
1.2
RISE
0.8
0.4
5
0
0
0 500 1K 1.5K 2K 2.5K 3K 3.5K 4K 4.5K 5K
0 100 200 300 400 500 600 700 800 900 1,000
LOAD CAPACITANCE (pF)
10ns/div
LOAD CAPACITANCE (pF)
LOOPBACK SCOPE SHOT PHOTO V.28
MODE (LOADED)
LOOPBACK SCOPE SHOT PHOTO V.10
MODE (LOADED)
MAX13172E toc16
MAX13172E toc17
RL = 3kΩ, CL = 2500pF
TIN
5V/div
TIN
5V/div
RL = 3.9kΩ
TOUT/RIN
5V/div
TOUT/RIN
ROUT
5V/div
ROUT
1µs/div
MAX13172E
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
RL = 450Ω
5V/div
5V/div
4µs/div
_______________________________________________________________________________________
7
+5V Multiprotocol, Software-Selectable
Clock Transceiver
MAX13172E
Pin Description
PIN
FUNCTION
1
VCC
Device Supply Voltage. Bypass VCC with a 1µF capacitor-to-ground as close as possible to the
device.
2
VDD
Positive Supply Voltage Input. VDD is generated by the MAX13170E. Bypass VDD with a 1µF capacitor
to ground.
3
T1IN
Transmitter 1 Logic Input
4
T2IN
Transmitter 2 Logic Input
5
T3IN
Transmitter 3 Logic Input
6
R1OUT
Receiver 1 Logic Output
7
R2OUT
Receiver 2 Logic Output
8
R3OUT
Receiver 3 Logic Output
9
T4IN
Transmitter 4 Logic input
10
R4OUT
Receiver 4 Logic Output
11
M0
Mode Select 0 Input. Internally pullup to VCC.
12
M1
Mode Select 1 Input. Internally pullup to VCC.
13
M2
Mode Select 2 Input. Internally pullup to VCC.
14
DCE/DTE
15
INVERT
16
T4OUTA/
R4INA
17
R3INB
Receiver 3 Noninverting Input
18
R3INA
Receiver 3 Inverting Input
19
R2INB
Receiver 2 Noninverting Input
20
R2INA
Receiver 2 Inverting Input
21
T3OUTB/
R1INB
Transmitter 3 Noninverting Output/Receiver 1 Noninverting Input
22
T3OUTA/
R1INA
Transmitter 3 Inverting Output/Receiver 1 Inverting Input
23
T2OUTB
Transmitter 2 Noninverting Output
DCE/DTE Input. Internally pullup to VCC. Logic level high selects DCE interface.
T4/R4 Select Input. Internally pullup to VCC. INVERT reverses the action of DCE/DTE for Channel 4.
Transmitter 4 Inverting Output/Receiver 4 Inverting Input
24
T2OUTA
Transmitter 2 Inverting Output
25
T1OUTB
Transmitter 1 Noninverting Output
26
T1OUTA
Transmitter 1 Inverting Output
27
GND
Ground
VEE
Negative Supply Input. VEE is generated by the MAX13170E. Bypass VEE with a 1µF capacitor to
ground.
28
8
NAME
_______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
T
A
R
VOD
VO
RL
VOC
R
Figure 3. V.10/V.28 Transmitter Test Circuit
Figure 1. V.11 DC Test Circuit
100pF
T
CL
B
B
T
A
R
R
100Ω
A
A
15pF
15pF
100pF
Figure 2. V.11 AC Test Circuit
Detailed Description
The MAX13172E is a four-driver/four-receiver, multiprotocol transceiver that operates from a single +5V supply. The charge pump operates from the MAX13170E.
The MAX13172E along with the MAX13170E and
MAX13174E, form a complete software-selectable
DTE or DCE interface port that supports the V.28
(RS-232), V.10/V.11 (RS-449/V.36, EIA-530, EIA-530A,
X.21, RS-423), and V.35 protocols. The MAX13172E
usually carries the control signals. The MAX13170E carries the high-speed clock and data signals, and the
MAX13174E provides termination for the clock and data
signals.
The MAX13172E features an ultra-low supply current
no-cable mode, fail-safe operation, and thermal-shut-
Figure 4. V.10/V.28 Receiver Test Circuit
down circuitry. Thermal shutdown protects the transmitter and receiver outputs against excessive power dissipation. When activated, the thermal-shutdown circuitry
places the driver outputs into a high-impedance state.
The state of the mode-select inputs M0, M1, and M2
determines which serial-interface protocol is selected
(Table 1). The state of the DCE/DTE input determines
whether the transceivers are configured as a DTE serial
port or a DCE serial port. When the DCE/DTE input is
logic-high, driver T3 is activated and receiver R1 is disabled. When the DCE/DTE input is logic-low, driver T3
disabled and receiver R1 is activated. The INVERT
input state changes the DCE/DTE functionality regarding T4 and R4 only. M0, M1, M2, INVERT, and
DCE/DTE are internally pulled up to V CC to ensure
logic-high if left unconnected.
_______________________________________________________________________________________
9
MAX13172E
Test Circuits
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
Switching Time Waveforms
VCC
TIN_
f = 1MHz: tr, tf ≤ 1ns
VCC/2
0
VCC/2
tPHL
tPLH
V0
A-B
50%
-V0
90%
90%
10%
50%
10%
tF
tR
Figure 5. V.11 Transmitter Propogation Delays
+1V
f = 1MHz: tr, tf ≤ 1ns
0
A -B
INPUT
0
-1V
tPLH
tPHL
V0H
90%
VCC/2
R
V0L
OUTPUT
10%
90%
VCC/2
10%
tF
tR
Figure 6. V.11 Receiver Propagation Delays
VCC
TIN_
0
V0H
tR, tF ≤ 10ns
VCC/2
VCC/2
tPHL
tPLH
90%
90%
0
0
A
10%
10%
-V0L
tR
tF
Figure 7. V.10 Transmitter Propagation Delays
VIH
A
VIL
tR, tF ≤ 10ns
0
tPLH
tPHL
V0H
R
V0L
0
90%
VCC/2
10%
tF
90%
10%
VCC/2
tR
Figure 8. V.10 Receiver Propogation Delays
10
______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
VCC
TIN_
0
tR, tF ≤ 10ns
VCC/2
VCC/2
tPHL
V0H
tPLH
3V
3V
0
0
A
-3V
-3V
-V0L
SRF = 6/tF
tF
tR
SRR = 6/tR
Figure 9. V.28 Transmitter Propagation Delays
(2.0V) VIH
A
(-0.3V) VIL
tR, tF ≤ 10ns
1.3V
1.3V
tPLH
tPHL
V0H
R
V0L
90%
VCC/2
90%
10%
10%
VCC/2
tR
tF
Figure 10. V.28 Receiver Propogation Delays
Table 1. Mode Select Table
M2
M1
M0
DCE/
DTE
INVERT
T1
T2
T3
R1
R2
R3
T4
R4
Not Used
(Default V.11)
0
0
0
0
0
V.11
V.11
Z
V.11
V.11
V.11
Z
V.10
RS-530A
0
0
1
0
0
V.11
V.10
Z
V.11
V.10
V.11
Z
V.10
RS-530
0
1
0
0
0
V.11
V.11
Z
V.11
V.11
V.11
Z
V.10
X.21
0
1
1
0
0
V.11
V.11
Z
V.11
V.11
V.11
Z
V.10
PROTOCOL
V.35
1
0
0
0
0
V.28
V.28
Z
V.28
V.28
V.28
Z
V.28
RS-449/V.36
1
0
1
0
0
V.11
V.11
Z
V.11
V.11
V.11
Z
V.10
V.28/RS-232
1
1
0
0
0
V.28
V.28
Z
V.28
V.28
V.28
Z
V.28
No Cable
1
1
1
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Not Used
(Default V.11)
0
0
0
0
1
V.11
V.11
Z
V.11
V.11
V.11
V.10
Z
RS-530A
0
0
1
0
1
V.11
V.10
Z
V.11
V.10
V.11
V.10
Z
RS-530
0
1
0
0
1
V.11
V.11
Z
V.11
V.11
V.11
V.10
Z
X.21
0
1
1
0
1
V.11
V.11
Z
V.11
V.11
V.11
V.10
Z
V.35
1
0
0
0
1
V.28
V.28
Z
V.28
V.28
V.28
V.28
Z
RS-449/V.36
1
0
1
0
1
V.11
V.11
Z
V.11
V.11
V.11
V.10
Z
V.28/RS-232
1
1
0
0
1
V.28
V.28
Z
V.28
V.28
V.28
V.28
Z
No Cable
1
1
1
0
1
Z
Z
Z
Z
Z
Z
Z
Z
______________________________________________________________________________________
11
MAX13172E
Switching Time Waveforms (continued)
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
Table 1. Mode Select Table (continued)
PROTOCOL
Not Used
(Default V.11)
RS-530A
RS-530
X.21
V.35
RS-449/V.36
V.28/RS-232
No Cable
Not Used
(Default V.11)
RS-530A
M2
M1
M0
DCE/
DTE
INVERT
T1
T2
T3
R1
R2
R3
T4
R4
0
0
0
1
0
V.11
V.11
V.11
Z
V.11
V.11
V.10
Z
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
V.11
V.11
V.11
V.28
V.11
V.28
Z
V.10
V.11
V.11
V.28
V.11
V.28
Z
V.11
V.11
V.11
V.28
V.11
V.28
Z
Z
Z
Z
Z
Z
Z
Z
V.10
V.11
V.11
V.28
V.11
V.28
Z
V.11
V.11
V.11
V.28
V.11
V.28
Z
V.10
V.10
V.10
V.28
V.10
V.28
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
1
1
V.11
V.11
V.11
Z
V.11
V.11
Z
V.10
0
0
1
1
1
V.11
V.10
V.11
Z
V.10
V.11
Z
V.10
RS-530
0
1
0
1
1
V.11
V.11
V.11
Z
V.11
V.11
Z
V.10
X.21
0
1
1
1
1
V.11
V.11
V.11
Z
V.11
V.11
Z
V.10
V.35
1
0
0
1
1
V.28
V.28
V.28
Z
V.28
V.28
Z
V.28
RS-449/V.36
1
0
1
1
1
V.11
V.11
V.11
Z
V.11
V.11
Z
V.10
V.28/RS-232
1
1
0
1
1
V.28
V.28
V.28
Z
V.28
V.28
Z
V.28
No Cable
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
The MAX13172E’s mode can be selected through software control of the M0, M1, M2, INVERT, and DCE/DTE
inputs. Alternatively, the mode can be selected by
shorting the appropriate combination of mode control
inputs to GND (the inputs left unconnected will be internally pulled up to VCC - logic-high). If the M0, M1, and
M2 mode inputs are all unconnected, the MAX13172E
will enter no-cable mode.
Fail-Safe
The MAX13172E guarantees a logic-high receiver output when the receiver inputs are open or shorted, or
when they are connected to a terminated transmission
line with all the drivers disabled. The V.11 receivers
threshold is set between -200mV and -50mV to guarantee fail-safe operation. If the differential receiver input
voltage (B - A) is ≥ -50mV, ROUT is logic-high. In the
case of a terminated bus with all transmitters disabled,
the receiver’s differential input voltage is pulled to 0 by
the termination. With the receiver thresholds of the
MAX13172E, this results in ROUT logic-high.
The V.10 receiver threshold is set between +50mV and
+250mV. If the V.10 receiver input voltage is less than or
equal to +50mV, ROUT is logic-high. The V.28 receiver
threshold is set between 0.8V and 2.0V. If the receiver input
voltage is less than or equal to 0.8V, ROUT is logic-high. In
the case of a terminated bus with transmitters disabled, the
receiver’s input voltage is pulled to 0 by the termination.
12
ESD Protection
As with all Maxim devices, a minimum of ±2kV-to-GND
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The driver outputs and
receiver inputs of the MAX13172E have extra protection
against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins
against ESD of ±10kV without damage (HBM). The ESD
structures withstand high ESD in all states: normal
operation, shutdown, and powered down. After an ESD
event, the MAX13172E keeps working without latchup
or damage. ESD protection can be tested in various
ways. The transmitter outputs and receiver inputs of the
MAX13172E are characterized for protection to the following limits:
•
•
•
±10kV using the Human Body Model
±3kV using the Contact Method specified in IEC
61000-4-2
±3kV using the Air Gap Discharge Method specified in IEC 61000-4-2
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
CHARGE-CURRENT
LIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
RD
1500Ω
RC
50MΩ TO 100MΩ
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
Figure 11a. Human Body ESD Test Model
IP 100%
90%
Cs
150pF
RD
330Ω
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 11c. IEC 61000-4-2 ESD Test Model
I
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
IPEAK
Ir
HIGHVOLTAGE
DC
SOURCE
MAX13172E
RC
1MΩ
AMPS
36.8%
10%
0
10%
0
tRL
TIME
tDL
CURRENT WAVEFORM
tr = 0.7ns TO 1ns
t
30ns
60ns
Figure 11b. Human Body Current Waveform
Figure 11d. IEC 61000-4-2 ESD Generator Current Waveform
Human Body Model
Figure 11a shows the Human Body Model, and Figure
11b shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
The major difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2 because series resistance is
lower in the IEC 61000-4-2 model. Hence, the ESD withstand voltage measured to IEC 61000-4-2 is generally
lower than that measured using the Human Body
Model. Figure 11c shows the IEC 61000-4-2 model, and
Figure 11d shows the current waveform for the IEC
61000-4-2 ESD Contact Discharge test.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. However, it
does not specifically refer to integrated circuits.
The MAX13172E helps equipment designs meet IEC
61000-4-2, without the need for additional ESD-protection components.
______________________________________________________________________________________
13
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
Applications Information
Cable-Selectable Configuration
Application
A cable-selectable, multiprotocol DTE/DCE interface is
shown in Figure 12. The mode control lines M0, M1,
and DCE/DTE are wired to the DB-25 connector. To
select the serial-interface mode, the appropriate combination of M0, M1, M2, and DCE/DTE are grounded within the cable wiring. The control lines that are not
grounded are pulled high by the internal pullups on the
MAX13170E. The serial-interface protocol of the
MAX13172E is now selected based on the cable that is
connected to the DB-25 interface.
V.10 (RS-423) Interface
The V.10 interface (Figure 13) is an unbalanced singleended interface capable of driving a 450Ω load. The
V.10 driver generates a minimum VO voltage of ±4V
across A’ and C’ when unloaded and a minimum voltage of 0.9 V O when loaded with 450Ω. The V.10
receiver has a single-ended input and does not reject
common-mode differences between C and C’. The V.10
receiver input trip threshold is defined between
+250mV and -250mV with input impedance characteristic shown in Figure 14.
The MAX13172E V.10 mode receiver has a threshold
between +50mV and +250mV. To ensure that the
receiver has proper fail-safe operation see the Fail-Safe
section. To aid in rejecting system noise, the
MAX13172E V.10 receiver has a typical hysteresis of
25mV. Switch S3 in Figures 16a and 16b is open in
V.10 mode to disable the V.28 5kΩ termination at the
receiver input. Switch S2 is closed and switch S1 is
open to internally ground the receiver B input.
V.11 (RS-422) Interface
As shown in Figure 15, the V.11 protocol is a fully balanced differential interface. The V.11 driver generates a
minimum of ±2V between nodes A and B when 100Ω
minimum resistance is presented at the load. The V.11
receiver is sensitive to differential signals of ±200mV at
receiver inputs A’ and B’. The V.11 receiver input must
comply with the impedance curve of Figure 14 and reject
common-mode signals developed across the cable
(referenced from C to C’ in Figure 15) of up to ±7V.
The MAX13172E V.11 mode receiver has a differential
threshold between -50mV and -200mV. To ensure that
the receiver has proper fail-safe operation; see the FailSafe section. To aid in rejecting system noise, the
MAX13172E V.11 receiver has a typical hysteresis of
15mV. Switch S3 in Figure 17 is open in V.11 mode to
14
disable the V.28 5kΩ termination at the inverting receiver input. Because the control signals are slow (60kbps),
100Ω termination resistance is generally not required for
the MAX13172E. The receiver inputs must also be compliant with the impedance curve shown in Figure 14.
V.28 (RS-232) Interface
The V.28 interface is an unbalanced single-ended interface (Figure 13). The V.28 generator provides a minimum of ±5V across the 3kΩ load impedance between
A’ and C’. The V.28 receiver has a single-ended input.
The MAX13172E V.28 mode receiver has a threshold
between +0.8V and +2.0V. To aid in rejecting system
noise, the MAX13172E V.28 receiver has a typical hysteresis of 0.25V. Switch S3 in Figures 18a and 18b is
closed in V.28 mode to enable the 5kΩ V.28 termination
at the receiver inputs.
No-Cable Mode
The MAX13172E will enter no-cable mode when the
mode-select pins are left unconnected or connected
high (M0 = M1 = M2 = 1). In this mode, the multiprotocol drivers and receivers are disabled and the supply
current is less than 10µA. The receiver outputs enter a
high-impedance state in no-cable mode, which allows
these output lines to be shared with other receiver outputs (the receiver outputs have an internal pullup resistor to pull the outputs high if not driven). Also, in
no-cable mode, the transmitter outputs enter a highimpedance state, so these output lines can be shared
with other devices.
DTE vs. DCE Operation
Figure 19 shows a port with one DB-25 connector that
can be configured for either DTE or DCE operation. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. Figures 20 and 21
illustrates a DCE or DTE controller-selectable interface.
The DCE/DTE and INVERT inputs switch the port’s
mode of operation (Table 1).
The MAX13170E and MAX13172E can be connected
for either DTE or DCE operation in one of two ways: a
dedicated DTE or DCE port with an appropriate gender
connector or a port with a connector that can be configured for DTE or DCE operation by rerouting the signals
to the MAX13170E and MAX13172E using a dedicated
DTE cable or dedicated DCE cable. The interface mode
is selected by logic outputs from the controller or from
jumpers to either VCC or GND on the mode select pins.
A dedicated DCE port using a DB-25 female connector
is shown in Figure 20. Figure 21 illustrates a dedicated
DTE port using a DB-25 male connector.
______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
MAX13172E
C6
C7 C8
100pF 100pF 100pF
3
8
11
12 13
VCC
5V
MAX13174E
14
27
26
CHARGE
PUMP
2
4
25
C4
4.7µF
DTE_TXD/DCE_RXD
5
DTE_SCTE/DCE_RXC
6
T2
7
R1
9
DTE_RXC/DCE_SCTE
R2
10
DTE_RXD/DCE_TXD
VEE
C12
1µF
5 4
6 7
9 10 16 15 18 17 19 20 22 23 24 1
VCC
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
DCE
RXD A
RXD B
RXC A
RXC B
20
19
15
12
TXC A
TXC B
18
17
16
15
17
9
T3
8
DTE_TXC/DCE_TXC
2
C5
4.7µF
24
23
22
21
T1
21
M0
1
C1
1µF
LATCH
C2
1µF
DCE/DTE
M2
M1
C3
4.7µF
C13
1µF
28
3
VCC
R3
3
16
7
MAX13170E
M0
12
M1
13
M2
14
DCE/DTE
TXC A
TXC B
RXC A SCTE A
RXC B SCTE B
RXD A TXD A
RXD B TXD B
SG
11
NC
1
SHIELD
DB-25
CONNECTOR
C9
1µF
VCC
1
C10
1µF
2
3
DTE_RTS/DCE_CTS
4
DTE_DTR/DCE_DSR
5
6
DTE_DCD/DCE_DCD
7
DTE_DSR/DCE_DTR
8
DTE_CTS/DCE_RTS
10
9
28
VCC
VEE
VDD
GND
T1
T2
27
25
DCE/DTE
21
M1
18
M0
4
RTS A CTS A
19 RTS B CTS B
20
DTR A DSR A
23
DTR B DSR B
26
25
24
23
T3
R1
R2
R3
R4
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13 CTS B
22
21
20
19
18
17
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
16
T4
MAX13172E
M0
12
M1
13
M2
14
15
DCE/DTE INVERT
11
NC
C11
1µF
CABLE WIRING FOR
MODE SELECTION
PIN 18
PIN 7
V.35
RS-449. V.36 N.C.
PIN 7
RS-232
MODE
CABLE WIRING FOR
DTE/DCE SELECTION
PIN 21
PIN 7
MODE PIN 25
PIN 7
DTE
PIN 7
N.C.
DCE
N.C.
Figure 12. Cable-Selectable Multiprotocol DTE/DCE Port
______________________________________________________________________________________
15
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
UNBALANCED
INTERCONNECTING
CABLE
GENERATOR
LOAD
CABLE
TERMINATION
A
A′
C
C′
RECEIVER
Figure 13. Typical V.10/V.28 Interface
IZ
GENERATOR
3.25mA
-3V
-10V
100Ω
MIN
-3.25mA
Figure 14. Receiver Input Impedance Curve
A′
B′
C′
A
MAX13172E
R5
55kΩ
R8
5kΩ
B
C
Figure 15. Typical V.11 Interface
A′
A
MAX13172E
R5
55kΩ
R8
5kΩ
R6
11kΩ
LOAD
CABLE
RECEIVER
TERMINATION
A′
A
VZ
+10V
+3V
BALANCED
INTERCONNECTING
CABLE
RECEIVER
S3
R6
11kΩ
RECEIVER
S3
+
1.4V
R7
11kΩ
B′
R4
55kΩ
B
S1
S2
C′
GND
Figure 16a. V.10 Internal Resistance Network for Receivers 1, 2,
and 3
16
C′
GND
Figure 16b. V.10 Internal Resistance Network for Receiver 4
______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
A
A′
R8
5kΩ
A
MAX13172E
R5
55kΩ
R6
11kΩ
RECEIVER
S3
+
1.4V
1.4V
R7
11kΩ
R4
55kΩ
B
R7
11kΩ
S1
B′
S2
C′
R4
55kΩ
B
S1
S2
C′
GND
GND
Figure 17. V.11 Internal Resistance Networks
A′
RECEIVER
S3
+
B′
MAX13172E
R5
55kΩ
R8
5kΩ
R6
11kΩ
MAX13172E
A′
Figure 18a. V.28 Internal Resistance Network for Receiver 1, 2,
and 3
A
MAX13172E
R5
55kΩ
R8
5kΩ
R6
11kΩ
RECEIVER
S3
C′
GND
Figure 18b. V.28 Internal Resistance Network for Receiver 4
______________________________________________________________________________________
17
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
C6
C7 C8
100pF 100pF 100pF
3
8
11
VCC
5V
12 13
MAX13174E
14
25
C4
4.7µF
DTE_TXD/DCE_RXD
5
DTE_SCTE/DCE_RXC
6
T2
7
C12
1µF
5 4
6 7
9 10 16 15 18 17 19 20 22 23 24 1
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
15
12
17
9
18
17
16
15
R2
10
DTE_RXD/DCE_TXD
VEE
20
19
R1
9
DTE_RXC/DCE_SCTE
+
DCE
RXD A
RXD B
RXC A
RXC B
T3
8
DTE_TXC/DCE_TXC
2
C5
4.7µF
24
23
22
21
T1
21
M0
27
26
CHARGE
PUMP
2
4
LATCH
C2
1µF
M1
1
C1
1µF
VCC
DCE/DTE
M2
C3
4.7µF
C13
1µF
28
3
R3
3
16
7
MAX13170E
M0
M1
13
M2
14
DCE/DTE
TXC A
TXC B
TXC A
TXC B
RXC A SCTE A
RXC B SCTE B
RXD A TXD A
RXD B TXD B
SG
11
12
1
SHIELD
DB-25
CONNECTOR
C9
1µF
C10
1µF
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
VCC
1
2
3
4
5
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
6
7
8
10
9
28
VCC
VEE
VDD
GND
T1
T2
27
C11
1µF
26
25
24
23
4
RTS A
19 RTS B
20
DTR A
23
DTR B
22
21
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13 CTS B
18
LLA
DSR A
DSR B
T3
R1
R2
R3
R4
20
19
18
17
16
T4
MAX13172E
M0
12
15
M1
INVERT
13
M2
14
DCE/DTE
11
INVERT
DCE/DTE
M2
M1
M0
Figure 19. Controller-Selectable Multiprotocol DCE/DTE Port with DB-25 Connector
18
CTS A
CTS B
______________________________________________________________________________________
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
LLA
+5V Multiprotocol, Software-Selectable
Clock Transceiver
MAX13172E
C6
C7 C8
100pF 100pF 100pF
3
8
VCC
5V
11
12 13
MAX13174E
14
27
26
CHARGE
PUMP
2
4
25
C4
4.7µF
RXD
5
RXC
6
T2
VEE
C12
1µF
5 4
6 7
9 10 16 15 18 17 19 20 22 23 24 1
VCC
3
16
17
9
15
12
24
11
18
17
16
15
R2
10
TXD
+
20
19
R1
9
SCTE
21
RXD A (104)
RXD B
RXC A (115)
RXC B
T3
8
TXC
2
C5
4.7µF
24
23
22
21
T1
7
LATCH
C2
1µF
M0
1
C1
1µF
VCC
DCE/DTE
M2
M1
C3
4.7µF
C13
1µF
28
3
R3
2
14
7
MAX13170E
M0
M1
13
M2
14
DCE/DTE
TXC A (114)
TXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
SGND (102)
11
12
C9
1µF
C10
1µF
DSR
VCC
1
3
4
5
DCD
DTR
RTS
LL
SHIELD (101)
DB-25
FEMALE
CONNECTOR
2
CTS
1
6
7
8
10
9
28
VCC
VEE
VDD
GND
T1
T2
27
C11
1µF
26
25
24
23
5
13
6
22
22
21
8
10
20
19
18
17
20
23
4
19
16
18
CTS A (106)
CTS B
DSR A (107)
DSR B
T3
R1
R2
R3
R4
DCD A (109)
DCD B
DTR A (108)
DTR B
RTS A (105)
RTS B
LL A (141)
T4
MAX13172E
M0
12
15
M1
INVERT
13
M2
14
NC
DCE/DTE
11
INVERT
M2
M1
M0
Figure 20. Controller-Selectable DCE Port with DB-25 Connector
______________________________________________________________________________________
19
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
C6
C7 C8
100pF 100pF 100pF
3
8
11
VCC
5V
12 13
MAX13174E
14
27
26
CHARGE
PUMP
2
4
25
C4
4.7µF
TXD
5
SCTE
6
T1
T2
7
R1
9
RXC
R2
10
RXD
21
2
C5
4.7µF
VEE
C12
1µF
5 4
6 7
9 10 16 15 18 17 19 20 22 23 24 1
24
23
22
21
2
TXD A (103)
14
TXD B
24
SCTE A (113)
11
SCTE B
20
19
15
12
18
17
16
15
17
9
T3
8
TXC
LATCH
C2
1µF
M0
1
C1
1µF
VCC
DCE/DTE
M2
M1
C3
4.7µF
C13
1µF
28
3
R3
3
16
7
MAX13170E
M0
12
M1
13
M2
14
DCE/DTE
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SG
11
1
SHIELD
DB-25 MALE
CONNECTOR
C9
1µF
C10
1µF
VCC
1
2
RTS
DTR
3
4
5
DCD
DSR
CTS
LL
6
7
8
10
9
28
VCC
VEE
VDD
GND
T1
T2
27
C11
1µF
26
25
24
23
4
RTS A (105)
19 RTS B
20
DTR A (108)
23
DTR B
22
21
20
19
18
17
8
DCD A (109)
10
DCD B
6
DSR A (107)
22
DSR B
5
CTS A (106)
13 CTS B
16
18
T3
R1
R2
R3
R4
LL A (141)
T4
MAX13172E
M0
12
15
M1
INVERT
13
M2
14
DCE/DTE
11
INVERT
M2
M1
M0
Figure 21. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
20
______________________________________________________________________________________
+5V Multiprotocol, Software-Selectable
Clock Transceiver
Chip Information
PROCESS: BiCMOS
TOP VIEW
+
VCC 1
28 VEE
VDD 2
27 GND
T1IN 3
26 T1OUTA
T2IN 4
25 T1OUTB
R1OUT 6
Package Information
24 T2OUTA
T3IN 5
MAX13172E
23 T2OUTB
R2OUT 7
22 T3OUTA/R1INA
R3OUT 8
21 T3OUTB/R1INB
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
T4IN 9
20 R2INA
R4OUT 10
19 R2INB
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
M0 11
18 R3INA
28 SSOP
A28+2
21-0056
90-0095
M1 12
17 R3INB
M2 13
16 T4OUTA/R4INA
15 INVERT
DCE/DTE 14
SSOP
______________________________________________________________________________________
21
MAX13172E
Pin Configuration
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/09
Initial release
1
8/11
Updated soldering temperature in Absolute Maximum Ratings, updated Fail-Safe
section, updated Package Information section, and added lead-free indicator to
Pin Configuration
DESCRIPTION
PAGES
CHANGED
—
2, 23, 38
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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