EVALUATION KIT AVAILABLE
MAX14001/MAX14002
General Description
The MAX14001/MAX14002 are isolated, single-channel
analog-to-digital converters (ADCs) with programmable
voltage comparators and inrush current control optimized
for configurable binary input applications. 3.75kVRMS
of integrated isolation is provided between the binary
input side (field-side) and the comparator output/SPI-side
(logic-side) of the MAX14001/MAX14002. An integrated,
isolated, DC-DC converter powers all field-side circuitry,
and this allows running field-side diagnostics even when
no input signal is present. The 20-pin SSOP package
provides 5.5mm of creepage and clearance with group II
CTI rating.
These devices continually digitize the input voltage on
the field-side of an isolation barrier and transmit the data
across the isolation barrier to the logic-side of the device
where the magnitude of the input voltage is compared to
programmable thresholds. The binary comparator output
pin is high when the input voltage is above the upper
threshold and low when it is below the lower threshold.
Response time of the comparator to an input change
is less than 150µs with filtering disabled. With filtering
enabled, the comparator uses the moving average of the
last 2, 4, or 8 ADC readings. Both filtered and unfiltered
ADC readings are available through the 5MHz SPI port,
which is also used to set comparator thresholds and other
device configuration.
The MAX14001/MAX14002 control the current of a binary
input through an external, high-voltage FET. This current
cleans relay contacts and attenuates input noise. An inrush
comparator monitoring the ADC readings triggers the inrush
current, or wetting pulse. The inrush trigger threshold, current magnitude, and current duration are all programmable
in the MAX14001 but are fixed in the MAX14002. When
the high-voltage FET is not providing inrush current, it
switches to bias mode. Bias mode places a small current
load on the binary input to attenuate capacitively coupled
noise. The level of bias current is programmable between
50µA and 3.75mA in both the MAX14001 and MAX14002.
This allows optimization of the tradeoff between noise
attenuation and power dissipation.
19-8514; Rev 1; 8/17
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Benefits and Features
●● Enables Robust Detection of Binary Inputs
• Programmable Input Bias Current Rejects Line Noise
• 3.75kVRMS of Isolation for 60 Seconds
• 5.5mm of Creepage and Clearance
• Group II CTI Package Material
●● Reduces BOM and Board Space Through High
Integration
• 10-bit, 10ksps ADC
• Binary Threshold Comparators
• Control Circuit for Driving a Depletion Mode FET
• Isolation for Both Data and DC-DC Supply
• 20-SSOP Package
●● Increases Equipment “Up Time” and Simplifies
System Maintenance
• Enables Field-Side Diagnostics
• Automatic Self-Diagnostics
●● Provides Unparalleled Flexibility
• Programmable Upper and Lower Input Thresholds
• Programmable Inrush Current Activation Threshold,
Magnitude, and Duration
• Daisy-Chainable SPI Interface
Applications
●●
●●
●●
●●
High-Voltage Binary Input (12V–300V)
Distribution Automation
Substation Automation
Industrial Control, Multi-Range, Digital Input Modules
with Individually Isolated Inputs
Safety Regulatory Approvals
●● UL According to UL1577
Ordering Information appears at end of data sheet.
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Absolute Maximum Ratings
VDDL to GNDL..........................................................-0.3V to +6V
VDD to GNDL...........................................................-0.3V to +6V
Logic-Side Inputs (CS, SCLK, SDI, FAULT) to GNDL
................................................................................. -0.3V to +6V
Logic-Side Outputs (SDO, COUT)
to GNDL............................................... -0.3V to (VDDL + 0.3V)
VREFIN, VAIN to AGND............................................-0.3V to +2V
AGND to GNDF.....................................................-0.3V to +0.3V
GATE to GNDF.........................................................-0.3V to +4V
IFET to GNDF........................................................-0.3V to +12V
ISET to GNDF..........................................................-0.3V to +2V
VDDF to GNDF.........................................................-0.3V to +6V
Short-Circuit Duration
(FAULT, COUT, SDO to GNDL or VDD).................Continuous
Continuous Power Dissipation (TA = +70°C)
20-pin SSOP...............................................................952.4mW
Operating Temperature Range.......................... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
20-pin SSOP
Junction-to-Ambient Thermal Resistance (θJA)...........84°C/W
Junction-to-Case Thermal Resistance (θJC)................32°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDDL - VGNDL = 1.71V to 5.5V, VDD - VGNDL = 3.0V to 3.6V, RISET = 120kΩ, TA = -40°C to +125°C, VGNDF = VGNDL. Typical values
are at TA = +25°C with VDDL = VDD = +3.3V, RISET = 120kΩ, VGNDF = VGNDL.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.71
5.5
V
0.7
1.5
mA
3.0
3.3
3.6
V
4.8
8
mA
0.2
ms
1
ms
POWER SUPPLIES
Logic Power Supply
VDDL
Logic Supply Current
IDDL
VDDL = 3.3V, no load, CS = high
Isolated DC-DC Power
Supply Input Voltage
VDD
Isolated DC-DC Supply
Input Current
IDD
VDD = 3.3V
Logic Power-Up Delay
Field Power-Up Delay
CVDDF = 0.1µF
Field Power Supply
VDDF
CVDDF = 0.1µF, unregulated output voltage
Gate Charge Pump
Voltage
VGATE
1µA pull-down
VUVLOL
VUVLOD
Logic-Side Undervoltage
Lockout Threshold
2.5
3.0
3.5
V
3
3.6
4
V
VDD ≥ 3V
1.5
1.6
1.66
V
VDDL ≥ 1.71V
2.69
2.82
2.95
V
Logic-Side Undervoltage
Lockout Threshold
Hysteresis
VUVLHYST
50
mV
VUVDHYST
100
mV
Field-Side Undervoltage
Lockout Threshold
VUVLOF
www.maximintegrated.com
(Note 4)
1.95
2.1
2.25
V
Maxim Integrated │ 2
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(VDDL - VGNDL = 1.71V to 5.5V, VDD - VGNDL = 3.0V to 3.6V, RISET = 120kΩ, TA = -40°C to +125°C, VGNDF = VGNDL. Typical values
are at TA = +25°C with VDDL = VDD = +3.3V, RISET = 120kΩ, VGNDF = VGNDL.) (Notes 2, 3)
PARAMETER
Field-Side Undervoltage
Lockout Threshold
Hysteresis
SYMBOL
CONDITIONS
MIN
VUVFHYST
TYP
MAX
UNITS
100
mV
PROTECTION
ESD
Any pin to GNDL or GNDF inclusive
±2
kV
EFT (Burst)
System-level requirement IEC 61000-4-4
common mode (Note 5)
3
kV
CMTI
(Note 6)
50
kV/µs
VAIN
Nominal measurement range
DYNAMIC
Common-Mode Transient
Immunity
ADC AND COMPARATOR
Input Voltage Range
Reference Input Range
ADC Resolution
0
VREFIN
(1.25)
V
VREFIN
1.15
1.25
1.35
V
10
Bits
Gain Error
GE
VIN = 98% VREF, excluding offset error and
reference errors
-0.55
+0.55
%
Offset Error
OE
VIN = 2% VREF, offset calculated
-0.2
+0.2
%FS
Differential Nonlinearity
DNL
±1
LSB
Integral Nonlinearity
INL
Included in the gain + offset window
±1
LSB
Input Leakage Current
IILR
VAIN = 1.25V
+200
nA
Throughput
Latency (No Filtering)
AIN step input to COUT transition (Notes 4, 7)
Latency (2 Readings)
-200
8
10
12
ksps
12
150
µs
AIN step input to COUT transition (Notes 4, 7)
92
270
µs
Latency (4 Readings)
AIN step input to COUT transition (Notes 4, 7)
180
510
µs
Latency (8 Readings)
AIN step input to COUT transition (Notes 4, 7)
340
990
µs
1.25
V
-5
+5
%
INTERNAL VOLTAGE REFERENCE
Nominal Output Voltage
Output Voltage Accuracy
Over the entire temperature range
Output Voltage
Temperature Drift
TCVOUT
50
ppm/°C
EXTERNAL VOLTAGE REFERENCE
Reference Voltage
Available Bias Current
When powered from VDDF (series) or REFIN
(shunt)
www.maximintegrated.com
1.15
1.25
70
1.35
V
µA
Maxim Integrated │ 3
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(VDDL - VGNDL = 1.71V to 5.5V, VDD - VGNDL = 3.0V to 3.6V, RISET = 120kΩ, TA = -40°C to +125°C, VGNDF = VGNDL. Typical values
are at TA = +25°C with VDDL = VDD = +3.3V, RISET = 120kΩ, VGNDF = VGNDL.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.375
3.75
4.125
mA
0.25
mA
50
100
µA
BIAS CURRENT DAC
Full-Scale Current
Excludes RISET errors
Resolution
Offset Error
Integral Nonlinearity
IBIAS[3:0] = 0 (see CFG register)
INL
0.25
LSB
INRUSH CURRENT DAC
Full-Scale Current
Excludes RISET errors
Resolution
Offset
Integral Nonlinearity
94.5
105
115.5
mA
7
mA
IINR[3:0] = 0 (see INRP register)
50
100
µA
INL
Inrush Current
0.25
MAX14002 only. Excludes RISET errors
44.1
LSB
49
53.9
mA
120
ms
INRUSH TIMER
Range
Nominal
Resolution
Programmed by TINR[3:0] (see INRP register)
Error
0
8
ms
-20
Maximum Duty Cycle
Inrush Duration
+20
DU1 = 0, DU0 = 1 (see INRP register)
1.6
DU1 = 1, DU0 = 0 (see INRP register)
3.1
DU1 = 1, DU0 = 1 (see INRP register)
6.3
MAX14002 only
38.4
%
%
48
57.6
ms
ADC FS
V
INRUSH COMPARATOR
Range
0
Resolution
10
Bits
Latency (No Filtering)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
22
160
µs
Latency (2 Readings)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
102
280
µs
Latency (4 Readings)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
192
520
µs
Latency (8 Readings)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
356
1000
µs
V
LOGIC I/O LEVELS
Input High Voltage
VIH
SCLK, SDI, CS
Input Low Voltage
VIL
SCLK, SDI, CS
Input Hysteresis
www.maximintegrated.com
VHYST
SCLK, SDI, CS
0.7 x VDDL
0.3 x VDDL
0.05 x
VDDL
V
V
Maxim Integrated │ 4
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(VDDL - VGNDL = 1.71V to 5.5V, VDD - VGNDL = 3.0V to 3.6V, RISET = 120kΩ, TA = -40°C to +125°C, VGNDF = VGNDL. Typical values
are at TA = +25°C with VDDL = VDD = +3.3V, RISET = 120kΩ, VGNDF = VGNDL.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
0.4
V
-1
+1
µA
SCLK, SDI, CS
-1
+1
µA
SCLK, SDI, CS, f = 1MHz
2
pF
5
MHz
Output High Voltage
VOH
SDO, COUT, sourcing 4mA
Output Low Voltage
VOL
SDO, COUT, FAULT, sinking 4mA
Output High-Impedance
Leakage Current
IOL
SDO, FAULT
Input Leakage Current
IIL
Input Capacitance
CIN
TYP
VDDL- 0.4
SPI TIMING CHARACTERISTICS
SCLK Clock Frequency
fSCLK
Single device
SCLK Clock Period
tSCLK
Single device
200
ns
SCLK Pulse-Width High
tSCLKH
Single device
80
ns
SCLK Pulse-Width Low
tSCLKL
Single device
80
ns
CS Fall-to-SCLK Rise
Time
tCS(lead)
80
ns
SCLK Fall-to-CS Rise
Time
tCS(lag)
80
ns
SDI Hold Time
tDINH
40
ns
SDI Setup Time
tDINSU
40
ns
SDO Enable Time (CS
Falling to SDO Valid)
tDOUT(en)
CL = 50pF
40
ns
SDO Disable Time (CS
Rising to SDO ThreeState)
tDOUT(dis)
CL = 50pF
40
ns
Output Data Propagation
Delay
tDO
CL = 50pF. SCLK falling-edge to SDO valid
Write-Command to Field
Implementation Delay
tFID
From CS de-assertion until field-side registers
are loaded
Inter-Access Gap
tIAG
Minimum time CS must be de-asserted between
commands
920
50
ns
165
ns
ns
Note 2: All devices are 100% production tested at TA = +25°C. Specifications for all temperature limits are guaranteed by design.
Note 3: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their
respective ground (GNDL or GNDF), unless otherwise noted.
Note 4: Guaranteed by characterization; not production tested.
Note 5: EFT voltage according to IEC 61004-4 is tested through direct coupling to the generator.
Note 6: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output states. CMTI
applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between
GNDF and GNDL (VCM = 1000V).
Note 7: Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and THU is set to mid-scale
value (0x1ff). Latency is the delay from the step at the ADC input to the digital comparator output.
www.maximintegrated.com
Maxim Integrated │ 5
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Insulation Characteristics
PARAMETER
Partial Discharge Test
Voltage
SYMBOL
VPR
CONDITIONS
VALUE
UNITS
Method B1 = VIORM x 1.875 (t = 1s, partial
discharge < 5pC)
1050
VP
Maximum Repetitive Peak
Isolation Voltage
VIORM
(Note 8)
560
VP
Maximum Working Isolation
Voltage
VIOWM
Continuous RMS voltage (Note 8)
400
VRMS
Maximum Transient
Isolation Voltage
VIOTM
t = 1s
6300
VP
Maximum Withstand
Isolation Voltage
VISO
t = 60s, f = 60Hz (Notes 8, 9)
3.75
kVRMS
Basic Insulation, 1.2/50µs surge pulse per
IEC 61000-4-5
7.5
kV
>109
Ω
Maximum Surge Isolation
Voltage
VIOSM
Insulation Resistance
Logic-to-Field
RS
TA = +125°C, VIO = 500V
Barrier Capacitance
Logic-to-Field
CIO
f = 1MHz (Note 10)
10
pF
Minimum Creepage
Distance
CPG
SSOP
5.5
mm
Minimum Clearance
Distance
CLR
SSOP
5.5
mm
Distance through insulation
0.015
mm
Material Group II (IEC 60112)
>400
Internal Clearance
Comparative Tracking
Resistance Index
CTI
Climatic Category
Pollution Degree (DIN VDE
0110, Table 1)
40/125/21
2
Note 8: VISO, VIOWM and VIORM are defined by the IEC 60747-5-5 standard.
Note 9: Product is qualified VISO for 60 seconds. 100% production tested at 120% of VISO for 1s.
Note 10: Capacitance is measured with all pins on field-side and logic-side tied together.
Safety Regulatory Approvals
UL
The MAX14001/MAX14002 are certified under UL1577. For more details, refer to File E351759.
Rated up to 3750VRMS isolation voltage for basic insulation.
www.maximintegrated.com
Maxim Integrated │ 6
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Typical Operating Characteristics
(VDDL = VDD = +3.3V, RISET = 120kΩ, isolated GNDF and GNDL, high-voltage FET is IXTY08N100D2, with TA = +25°C unless
otherwise noted.)
INTERNAL VOLTAGE REFERENCE
vs. TEMPERATURE
toc01
1.2875
1.2625
VDDF STARTUP
toc02
1.2375
1.2125
1.1875
VDD = 0 - 3V step
1.2375
VDDF
1V/div
1.2125
CVDDF = 0.1µF||1000pF
1.1875
-40 -25 -10 5
20 35 50 65 80 95 110 125
2.3
2.6
TEMPERATURE (°C)
2.9
3.2
3.5
3.8
200µs/div
VDDF VOLTAGE (V)
VGATE STARTUP
toc04
VGATE VOLTAGE vs. CURRENT LOAD
3.6
toc05
3.2
VDDF VOLTAGE (V)
VGATE
1V/div
3.5
3.45
3.4
CGATE = 0.01µF
ILOAD = 0µA
3
2.9
2.8
ILOAD = 70µA
2.6
0
1
2
3
4
5
6
-40 -25 -10 5
CURRENT LOAD (µA)
VDDF VOLTAGE vs. CURRENT LOAD
3.07
0.62
VISET VOLTAGE vs. TEMPERATURE
toc08
VDD = 3.3V
0.61
VDD = 3.6V
3.05
3.04
VISET VOLTAGE (V)
VDDF VOLTAGE (V)
toc07
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
VDD = 3V
3.06
3.03
3.02
3.01
3.00
0.6
0.59
0.58
2.99
120KΩ RESISTOR
ON ISET PIN
TA = 25°C
2.98
0
10
20
30
40
0.57
50
CURRENT LOAD (µA)
www.maximintegrated.com
toc06
2.7
3.35
400µs/div
VDDF VOLTAGE vs. TEMPERATURE
3.1
3.55
VDD
1V/div
VGATE VOLTAGE (V)
VDD = 0 - 3V step
toc03
VDD
1V/div
1.2625
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1.2875
INTERNAL VOLTAGE REFERENCE
vs. VDDF VOLTAGE
60
70
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 7
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Typical Operating Characteristics (continued)
(VDDL = VDD = +3.3V, RISET = 120kΩ, isolated GNDF and GNDL, high-voltage FET is IXTY08N100D2, with TA = +25°C unless
otherwise noted.)
INPUT BIAS CURRENT
vs. TEMPERATURE
INPUT BIAS CURRENT
vs. INPUT VOLTAGE
toc09
53.5
53
INPUT BIAS CURRENT ERROR
toc10
1.5
6
1.495
4
1.49
2
52
51.5
51
50.5
50
-40 -25 -10 5
1.485
0
-2
1.48
TA = +125°C
-4
1.475
-6
1.47
20 35 50 65 80 95 110 125
0
TEMPERATURE (°C)
50
100
150
200
250
0.25
300
0.75
1.25
INRUSH CURRENT ERROR
toc12
1.75
2.25
2.75
3.25
3.75
INPUT BIAS CURRENT (mA)
INPUT VOLTAGE (V)
5
INRUSH CURRENT vs. TIME
4
toc13
VIN
5V/div
3
2
ERROR (%)
TA = +25°C
TA = -40°C
CFG:IBIAS = '0110' (DEFAULT)
CFG: IBIAS = '0000'
49.5
ERROR (%)
INPUT BIAS CURRENT (mA)
INPUT BIAS CURRENT (µA)
52.5
toc11
TA = +125°C
IIINR
20mA/div
1
0
-1
TA = +25°C
-2
TA = -40°C
-3
TINR = '0001' (8ms)
IINR = '0111' (49mA)
IBIAS = '0001' (0.25mA)
FAST MODE
-4
-5
7
21
35
49
63
77
91
105
1ms/div
INRUSH CURRENT (mA)
INRUSH CURRENT vs. TIME
toc14
VIN
5V/div
INRUSH CURRENT vs. TIME
VIN
100V/div
toc15
IIINR
20mA/div
IIINR
20mA/div
www.maximintegrated.com
TINR = '0001' (8ms)
IINR = '0111' (49mA)
IBIAS = '0001' (0.25mA)
INRT = 0x021 (9.68V)
VOLTAGE MODE
TINR = '0001' (8ms)
IINR = '0111' (49mA)
IBIAS = '0001' (0.25mA)
INRT = 0x1FE (149.56V)
VOLTAGE MODE
1ms/div
1ms/div
Maxim Integrated │ 8
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Typical Operating Characteristics (continued)
(VDDL = VDD = +3.3V, RISET = 120kΩ, isolated GNDF and GNDL, high-voltage FET is IXTY08N100D2, with TA = +25°C unless
otherwise noted.)
INPUT BIAS CURRENT AT STARTUP
INTEGRAL NONLINEARITY vs. CODE
toc16
toc17
0.4
0.3
VDD/VDDL
1V/div
0.2
0.1
INL (LSB)
VIBIAS
200mV/div
0
-0.1
-0.2
MEASURED ACROSS 10KΩ RESISTOR
IN SERIES WITH EXTERNAL FET
VIN = 300V
VDD = VDDL = 0 - 3.3V STEP
-0.3
TA = +25°C
-0.4
0
400µs/div
128
256
384
512
640
768
896 1024
OUTPUT CODE (DECIMAL)
COUT CHANGE ON RISING EDGE
COUT CHANGE ON FALLING EDGE
toc18B
toc18A
COUT
1V/div
COUT
1V/div
VAIN
1V/div
VAIN
1V/div
DEFAULT REGISTER SETTINGS
THL = 0x100 (0.313V)
VAIN = 1 - 0V STEP
DEFAULT REGISTER SETTINGS
THU = 0x200 (0.625V)
VAIN = 0 - 1V STEP
100µs/div
100µs/div
INRUSH TIMER vs. TEMPERATURE
50
toc19
INRUSH TIME (ms)
49
48
47
46
45
INRP:TINR = '0110' (48ms)
44
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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Maxim Integrated │ 9
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Pin Configuration
TOP VIEW
+
ISET
1
20 VDDL
GNDF
2
19 GNDL
AIN
3
18 FAULT
AGND
4
REFIN
5
MAX14001
MAX14002
17 COUT
16 CS
IC
6
15 SCLK
IFET
7
14 SDI
GATE
8
13 SDO
VDDF
9
12 VDD
GNDF
10
11 GNDL
7.33mm
20-SSOP
7.9mm
Pin Description
PIN
NAME
REFERENCE
FUNCTION
POWER SUPPLY
20
VDDL
GNDL
Power Input for the Logic-Side of the MAX14001/MAX14002. Bypass with
10µF||1000pF capacitors to GNDL.
12
VDD
GNDL
Power Input for the Isolated DC-DC Converter. The DC-DC converter powers the
field-side of the MAX14001/MAX14002. Bypass with 10µF||1000pF capacitors to
GNDL.
11, 19
GNDL
—
9
VDDF
GNDF
Unregulated Output of the DC-DC Converter. Bypass to GNDF with 0.1µF||1000pF
capacitors. The 1000pF capacitor should be placed as close to the pin as possible.
8
GATE
GNDF
Bias Voltage for the Gate of the External Depletion Mode FET. Connect a 0.01µF
capacitor from GATE to GNDF.
2, 10
GNDF
—
Field-side ground for everything except the ADC front-end and voltage reference.
1
ISET
GNDF
Connect a 120kΩ Resistor From ISET to GNDF. This generates a reference current
used to establish the correct bias and inrush currents. Parasitic capacitance on this
pin should not exceed 10pF.
7
IFET
GNDF
Current Sink Input for Inrush and Bias Current. This pin is buffered from high
voltage by connecting it to the source of the external high-voltage FET. Connect a
1000pF capacitor from IFET to GNDF.
3
AIN
AGND
Analog Input. The ADC measures the voltage on this pin with respect to AGND.
4
AGND
—
5
REFIN
AGND
Optional External Voltage Reference Input (Nominally 1.25V). When an external
reference is used, connect a 0.1μF bypass capacitor from REFIN to AGND. When
an internal reference is used, connect REFIN directly to AGND.
6
IC
GNDF
Internally Connected. Connect to GNDF.
Power and Signal Ground for All Logic-Side Pins.
ANALOG
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Analog Ground Reference for AIN and REFIN
Maxim Integrated │ 10
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Pin Description (continued)
PIN
NAME
REFERENCE
FUNCTION
18
FAULT
GNDL
Open-Drain Output That Asserts Low During a Number of Different Error
Conditions. The cause of the error is latched in the FLAGS register. See Diagnostic
and Fault Reporting Features for details on clearing FAULT.
17
COUT
GNDL
Digital Comparator Output. COUT is high when AIN is above the upper threshold
(THU) and low when AIN is below the lower threshold (THL).
16
CS
GNDL
Chip Select for SPI Interface. Assert low to enable SPI functions and SDO. SDO is
high impedance when CS is high.
15
SCLK
GNDL
Serial Clock for SPI Interface
14
SDI
GNDL
Serial Data Input for SPI Interface (MOSI)
13
SDO
GNDL
Serial Data Out for SPI Interface (MISO)
DIGITAL
Functional Diagram
LOGIC SIDE
FIELD SIDE
CFG:EXRF
REFIN
MAX14001 /MAX14002
INTERNAL
VREF 1.25V
VIN
AIN
BINARY
COMP
COUT
DATA
RECEIVER
10-BIT ADC
INRUSH
COMP
AGND
VDDL
GATE
CONTROL
REGISTER
3.6V
0.01µF
FAULT
IFET
1000 pF
ISET
600mV
120kΩ
µPOWER DC -DC
IC
GNDF
www.maximintegrated.com
CS
SCLK
SDI
SDO
LOGIC AND
SPI INTERFACE
CURRENT
SINKING DAC
VDDF
VDD
GNDL
Maxim Integrated │ 11
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Detailed Description
The MAX14001/MAX14002 are 10-bit ADCs with
a 3.75kVRMS isolated SPI interface. Additional features
include a programmable magnitude comparator,
programmable inrush current for cleaning relay contacts,
and programmable input bias current to optimize power
dissipation while reducing capacitively coupled input
noise. The ADC and all field-side circuits are powered
by an integrated, isolated, DC-DC converter that allows
field-side functionality to be verified even when there is
no input signal or other field-side supply. This makes the
MAX14001/MAX14002 ideally suited for high density,
multi-range, individually isolated, binary input modules.
ADC
The devices’ ADC employs a 10-bit SAR architecture
with a nominal sampling rate of 10ksps, and has an input
voltage range of 0V to +1.25V with respect to AGND. After
power-up, the ADC runs continually at the nominal sampling
rate. The 10-bit unfiltered ADC reading and filtered ADC
reading are both available via the SPI interface. Filtering
averages the most recent 2, 4, or 8 readings depending
on the value of the FT[1:0] bits in the CFG register. A binary
comparator responds within 150µs to changes in input
voltage by continually comparing the latest ADC reading
to the programmed thresholds (refer to the EC table for
response times when using the ADC filter). When the latest
ADC reading is higher than the upper threshold (THU),
the comparator’s output pin (COUT) is high and when it
is lower than the lower threshold (THL), the comparator’s
output pin (COUT) is low.
Internal/External Voltage Reference Configuration
The MAX14001/MAX14002 feature both internal
and external voltage reference capability. The 1.25V
internal reference has a maximum error of ±5% over the
entire operating temperature range. If higher accuracy is
required, an external reference may be used. The external
reference may be either series or shunt, but must not
draw more than 70µA of supply current. Series references
must be powered from VDDF while shunt references are
powered from an internal 70µA current source that is
connected to the REFIN pin. Internal/external voltage
reference mode is selected using the SPI interface to
program the CFG register. Refer to Table 1 for the
CFG register configuration, Figure 1 for shunt reference
hardware connection, and Figure 2 for series reference
hardware connection.
FIELD SIDE
FIELD SIDE
EXTERNAL V REF = 1.25V
NOMINAL
REFIN
SHUNT
VOLTAGE
REFERENCE
EXTERNAL V REF = 1.25V
NOMINAL
SERIES VOLTAGE
REFERENCE
IN
0.1µF
OUT
REFIN
0.1µF
GND
AGND
MAX14001 /
MAX14002
AGND
AGND
AGND
VDDF
0.1µF
1000 pF
GNDF
GNDF
REGISTER
CONFIGURATION :
CFG: EXRF = 1
CFG: EXTI = 1
Figure 1. Shunt Voltage Reference Connection
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MAX14001/
MAX14002
VDDF
0.1µF
1000pF
GNDF
GNDF
REGISTER
CONFIGURATION :
CFG: EXRF = 1
CFG: EXTI = 0
Figure 2. Series Voltage Reference Connection
Maxim Integrated │ 12
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Table 1. Voltage Reference Register Configuration
REFERENCE
CONFIGURATION
CFG:EXRF
CFG:EXTI
CONNECTION
Internal Reference
0
0
Connect REFIN directly to AGND.
External Series Reference
1
0
Series reference is supplied by VDDF. Output is connected to the REFIN
pin. Bypass REFIN to AGND with a 0.1μF capacitor.
External Shunt Reference
1
1
Internal current source is turned on. Shunt reference is connected
between REFIN and AGND. Bypass REFIN to AGND with a 0.1μF
capacitor.
ADC Error
The uncalibrated error of the ADC lies within the window
shown in the Figure 3 ADC Error Window. The boundaries
of the box are defined by the offset and gain error from
the EC table and include INL errors as well as drift over
temperature. The upper-boundary is set by the most
positive offset combined with the most positive gain error.
Conversely, the lower-boundary is set by the most negative
offset combined with the most negative gain error.
10
8
ERROR ( mV)
6
If a resistor-divider is used in front of the ADC, FS and
VIN can be the voltages at the input of the divider. For
total system error, the resistive-divider error and the error
of the voltage reference in percent are added to the gain
error of the ADC.
SYSTEM ERRORMAX = OE × FS + VIN x
(GE + ERRORR + ERRORVREF)
Where OE is the offset error in %FS, FS is the full scale
voltage, VIN is the input voltage being measured, GE is the
gain error in %, ERRORR is the resistive-divider error in %,
and ERRORVREF is the voltage reference error in %.
For example, assume:
●● All errors specs are symmetrical.
• |Maximum Positive Error| = |Maximum Negative
Error|
●● The input resistive-divider is made of 1% resistors and
divides the binary voltage by a nominal factor of 240.
• Maximum resistive-divider error ERRORR = 2%
www.maximintegrated.com
2
0
-2
-4
-6
-8
-10
ERRORMAX = OE × FS + VIN x GE
Where OE is the offset error in %FS, FS is the full scale
voltage, VIN is the input voltage being measured, and GE
is the gain error in %.
4
0.00
0.20
0.40
0.60
0.80
1.00
1.20
VAIN (V)
UPPER ERROR LIMIT
LOWER ERROR LIMIT
Figure 3. ADC Error Window (Excludes VREF Error)
●● A nominal 1.25V reference with an error of 5%
• Full-scale input voltage FS = 1.25V x 240 = 300
• ERRORVREF = 5%
●● ADC offset error OE = 0.3%
●●
ADC gain error GE = 0.3%
●●
Input voltage VIN = 200V
SYSTEM ERRORMAX = 0.3% x 300V +
VIN x (0.3%+2%+5% )
When VIN = 200V, the maximum error is 15.5V.
If the comparator threshold is set at 200V (ADC reading
of decimal 682), the comparator could trip with a voltage
as low as 184.5V or as high as 215.5V. Conversely, if the
ADC is to read 682, the nominal input voltage would be
200V, but the actual voltage could be as high a 215.5V or
as low as 184.5V.
Maxim Integrated │ 13
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
High-Voltage FET Current Control
The devices control a high-voltage depletion mode FET
that can be used to sink inrush current for cleaning relay
contacts while contacts are closing, or a smaller bias
current for input noise suppression while contacts are
open. When the inrush pulse is finished, the FET current
is reduced to the bias level, lowering power dissipation
in the FET while still providing an input load. Inrush current is fixed in the MAX14002 (49mA for 48ms) but is
configurable in the MAX14001. The MAX14001’s inrush
current magnitude and duration are both programmable:
the magnitude ranges from 50µA to 105mA in 7mA
increments, and the duration ranges from 0ms to 120ms
in 8ms increments. Bias current is adjustable in both the
MAX14001 and MAX14002, and ranges from 50uA to
3.75mA in 0.25mA increments.
The MAX14001’s inrush pulse can be initiated in one of
two ways: voltage triggered inrush mode based on the
ADC reading or FAST inrush mode based on the highvoltage FET current level. In voltage triggered inrush
mode (FAST bit in the CFG register = 0), the pulse is
initiated when the ADC reading equals or exceeds the
programmed trigger threshold in the INRT register. Once
an inrush pulse has been triggered, the ADC reading must drop below the re-arm threshold in the INRR
register before another inrush pulse can be triggered. In
FAST mode (FAST bit in the CFG register = 1), the inrush
pulse starts as soon as the input signal is able to supply
the inrush current. Re-arming occurs when the input no
longer supplies enough current to the high-voltage FET
(either inrush or bias current depending on the present
mode). The MAX14002 operates in FAST mode only.
Figure 4 and Figure 5 illustrate the two methods for triggering a pulse of inrush current.
Voltage Mode
A) The high-voltage FET is trying to sink bias current,
but cannot because the input signal is not supplying
enough current.
B) When the input voltage increases to the inrush trigger
threshold (INRT), the FET current is increased to the
inrush level and the inrush timer is started.
C) Contact bounce causes the input voltage to drop
below the inrush reset threshold (INRR). The FET
current is reduced to the bias level and the inrush
timer is reset.
D) The input voltage again rises to the inrush trigger
threshold. The FET current is increased to the inrush
level and the inrush timer is started.
E) The inrush timer expires and the FET current is
reduced to the bias level.
F) The input voltage drops below the inrush re-arm
threshold (INRR). The inrush timer is reset and
prepared to deliver the next inrush pulse. The FET
current remains at the bias level.
G) The noise pulse is fully clamped at the turn-on
voltage of the FET circuit.
H) Higher energy noise pulse that is partially clamped
by the bias current. Noise current exceeds the bias
current so the voltage rises above the turn-on
voltage of the FET circuit.
E
B
3
D
F
H
A
INPUT CURRENT
INPUT VOLTAGE
INRT
Figure 4. Voltage Triggered Inrush Mode
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4
2
C
INRR
G
1
INPUT CURRENT
8
6
INPUT VOLTAGE
5
7
Figure 5. FAST Inrush Mode
Maxim Integrated │ 14
MAX14001/MAX14002
FAST Mode
1) The high-voltage FET is trying to sink the inrush
current, but cannot because the input signal is not
supplying enough current. Since the current level
cannot be met, the FET current is set to the inrush
level, and the inrush timer is reset.
2) The input voltage increases and supplies enough current
for the inrush pulse. The inrush timer is started.
3) The inrush timer expires and the FET current is
reduced to the bias level.
4) The input voltage drops and can no longer supply the
bias current. The inrush timer is reset and the FET
current is set to the inrush level.
5) Contact bounce raises the input voltage and supplies
enough current for an inrush pulse. The inrush timer
is started.
6) The input voltage drops and can no longer supply the
inrush current. The inrush timer is reset and the FET
current remains the inrush level.
7) The noise pulse is fully clamped at the turn-on voltage
of the FET circuit.
8) Higher energy noise pulse is fully clamped by the inrush
current. Noise current exceeds the bias current, but
since the FET is trying to sink the larger input current,
the input current rises and the voltage remains clamped
at the turn-on voltage of the FET circuit.
Repetitive Inrush Pulse Limiting (MAX14001 Only)
The MAX14001 can limit repetitive inrush pulses to
prevent overheating from abnormal input signals that
would otherwise trigger a continuous stream of inrush
pulses. When the pulse limiting function is enabled, the
MAX14001 monitors the percentage of time that the
inrush current is flowing. When it exceeds the duty cycle
threshold over the last 10 seconds, additional inrush
pulses are disabled for the next 10 seconds. When the
pulse limiting is triggered, the INRD bit in the FLAGS
register is set and FAULT is asserted if the EINRD bit in
the FLTEN register is set. The pulse limiting function can
be turned off or the pulse duty cycle can be set to 1.6%,
3.1%, or 6.3% using the DU[1:0] bits in the INRP register.
The MAX14002 does not provide a repetitive inrush pulse
limiting feature.
Diagnostic and Fault Reporting Features
The MAX14001/MAX14002 continuously monitor seven
possible fault conditions, and a hardware alert is provided
via the open drain FAULT pin, which asserts low when an
enabled fault is detected. The possible faults are: ADC
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Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
functionality error, repetitive inrush pulses being triggered,
SPI framing error, loss of internal isolated data stream,
CRC errors from internal communication, high-voltage
FET failure, and corrupted memory error.
The bits in the FLTEN register determine how the FAULT
output responds to the seven error conditions, and the
FAULT output is asserted if the corresponding bit is
enabled in the FLTEN register. If the FLTEN register bit
DYEN = 0, FAULT operates as a latched output and remains
asserted until the FLAGS register is cleared but if the bit
DYEN = 1, FAULT operates as a dynamic output and
de-asserts when the faults are no longer detected even
though bits in the FLAGS register remain set.
If the corresponding bit in the FLTEN register is not set,
when an error is flagged, FAULT will not be asserted,
but the bit in the FLAGS register will still be latched and
remain set until the register is read, which automatically
clears all bits in the FLAGS register. Note that if a fault
condition still exists when the register is read, the cleared
fault bit will immediately be set again.
In a typical application, FAULT triggers an interrupt routine
in the microcontroller or FPGA, which will read the FLAGS
register to determine the cause of the interrupt.
Diagnostic Conditions
The diagnostic features implemented on the MAX14001/
MAX14002 can be summarized as follows:
1) ADC Functionality Error: ADC functionality is
checked by looking for changes in the ADC output. To
ensure that a change should have occurred, a special
test measurement is made while injecting a small current at the input of the ADC. This special measurement
used for ADC functionality verification is interleaved
between normal measurements and does not affect
the ADC sampling time. If the ADC reading does not
change, an ADC functional failure is declared and bit
ADC (bit 1) in the FLAGS register is set.
2) Repetitive Inrush Pulses: If the repetitive inrush pulse
limiting feature of the MAX14001 is turned on, and
pulse limiting is triggered, bit INRD (bit 2) in the FLAGS
register is set. See Repetitive Inrush Pulse Limiting
(MAX14001 Only) for details on inrush pulse limiting.
3) SPI Framing Error: After CS transitions from low to
high, if the number of bits clocked in while CS was
low is not an integer multiple of 16, an SPI framing
error is declared and bit SPI (bit 3) in the FLAGS
register is set. The instruction in the SPI shift register
is not decoded and no register value is changed.
4) Loss of Data Stream: The field-side sends ADC
Maxim Integrated │ 15
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
data across the isolation barrier to the logic-side
every 100µs, except for the startup period. If the
periodic field-side data is not received, a loss of
data stream fault is declared and bit COM (bit 4) in
the FLAGS register is set. It is possible to recover
from a loss of data stream fault by asserting a hard
reset through the ACT register, which will return all
of the registers to their default state, thus requiring
the MAX14001/MAX14002 to go through the startup
configuration process.
5) CRC Errors From Internal Communication: Internal
communication across the isolation barrier includes
a CRC code to ensure that corrupt data does not
cause system problems. If the CRC indicates an error,
the received data is discarded. If six consecutive
CRCs fail, a CRC fault is declared and bit CRCL (bit
5) or CRCF (bit 6) in the FLAGS register is set.
6) High-Voltage FET Failure: If the ADC reading is greater
than the inrush re-arm threshold (INRR), and IFET is
not able to sink the programmed current, a FET fault
is declared and bit FET (bit 7) in the FLAGS register is
set. INRR is permanently set to 0x0C0 in MAX14002.
7) Memory Error: The devices continually compare
the bits of each verification register to the bits of
their corresponding configuration register. If any of
the bits do not match, a memory fault is declared
and bit MV (bit 8) in the FLAGS register is set. No
information on which register failed is provided. Note
that the default value for each verification register is
the 1’s complement of its corresponding configuration
register (each verification register value is bitwise
inverting of the corresponding configuration register
value.), which guarantees an MV fault any time power
is lost and restored.
Isolated Power and Data Transfer
A simplified view of the isolated power and data transfer
sections is shown in the Functional Diagram. The logic-side
supply VDD powers an integrated, inductively coupled,
DC-DC converter that generates a nominal 3V with
just enough output current to power the field-side of
the MAX14001/MAX14002 and an external circuit that
consumes less than 70µA, such as an external series
reference (Figure 2).
Serial data is transferred by capacitively-isolated differential
transceivers. To verify reliable communication through the
isolation barrier, a cyclic redundancy check (8-bit CRC)
is embedded in the transmitted serial data streams. If a
CRC fails, the data is discarded and no action is taken. If
six consecutive CRCs fail, the CRC bit in the FLAGS register
is set and FAULT is asserted if the CRC fault enable bit is
set in the FLTEN register.
Configuration and Monitoring
An SPI interface is used for transferring configuration,
control and diagnostic data as well as ADC readings
between a master (FPGA or microcontroller) and single/
multiple MAX14001/MAX14002(s). The interface can
support daisy-chain configuration and consists of four
ports: SCLK, CS, SDI and SDO.
SPI Interface
SPI communication includes the following features:
●●
Support for daisy-chain operation
●●
Able to verify the previous command was correctly
received by reading SDO on the next instruction cycle
●●
Able to read/verify all written registers (except ACT
register)
FAULT at Power-On
●●
The devices’ internal memory is volatile and must be
reprogrammed after power cycling. To protect against
undetected power glitches and the remote possibility that a
memory bit would be lost during years of static operation,
the devices monitor their configuration registers and assert
bit MV (bit 8) in the FLAGS register any time the memory is
corrupted. Verification registers have the 1’s complement of
the POR values compared to the configuration registers and,
therefore, the MAX14001/MAX14002 start with a memory
fault condition and assert the FAULT pin at startup.
Identify when commands are not a multiple of 16-bits
and set the SPI fault flag
●●
Commands of all 0s or all 1s do not change any
writable registers
●●
A single command cannot program both the
configuration and verification register
●●
Serial clock up to 5MHz
The command is 16-bits in length and the structure of the
16-bit data is shown in the Table 2.
Table 2. SPI Command
ADDRESS
CONTROL
DATA
5-bits A[4:0], MSB to LSB
W/R bit, Read = 0, Write = 1
10-bits D[9:0], MSB to LSB
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Maxim Integrated │ 16
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
The first bit clocked into the SDI port is D[0], the data
LSB (note: many SPI products clock MSB first so the
microcontroller or FPGA needs to reverse data prior
to outputting it to the MAX14001/MAX14002 SDI pin).
As long as CS is in a logic-low state, the SPI interface
is working as a simple shift register, and SDI data is
shifted on the rising edge of SCLK without decoding the
commands. When CS goes back to logic-high state, the
bits in the shift register are decoded. If the command is a
write, the data portion of the SPI shift register is copied to
the specified register and the shift register is unchanged.
If the command is a read, the content of the specified
register is copied to the data portion of the SPI shift register, while the address bits A[4:0] and control bit W/R are
unchanged. The read action is completed during the next
instruction cycle when CS again goes to logic-low state
and the contents of the shift register are clocked out of
SDO on the falling edge of SCLK.
during CS logic-low state must be a multiple of 16.
Otherwise, the received command will be ignored.
Chip Select (CS): The CS input enables the SPI
interface. During a logic-low state, data is transferred on
the edges of SCLK. A logic-high state on CS forces SDO
to high impedance mode and any SCLK transitions are
ignored.
During a write cycle, the content of the shift register is
transferred to the addressed internal register on the
rising edge of CS. During a read cycle, the content of the
internal register that was addressed is transferred to the
shift register on the rising edge of CS and the data will
be clocked out of the SDO pin during the next SPI cycle.
Serial Input (SDI): SDI or MOSI is the serial input port
of the SPI shift register and data is clocked LSB first
into the shift register on the rising edge of SCLK. On the
rising edge of CS, the input data is latched into the
internal registers.
The functionality of each SPI pin can be summarized as
follows.
Serial Output (SDO): SDO or MISO is the serial output
port of the SPI shift register, and is in a high impedance
state until the CS pin goes to logic-low state. Data is
clocked LSB first out of the shift register on the falling
edge of SCLK.
Serial Clock (SCLK): Input for the master serial clock
signal. The clock signal determines the speed of the
data transfer (5MHz maximum) and all data transfers are
synchronous to this clock. SCLK must remain low when
CS transitions are from high to low and from low to high.
The number of SCLK rising edges that are received
The SPI interface Read and Write Timing Diagrams are
shown in Figure 6, Figure 7, and Figure 8.
CS
1
SCLK
SDI
SDO
HIGH-Z
2
3
8
9
10
11
12
13
14
15
16
D0
D1
D2
...
D7
D8
D9
W*
A0
A1
A2
A3
A4
“X”
“X”
“X”
...
“X”
“X”
“X”
W*
A0
A1
A2
A3
A4
HIGH-Z
* W = “1”
Figure 6. SPI Write
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Maxim Integrated │ 17
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
CS
SCLK
1
2
3
8
9
10
11
12
13
14
15
16
SDI
“0”
“0”
“0”
“0”
“0”
“0”
R*
A0
A1
A2
A3
A4
SDO
HIGH-Z “X”
“X”
“X”
“X”
“X”
“X”
R*
A0
A1
A2
A3
A4
1
HIGH-Z
2
3
8
9
10
11
12
13
14
15
16
“0”
“0”
“0”
“0”
“0”
“0”
R*
A0
A1
A2
A3
A4
D0
D1
D2
D7
D8
D9
R*
A0
A1
A2
A3
A4
HIGH-Z
* R = “0”
Figure 7. SPI Read
tIAG
tCS(LEAD)
tCS(LAG)
CS
tSCLKH
1
SCLK
2
...
tSCLKL
10
11
D0
13
D1
...
D9
W/R*
A0
A1
HIGH-Z
“X”
15
16
A2
A3
A4
A3
A4
tDO
tDOUT(EN)
SDO
14
tDINH
tDINSU
SDI
tSCLK
12
“X”
...
“X”
W/R*
A0
A1
A2
tDOUT(DIS)
HIGH-Z
tFID
FIELD
* R = “0”, W = “1”
Figure 8. SPI Timing Diagram
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Maxim Integrated │ 18
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Daisy-Chain SPI Operation
The device supports daisy-chain operation, allowing
control/monitoring of multiple MAX14001/MAX14002
devices from a single serial interface host with common
CS and SCLK signals as illustrated in Figure 9. The data
that is clocked into SDI is clocked out of SDO with a
16-SCLK-cycle delay for each device in the daisy-chain,
which is illustrated in Figure 10 and Figure 11.
MOSI
RPULL-UP
CS
VDDL
CS
VDDL
CS
VDDL
CS
VDDL
...
SDI
MAX14001 /02 SDO
DEVICE 1
SDI
MAX14001 /02 SDO
DEVICE 2
SDI
MAX14001 /02 SDO
DEVICE N
MISO
MICRO CONTROLLER
...
FAULT
SCLK
FAULT
SCLK
FAULT
SCLK
GPI
SCLK
Figure 9. Daisy-Chain Connection
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Maxim Integrated │ 19
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
CS
SCLK
1
SDI 1
D0N
SDO 1
SDI 2
...
SDO N-1
SDI N
SDO N
...
...
10
11
12
D9N
W N*
A0N
...
...
16
1
A4N
...
10
11
12
...
16
1
...
10
11
12
...
16
...
D02
...
D92
W 2*
A02
...
A42
D01
...
D91
W 1*
A01
...
A41
D03
...
D93
W 3*
A03
...
A43
D02
...
D92
W 2*
A02
...
A42
HIGH-Z
D0N
...
D9N
W N*
A0N
...
A4N
HIGH-Z
HIGH-Z
“X”
...
HIGH-Z
“X”
...
“X”
HIGH-Z
“X”
...
“X”
HIGH-Z
“X”
* W = “1”
Figure 10. SPI Daisy-Chain Write
CS
SCLK
1
...
10
11
12
...
16
SDI 1
“X”
...
“X”
R N*
A0N
...
A4N
SDO 1
SDI 2
...
SDO N-1
SDI N
SDO N
1
...
10
11
12
...
16
1
...
“X”
...
“X”
R 2*
A02
...
A42
“X”
“X”
...
“X”
R 3*
A03
...
A43
HIGH-Z
“X”
...
HIGH-Z
“X”
...
“X”
HIGH-Z
“X”
...
“X”
...
10
11
12
...
16
...
“X”
R 1*
A01
...
A41
“X”
...
“X”
R 2*
A02
...
A42
“X”
...
“X”
R N*
A0N
...
A4N
HIGH-Z
HIGH-Z
HIGH-Z
“X”
CS
1
...
10
11
12
...
16
1
...
10
11
12
...
16
...
“X”
...
“X”
R 2*
A02
...
A42
“X”
...
“X”
R 1*
A01
...
A41
A41
...
“X”
...
“X”
R 3*
A03
...
A43
“X”
...
“X”
R 2*
A02
...
A42
HIGH-Z
SCLK
16
1
...
10
11
12
...
16
SDI 1
A41
“X”
...
“X”
R N*
A0N
...
A4N
R 1*
A01
...
SDO 1
A42
HIGH-Z
D01
...
D91
SDI N
A4N
HIGH-Z
D0N-1
...
D9N-1 RN-1* A0N-1
...
A4N-1
...
D01
...
D91
R 1*
A01
...
A41
“X”
...
“X”
R N*
A0N
...
A4N
HIGH-Z
SDO N
“X”
HIGH-Z
D0N
...
D9N
...
A4N
...
D02
...
D92
R 2*
A02
...
A42
D01
...
D91
R 1*
A01
...
A41
HIGH-Z
SDI 2
...
SDO N-1
R N*
A0N
* R = “0”
Figure 11. SPI Daisy-Chain Read
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Maxim Integrated │ 20
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FLTEN
THL
THU
INRR
INRT
INRP
CFG
ENBL
ACT
WEN
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
PURPOSE
Filtered ADC reading
Unfiltered ADC
reading
RW
CFGV
ENBLV
0x19
0x1A
0x1B-0x1F
Reserved
Enable Verification
CFG Verification
* Register is read only for the MAX14002
RW
INRTV
INRPV
0x18
6. “x” is unused.
5: Setting IBIAS = 0 forces IFET = 50µA
4: Setting IINR = 0 forces IFET = 50µA
3: INRP = INRPV = 0x1D8 for MAX14002
2: INRT = INRTV = 0x180 for MAX14002
1: INRR = INRRV = 0x0C0 for MAX14002
Notes:
WEN[9:0]
x
ENA
THUV[9:0]
THLV[9:0]
FLTV[9:0]
Reserved. Do not use
x
x
Reserved. Do not use
ENBLV[9:0]
CFGV[9:0]
INRTV[9:0]
SRES
x
INRPV[9:0]
RSET
x
RW* INRP Verification(3)
x
x
SPI
3
x
x
INRD
2
x
x
EINRD
FT[1:0]
ESPI
TINR[3:0]
EXTI
RW* INRT Verification(2)
INPLS
x
EXRF
INRRV[9:0]
THU Verification
THL Verification
FLTEN Verification
Reserved
Write Enable
Action
Enable
Configuration
IBIAS[3:0](5)
INRT[9:0]
Inrush Trigger
Threshold(2)
RW* INRR Verification(1)
RW
RW
RW
RW
WC
RW
RW
COM
ECOM
INRR[9:0]
IINR[3:0](4)
ADC[9:0]
4
FADC[9:0]
ECRCL
CRCL
5
Inrush Re-arm
Threshold(1)
ECRCF
CRCF
6
THU[9:0]
EFET
FET
7
Upper Comparator
Threshold
EMV
MV
8
THL[9:0]
x
x(6)
9
Lower Comparator
Threshold
FAULT Enable
RW* Inrush Pulse(3)
RW*
RW*
RW
RW
RW
COR Error Flags
R
R
TYPE
0x17
THUV
INRRV
0x16
0x14
0x15
FLTV
THLV
0x13
0x0D-0x12
FADC
FLAGS
0x02
ADC
0x00
0x01
NAME
ADDR
Table 3. Register Map
The MAX14001/MAX14002 registers and their default Power-On-Reset (POR) values are shown in Table 3:
Register Map
x
x
FAST
x
0
DYEN
x
x
IRAW
DU[1:0]
EADC
ADC
1
0x3FF
0x27C
0x227
0x27F
0x33F
0x1FF
0x2FF
0x000
0x000
0x000
0x000
0x183
0x1D8
0x180
0x0C0
0x200
0x100
0x1FF
0x100
DEFAULT
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Maxim Integrated │ 21
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Register Type Legend:
R - Read only
RW - Read and write
COR - Latched read only, clear on read
WC - Write and clear (Write only, executes and clears immediately)
Register Detailed Description
ADC (Read)
Address = 0x00
BIT
FIELD NAME
9:0
ADC[9:0]
DESCRIPTION
Contains the latest ADC reading (straight binary)
FADC (Read)
Address = 0x01
BIT
FIELD NAME
9:0
FADC[9:0]
DESCRIPTION
Contains the latest filtered ADC reading as set by bits FT[1:0] in the CFG register (straight binary)
FLAGS (Latched, Clear On Read)
Address = 0x02
Default = 0x100
Latched flags indicate errors and why the FAULT pin was asserted if the fault is enabled in the FLTEN register. Reading
the register clears all flags.
Note: Faults conditions are latched and the relevant bits are set; reading the value of this register will reset the fault flags
that are not active anymore. However, if the fault is still valid, reading the FLAGS register will not be able to clear the
specific bit.
BIT
FIELD NAME
0
FLAG0
1
ADC
ADC reading stuck at one value
2
INRD
Exceeding specified duty-cycle for the inrush current
3
SPI
4
COM
Field-side communication failure
5
CRCL
Field-to-logic-side transmission had 6 consecutive CRC errors reported
6
CRCF
Logic-to-field-side transmission had 6 consecutive CRC errors reported
7
FET
Input voltage detected without input current
8
MV
Failed memory validation
9
FLAG9
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DESCRIPTION
Unused
Number of bits clocked in while CS was asserted is not an integer multiple of 16
Unused
Maxim Integrated │ 22
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
FLTEN (Read/Write)
Address = 0x03
Default = 0x1FF
Enables fault conditions to assert the FAULT signal.
Note: Fault enable bits only effect fault reporting through the FAULT pin. Bits in the FLAGS register will be set regardless
whether fault is enabled or disabled by the FLTEN register.
BIT
FIELD NAME
DESCRIPTION
0
DYEN
0: FAULT is latched; it is cleared after the FLAGS register is read.
1: FAULT is dynamic; it is cleared as soon as the fault condition disappears. (Default)
1
EADC
0: Prevents ADC error from asserting FAULT
1: Allows ADC error to assert FAULT (Default)
2
EINRD
0: Prevents INRD error from asserting FAULT
1: Allows INRD error to assert FAULT (Default)
3
ESPI
4
ECOM
0: Prevents COM error from asserting FAULT
1: Allows COM error to assert FAULT (Default)
5
ECRCL
0: Prevents CRCL error from asserting FAULT
1: Allows CRCL error to assert FAULT (Default)
6
ECRCF
0: Prevents CRCF error from asserting FAULT
1: Allows CRCF error to assert FAULT (Default)
7
EFET
0: Prevents FET error from asserting FAULT
1: Allows FET error to assert FAULT (Default)
8
EMV
0: Prevents MV error from asserting FAULT
1: Allows MV error to assert FAULT (Default)
9
FLTEN9
0: Prevents SPI error from asserting FAULT
1: Allows SPI error to assert FAULT (Default)
Unused
THL (Read/Write)
Address = 0x04
Default = 0x100
User-programmed lower comparator threshold. When the output of the comparator is high, this value is compared to ADC
(or FADC as set by IRAW, FT0 and FT1). If ADC ≤ THL, the comparator output COUT is set low. To prevent oscillation,
the value of THL should be smaller than THU.
BIT
FIELD NAME
9:0
THL[9:0]
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DESCRIPTION
Lower comparator threshold (straight binary)
Maxim Integrated │ 23
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
THU (Read/Write)
Address = 0x05
Default = 0x200
User-programmed upper comparator threshold. When the output of the comparator is low, this value is compared to ADC
(or FADC as set by IRAW, FT0, and FT1). If ADC ≥ THU, the comparator output COUT is set high. To prevent oscillation,
the value of THU should be larger than THL.
BIT
FIELD NAME
9:0
THU[9:0]
DESCRIPTION
Upper comparator threshold (straight binary)
INRR (Read/Write) (Read only for MAX14002)
Address = 0x06
Default = 0x0C0
User-programmed inrush timer re-arm threshold. ADC reading must drop below this value before another inrush pulse
will occur when the input voltage exceeds INRT. This register is not used in the MAX14002, which always uses FAST
mode (see bit 1 of the CFG register).
BIT
FIELD NAME
9:0
INRR[9:0]
DESCRIPTION
Inrush re-arm threshold (straight binary)
INRT (Read/Write) (Ready only for MAX14002)
Address = 0x07
Default = 0x180
User-programmed inrush current trigger threshold. When the inrush timer is armed, an inrush pulse is initiated when the
ADC reading equals or exceeds this value. This register is not used in the MAX14002, which always uses FAST mode
(see bit 1 of the CFG register).
BIT
FIELD NAME
9:0
INRT[9:0]
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DESCRIPTION
Inrush trigger threshold (straight binary)
Maxim Integrated │ 24
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
INRP (Read/Write) (Read only for MAX14002)
Address = 0x08
Default = 0x1D8
Contains user-programmed values for the inrush current pulse magnitude, inrush pulse duration, and inrush pulse duty cycle.
IT
1:0
5:2
9:6
FIELD NAME
DU[1:0]
DESCRIPTION
DU1 and DU0 set the maximum duty cycle for inrush current over the last 10 seconds.
DU[1:0] = 00 Duty Cycle limiting function off (Default)
DU[1:0] = 01 Duty Cycle = 1.6%
DU[1:0] = 10 Duty Cycle = 3.1%
DU[1:0] = 11 Duty Cycle = 6.3%
TINR[3:0]
4-bit inrush time, 0 to 120ms in 8ms steps, straight binary
TINR[3:0] = 0000 = 0ms
TINR[3:0] = 0001 = 8ms
........
TINR[3:0] = 0110 = 48ms (Default)
…….
TINR[3:0] = 1110 = 112ms
TINR[3:0] = 1111 = 120ms
IINR[3:0]
4-bit inrush current, 50µA to 105mA in 7mA steps, straight binary
IINR[3:0] = 0000 = 50µA
IINR[3:0] = 0001 = 7mA
........
IINR[3:0] = 0111 = 49mA (Default)
…….
IINR[3:0] = 1110 = 98mA
IINR[3:0] = 1111 = 105mA
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Maxim Integrated │ 25
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
CFG (Read/Write)
Address = 0x09
Default = 0x183
Configuration register controls functions within the MAX14001/MAX14002.
BIT
0
1
3:2
FIELD NAME
DESCRIPTION
IRAW
Selects Inrush comparator input multiplexer
0: Inrush comparator input is connected to filtered data in the FADC register
1: Inrush comparator input is connected to ‘raw’ data in the ADC register (default)
FAST
Selects FAST Inrush Mode. ADC is not used to trigger inrush. Inrush starts as soon as
sufficient voltage is present at high-voltage FET to provide the current. Inrush timer is reset
when there is not sufficient voltage to sustain the bias/inrush current.
Note: MAX14002 only works in FAST inrush mode.
0: ADC controlled (unused in MAX14002)
1: FAST inrush mode (default)
FT[1:0]
FT1 and FT0 control the number of readings that are averaged in the ADC filter
FT[1:0] = 00 Filtering off (default)
FT[1:0] = 01 Average 2 readings
FT[1:0] = 10 Average 4 readings
FT[1:0] = 11 Average 8 readings
4
EXTI
Connects the 70µA current source to the REFIN pin. This current powers an external shunt
voltage reference.
0: Current source off (default)
1: Current source on and connected to the REFIN pin (external shunt reference)
5
EXRF
Selects the voltage reference source for the ADC.
0: Internal voltage reference enabled (default)
1: External voltage reference enabled
9:6
IBIAS[3:0]
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4-bit bias current, 50µA to 3.75mA in 0.25mA steps. This current flows through the highvoltage FET when not in inrush mode.
IBIAS[3:0] = 0000 = 50µA
IBIAS[3:0] = 0001 = 0.25mA
........
IBIAS[3;0] = 0110 = 1.5mA (Default)
…….
IBIAS[3:0] = 1110 = 3.5mA
IBIAS[3:0] = 1111 = 3.75mA
Maxim Integrated │ 26
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
ENBL (Read/Write)
Address = 0x0A
Default = 0x000
The ENA bit in the ENBL register enables the inrush and bias current. At POR, ENA is set to “0”. After programming
all the configuration registers, the user sets ENA to “1”, which enables the IFET current sink. This procedure prevents
unintentional currents from flowing during the configuration process. It is recommended to set this bit at the very end of
the configuration procedure.
BIT
FIELD NAME
3:0
ENBL[3:0]
4
ENA
9:5
ENBL[9:5]
DESCRIPTION
Unused
0: Prevents the field-side current sink (default)
1: Enables the field-side current sink
Unused
ACT (Write and Clear)
Address = 0x0B
Default = 0x000
Immediate action register. When a bit is written to this register, action is taken immediately and the bit is then cleared.
Note: The SRES bit (bit 6) resets only the SPI registers while the RSET bit (bit 7) is acting as the global POR, the DC-DC
converter will turn off and field-side will be reset as well as the logic-side (SPI interface).
BIT
FIELD NAME
DESCRIPTION
5:0
ACT[5:0]
6
SRES
Software reset. Restores all registers to their POR value.
0: Normal operation (default)
1: Software reset
7
RSET
Reset. Has the same effect as a power on reset.
0: Normal operation (default)
1: Reset
8
ACT8
Unused
9
INPLS
Trigger an inrush current pulse. Has no effect when ENA = 0 (in the ENBL Register)
0: Normal operation (default)
1: Trigger an inrush current
Unused
WEN (Read/Write)
Address = 0x0C
Default = 0x000
Write enable register. A value of 0x294 in this register enables writing to the SPI registers. Set to 0x294 prior to writing
to any configuration or verification registers. Set to 0x000 after configuring all registers. Its purpose is to make it highly
unlikely that any settings will be unintentionally changed by noise on the SPI bus.
Note: This register should be reset to 0x000 after configuring the device prior to normal operation.
BIT
FIELD NAME
9:0
WEN[9:0]
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DESCRIPTION
This register must be set to 0x294 prior to writing to any SPI registers.
Maxim Integrated │ 27
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
FLTV (Read/Write)
Address = 0x13
Default = 0x000
FLTEN verification register. Bits are continually compared to the FLTEN register. If any bits do not match, the MV bit in
the FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of FLTEN register POR value.
BIT
FIELD NAME
9:0
FLTV[9:0]
DESCRIPTION
FLTEN verification register. Bits are continually compared to the FLTEN register.
THLV (Read/Write)
Address = 0x14
Default = 0x2FF
THL verification register. Bits are continually compared to the THL register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of THL register POR value.
BIT
FIELD NAME
9:0
THLV[9:0]
DESCRIPTION
THL verification register. Bits are continually compared to the THL register.
THUV (Read/Write)
Address = 0x15
Default = 0x1FF
THU verification register. Bits are continually compared to the THU register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of THU register POR value.
BIT
FIELD NAME
9:0
THUV[9:0]
DESCRIPTION
THU verification register. Bits are continually compared to the THU register.
INRRV (Read/Write) (Read only for MAX14002)
Address = 0x16
Default = 0x33F (0x0C0 for MAX14002)
INRR verification register. Bits are continually compared to the INRR register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of INRR register POR value.
Note: this register is not used in MAX14002. Default value is fixed at 0x0C0.
BIT
FIELD NAME
9:0
INRRV[9:0]
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DESCRIPTION
INRR verification register. Bits are continually compared to the INRR register.
Maxim Integrated │ 28
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
INRTV (Read/Write) (Read only for MAX14002)
Address = 0x17
Default = 0x27F (0x180 for MAX14002)
INRT verification register. Bits are continually compared to the INRT register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of INRT register POR value.
Note: this register is not used in MAX14002. Default value is fixed at 0x180.
BIT
FIELD NAME
9:0
INRTV[9:0]
DESCRIPTION
INRT verification register. Bits are continually compared to the INRT register.
INRPV (Read/Write) (Read only for MAX14002)
Address = 0x18
Default = 0x227 (0x1D8 for MAX14002)
INRP verification register. Bits are continually compared to the INRP register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of INRP register POR value.
Note: this register is not used in MAX14002. Default value is fixed at 0x1D8.
BIT
FIELD NAME
9:0
INRPV[9:0]
DESCRIPTION
INRP verification register. Bits are continually compared to the INRP register.
CFGV (Read/Write)
Address = 0x19
Default = 0x27C
CFG verification register. Bits are continually compared to the CFG register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of CFG register POR value.
BIT
FIELD NAME
9:0
CFGV[9:0]
DESCRIPTION
CFG verification register. Bits are continually compared to the CFG register.
ENBLV (Read/Write)
Address = 0x1A
Default = 0x3FF
ENBL verification register. Bits are continually compared to the ENBL register. If any bits do not match, the MV bit in the
FLAGS register is set and FAULT is asserted if the EMV bit in the FLTEN register is set. POR value is 1’s complement
of ENBL register POR value.
BIT
FIELD NAME
9:0
ENBLV[9:0]
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DESCRIPTION
ENBL verification register. Bits are continually compared to the ENBL register.
Maxim Integrated │ 29
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Configuration Flowchart
POWER UP
FIELD SIDE POWER UP
WAIT 100ms
FAULT ASSERTED
FLAGS:MV = 1
READ FLAGS
0x02
DETERMINE ERROR(S)
(EXCEPT MV FLAG)
N
*FLAGS= 0x100?
Y
ENABLE SPI REGISTERS
WRITE
WRITE WEN
VALUE = 0x294
PREVENT MV FLAG
FROM GENERATING FAULT
DISABLE FAULT MV
FLTEN:EMV = 0
INCLUDING FLTEN, THL,
THU, INRR, INRT, INRP,
CFG, AND WRITE ENBL
VALUE = 0x000
WRITE
CONFIGURATION REGISTERS
INCLUDING FLTV, THLV,
THUV, INRRV, INRTV,
INRPV, CFGV, AND WRITE
ENBLV VALUE = 0x000
WRITE
VERIFICATION REGISTERS
ENABLE MV FLAG
TO GENERATE FAULT
ENABLE FAULT MV
WRITE FLTEN AND FLTEV
DISABLE SPI REGISTERS
WRITE
WRITE WEN
VALUE = 0x000
VERIFY SYSTEM SETTINGS
READ BACK
CONFIGURATION REGISTERS
READ TO CLEAR FLAGS:MV
BIT
READ FLAGS
0x02
WRITE WEN
VALUE = 0x294
ENABLE REGISTERS WRITE
WRITE ENBL AND
ENBLV VALUE = 0x010
ENABLE FIELD SIDE CURRENT SINK
READ TO CLEAR FLAGS:MV BIT
READ FLAGS
0x02
FLAGS:MV IS SET DUE TO ENBL AND
ENBLV WRITE.
READ FLAGS
0x02
DETERMINE
ERROR(S)
N
*FLAGS= 0x000?
Y
DISABLE SPI REGISTERS
WRITE
WRITE WEN
VALUE = 0x000
NORMAL OPERATION
READ FLAGS
0x02
DETERMINE
ERROR(S)
N
*FLAGS= 0x000?
Y
Figure 12. Register Programming for Configuration of MAX14001/MAX14002 After Power-On-Reset
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Maxim Integrated │ 30
MAX14001/MAX14002
MAX14002 vs. MAX14001
The MAX14002 is a reduced functionality version of the
MAX14001. The MAX14002 only works in FAST mode
and does not limit the number of inrush pulses. In the
MAX14002, write access is permanently disabled to three
registers: INRR, INRT, and INRP. In addition to disabling
write access to these registers, the three corresponding
verification registers INRRV, INRTV, and INRPV will
default to the same value as the configuration registers,
and an MV fault in the FLAGS register related to these
registers is not generated during startup unless the
memory is corrupted.
All other functions are the same as the MAX14001.
Applications Information
Typical Application Circuit
The MAX14001/MAX14002 are designed for industrial
configurable binary input applications. The input voltage
on the field-side is continuously measured by the integrated
ADC, and results are transmitted across the isolation
barrier and compared to the programmable high and low
thresholds on the logic-side. The COUT pin presents the
real-time result of the comparison and notifies the system
if the binary input is a logic-high/logic-low voltage level.
The MAX14001/MAX14002 also provide current control
through a high-voltage depletion mode FET. While the
drain of the high-voltage FET is connected to the binary
module input, the gate voltage of the FET is set at a
nominal 3.6V by the MAX14001/MAX14002’s GATE pin.
The IFET pin is connected to the source of the FET to sink
a programmable inrush or bias current. When the binary
module input voltage is higher than the trigger threshold,
typically in the case of an external relay closing, an inrush
current is triggered to clean the relay contacts. Control
of the inrush current allows the binary input module to
be used in different pulse counting and relay monitoring
applications. See the Typical Application Circuit for
connection between the devices and the high-voltage FET.
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Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
These devices are configured and monitored through an
SPI interface. The FAULT output can be configured to
generate an interrupt when certain errors are detected
by the embedded self-diagnostic circuit. FAULT is an
open-drain digital output so an external pullup resistor is
needed, typically 4.7kΩ.
Layout, Grounding and Bypassing
Power Supply Recommendations
It is recommended to decouple both the VDD and VDDL
supplies with 10µF capacitors in parallel with 1000pF
capacitors to GNDL. Place the 1000pF capacitors as close
to VDD and VDDL as possible. It is preferred to decouple
the VDD pin through the GNDL pin 11, and the VDDL pin
through the GNDL pin 19. The VDDF pin is the integrated
DC-DC converter output and it is recommended to decouple it with low-ESR capacitors of 0.1µF in parallel with
1000pF to GNDF (pin 10). Place the 1000pF capacitor as
close to VDDF as possible.
For best performance, bypass the GATE pin to the GNDF
plane with a low-ESR capacitor of 0.01µF and bypass the
IFET pin to the GNDF plane with a low-ESR capacitor of
1000pF. REFIN is the optional external voltage reference
input, and, for best performance, bypass REFIN to AGND
with a 0.1µF ceramic capacitor when an external voltage
reference is used. Refer to the Typical Application Circuit
for a connection example.
Layout Considerations
It is recommended to design an isolation or keep-out
channel underneath the MAX14001/MAX14002 that is
free from ground and signal planes. Any galvanic or
metallic connection between the field-side and the logicside defeats the isolation.
Ensure that the decoupling capacitors between VDDL,
VDD and GNDL and between VDDF and GNDF are located
as close as possible to the IC to minimize inductance.
Route important signal lines close to the ground plane to
minimize possible external influences. On the field-side,
it is good practice to separate the ADC input and voltage
reference ground AGND from the GATE and IFET reference
ground GNDF.
Maxim Integrated │ 31
MAX14001/MAX14002
High-Voltage FET
The MAX14001/MAX14002 are designed to use a low
cost, readily available high-voltage depletion mode FET
as the external high-voltage power device. The high voltage
binary input is connected to the FET’s drain while the
gate and source are at low voltages compatible with the
MAX14001/MAX14002. The FET is driven in a cascade
fashion with its gate held at a constant voltage by the
GATE pin. The IFET pin sinks the specified inrush or
bias current from the FET’s source and in the process
modulates the FET’s source voltage. Refer to the Typical
Application Circuit for a connection example.
The MAX14001/MAX14002 need at least 1V on the IFET
pin under worst-case conditions. With a typical voltage of
3.6V, the GATE pin provides a maximum VGS of 2.6V to
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Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
the FET. The required maximum FET on resistance RON
can be calculated as:
RON ≤ (VDRAIN - VIFET)/IINRUSH
Where IINRUSH can be configured to 105mA maximum
and VIFET = 1V. For example, if the FET VDRAIN = 24V,
the maximum RON is calculated to be 219Ω at VGS = 2.6V.
When selecting the FET, temperature tolerance should
also be taken into consideration.
For applications where the peak input voltage does not
exceed 600V, it is recommended to use the following devices:
●●
Infineon BSP135
●●
IXYS IXTY08N100D2
Maxim Integrated │ 32
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Typical Application Circuit
FIELD SIDE
LOGIC SIDE
1.71V TO 5.5V
INTERNAL V REF
10µF
AGND
VIN
GNDF
1000 pF
GNDL
RPULL-UP
IC
REFIN
VDDL
AIN
FAULT
GPI
COUT
GPI
VDD
AGND
SPI Host
AGND
DEPLETION
MODE FET
MAX14001 /MAX14002
GATE
0.01µF
GNDF
IFET
CS
CS
SCLK
SCLK
SDI
MOSI
SDO
MISO
ISET
1000 pF
GNDF
VDDF
120kΩ
GNDF
GNDL
GND
VDD
3.0V TO 3.6V
GNDL
10µF
GNDF
1000 pF
1000 pF
0.1µF
GNDL
GNDF
Ordering Information
Package Information
PART
TEMP RANGE
MAX14001AAP+
-40°C to 125°C
20-SSOP
MAX14002AAP+
-40°C to 125°C
20-SSOP
Chip Information
PROCESS: BiCMOS
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PIN-PACKAGE
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
SSOP-20
A20MS-6
21-0056
90-0094
Maxim Integrated │ 33
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Revision History
REVISION
NUMBER
REVISION
DATE
0
5/16
Initial release
1
8/17
Added UL certification and general data sheet updates
DESCRIPTION
PAGES
CHANGED
—
1, 16, 21, 22, 30
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 34
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