19-3741; Rev 1; 8/10
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
The MAX1434/MAX1436/MAX1437/MAX1438 evaluation
kits (EV kits) are fully assembled and tested circuit
boards that contain all the components necessary to
evaluate the performance of this family of octal 10-/12bit analog-to-digital converters (ADCs). These ADCs
accept differential analog input signals. The EV kits
generate these signals from user-provided singleended input sources. The EV kits’ digital outputs can be
easily sampled with a user-provided high-speed logic
analyzer or data-acquisition system. The EV kits also
feature an on-board deserializer to simplify integration
with standard logic analysis systems. The EV kits operate from 1.8V and 3.3V (plus 1.5V if the FPGA is used)
power supplies and include circuitry that generates a
clock signal from an AC signal provided by the user.
Features
o Low-Voltage and Low-Power Operation
o Optional On-Board Clock-Shaping Circuitry
o Serial Scalable Low-Voltage Signaling
(SLVS)/Low-Voltage Differential Signaling (LVDS)
Outputs
o On-Board LVPECL Differential Output Drivers
o On-Board Deserializer
o LVDS Test Mode
o Fully Assembled and Tested
Part Selection Table
Ordering Information
BITS
SPEED (Msps)
PART
TYPE
MAX1434ECQ+D
10
50
MAX1434EVKIT
EV Kit
MAX1436ECQ+D
12
40
MAX1436EVKIT
EV Kit
MAX1437ECQ+D
12
50
MAX1437EVKIT
EV Kit
MAX1438ECQ+D
12
65
MAX1438EVKIT
EV Kit
PART NUMBER
+Denotes lead(Pb)-free and RoHS compliant.
D = Dry Pack.
Component List
DESIGNATION QTY
C1–C8, C10,
C11, C12,
C57–C64,
C81–C85,
C139, C140,
C147–C156
36
DESCRIPTION
0.1µF ±10%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104K
C9, C29–C44,
C56, C77, C78,
C80, C92, C93,
C134–C137,
C146
28
C13–C20,
C65–C72
0
Not installed, ceramic capacitors
(0603)
C21–C28,
C126–C133
16
39pF ±5%, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H390J
1.0µF ±10%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105K
DESIGNATION QTY
DESCRIPTION
C45, C46, C47,
C86–C89, C143
8
220µF ±20%, 6.3V tantalum
capacitors (C-case)
AVX TPSC227M006R0250
C48, C49, C50,
C144
0
Not installed, capacitors (C-case)
C51, C52, C53,
C90, C91, C145
6
10µF ±10%, 10V X5R ceramic
capacitors (1210)
TDK C3225X5R1A106K
C54
1
2.2µF ±20%, 6.3V X5R ceramic
capacitor (0603)
TDK C1608X5R0J225M
C55,
C157–C176
21
0.01µF ±10%, 25V X7R ceramic
capacitors (0402)
TDK C1005X7R1E103K
C73–C76,
C122–C125
0
Not installed, ceramic capacitors
(0402)
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
General Description
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Component List (continued)
DESIGNATION QTY
C79, C138,
C142
C94–C121
C141
D1
DESCRIPTION
3
10µF ±10%, 4V X5R ceramic
capacitors (0603)
TDK C1608X5R0G106K
28
0.1µF ±20%, 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
1
1
100µF ±20%, 6.3V X5R ceramic
capacitor (1210)
TDK C3225X5R0J107M
Dual Schottky diode (SOT23)
Central Semi CMPD6263S or
Diodes Inc. BAS70-04
DESIGNATION QTY
DESCRIPTION
R45–R50,
R100–R103
10
100Ω ±1% resistors (0603)
R51
1
100kΩ potentiometer, 19-turn, 3/8in
R52, R53, R56
3
4.02kΩ ±1% resistors (0603)
R54
1
5kΩ potentiometer, 19-turn, 3/8in
R55
1
2kΩ ±1% resistor (0603)
R57
1
13.0kΩ ±1% resistor (0603)
R94, R95
2
4.7kΩ ±5% resistors (0603)
R96, R97
2
330Ω ±5% resistors (1206)
R99
1
162Ω ±1% resistor (0603)
R104
1
10kΩ ±5% resistor (0603)
D2, D3
2
Green surface-mount LEDs (0603)
SW1
1
Momentary contact switch
IN0–IN7,
CLOCK
9
SMA PC-mount vertical connectors
T1–T8
8
1:1 800MHz RF transformers
Mini-Circuits ADT1-1WT
J1–J8, JU14
9
2-pin headers
J9–J13, J15
6
Dual-row, 40-pin (2 x 20) headers
TP1–TP8, TP13,
TP14, TP15
0
Test points, not installed
J14
1
9-pin header
TP9–TP12
4
PC test points (red)
TP16
1
PC test point (black)
U1
1
See EV kit specific component list
U2
1
Single LVDS line receivers (8 SO)
Maxim MAX9111ESA
U3
1
Low-noise, low-distortion op amp
(5 SOT23)
Maxim MAX4250EUK
U4
1
TinyLogic UHS dual inverter
(6 SC70)
Fairchild NC7WZ04P6X
U5
1
Virtex II platform FPGA (256 FGBGA)
Xilinx XC2V80-5FG256C or
Xilinx XC2V80-5FG256I
U6
1
PROM (SO-20)
Xilinx XC18V01SO20C
U7–U16
10
LVDS/anything-to-LVPECL translators
(8 µMAX®)
Maxim MAX9375EUA
None
14
Shunts (JU1–JU14)
None
1
PCB: MAX1434/6/7/8 EVALUATION
KIT
JU1–JU11,
JU13
12
3-pin headers
JU12
1
Dual-row, 8-pin (2 x 4) header
1
Digital logic n-channel MOSFET
(SOT23)
Central Semi 2N7002
N1
R1–R8,
R22–R25,
R62–R73
0
R9–R16,
R26–R35,
R77–R81,
R87–R93, R98
0
R17–R21,
R58–R61
9
49.9Ω ±1% resistors (0603)
R36,
R105–R133
30
49.9Ω ±1% resistors (0402)
R37–R44, R74,
R75, R76,
R82–R86
16
10Ω ±1% resistors (0805)
Not installed, resistors (0603)
Not installed, resistors (0402)
µMAX is a registered trademark of Maxim Integrated Products, Inc.
2
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
EV KIT PART NUMBER
DESIGNATION
MAX1434EVKIT
DESCRIPTION
MAX1434ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1436EVKIT
U1
MAX1437EVKIT
MAX1438EVKIT
MAX1436ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1437ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1438ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
Component Suppliers
SUPPLIER
PHONE
WEBSITE
AVX Corporation
843-946-0238
www.avxcorp.com
Central Semiconductor Corp.
631-435-1110
www.centralsemi.com
Diodes Incorporated
805-446-4800
www.diodes.com
Fairchild Semiconductor Corp.
888-522-5372
www.fairchildsemi..com
Mini-Circuits
718-934-4500
www.minicircuits.com
TDK Corp.
847-803-6100
www.component.tdk.com
Note: Indicate that you are using the MAX1434, MAX1436, MAX1437, or MAX1438 when contacting these component suppliers.
Quick Start
Recommended Equipment
•
DC power supplies:
Clock (CVDD) 3.3V, 100mA
Analog (AVDD) 1.8V, 500mA
Digital (OVDD) 1.8V, 150mA
Procedure
The EV kit is a fully assembled and tested surfacemount board. Follow the steps below to verify board
operation. Do not turn on power supplies or enable
signal generators until all connections are completed.
1) Verify that shunts are installed in the following
locations:
JU1 (pins 2-3) → single termination
Optional
Buffers (VPECL) 3.3V, 400mA
Deserializer Core (VD1.5) 1.5V, 200mA
Deserializer I/O (VD3.3) 3.3V, 200mA
•
Signal generator with low phase noise and low jitter
for clock input signal (e.g., HP 8662A, HP 8644B)
•
Signal generator for analog signal inputs (e.g., HP
8662A, HP 8644B)
•
Logic analyzer or data-acquisition system (e.g., HP
16500C, TLA715)
•
Analog bandpass filters (e.g., Allen Avionics, K&L
Microwave) for input signal and clock signal
•
Digital voltmeter
JU2 (pins 2-3) → LVDS outputs
JU3 (pins 2-3) → normal operation
JU4 (pins 2-3) → ADC enabled
JU7 (pins 2-3) → two’s-complement output
JU8 (pins 2-3) → FPGA enabled
JU9, JU10, JU11 (pins 2-3) → channels 0–3
output from FPGA
JU12 (pins 3-4) → internal reference enabled
JU14 (not installed) → disconnect external reference buffer
2) Verify that shunts are installed in the following
locations for configuring the specific EV kit:
a)
JU5 (pins 1-2), JU6 (pins 2-3), JU13 (pins 2-3)
→ 39MHz to 50MHz clock frequency range for
the MAX1434 EV kit.
_______________________________________________________________________________________
3
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
EV Kit Component List
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
b)
JU5 (pins 1-2), JU6 (pins 2-3), JU13 (pins 2-3)
→ 32.5MHz to 40MHz clock frequency range for
the MAX1436 EV kit.
c)
JU5, JU6, JU13 (pins 2-3) → 45MHz to 50MHz
clock frequency range for the MAX1437 EV kit.
d)
JU5, JU6, JU13 (pins 2-3) → 45MHz to 65MHz
clock frequency range for the MAX1438 EV kit.
3) Connect the clock signal generator to the input of
the clock bandpass filter.
4) Connect the output of the clock bandpass filter to
the clock SMA connector.
5) Connect the analog input signal generator to the
input of the analog bandpass filter.
6) Connect the output of the analog bandpass filter to
either one of the SMA connectors labeled IN0–IN7.
The analog input signals can also be monitored at
the 2-pin headers J1–J8.
Note: All eight channels can be operated independently or simultaneously.
7) Connect the logic analyzer to either header J9
(SLVS- or LVDS-compatible signals) or J10–J13
(deserialized 3.3V CMOS-compatible signals). See
the Output Bit Locations section in this document
for header connections.
8) Connect the 1.8V, 500mA power supply to AVDD.
Connect the ground terminal of this supply to GND.
9) Connect the 1.8V, 150mA power supply to OVDD.
Connect the ground terminal of this supply to GND.
10) Connect the 3.3V, 100mA power supply to CVDD.
Connect the ground terminal of this supply to GND.
11) Connect the 3.3V, 400mA power supply to VPECL.
Connect the ground terminal of this supply to GND.
12) Connect the 1.5V, 200mA power supply to VD1_5.
Connect the ground terminal of this supply to GND.
13) Connect the 3.3V, 200mA power supply to VD3_3.
Connect the ground terminal of this supply to GND.
14) Turn on the VD3_3 power supply.
15) Turn on the VD1_5 power supply.
16) Verify that the PROGRAMMING LED (D2) and the
LOCKED LED (D3) are off.
17) Turn on the remaining power supplies.
18) Enable the signal generators. Set the clock signal
generator to output as specified to configuration
signal, with a 2.6VP-P amplitude or higher. Set the
analog input signal generators to output the desired
4
frequency with an amplitude ≤1.4VP-P. All signal
generators should be phase-locked.
19) Verify that the PROGRAMMING LED (D2) is off.
20) Momentarily press switch SW1 and verify that the
LOCKED LED (D3) is on.
21) Enable the logic analyzer.
22) Collect data using the logic analyzer.
Detailed Description of Hardware
The EV kit is a fully assembled and tested circuit board
that contains all the components necessary to evaluate
the performance of the MAX1438, MAX1437, MAX1436,
or MAX1434.
The ADCs accept differential input signals; however,
on-board transformers (T1–T8) convert the singleended signals applied to the IN0–IN7 SMA connectors,
to the required differential signal. The input signals of
the ADC can be measured using a differential oscilloscope probe at headers J1–J8.
Output level translators (U7–U16) buffer and convert
the SLVS or LVDS output signals of the ADC to higher
voltage LVPECL signals, which can be captured by a
wide variety of logic analyzers. The SLVS/LVDS output
signals are accessible at header J9 and the LVPECL
output signals are accessible at header J15.
The EV kit PC board is designed as a six-layer board to
optimize performance of the ADC. Separate analog,
digital, clock, and buffer power planes minimize noise
coupling between analog and digital signals. 50Ω
coplanar transmission lines are used for analog and
clock inputs. 100Ω differential coplanar transmission
lines are used for all digital LVDS outputs. All differential
outputs are terminated with 100Ω termination resistors
between the true and complementary digital outputs.
The trace lengths of the 100Ω differential SLVS/LVDS
lines are matched to within a few thousands of an inch
to minimize layout-dependent data skew.
Power Supplies
For best performance, the EV kit requires separate analog, digital, clock, and buffer power supplies. Two 1.8V
power supplies are used to power the analog (AVDD)
and digital (OVDD) portion of the ADC. The clock circuitry (CVDD) is powered by a 3.3V power supply. A
separate 3.3V power supply (VPECL) is used to power
the output buffers (U7–U16) of the EV kit. 1.5V (VD1_5)
and 3.3V (VD3_3) power supplies are required to power
the deserializer circuit.
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Table 2. MAX1434 PLL Jumper Settings
(JU5, JU6, JU13)
Table 1. Power-Down Jumper Settings (JU4)
2-3*
AVDD
GND
EV KIT FUNCTION
ADC disabled
ADC enabled
*Default configuration: JU4 (2-3).
Clock
By default, the user-provided AC-coupled clock signal
applied to the EV kit CLOCK SMA connector is buffered
on board with two inverters (U4). In this mode, diode
D1 limits the amplitude of the clock signal. Overdriving
the clock input can increase the slew rate of the differential signal, thereby reducing clock jitter. The frequency of the signal should not exceed the maximum
sampling rate of the ADC. The sinusoidal input signal
frequency (fCLK) determines the sampling rate of the
ADC. The clock signal applied to the ADC can be
observed at test point TP10.
Optional Clock-Shaping Circuit
The EV kit also features an optional on-board clockshaping circuit that generates a clock signal with variable duty cycle from the AC-coupled sine-wave signal
applied to the CLOCK SMA connector. The MAX9111
differential line receiver (U2) processes the clock input
signal and generates the required CMOS clock signal.
To use this circuitry, cut the trace on the printed circuit
(PC) board at R78 and install 0Ω resistors at R35 and
R77. The signal’s duty cycle can be adjusted with potentiometer R54. With a 3.3V clock supply voltage (CVDD),
a clock signal with a 50% duty cycle (recommended)
can be achieved by adjusting R54 until a voltage of
1.32V is produced across test points TP12 and TP16.
SHUNT POSITION
1-2
POWER-DOWN
CONNECTIONS
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
MIN
MAX
2-3
2-3
2-3
2-3*
2-3*
1-2*
39.0
Unused
50.0
2-3
1-2
2-3
27.0
39.0
2-3
1-2
1-2
19.5
27.0
1-2
2-3
2-3
13.5
19.5
1-2
2-3
1-2
9.8
13.5
1-2
1-2
2-3
6.8
9.8
1-2
1-2
1-2
4.8
6.8
*Default configuration: JU5, JU6 (2-3), JU13 (1-2).
Table 3. MAX1436 PLL Jumper Settings
(JU5, JU6, JU13)
CLOCK INPUT RANGE
(MHz)
JUMPER
JU13
(PLL1)
SHUNT POSITION
SHUNT
POSITION
CLOCK INPUT RANGE
(MHz)
JUMPER
JU6
(PLL2)
JU5
(PLL3)
MIN
MAX
2-3
2-3
2-3
2-3*
2-3*
1-2*
32.5
Unused
40.0
2-3
1-2
2-3
22.5
32.5
2-3
1-2
1-2
16.3
22.5
1-2
2-3
2-3
11.3
16.3
1-2
2-3
1-2
8.1
11.3
1-2
1-2
2-3
5.6
8.1
1-2
1-2
1-2
4.0
5.6
*Default configuration: JU5, JU6 (2-3), JU13 (1-2).
PLL Frequency Mode Selection
When driving the EV kit with clock signals lower than
the maximum specified sampling rate of the ADC, the
phased-locked-loop (PLL) circuit of the ADC must be
set accordingly. Refer to the PLL Inputs (PLL0–PLL3)
section in the ADC data sheet for further details about
the operation of the internal PLL. Jumpers JU5, JU6,
and JU13 control the PLL mode of the ADC. See Tables
2, 3, 4, or 5 for shunt positions. Configure jumpers JU5,
JU6, and JU13 accordingly and ensure that the clock
signal frequency falls between the minimum and maximum limits listed in Table 2 through Table 5.
_______________________________________________________________________________________________________
5
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Power-Down
Jumper JU4 controls the power-management feature of
data converter U1. See Table 1 for jumper JU4 shunt
positions.
Table 4. MAX1437 PLL Jumper Settings
(JU5, JU6, JU13)
CLOCK INPUT RANGE
(MHz)
SHUNT POSITION
JUMPER
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
2-3*
2-3*
2-3*
45.0
50.0
2-3
2-3
1-2
32.5
45.0
2-3
1-2
2-3
22.5
32.5
2-3
1-2
1-2
16.3
22.5
1-2
2-3
2-3
11.3
16.3
1-2
2-3
1-2
8.1
11.3
1-2
1-2
2-3
5.6
8.1
1-2
1-2
1-2
4.0
5.6
MIN
MAX
Table 6. Reference Jumper Settings (JU12)
SHUNT
POSITION
Table 5. MAX1438 PLL Jumper Settings
(JU5, JU6, JU13)
CLOCK INPUT RANGE
(MHz)
JUMPER
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
MIN
MAX
2-3*
2-3*
2-3*
45.0
65.0
2-3
2-3
1-2
32.5
45.0
2-3
1-2
2-3
22.5
32.5
2-3
1-2
1-2
16.3
22.5
1-2
2-3
2-3
11.3
16.3
1-2
2-3
1-2
8.1
11.3
1-2
1-2
2-3
5.6
8.1
1-2
1-2
1-2
4.0
5.6
*Default configuration: JU5, JU6, JU13 (2-3).
REFADJ PIN
CONNECTION
EV KIT FUNCTION
1-2
Connected to
AVDD
Internal reference disabled.
Apply an external reference
voltage at the REFIO pad.
Verify that a shunt is installed
on jumper JU14.
3-4*
Connected to
GND
Internal reference enabled.
Verify that a shunt is not
installed on jumper JU14.
5-6**
Connected to
REFIO through
R57 and R51
Increase full-scale range by
adjusting potentiometer R51.
7-8**
Connected to
GND through
R57 and R51
Compensate for gain errors by
adjusting potentiometer R51.
*Default configuration: JU5, JU6, JU13 (2-3).
SHUNT POSITION
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
*Default configuration: JU12 (3-4).
**Refer to the Full-Scale Range Adjustments using the Internal
Reference section in the MAX1434, MAX1436, MAX1437, or
MAX1438 IC data sheet.
ence. Use the 2 x 4 header JU12 to configure the
desired reference mode. See Table 6 for the appropriate shunt settings.
Output Signal
The ADC features eight serial LVDS-compatible digital
outputs. Each output transmits the converted analog
input signals of channels 0 through 7. Two additional
outputs (CLKOUT and FRAME) are provided for data
synchronization. Refer to the MAX1434, MAX1436,
MAX1437, or MAX1438 data sheet for more details.
Output Format
The digital output coding can be chosen to be two’s
complement or straight offset binary by configuring
jumper JU7. See Table 7 for the appropriate jumper
configuration.
Input Signal
Although the ADC accepts differential analog input signals, the EV kit only requires a single-ended analog
input signal with an amplitude of less than 1.4VP-P provided by the user. On-board transformers (T1–T8) convert the single-ended analog input signal and generate
differential analog signals at the ADCs’ differential input
pins. Connect the single-ended analog input signals to
SMA connectors IN0–IN7 for channel 0 to channel 7,
respectively.
Reference Voltage
The EV kit can be configured to use the ADC’s 1.24V
internal reference, or a stable, low-noise, external refer6
Table 7. Output Format Jumper Settings (JU7)
SHUNT
POSITION
T/B PIN
CONNECTION
DESCRIPTION
1-2
AVDD
Straight Offset Binary Selected.
Digital output in straight offset
binary format.
2-3*
GND
Two’s Complement Selected.
Digital output in two’scomplement format.
*Default configuration: JU7 (2-3).
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Table 8. Double-Termination Jumper
Settings (JU1)
SHUNT
POSITION
DT PIN
CONNECTION
EV KIT FUNCTION
1-2
AVDD
Double Termination Selected.
Outputs are double-terminated.
2-3*
GND
Single Termination Selected.
Outputs are single-terminated.
*Default configuration: JU1 (2-3).
SLVS/LVDS Outputs
The ADC is capable of generating SLVS or LVDS signals
at its outputs. Jumper JU2 controls this feature of the
ADC. See Table 9 for shunt positions. Regardless of
which output signal type is selected, the output buffers
(U7–U16) will convert the data to LVPECL logic levels.
When operating in SLVS output mode, JU1 must be configured for double-termination (shunt across pins 1 and 2).
Table 9. SLVS/LVDS Jumper Settings (JU7)
SHUNT
POSITION
SLVS/LVDS PIN
CONNECTION
1-2
AVDD
SLVS
2-3*
GND
LVDS
ADC OUTPUT
*Default configuration: JU7 (2-3).
LVDS Test Pattern
To debug signal integrity problems, the ADC can generate a factory-set test pattern on all of the output channels. Jumper JU3 controls this feature. See Table 10 for
the appropriate shunt positions. The test pattern for the
MAX1436, MAX1437, and MAX1438 is 0000 1011 1101.
The test pattern for the MAX1434 is 00 0101 1101 (MSB
to LSB).
Table 10. LVDS Test Pattern Jumper
Settings (JU3)
SHUNT
POSITION
LVDSTEST PIN
CONNECTION
EV KIT FUNCTION
1-2
AVDD
Test pattern transmitted, LSB
first, on all SLVS/LVDS outputs
2-3*
GND
Normal operation
*Default configuration: JU3 (2-3).
Output Bit Locations
The digital outputs of the ADC are connected to the 40pin header J9. All PC board trace lengths are matched
to minimize data skew and improve the overall dynamic
performance of the device. Additionally, 10 drivers
(U7–U16) buffer and level-translate the digital outputs
to LVPECL-compatible signals. The drivers increase the
differential voltage swing, and are capable of driving
large capacitive loads, which may be present at the
logic analyzer connection. The outputs of the buffers
are connected with 40-pin header J15. See Table 11 for
bit locations of headers J9 and J15.
Table 11. Output Bit Locations
UNBUFFERED BUFFERED
DESCRIPTION
(LVDS or SLVS) (LVPECL)
SIGNAL
CH0
CH1
CH2
CH3
CLKOUT
FRAME
CH4
CH5
CH6
CH7
P
J9-1
J15-1
N
J9-2
J15-2
P
J9-5
J15-5
N
J9-6
J15-6
P
J9-9
J15-9
N
J9-10
J15-10
P
J9-13
J15-13
N
J9-14
J15-14
P
J9-17
J15-17
N
J9-18
J15-18
P
J9-21
J15-21
N
J9-22
J15-22
P
J9-25
J15-25
N
J9-26
J15-26
P
J9-29
J15-29
N
J9-30
J15-30
P
J9-33
J15-33
N
J9-34
J15-34
P
J9-37
J15-37
N
J9-38
J15-38
Channel 0
Channel 1
Channel 2
Channel 3
Clock
Frame
Channel 4
Channel 5
Channel 6
Channel 7
P = True (+).
N = Complementary (-).
_______________________________________________________________________________________
7
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Double-Termination Settings
The ADC features trimmed, internal 100Ω termination
resistors between the positive (true) and negative
(complementary) line of each output (D0–D7, CLKOUT,
and FRAME). The EV kit circuit also features 100Ω termination resistors located at the far end of each differential output pair. Activating the internal termination
helps eliminate unwanted reflections on the signal
traces. Use jumper JU1 to activate either single or double-termination. See Table 8 for appropriate shunt positions that select the termination architecture.
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
On-Board Deserializer
Deserializer Output Enabled
The EV kit features an on-board deserializer that converts the serial outputs of the ADC to a parallel data
stream. The deserializer uses a delay-locked loop (DLL)
to synchronize itself with the incoming serial data stream.
After every change in ADC clock frequency, reset
this DLL by pressing switch SW1. If the LOCKED LED
D3 is not lit, the serial data stream is not synchronized
and the outputs of the deserializer are not valid.
Channel 0 through channel 7 data is captured on headers J10–J13. Only four channels can be captured at
one time on the EV kit. Configure jumpers JU9, JU10,
and JU11 to select the location of the channels. See
Table 12 for jumper JU9, JU10, JU11 configuration.
See Table 13 for bit locations.
Jumper JU8 controls the output enabled of the deserializer. See Table 14 for jumper JU8 configuration.
Table 14. Deserializer Output Enables (JU8)
SHUNT
POSITION
EV KIT FUNCTION
1-2
Deserializer output disabled
2-3*
Deserializer output enabled
*Default configuration: JU8 (2-3).
Table 12. Output Channel Locations (JU9,
JU10, JU11)
JU9 (S2) JU10 (S1) JU11 (S0)
SHUNT
SHUNT
SHUNT
POSITION POSITION POSITION
J10
J11
J12
J13
2-3
2-3
2-3
CH0
CH1 CH2
CH3
2-3
2-3
1-2
CH4
CH5 CH6
CH7
2-3
1-2
2-3
CH0
CH4 CH1
CH5
2-3
1-2
1-2
CH0
CH6 CH1
CH7
1-2
2-3
2-3
CH2
CH4 CH3
CH5
1-2
2-3
1-2
CH2
CH6 CH3
CH7
Table 13. Output Bit Locations (J10–J13)
BIT
POSITION
CLK
J10-38
J11-38
J12-38
J13-38
D11
J10-26
J11-26
J12-26
J13-26
D10
J10-24
J11-24
J12-24
J13-24
D9
J10-22
J11-22
J12-22
J13-22
D8
J10-20
J11-20
J12-20
J13-20
D7
J10-18
J11-18
J12-18
J13-18
D6
J10-16
J11-16
J12-16
J13-16
D5
J10-14
J11-14
J12-14
J13-14
D4
J10-12
J11-12
J12-12
J13-12
D3
J10-10
J11-10
J12-10
J13-10
D2
J10-8
J11-8
J12-8
J13-8
D1
J10-6
J11-6
J12-6
J13-6
D0
J10-4
J11-4
J12-4
J13-4
Note: Odd numbered pins are connected to ground.
Remaining pins are no connects.
8
_______________________________________________________________________________________
Figure 1. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—ADC (Sheet 1 of 6)
_______________________________________________________________________________________
IN7
IN6
IN5
IN4
IN3
IN2
IN1
R61
49.9Ω
1%
R60
49.9Ω
1%
R59
49.9Ω
1%
R58
49.9Ω
1%
R20
49.9Ω
1%
R19
49.9Ω
1%
R18
49.9Ω
1%
R65
SHORT
C60
0.1µF
R64
SHORT
C59
0.1µF
R63
SHORT
C58
0.1µF
R62
SHORT
C57
0.1µF
R25
SHORT
C4
0.1µF
R24
SHORT
C3
0.1µF
R23
SHORT
C2
0.1µF
R22
SHORT
2
4
3
6
5
T8
4
3
1
2
6
5
T7
4
1
2
3
6
5
T6
4
1
2
3
6
5
T5
4
1
2
3
6
5
1
4
3
T4
2
6
5
T3
4
3
1
2
5
6
3
T2
4
5
1
2
R73
SHORT
C64
TP8 0.1µF
R72
SHORT
R71
SHORT
C63
TP7 0.1µF
R70
SHORT
R69
SHORT
C62
TP6 0.1µF
R68
SHORT
R67
SHORT
C61
TP5 0.1µF
R66
SHORT
R8
SHORT
C8
TP4 0.1µF
R7
SHORT
R6
SHORT
C7
TP3 0.1µF
R5
SHORT
R4
SHORT
C6
TP2 0.1µF
R3
SHORT
R2
SHORT
C72
SHORT
C71
SHORT
C70
SHORT
C69
SHORT
C68
SHORT
C67
SHORT
C66
SHORT
C65
SHORT
C20
SHORT
C19
SHORT
C18
SHORT
C17
SHORT
C16
SHORT
C15
SHORT
C14
SHORT
C125
OPEN
R86
10Ω
1%
R85
10Ω
1%
C124
OPEN
R84
10Ω
1%
R83
10Ω
1%
C123
OPEN
R82
10Ω
1%
R76
10Ω
1%
C122
OPEN
R75
10Ω
1%
R74
10Ω
1%
C76
OPEN
R44
10Ω
1%
R43
10Ω
1%
C75
OPEN
R42
10Ω
1%
R41
10Ω
1%
C74
OPEN
R40
10Ω
1%
R39
10Ω
1%
C73
OPEN
R38
10Ω
1%
C133
39pF
C132
39pF
C131
39pF
C130
39pF
C129
39pF
C128
39pF
C127
39pF
C126
39pF
C28
39pF
C27
39pF
C26
39pF
C25
39pF
C24
39pF
C23
39pF
C22
39pF
R98
SHORT
R16
OPEN
R93
SHORT
R92
SHORT
R15
OPEN
R91
SHORT
R90
SHORT
R14
OPEN
R89
SHORT
R88
SHORT
R13
OPEN
R87
SHORT
R33
SHORT
R12
OPEN
R32
SHORT
R31
SHORT
R11
OPEN
R30
SHORT
R29
SHORT
R10
OPEN
R28
SHORT
R27
SHORT
R9
OPEN
J8
J7
J6
J5
J4
J3
J2
J1
29
28
24
23
21
20
18
17
9
8
6
5
3
2
98
28
IN6N
IN6P
IN5N
IN5P
IN4N
IN4P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
IN7N
29
AVDD
1
AVDD
4
AVDD
AGND
AVDD
AGND
AVDD
AGND
AVDD
7 10 16 19
U1
MAX1434 ADC FOR MAX1434 EVKIT
MAX1436 ADC FOR MAX1436 EVKIT
MAX1437 ADC FOR MAX1437 EVKIT
MAX1438 ADC FOR MAX1438 EVKIT
AVDD
AVDD
AGND
22 25 26 27 30 36 92 96 99 100 89
AGND
97
AVDD
AGND
C5
TP1 0.1µF
AVDD
AGND
6
AVDD
AGND
T1
AGND
1
CVDD
AGND
R26
SHORT
OVDD
AGND
C21
39pF
OVDD
AGND
C13
SHORT
OVDD
N.C.
AGND
AGND
AGND
AVDD
C79
10µF
OUT3N
OUT3P
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
91
C138
10µF
REFADJ
REFIO
CMOUT
CLK
DT
SLVS/LVDS
LVDSTEST
PD
PLL3
PLL2
PLL1
T/B
OUT7N
OUT7P
OUT6N
OUT6P
OUT5N
OUT5P
OUT4N
OUT4P
FRAMEN
FRAMEP
CLKOUTN
CLKOUTP
C142
10µF
OVDD
14 31 50 51 70 75 76 90
N.C.
R1
SHORT
OVDD
AGND
C1
0.1µF
OVDD
AGND
R17
49.9Ω
1%
OVDD
43 46 49 54 57 60 63 64 67 71 74 77
OVDD
N.C.
IN0
AVDD
CVDD
OVDD
N.C.
34
OVDD
N.C.
39 40 41 42 86 87 88
OVDD
N.C.
AVDD
OVDD
N.C.
94
93
95
35
32
33
80
81
82
83
84
85
44
45
47
48
52
53
55
56
58
59
61
62
65
66
68
69
72
73
78
79
R103
100Ω
1%
R102
100Ω
1%
R101
100Ω
1%
R100
100Ω
1%
R50
100Ω
1%
R49
100Ω
1%
R48
100Ω
1%
R47
100Ω
1%
R46
100Ω
1%
R45
100Ω
1%
REFADJ
CLK
DT
SLVS/LVDS
LVDSTEST
PD
PLL3
PLL2
PLL1
T/B
OUT7N
OUT7P
OUT6N
OUT6P
OUT5N
OUT5P
OUT4N
OUT4P
FRAMEN
FRAMEP
CLKOUTN
CLKOUTP
OUT3N
OUT3P
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
C30
1.0µF
C31
1.0µF
C32
1.0µF
C33
1.0µF
C34
1.0µF
C35
1.0µF
C134
1.0µF
C37
1.0µF
C135
1.0µF
C38
1.0µF
C136
1.0µF
C39
1.0µF
C137
1.0µF
C40
1.0µF
C41
1.0µF
C42
1.0µF
C43
1.0µF
T/B
REFIO
DT
SLVS/LVDS
LVDSTEST
PD
PLL3
PLL2
TP9
C56
1.0µF
3
3
3
3
3
3
3
3
JU1
2
JU2
2
JU3
2
JU4
2
JU5
2
JU6
2
JU13
2
JU7
2
1
1
1
1
1
1
1
1
AVDD
GND
VPECL
GND
AVDD
GND
OVDD
GND
CVDD
C45
220µF
6.3V
C46
220µF
6.3V
C47
220µF
6.3V
C143
220µF
6.3V
VPECL
AVDD
OVDD
CVDD
CVDD
C144
OPEN
C48
OPEN
C50
OPEN
C49
OPEN
PLACE CAPACITORS NEXT TO PINS 43, 46, 49, 54, 57, 60, 63/64, 67, 71, 74, 77 OF U1.
OVDD
OVDD
PLL1
C9
1.0µF
C29
1.0µF
PLACE CAPACITORS NEXT TO PINS 11/12, 13, 15, 37/38, 39/40, 41/42, 86/87, 88 OF U1.
AVDD
C145
10µF
C51
10µF
C53
10µF
C52
10µF
C44
1.0µF
C36
1.0µF
C146
1.0µF
C77
1.0µF
C80
1.0µF
C78
1.0µF
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
IN7P
OVDD
REFN
11 12 13 15 37 38
REFP
R37
10Ω
1%
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
9
10
Figure 2. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—Clock, Voltage Reference (Sheet 2 of 6)
______________________________________________________________________________________
OUT7P
OUT6P
OUT5P
OUT4P
FRAMEP
CLKOUTP
OUT3P
OUT2P
OUT1P
OUT0P
C140
0.1µF
CVDD
5
VCC
J9-39 J9-40
J9-37 J9-38
J9-35 J9-36
J9-33 J9-34
J9-31 J9-32
J9-29 J9-30
J9-27 J9-28
J9-25 J9-26
J9-23 J9-24
J9-21 J9-22
J9-19 J9-20
J9-17 J9-18
J9-15 J9-16
J9-13 J9-14
J9-11 J9-12
J9-10
J9-8
J9-9
J9-6
J9-7
J9-4
J9-3
J9-5
J9-2
2
J9-1
J9
GND
1
Y1 U4 A1
TP10
NC7WZ04
3
4
A2
Y2
6
D1
3
R57
13.0kΩ
1%
3
OUT7N
OUT6N
OUT5N
OUT4N
FRAMEN
CLKOUTN
OUT3N
OUT2N
OUT1N
1
6
7
R51
100kΩ
2
R35
OPEN
1
OUT0N
TP11
CLK
REFADJ
2
R
CVDD
L
N.C.
OUT
8
U2
VCC
BD7P
BD6P
BD5P
BD4P
BFMP
BCKP
BD3P
BD2P
BD1P
BD0P
5
GND
JU12-6
JU12-5
J15-8
J15-6
J15-4
J15-2
J15-10
J15
J15-39 J15-40
J15-37 J15-38
J15-35 J15-36
J15-33 J15-34
J15-31 J15-32
J15-29 J15-30
J15-27 J15-28
J15-25 J15-26
J15-23 J15-24
J15-21 J15-22
J15-19 J15-20
J15-17 J15-18
J15-15 J15-16
J15-13 J15-14
J15-11 J15-12
J15-9
J15-7
J15-5
J15-3
J15-1
JU12-8
JU12-4
JU12-3
JU12-7
TP12
R78
SHORT
C11
0.1µF
JU12-2
JU12
4
2
3
1
JU12-1
N.C.
IN1P
N.C.
IN1N
C10
0.1µF
C54
2.2µF
MAX9111
C55
0.01µF
CVDD
REFADJ
AVDD
R55
2kΩ
1%
BD7N
BD6N
BD5N
BD4N
BFMN
BCKN
BD3N
BD2N
BD1N
BD0N
REFIO
R77
OPEN
R54
5kΩ
TP16 3
1
2
R52
4.02kΩ
1%
CVDD
C141
100µF
R34
SHORT
R53
4.02kΩ
1%
R56
4.02kΩ
1%
CVDD
R99
162Ω
1%
C12
0.1µF
REFIN
JU14
R21
49.9Ω
1%
3
2
1
CLOCK
IN+
VSS
OUT
MAX4250
U3
VDD
IN-
5
4
CVDD
C139
0.1µF
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
______________________________________________________________________________________
OUT3N
OUT3P
OUTON
3
2
3
2
IN
IN
IN
IN
1
4
4
U7
8
MAX9375
GND
U10
8
5
C147
0.1µF
6
7
OUT
OUT
6
7
C163
0.01µF
C150
0.1µF
OUT
OUT
C157
0.01µF
VPECL
5
MAX9375
VCC
GND
OUTOP
VCC
1
VCC
GND
R115
49.9Ω
1%
R114
49.9Ω
1%
R106
49.9Ω
1%
R105
49.9Ω
1%
R116
49.9Ω
1%
BD3N
BD3P
BDON
R107
49.9Ω
1%
BDOP
C164
0.01µF
C158
0.01µF
CLKOUTN
CLKOUTP
OUT1N
OUT1P
3
2
3
2
IN
IN
IN
IN
1
1
4
4
U8
8
MAX9375
U11
8
5
OUT
6
7
C165
0.01µF
C151
0.1µF
OUT
VPECL
5
OUT
6
7
C159
0.01µF
C148
0.1µF
OUT
VPECL
MAX9375
VCC
GND
VCC
GND
VCC
GND
VCC
GND
R118
49.9Ω
1%
R117
49.9Ω
1%
R109
49.9Ω
1%
R108
49.9Ω
1%
BCKN
R119
49.9Ω
1%
BCKP
BD1N
R110
49.9Ω
1%
BD1P
FRAMEP
OUT2N
FRAMEN
C166
0.01µF
C160
0.01µF
OUT2P
3
2
3
2
IN
IN
IN
IN
1
1
4
4
U9
8
MAX9375
U12
8
5
6
OUT
6
7
C167
0.01µF
C152
0.1µF
OUT
VPECL
5
OUT
7
C161
0.01µF
C149
0.1µF
OUT
VPECL
MAX9375
VCC
GND
VCC
R121
49.9Ω
1%
R120
49.9Ω
1%
R112
49.9Ω
1%
R111
49.9Ω
1%
R113
49.9Ω
1%
BFMN
R122
49.9Ω
1%
BFMP
BD2N
BD2P
C168
0.01µF
C162
0.01µF
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
GND
VCC
GND
VCC
GND
VCC
GND
VPECL
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 3. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—LVPECL Level Translators (Sheet 3 of 6)
11
OUT5N
OUT5P
OUT4N
3
2
3
2
IN
IN
IN
IN
1
4
4
U13
8
MAX9375
GND
U14
8
5
C153
0.1µF
6
7
OUT
OUT
6
7
C171
0.01µF
C154
0.1µF
OUT
OUT
C169
0.01µF
VPECL
5
MAX9375
VCC
GND
OUT4P
VCC
1
VCC
GND
R130
49.9Ω
1%
R129
49.9Ω
1%
R124
49.9Ω
1%
R123
49.9Ω
1%
R125
49.9Ω
1%
R131
49.9Ω
1%
BD5N
BD5P
BD4N
BD4P
C172
0.01µF
C170
0.01µF
OUT7N
OUT7P
OUT6N
OUT6P
3
2
3
2
IN
IN
IN
IN
1
1
4
4
U15
8
MAX9375
U16
8
5
6
OUT
6
7
C175
0.01µF
C156
0.1µF
OUT
VPECL
5
OUT
7
C173
0.01µF
C155
0.1µF
OUT
VPECL
MAX9375
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
12
GND
VPECL
R133
49.9Ω
1%
R132
49.9Ω
1%
R127
49.9Ω
1%
R126
49.9Ω
1%
R36
49.9Ω
1%
BD7N
BD7P
BD6N
R128
49.9Ω
1%
BD6P
C176
0.01µF
C174
0.01µF
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 4. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—LVPECL Level Translators (Sheet 4 of 6)
______________________________________________________________________________________
______________________________________________________________________________________
BD1N
BD1P
BD2N
BD2P
BD3N
BD3P
BCKN
BCKP
BFMN
BFMP
BD4N
BD4P
BD5N
BD5P
BD6N
BD6P
J10-2
J10-4
J10-6
J10-8
J10-10
J10-12
J10-14
J10-16
J10-18
J10-20
J10-22
J10-24
J10-26
J10-28
J10-30
J10-32
J10-34
J10-36
J10-38
J10-40
J10
B13
C13
A12
B12
A10
B10
A9
B9
B8
A8
B7
A7
B5
A5
C4
B4
M1
N1
P1
T3
T4
T7
T8
T9
T10
P16
N16
M16
C10
C11
D11
G16
U5-H
LO1N_1
LO1P_1
XC2V80-6FG256C
LO3N_1/VRP_1
LO3P_1/VRN_1
L94N_1
L94P_1/VREF_1
L96N_1/GCLK3P
L96P_1/GLCK2S
L96N_0/GLCK5P
L96P_0/GLCK4S
L94N_0/VREF_0
L94P_0
LO3N_0/VRP_0
LO3P_0/VRN_0
LO1N_0
LO1P_0
LO1P_2
LO1N_2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
LO1P_7
LO1N_7
XC2V80–5FG256C
CLKDES
LO2N_7/VRP_7
L96P_6
L94N_6
LO2N_1
L95N_1/GCLK1P
L95P_0/GCLK6S
LO3P_4/D3/AVN4
LO2P_0
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D3
J2
J3
C12
C9
C8
P12
C5
B6
A6
B11
A11
G12
F12
F15
F16
J11-1
J11-3
J11-5
J11-7
J11-9
J11-11
J11-13
J11-15
J11-17
J11-19
J11-21
J11-23
J11-25
J11-27
J11-29
J11-31
J11-33
J11-35
J11-37
J11-39
J11
D16
C16
M6
M11
N6
N11
P6
P11
R5
R6
R11
R12
T6
T11
D1
C1
BD0P
BD0N
BD7P
BD7N
J11-2
J11-4
J11-6
J118
J11-10
J11-12
J11-14
J11-16
J11-18
J11-20
J11-22
J11-24
J11-26
J11-28
J11-30
J11-32
J11-34
J11-36
J11-38
J11-40
K1
M2
N2
R4
R7
R8
R9
R10
R13
N15
M15
K16
D10
E10
E11
G2
LO2P_7/VRN_7
LO3P_2/VREF_2
LO3N_2
N.C.
N.C.
N.C.
N.C.
LO2P_2/VRN_2
LO2N_2/VRP_2
LO2P_1
L95P_1/GCLK0S
L95N_O/GCLK7P
N.C.
N.C.
N.C.
N.C.
U5-B
XC2V80–6FG256C
CLKDES
L93N_6/VREF_6
L04P_6
LO2N_6/VRP_6
LO2N_5/D6
L94P_5/VREF_5
L96P_5/GCLK6P
L96N_4/GCLK1S
L94N_4/VREF_4
LO2P_4/D1
LO2N_3/VRP_3
LO4P_3
L93N_3/VREF_3
N.C.
N.C.
N.C.
L93N_7
3
3
U5-A
JU9 2
JU8 2
LO4N_6
LO1N_6
LO1P_6
LO1P_5/CS
LO1N_5/RDWR
L94N_5
L96N_5/GCLK7S
L96P_4/GCLKOP
L94P_4
LO1P_3
LO1N_3
LO4N_3
N.C.
N.C.
N.C.
L93P_2/VREF_2
1
1
D2
E14
E13
P7
P10
T5
T12
D15
D14
D12
D9
D8
K12
L12
L15
L16
J12-1
J12-3
J12-5
J12-7
J12-9
J12-11
J12-13
J12-15
J12-17
J12-19
J12-21
J12-23
J12-25
J12-27
J12-29
J12-31
J12-33
J12-35
J12-37
J12-39
J12-2
J12-4
J12-6
J12-8
J12-10
J12-12
J12-14
J12-16
J12-18
J12-20
J12-22
J12-24
J12-26
J12-28
J12-30
J12-32
J12-34
J12-36
J12-38
J12-40
J12
J1
K2
L3
M4
N5
N8
N9
N12
M13
L14
K15
J16
C6
C7
D6
G3
XC2V80–6FG256C
CLKDES
LO2N_0
L95P_4/GCLK2P
L94N_2
LO4N_2
L93N_2
L91P_2
L91N_2
L93P_7/VREF_7
LO6P_2
LO6N_2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
U5-C
L96N_6
L93P_6
LO6N_6
LO3P_6
LO3P_5/D5/AVN5
L95P_5/GCLK4P
L95N_4/GCLK3S
LO3N_4/D2/AVP4
LO3P_3
LO6N_3
L93P_3
L96N_3
N.C.
N.C.
N.C.
L91P_7
3
JU10 2
1
VD3.3
D5
P9
H13
E15
G15
G14
G13
G1
F14
F13
N7
N10
K5
L5
L2
L1
J13-1
J13-3
J13-5
J13-7
J13-9
J13-11
J13-13
J13-15
J13-17
J13-19
J13-21
J13-23
J13-25
J13-27
J13-29
J13-31
J13-33
J13-35
J13-37
J13-39
J13-2
J13-4
J13-6
J13-8
J13-10
J13-12
J13-14
J13-16
J13-18
J13-20
J13-22
J13-24
J13-26
J13-28
J13-30
J13-32
J13-34
J13-36
J13-38
J13-40
J13
H1
H2
H3
J4
K4
L4
L13
K13
J13
H14
H15
H16
D7
E6
E7
G4
L94N_7
L95N_5/GCLK5S
LO3N_5/D4/AVP5
LO2P_5/D7
LO2P_3/VRN_3
LO2P_6/VRN_6
LO3N_3/VREF_3
LO3N_6/VREF_6
L91N_3
L91N_6
L96P_3
L94N_3
N.C.
N.C.
N.C.
N.C.
U5-D
XC2V80–6FG256C
CLKDES
L96P_7
L96N_7
L94P_7
L94P_6
L91P_6
LO6P_6
LO6P_3
L91P_3
L94P_3
L94P_2
L96N_2
L96P_2
N.C.
N.C.
N.C.
L91N_7
3
JU11 2
1
VD3.3
H4
P8
P5
P4
N14
N3
M14
M3
K14
K3
J15
J14
G5
F5
F2
F1
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
J10-1
J10-3
J10-5
J10-7
J10-9
J10-11
J10-13
J10-15
J10-17
J10-19
J10-21
J10-23
J10-25
J10-27
J10-29
J10-31
J10-33
J10-35
J10-37
J10-39
VD3.3
VD3.3
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 5. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—Deserializer Input and Outputs (Sheet 5 of 6)
13
14
Figure 6. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—PROM and FPGA (Sheet 6 of 6)
______________________________________________________________________________________
GND
VD1_5
GND
VD3_3
TCK
TMS
GND
GND
GND
C87
220µF
6.3V
C89
220µF
6.3V
D3
D2
D1
D0
D4/CF
VCCO
19
7
15
2
16
1
C119
0.1µF
VD3.3
E9
F9
F10
E8
F7
F8
H10
H9
H8
H7
G10
G9
G8
G7
C91
10µF
C93
1.0µF
C94
0.1µF
VD3.3
C118
0.1µF
C95
0.1µF
C96
0.1µF
C120
0.1µF
M8
L9
L10
M9
K11
J12
J11
G11
H11
VD3.3
TDI-FPGA
F11
17
CCLK D2
R96
330Ω
VD3.3
PROGRAM
H12
C92
1.0µF
TDO
8
13
10
3
12
9
R94
4.7kΩ
VD3.3
DIN
F6
C14
C3
B15
B2
A16
CEO
CE
CLK
D7
D6
OE/RESET
11
GND
A1
C90
10µF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VD3.3
U6
14
D5
XC18V01S020
20
GND
GND
C88
220µF
6.3V
VD1.5
6
5
TDI
VCC
U5-E
XC2V80-6FG256C
GND
C86
220µF
6.3V
VD3.3
J7
J8
J9
J10
K7
K8
K9
K10
L6
L11
P3
P14
R2
R15
T1
T16
TCK
TMS
TDI
4
18
VD3.3
C97
0.1µF
C121
0.1µF
VCC0_5
VCC0_4
VCC0_4
VCC0_4
VCC0_3
VCC0_3
VCC0_3
VCC0_2
VCC0_2
VCC0_2
VCC0_1
VCC0_1
VCC0_1
VCC0_0
VCC0_0
VCC0_0
C98
0.1µF
C110
0.1µF
VD1.5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
U5-F
XC2V80-6FG256C
DONE
R95
4.7kΩ
VD3.3
L8
L7
K6
J6
J5
H5
H6
G6
C111
0.1µF
C99
0.1µF
N13
N4
M12
M5
E12
E5
D13
D4
VD1.5
INIT
C100
0.1µF
C112
0.1µF
VD3.3
C101
0.1µF
C113
0.1µF
R81
SHORT
J14-9
J14-8
J14-7
J14-6
J14-5
J14-4
J14-3
J14-2
J14-1
J14
C102
0.1µF
C114
0.1µF
R80
SHORT
INIT
TDI-FPGA
TDO
TMS
CCLK
PROGRAM
DONE
TCK
DIN
TMS
TDI
TDO
TCK
C103
0.1µF
C115
0.1µF
R79
SHORT
VD3.3
P13
A4
C116
0.1µF
M2
M1
M0
RSVD
RSVD
C104
0.1µF
R3
P2
T2
A13
C105
0.1µF
E4
F3
F4
E16
B1
B16
R1
R16
C106
0.1µF
VBATT
HSWAP_EN
PWRDOWN
N.C.
N.C.
LO4P_7
D3
C108
0.1µF
2
SW1
R104
10kΩ
C109
0.1µF
C83
0.1µF
3
1
VD3.3
3
N1
R97
330Ω
VD3.3
C82
0.1µF
TP13
TP14
C107
0.1µF
C81
0.1µF
VD3.3
A14
B3
T15
M7
1
TP15
VD3.3
M10
E1
LO3P_7/ E3
VREF_7
E2
LO4N_7
LO3N_7
LO6P_7
LO6N_7
LO4P_2
VCCAUX
VCCAUX
VCCAUX
C117
0.1µF
LO1P_4/INIT
TDI
TDO
TMS
CCLK
PROG
DONE
TCK
LO2N_4/DO/DIN VCCAUX
T14 LO1N_4/BY/
DOUT
A3
RSVD
T13
C2
C15
B14
P15
A2
R14
A15
U5-G
XC2V80-6FG256C
C84
0.1µF
C85
0.1µF
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Figure 7. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Component Placement Guide—Component Side
______________________________________________________________________________________
15
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 8. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout—Component Side
16
______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Figure 9. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 2)—Ground Planes
______________________________________________________________________________________
17
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 10. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 3)—Power Planes
18
______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Figure 11. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 4)—Signal Layer
______________________________________________________________________________________
19
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 12. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 5)—Signal Layer
20
______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Figure 13. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout—Solder Side
______________________________________________________________________________________
21
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 14. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Component Placement Guide—Solder Side
22
______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
REVISION
NUMBER
REVISION
DATE
0
6/05
Initial release
1
8/10
Added lead-free parts to Part Selection Table and EV Kit Component List and
updated Component Suppliers
DESCRIPTION
PAGES
CHANGED
—
1, 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Revision History
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