MAX14690
Wearable Charge-Management Solution
General Description
The MAX14690 is a battery-charge-management solution
ideal for low-power wearable applications. The device
includes a linear battery charger with a smart power
selector and several power-optimized peripherals. The
MAX14690 features two ultra-low-power buck regulators
with a typical quiescent current of 900nA. In addition,
three ultra-low power low-dropout (LDO) linear regulators,
with a typical quiescent current of 600nA are included.
In total, the MAX14690 can provide up to five regulated
voltages, each with an ultra-low quiescent current,
critical to battery life for the unique power profile in 24/7
operation devices, such as those in the wearable market.
The battery charger features a smart power selector that
allows operation on a dead battery when connected to a
power source. To avoid overloading a power adapter, the
input current to the smart power selector is limited based
on an I2C register setting. If the charger power source
is unable to supply the entire system load, the smart
power control circuit supplements the system load with
current from the battery.
The two synchronous, high-efficiency step-down buck
regulators feature a fixed-frequency PWM mode for
tighter regulation and a burst mode for increased
efficiency during light-load operation. The output voltage
of these regulators can be programmed through I2C with
the default preconfigured.
The three configurable LDOs each have a dedicated
input pin. Each LDO regulator output voltage can be
programmed through I2C with the default preconfigured.
The linear regulators can also be configured to operate
as power switches that may be used to disconnect the
quiescent load of the system peripherals.
Benefits and Features
●● Extend System Use Time Between Battery Charging
• Dual Ultra-Low-IQ 200mA Buck Regulators
-- Output Programmable from 0.8V to 1.8V and
1.5V to 3.3V
-- 0.9μA (typ) Quiescent Current
-- Automatic Burst or Forced-PWM Modes
• Three Ultra-Low-IQ 100mA LDOs
-- Output Programmable from 0.8V to 3.6V
-- 0.6μA (typ) Quiescent Current
-- 2.7V to 5.5V Input with Dedicated Pin
●● Easy-to-Implement Li+ Battery Charging
• Smart Power Selector
• 28V/-5.5V Tolerant Input
• Thermistor Monitor
●● Minimize Solution Footprint Through High Integration
• Provides Five Regulated Voltage Rails
• Switch Mode Option on Each LDO
●● Optimize System Control
• Monitors Pushbutton for Ultra-Low Power Mode
• Power-On Reset Delay and Voltage Sequencing
• On-Chip Voltage Monitor Multiplexer
Applications
●● Wearable Electronics
●● Fitness Monitors
●● Portable Medical Devices
Block Diagram
MAX14690
POWER
The MAX14690 features a programmable power controller
that allows the device to be configured for applications
that require the device be in a true-off, or always-on,
state. The controller also provides a delayed reset signal
and voltage sequencing.
The MAX14690 is available in a 36-bump, 0.4mm pitch,
2.72mm x 2.47mm wafer-level package (WLP).
28V INPUT
PROTECTION
LINEAR
Li+ BATTERY CHARGER
WITH POWER SELECTOR
POWER
SEQUENCER
BUCK 1
MONITOR
BUCK 2
LDO/SWITCH 1
DATA
CONTROL
LDO/SWITCH 2
SYS
Ordering Information appears at end of data sheet.
19-7480; Rev 11; 5/16
LDO/SWITCH 3
MAX14690
Wearable Charge-Management Solution
Typical Application Circuit
MAX14690
SET
CHGIN
1µF
GND
CAP
Li+ BATTERY
CHARGER WITH
SMART POWER
SELECTOR
THM
BAT
1µF
1µF
EXT
VIO
SYS
VSYS 10µF
(*)
SCL
SCL
SDA
BUCK 1
INT
INT
MPC0
MPC0
MPC1
MPC1
PFN2
RST
CONTROL
BUCK 2
PFN2
RST
LDO/
SWITCH 1
PFN1
VSYS
B1LX
MON
MUX/
DIVIDER
LDO/
SWITCH 3
2.2µH
B2LX
L1IN
2.2µH
L3OUT
VL1
1µF
VL2
1µF
VL3
1µF
VSYS
L2OUT
L3IN
10µF
VSYS
L1OUT
L2IN
10µF
VB2
B2OUT
LED
LDO/
SWITCH 2
MON
VB1
B1OUT
SDA
VSYS
* OPTIONAL EXTERNAL FET
www.maximintegrated.com
Maxim Integrated │ 2
MAX14690
Wearable Charge-Management Solution
Absolute Maximum Ratings
(Voltages referenced to GND.)
SDA, SCL, THM, RST, SYS, PFN1, PFN2,
MPC0, MPC1, INT, MON, BAT LED,
L1IN, L2IN, L3IN............................................... -0.3V to +6.0V
B1LX, B2LX, B1OUT, B2OUT, EXT....... -0.3V to (VSYS + 0.3V)
L1OUT.................................................... -0.3V to (VL1IN + 0.3V)
L2OUT.................................................... -0.3V to (VL2IN + 0.3V)
L3OUT.................................................... -0.3V to (VL3IN + 0.3V)
CHGIN ..................................................................... -6V to +30V
CAP..................................... -0.3V to min (VCHGIN + 0.3V, +6V)
SET .......................................................... -0.3V to VBAT + 0.3V
Continuous Current into CHGIN, BAT, SYS .................±1000mA
Continuous Current into any other terminal ...................±100mA
Continuous Power Dissipation (multilayer board at +70°C):
6 x 6 Array 36-Bump 2.72mm x 2.47mm
0.4mm Pitch WLP (derate 21.70mW/°C)........................1.74W
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature Soldering (10s)...................................+300°C
Soldering Temperature (reflow)........................................+260°C
Package Thermal Characteristics (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (θJA)...........46°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL SUPPLY CURRENT (L_IN Connected to SYS)
All functions disabled
Charger Input Current
ICHG
Power off, VCHGIN = 0V,
SYS switch open
BAT Input Current
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IBAT
0.26
Power on, VCHGIN = 5V
SYS switch closed, buck regulators in
burst mode, LDO1 enabled, ISYS = 0A,
IB_OUT = 0A, IL_OUT = 0A
2
mA
0.95
Power on, VCHGIN = 0V
SYS switch closed, 2x buck regulators
in Burst mode, LDOs disabled.
ISYS = 0A, IB_OUT = 0A
3
Power on, VCHGIN = 0V
SYS switch closed, 2x buck regulators
in Burst mode, LDO1 enabled,
ISYS = 0A, IB_OUT = 0A, IL_OUT = 0A
3.5
Power on, VCHGIN = 0V
SYS switch closed, 2x buck regulators
in burst mode, 3x LDOs enabled,
ISYS = 0A, IB_OUT = 0A, IL_OUT =0A
4.6
µA
Maxim Integrated │ 3
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUCK REGULATOR 1
(VSYS = +3.7V, Burst mode operation, L = 2.2µH, C = 10µF, VB1OUT = 1.2V)
Input Voltage
Output Voltage
Quiescent Supply Current
VIN_BUCK1
VOUT_BUCK1
IQ_BUCK1
IPWM1_BUCK1
Output Accuracy
ACCBUCK1
Load Regulation
VERR_BUCK1
Peak-to-Peak Ripple in
Burst Mode
VPPRIPPLE1
Maximum Operative Output
Current
IOUT_BUCK1
B1OUT Pulldown Current
ILEAK_B1OUT
Input voltage = VSYS
2.7
5.5
V
25mV step resolution (Note 3)
0.8
1.8
V
0.915
2
µA
2.5
3.5
mA
+2.9
%
Burst mode, IOUT = 0mA (Note 4)
FPWM mode, L = 4.7µH (ESR = 0.6Ω,
2MHz RAC = 2.13Ω), IOUT = 0mA
IOUT = 1mA
(VOUT_BUCK1 > 1V, C > 50µF)
From IOUT = 0 to 200mA
(VB1OUT = 1.2V average voltage)
-2.6
-3
-1
IOUT = 10mA, C = 20µF
25
IOUT = 10mA, C = 10µF
43
%
mV
200
mA
VOUT = VSYS
200
350
µA
VREG < VOUT < VREG + 0.1V
10
100
nA
pMOS On-Resistance
RONP_BUCK1
0.22
0.4
nMOS On-Resistance
RONN_BUCK1
0.18
0.3
Oscillator Frequency
fBUCK1
2
2.24
MHz
Maximum Duty Cycle
DMAX_BUCK1
Short-Circuit Current Limit
ISHRT_BUCK1
BLX Leakage Current
Active Discharge Current
ID_BUCK1
TON_BUCK1
Thermal-Shutdown
Temperature
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1.78
100
VB1OUT = 1.2V
Time from enable to full current capability
%
1.1
1.3
1.62
1
µA
8
18
36
mA
IBLX_BUCK1
Full Turn-On Time
Thermal-Shutdown
Temperature Hysteresis
FPWM mode
A
58
ms
TSHDN_BUCK1
150
°C
TSHDN_HYST_BUCK1
20
°C
Maxim Integrated │ 4
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
BUCK REGULATOR 2
(VSYS = +3.7V, Burst mode operation, L = 2.2µH, C = 10µF, VB2OUT = 1.8V.)
Input Voltage
Output Voltage
Quiescent Supply Current
(Note 4)
VIN_BUCK2
Input voltage = VSYS
2.7
VOUT_BUCK2
50mV step resolution
1.5
IQ_BUCK2
IPWM1_BUCK2
Burst mode, IOUT = 0mA (Note 4)
FPWM mode, L = 4.7µH (ESR = 0.6W,
2MHz RAC = 2.13W) IOUT = 0mA
IOUT = 1mA, VOUT_BUCK2 > 1.5V,
C > 50µF, VSYS > VB2OUT + 150mV
3.3
V
1
2
µA
2.4
3.5
mA
+2.93
%
Output Accuracy
ACCBUCK2
Load Regulation
VERR_BUCK2
Peak-to-Peak Ripple In
Burst Mode
VPPRIPPLE2
Maximum Operative Output
Current
IOUT_BUCK2
B2OUT Pulldown Current
ILEAK_B2OUT
pMOS On-Resistance
RONP_BUCK2
0.22
0.4
Ω
nMOS On-Resistance
RONN_BUCK2
0.18
0.3
Ω
2.00
2.24
MHz
Oscillator Frequency
fBUCK2
Maximum Duty Cycle
DMAX_BUCK2
Short-Circuit Current Limit
ISHRT_BUCK2
BLX Leakage Current
Active Discharge Current
ID_BUCK2
tON_BUCK2
Thermal-Shutdown
Temperature
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-3.1
-1
IOUT = 10mA, C = 20µF
38
IOUT = 10mA, C = 10µF
54
%
mV
200
VOUT = VSYS
5
VREG < VOUT < VREG + 0.1V
FPWM mode
mA
10
10
1.78
1.4
1.8
VB2OUT = 1.8V
Time from enable to full current capability
8
18
µA
nA
100
IBLX_BUCK2
Full Turn-On Time
Thermal-Shutdown
Temperature Hysteresis
From IOUT = 0 to 200mA,
VB2OUT = 1.8V average voltage
-2
%
2.2
A
1
µA
36
mA
58
ms
TSHDN_BUCK2
150
°C
TSHDN_HYST_BUCK2
20
°C
Maxim Integrated │ 5
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDOs
(C = 1µF, unless otherwise noted. Typical values are at VL_IN = 3.7V, with IL_OUT = 10mA, VL_OUT = 3V.)
Input Voltage
Quiescent Supply Current
Maximum Output Current
VIN_LDO
IQ_LDO
IQ_LDO_AD
LDO_Mode = 0
2.7
5.5
V
LDO_Mode = 1
1.8
5.5
V
1.2
µA
IL_OUT = 0mA
0.56
IL_OUT = 0mA, VL_IN = 1.8V, LDO_
ActDSC = 1, LDO_En = 00
40
IL_OUT_MAX
100
Output Voltage
VL_OUT
0.8
Output Accuracy
ACCLDO
Dropout Voltage
VDROP_LDO
µA
mA
VL_IN = (VL_OUT + 0.5V) or higher,
IL_OUT = 100µA
VL_IN = 3.3V, IL_OUT_ = 100mA, VL_
OUT = 3.3V
3.6
V
3
%
100
mV
Line Regulation Error
VLINEREG_LDO
VL_IN = (VL_OUT + 0.5V) to 5.5V
-0.09
0.09
%/V
Load Regulation Error
VLOADREG_LDO
IL_OUT = 100µA to 100mA
0.003
0.008
%/mA
Line Transient
VLINETRAN_LDO
Load Transient
VLOADTRAN_LDO
Active Discharge Current
Turn-On Time
Short-Circuit Current Limit
Switch Mode Resistance
Thermal-Shutdown
Temperature
Thermal-Shutdown
Temperature Hysteresis
Output Noise
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IPDL
tON_LDO
ISHRT_LDO
RON_LDO
VL_IN = 4V to 5V, 200ns rise time
±36
mV
VL_IN = 4V to 5V, 1µs rise time
±28
mV
IL_OUT = 0mA to 10mA, 200ns rise time
145
mV
IL_OUT = 0mA to 100mA, 200ns rise time
VL_IN = 3.7V
290
9
21
mV
37
mA
IL_OUT = 0mA, time to 90% of final value
2.3
ms
VL_IN = 3V, switch mode,
IL_OUT = 0mA, time to 90% of final value
0.45
ms
VL_OUT = GND
385
mA
VL_OUT = GND, switch mode
375
VL_IN = 2.7V, switch mode
0.58
0.9
mA
Ω
VL_IN = 1.8V, switch mode
0.89
1.35
Ω
TSHDN_LDO
150
°C
TSHDN_HYST_LDO
16
°C
OUTNOISE
10Hz to 100kHz, VL_IN = 5V,
VL_OUT = 3.3V
110
10Hz to 100kHz, VL_IN = 5V,
VL_OUT = 2.5V
95
10Hz to 100kHz, VL_IN = 5V,
VL_OUT = 1.2V
60
10Hz to 100kHz, VL_IN = 5V,
VL_OUT = 0.8V
60
µVRMS
Maxim Integrated │ 6
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHGIN TO SYS PATH
(VCHGIN = 5.0V, VSYS = VSYS_REG.) (Note 2)
Allowed CHGIN Input
Voltage Range
Allowed BAT Voltage Range
VCHGIN_RNG
-5.5
28
V
VBAT_RNG
0
5.5
V
VCHGIN Detect Threshold
VCHGIN_DET
VCHGIN Overvoltage
Threshold
VCHGIN_OV
VCHGIN Overvoltage
Threshold Hysteresis
VCHGIN_OV_HYS
VCHGIN Valid Trip Point
VCHGIN-SYS_TP
VCHGIN Valid Trip-Point
Hysteresis
VCHGIN-SYS_TP_HYS
Input Limiter Current
ILIM
Internal CAP Regulator
VCAP
SYS Regulation Voltage
SYS Regulation Voltage
Dropout
CHGIN-to-SYS
On-Resistance
Thermal-Shutdown
Temperature
Rising
3.8
3.9
4.1
Falling
3.0
3.1
3.2
Rising
7.2
7.5
7.8
200
VCHGIN - VSYS, rising, VBAT = 4V
45
145
0
ILimCntl[1:0] = 01
90
ILimCntl[1:0] = 10
450
ILimCntl[1:0] = 11
1000
V
mV
280
200
ILimCntl[1:0] = 00
V
mV
mV
mA
VCHGIN = 5V
3.9
4.2
4.7
V
VSYS_REG
VCHGIN = 5V, ISYS = 1mA
4.55
4.65
4.75
V
VCHGIN-SYS
VCHGIN = 4V, ISYS = 1mA
RCHGIN-SYS
VCHGIN = 4.4V, ISYS = 400mA
0.370
(Note 5)
+150
°C
TCHGIN_SHDN
40
mV
0.66
Thermal-Shutdown
Temperature Hysteresis
TCHGIN_SHDN_HYS
20
°C
Input Current Soft-Start
Time
tSFST_LIM
1
ms
Internal Supply Switchover
Threshold
VCCINT_TH
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VCHGIN = VCAP rising, VBAT = 4.2V
2.5
2.8
3.0
V
Maxim Integrated │ 7
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.644
2.69
V
2.618
2.67
V
SYS, BATTERY, AND VCCINT UVLOs
SYS UVLO Threshold
VSYSUVLO_R
Rising
VSYSUVLO_F
Falling
2.57
SYS UVLO Threshold
Hysteresis
VSYSUVLO_HYS
Hysteresis
26
mV
SYS UVLO Falling
Debounce Time
tSYSUVLO_FDEB
SYS falling
20
µs
VCCINT UVLO Threshold
(POR)
VUVLO
VCCINT UVLO Threshold
Hysteresis
VUVLO_HYS
BAT UVLO Threshold
VBAT_UVLO
BAT UVLO Threshold
Hysteresis
VBAT_UVLO_HYS
VCCINT rising
0.8
1.82
2.6
140
Rising (valid only when CHGIN is
present, when VBAT < VBAT_UVLO,
the BAT-SYS switch opens and BAT is
connected to SYS through a diode.)
1.9
Hysteresis
2.05
V
mV
2.2
50
V
mV
BATTERY CHARGER
(VBAT = 4.2V. Typical values are at VCHRGIN = 5.0V, VSYS = VSYS_REG.)
BAT-to-SYS
On-Resistance
RBAT-SYS
VBAT = 4.2V, IBAT = 300mA
80
Current Reduce Thermal
Threshold Temperature
TCHG_LIM
(Note 6)
120
140
m
°C
BAT-to-SYS Switch On
Threshold
VBAT-SYS-ON
SYS falling
10
22
35
mV
BAT-to-SYS Switch Off
Threshold
VBAT-SYS-OFF
SYS rising
-3
-1.5
0
mV
SYS Threshold Voltage
Charger Limiting Current
VSYS_LIM
Threshold at which the charger starts to
limit the current due to SYS falling
4.36
V
FChg-MtChg Threshold
VFCHG-MTCHG
If VSYS drops below this value the
charger will not move to maintain charge
4.49
V
FChg-MtChg Threshold
Hysteresis
VFCHG-MTCHG_HYS
50
mV
tCHG_SOFT
1
ms
Charger Current Soft-Start
Time
PRECHARGE
IPChg = 00
Precharge Current
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IPCHG
IPChg = 01
5
9
10
IPChg = 10
20
IPChg = 11
30
11
%IFChg
Maxim Integrated │ 8
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
VPChg = 000, VBAT rising
VPChg = 001, VBAT rising
Prequalification Threshold
Prequalification
Threshold Hysteresis
VBAT_PChg
TYP
MAX
UNITS
2.1
2.15
2.25
VPChg = 010, VBAT rising
2.40
VPChg = 011, VBAT rising
2.55
VPChg = 100, VBAT rising
2.7
VPChg = 101, VBAT rising
2.85
VPChg = 110, VBAT rising
3.0
VPChg = 111, VBAT rising
3.15
2.35
V
VBAT_PChg_HYS
90
mV
SET Current Gain Factor
KSET
2000
A/A
SET Regulation Voltage
VSET
1
V
FAST CHARGE
RSET = 400kW
Fast-Charge Current
IFChg
5
RSET = 40kW
45
RSET = 4kW
50
55
mA
500
1/2 Fast-Charge Current
Comparator Threshold
IFC_HALF
50
%IFChg
1/5 Fast-Charge Current
Comparator Threshold
IFC_FIFTH
20
%IFChg
MAINTAIN CHARGE
ChgDone = 00
Charge Done
Qualification
IChg_DONE
5
ChgDone = 01
8.5
ChgDone = 10
20
ChgDone = 11
30
BatReg = 000
4.05
BatReg = 001
4.10
BatReg = 010
BAT Regulation Voltage
VBatReg
BatReg = 011
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VBatReChg
%IFChg
4.15
4.179
4.2
4.221
TA = -40°C to +85°C
4.158
4.2
4.242
V
4.25
BatReg = 101
BatReg = 110
11.5
TA = +25°C
BatReg = 100
BAT Recharge Threshold
10
TA = +25°C
4.32
4.3
4.35
4.38
TA = -40°C to +85°C
4.30
4.35
4.40
BatReChg = 00
70
BatReChg = 01
120
BatReChg = 10
170
BatReChg = 11
220
mV
Maxim Integrated │ 9
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHARGER TIMER
Maximum Prequalification
Time
Maximum Fast-Charge
Time
Maintain-Charge Time
tPChg
tFChg
tMTChg
PChgTmr = 00
30
PChgTmr = 01
60
PChgTmr = 10
120
PChgTmr = 11
240
FChgTmr = 00
75
FChgTmr = 01
150
FChgTmr = 10
300
FChgTmr = 11
600
TOChgTmr = 00
0
TOChgTmr = 01
15
TOChgTmr = 10
30
TOChgTmr = 11
Timer Accuracy
tCHG_ACC
min
min
min
60
-10
Timer Extend Threshold
TIMEXD_THRES
If charge current is reduced due to
ILIM or TDIE, this is the percentage of
charge current below which timer clock
operates at half speed
Timer Suspend Threshold
TIMSUS_THRES
If charge current is reduced due to ILIM
or TDIE, this is the percentage of charge
current below which timer clock pauses
+10
%
50
%
20
%
THERMISTOR MONITOR AND NTC DETECTION (RPU = 10k, RTHM = 10k, 3380ß)
THM Hot Threshold
T4
VTHM falling
21.3
23.3
25.3
THM Warm Threshold
T3
VTHM falling
30.9
32.9
34.9
THM Cool Threshold
T2
VTHM rising
62.5
64.5
66.5
THM Cold Threshold
T1
VTHM rising
71.9
73.9
75.9
THM Disable Threshold
THMDIS
VTHM rising
91
93
95
THM Threshold Hysteresis
THMHYS
THM Input Leakage
ILKG_THM
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60
-1
%CAP
mV
+1
µA
Maxim Integrated │ 10
MAX14690
Wearable Charge-Management Solution
Electrical Characteristics (continued)
(VCHGIN = 5.0V, VBAT = 3.7V, TA = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+10
%
DIGITAL SIGNALS
PFN1 PFN2 Button Timer
Accuracy
-10
Input Logic-High (SDA,
SCL, MPC0, MPC1, PFN1,
PFN2)
VIH
Input Logic-Low (SDA,
SCL, MPC0, MPC1, PFN1,
PFN2)
VIL
Output Logic-Low (SDA,
RST, INT, LED, PFN2)
VOL
High Level Leakage Current
(SDA, RST, INT, LED,
PFN2)
ILK
SCL Clock Frequency
fSCL
Bus Free Time Between
a STOP and START
Condition
tBUF
START Condition
(Repeated) Hold-Time
tHD:STA
1.4
V
IOL = 4mA
-1
(Note 7)
0.5
V
0.4
V
+1
µA
400
kHz
1.3
µs
0.6
µs
Low Period of SCL Clock
tLOW
1.3
µs
High Period of SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated
START Condition
tSU:STA
0.6
µs
Data Hold Time
tHD:DAT
(Notes 8)
0
Data Setup Time
tSU:DAT
(Note 8)
100
ns
Setup Time for STOP
Condition
tSU:STO
0.6
µs
Spike Pulse Widths
Suppressed by Input Filter
Note 2:
Note
Note
Note
Note
Note
Note
Note
3:
4:
5:
6:
7:
8:
9:
tSP
(Note 9)
0.9
50
µs
ns
All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design.
For input voltages larger than 4.4V, output regulated voltage below 1V are available ONLY in burst mode.
This value is included in the IBAT quiescent current values for the on states.
When the die temperature exceeds TCHGIN_SHDN, the CHGIN-to-SYS path, and the charger is turned off.
When the die temperature exceeds TCHG_LIM, the charger current starts to decrease.
fSCL must meet the minimum clock low time plus the rise/fall times.
The maximum tHD:DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
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Maxim Integrated │ 11
MAX14690
Wearable Charge-Management Solution
Typical Operating Characteristics
(VBAT = 3.7V, VCHGIN = 0V, registers in their default state, TA = +25°C, unless otherwise noted.)
VBAT = 3.7V
8
BUCKS ON, LDOS ON
BUCKS ON
4
2
-15
10
35
60
BUCKS ON, LDOS ON
4
2
0
2.7
3
3.3
3.6
3.9
4.2
IBAT/VBAT vs. TIME
600
toc05
250mAhr BATTERY
IChgDone[1:0] = 11
IPChg[1:0 = 01
VPChg[2:0] = 100
500
4.2
VBAT
300
IBAT
100
0
35
60
85
0
20
6.0
6.0
ICHGIN vs. TEMPERATURE
40
60
80
100
120
5.0
5.0
4.0
4.0
toc07
140
2.0
1.0
1.0
0.0
0.0
fBUCK (MHz)
ICHGIN (mA)
ILimCntl REGISTER = 0x02
ILimCntl REGISTER = 0x01
200
10
35
TEMPERATURE (°C)
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3
4
5
6
7
8
PWM MODE
IBOUT = 50mA
toc8
VBAT = 4.2V
2.1
400
-15
toc06
VBAT = 2.0V
BUCK FREQUENCY vs. TEMPERATURE
2.2
ISYS = 600mA
-40
85
3.0
2.0
VCHGIN = 5V
0
60
VCHGIN (V)
VBAT = 3.7V
600
35
VSYS vs. VCHGIN
TIME (minutes)
TEMPERATURE (°C)
800
10
TEMPERATURE (°C)
3.0
200
10
-15
RSYS = 50Ω
4.15
-15
-40
RSET = 20kΩ
IBAT (mA)
VBAT_REG (V)
toc04
VCHGIN = 5V
BatReg[2:0] = 011
RSET = 40kW
NO LOAD
-40
VBAT = 3.7V
VBAT = 2V
20
400
4.1
40
VBAT (V)
VBAT_REG vs. TEMPERATURE
4.25
60
BUCKS ON
POWER OFF
TEMPERATURE (°C)
4.3
RSET = 40kΩ
IPChg[1:0] = 01
80
6
85
toc03
VCHGIN = 5V
8
0
-40
IFCHG vs. TEMPERATURE
100
VSYS (V)
0
POWER OFF
toc02
VBAT (V)
6
IBAT vs. VBAT
10
IBAT (µA) BATTERY INPUT CURRENT
IBAT (µA) BATTERY INPUT CURRENT
toc01
IFCHG (mA)
IBAT vs. TEMPERATURE
10
60
2
VBAT = 3.3V
1.9
85
1.8
-40
-15
10
VBAT = 3.7V
35
60
85
TEMPERATURE (°C)
Maxim Integrated │ 12
MAX14690
Wearable Charge-Management Solution
Typical Operating Characteristics (continued)
(VBAT = 3.7V, VCHGIN = 0V, registers in their default state, TA = +25°C, unless otherwise noted.)
VB2OUT vs. LOAD
1.9
toc9
VBAT = 3.3V, 3.7V, 4.2V
1.65
VBAT = 3.7V
VBAT = 3.3V
50
40
100
200
300
1
0.01
0.1
1
10
100
1000
1
200
VBAT = 4.2V
10
100
V B1OUT
toc14
3.05
VBAT = 3.7V
VBAT = 3.3V
2.95
50mV/div
2.9
20∝s/div
0
20
40
toc15
LDO PSRR vs. FREQUENCY
(VBAT = 4.2V, VIN = 2.7V, VOUT = 1.8V
0
-10
-10
-30
-30
-40
-40
-50
-70
LOAD = 1mA
-80
-90
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100
0.01
0.10
1.00
10.00
LOAD = 10mA
100.00
FREQUENCY (kHz)
1000.00 10000.00
toc17
LOAD = 100mA
-20
-60
2ms/div
80
LDO PSRR vs. Frequency
(VBAT = 4.2V, VIN = 3.7V, VOUT = 3.0V
0
PSRR (dB)
PSRR (dB)
50mA/div
toc16
LOAD = 100mA
-20
200mV/div
60
IL1OUT (mA)
LDO TRANSIENT RESPONSE
VOUT
VBAT = 4.2V
3
IB1OUT (mA)
IOUT
400
3.1
50mA/div
1000
300
VL1OUT vs. LOAD
toc13
VL1OUT (V)
EFFICIENCY (%)
VBAT = 3.7V
20
0.1
100
BUCK1 TRANSIENT RESP ONSE
toc12
60
VBAT = 3.3V
0
IB1OUT (mA)
IB1OUT
0.01
SKIP MODE----PWM MODE .....
IB2OUT (mA)
80
0
0.001
VBAT = 3.3V, 3.7V, 4.2V
1.05
0
0.001
400
BUCK1 EFFICIENCY vs. LOAD
40
1.15
10
IB1OUT (mA)
100
VBAT = 3.3V, 3.7V, 4.2V
1.2
1.1
30
20
SKIP MODE----PWM MODE .....
0
VBAT = 4.2V
60
VB1OUT (V)
EFFICIENCY (%)
1.7
toc11
1.25
70
1.75
VB1OUT vs. LOAD
1.3
80
VBAT = 3.3V, 3.7V, 4.2V
1.8
VB2OUT (V)
toc10
90
1.85
1.6
BUCK2 EFFICIENCY vs. LOAD
100
-50
-60
-70
LOAD = 1mA
-80
-90
0.01
0.10
1.00
10.00
LOAD = 10mA
100.00
1000.00 10000.00
FREQUENCY (kHz)
Maxim Integrated │ 13
MAX14690
Wearable Charge-Management Solution
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX14690
1
2
3
4
5
6
A
L1OUT
L1IN
CAP
GND
B2OUT
B2LX
B
L2OUT
L2IN
INT
MON
BAT
BAT
C
L3OUT
L3IN
GND
GND
SET
SYS
D
LED
PFN2
GND
GND
EXT
SYS
E
RST
MPC0
MPC1
PFN1
CHGIIN
CHGIN
F
SDA
SCL
THM
GND
B1OUT
B1LX
+
WLP
(2.72mm x 2.47mm)
Bump Description
BUMP
NAME
A1
L1OUT
A2
L1IN
LDO1 Input
A3
CAP
Bypass for Internal LDO. Bypass with a 1µF capacitor to GND.
A4, C3, C4
D3, D4, F4
GND
Ground
A5
B2OUT
A6
B2LX
B1
L2OUT
B2
L2IN
LDO2 Input
B3
INT
Open-Drain, Active-Low Interrupt Output.
B4
MON
Voltage Monitor Pin
B5,B6
BAT
Battery Connection. Connect BAT to a positive battery terminal, bypass BAT with a minimum 1µF
capacitor to GND.
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FUNCTION
LDO1 Output. Bypass with a minimum 1µF capacitor to GND.
1.5V – 3.3V Buck Regulator Output Feedback. Bypass with a minimum 10µF capacitor to GND.
1.5V – 3.3V Buck Regulator Switch. Connect 2.2µH inductor to B2OUT.
LDO2 Output. Bypass with a minimum 1µF capacitor to GND.
Maxim Integrated │ 14
MAX14690
Wearable Charge-Management Solution
Pin Description (continued)
PIN
NAME
FUNCTION
C1
L3OUT
C2
L3IN
LDO3 Input
C5
SET
External Resistor For Battery Charge Current Level Setting. Do not connect any external capacitance
on this pin; maximum allowed capacitance (CSET < 5µs/RSET) pF.
C6, D6
SYS
System Load Connection. Connect SYS to the system load. Bypass SYS with a minimum 10µF lowESR ceramic capacitor to GND.
D1
LED
LED Open-Drain Pulldown Current. Add an external current limiting pullup resistor.
D2
PFN2
D5
EXT
Push-Pull Gate Drive for Optional External pFET from BAT-to-SYS. Output is pulled to GND when
charger is disconnected and internal BAT-SYS FET is switched on. Otherwise, this output is pulled
high to the SYS voltage.
E1
RST
Power-On Reset Output. Active-low, open-drain.
E2
MPC0
Multipurpose Configuration Input 0
E3
MPC1
Multipurpose Configuration Input 1
E4
PFN1
Power Function Control Input. Programmable functionality via PwrFnMode. See Table 1.
E5, E6
CHGIN
F1
SDA
Open-Drain, I2C Serial Data Input/Output.
F2
SCL
I2C Serial Clock Input
F3
THM
Battery Temperature Thermistor Measurement Connection. Connect a 10kΩ resistor from THM to
CAP and a 10kΩ, 3380A NTC thermistor from THM to GND.
F5
B1OUT
0.8V – 1.8V Buck Regulator Output Feedback. Bypass B1OUT with a minimum 10µF capacitor to
GND.
F6
B1LX
LDO3 Output. Bypass with a minimum 1µF capacitor to GND.
Power Function Control Input/Output. Programmable functionality via PwrFnMode. See Table 1.
+28V Protected Charger Input. Bypass CHGIN with 1µF capacitor to GND.
0.8V – 1.8V Buck Regulator Switch Terminal. Connect B1LX to B1OUT with a 2.2µH inductor.
Note: All capacitance values listed in this document refer to effective capacitance. Be sure to specify capacitors that will meet these
requirements under typical system operating conditions taking into consideration the effects of voltage and temperature.
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Maxim Integrated │ 15
MAX14690
Wearable Charge-Management Solution
Block Diagram
MAX14690
POWER
28V INPUT
PROTECTION
LINEAR
Li+ BATTERY CHARGER
WITH POWER SELECTOR
POWER
SEQUENCER
BUCK 1
MONITOR
BUCK 2
LDO/SWITCH 1
DATA
CONTROL
LDO/SWITCH 2
SYS
Detailed Description
Power Regulation
The MAX14690 family includes two high-efficiency, low
quiescent current buck regulators, and three low quiescent current linear regulators that are also configurable
as power switches. Excellent light-load efficiency allows
the switching regulators to run continuously without
significant energy cost. The standard operating mode for
the buck regulators is burst mode, but they can be forced
to operate in PWM mode through an I2C register.
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LDO/SWITCH 3
Power On/Off and Reset Control
The behavior of power function control pins (PFN1 and
PFN2) is preconfigured to support one of the multiple
types of wearable application cases. Table 1 describes
the behavior of the PFN1 and PFN2 pins based on
the PwrRstCfg[3:0] bits and Figure 1 shows basic flow
diagrams associated with each mode.
A soft reset will reset all register values and pulls the RST
line low. Hard reset initiates a complete Power-On Reset
sequence.
Maxim Integrated │ 16
MAX14690
Wearable Charge-Management Solution
Table 1. Power Function Input Control Modes
PwrRstCfg
[3:0]
0000
PFN1
Enable
0001
Disable
0010
Hard-Reset
on Rising
Edge
0011
Hard-Reset
on Falling
Edge
0100
Hard-Reset
After CHGIN
Attach When
High
PFN1 PU/PD
PFNxResEna = 1
(0x1D[7])
Pulldown
PFN2
Active-Low
Manual Reset
Pullup*
Active-Low
Manual Reset
Pulldown
Soft-Reset on
Rising-Edge
PFN2 PU/PD
PFNxResEna =
1 (0x1D[7])
NOTES
Pullup*
On/off Mode with 10ms debounce. Active-high
on/off control on PFN1. Logic-low on PFN2
generates 10ms pulse on RST.
Note that, in this mode, the PWR_OFF_CMD in
I2C has no effect.
Pullup*
On/off Mode with 10ms debounce. Active-low
on/off control on PFN1. Logic-low on PFN2
generates 10ms pulse on RST. Note that, in
this mode, the PWR_OFF_CMD in I2C has no
effect.
Pulldown
Always-On Mode (i.e., device can only be put
in off state through PWR_OFF_CMD). 50ms
hard-reset off time. 10ms soft-reset pulse time.
200ms delay prior to both reset behaviors.
Always-On Mode (i.e., device can only
be put in off state via PWR_OFF_CMD).
50ms hard-reset off time. 10ms soft-reset
pulse time. 200ms delay prior to both reset
behaviors.
Charger Reset High Mode (i.e., device can only
be put in off state through PWR_OFF_CMD).
50ms hard-reset off time. 10ms soft-reset
pulse time. 200ms delay prior to both reset
behaviors.
Pullup*
Soft-Reset
Falling-Edge
Pullup*
Pulldown
Soft-Reset
After CHGIN
Attach When
High
Pulldown
0101
Hard-Reset
After CHGIN
Attach When
Low
Pullup*
Soft-Reset
After CHGIN
Attach When
Low
Pullup*
Charger Reset Low Mode (i.e., device can only
be put in off state through PWR_OFF_CMD).
50ms hard-reset off time. 10ms soft-reset
pulse time. 200ms delay prior to both reset
behaviors.
0110
KIN
Pullup*
KOUT
None
On/Off mode through specific long-press button
timing or PWR_OFF_CMD.
Custom Soft-Reset. Off mode through
PWR_OFF_CMD (30ms delay). On mode
through specific long-press (3s) or CHGIN
insertion. Soft-reset through specific long press
(12s).
0111
KIN
Pullup*
KOUT
None
1000-1111
—
—
—
—
Reserved
* Pullup is connected to VCCINT.
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Maxim Integrated │ 17
MAX14690
Wearable Charge-Management Solution
ALWAYS-ON MODE, HARD-RESET
(PwrRstCfg[3:0] = 0010, 0011 or 0100, 0101)
ALWAYS-ON MODE, SOFT-RESET
(PwrRstCfg[3:0] = 0010, 0011 or 0100, 0101)
POWER-ON
RESET
POWER-ON
RESET
POWER
SEQUENCING
POWER
SEQUENCING
30ms + tRST DELAY
VIA PWR _OFF_CMD
ON
VIA PFN 2
(GATED BY CHGIN INSERTION
FOR PwrRstCfg [3:0] = 010x)
SHUTDOWN
RST = LOW
PASSIVELY DISCHARGE
OUTPUTS
10ms DELAY
SOFT RESET
RST = LOW
OFF
PASSIVELY
DISCHARGE
OUTPUTS
VIA PFN 1
(GATED BY CHGIN INSERTION
FOR PwrRstCfg = 010x)
SHUTDOWN
RST = LOW
PASSIVELY DISCHARGE
OUTPUTS
200ms DELAY
50ms DELAY
30ms + tRST DELAY
VIA PWR _OFF_CMD
ON
OFF
PASSIVELY
DISCHARGE
OUTPUTS
10ms DELAY
200ms DELAY
HARD RESET
RST = LOW
ACTIVELY DISCHARGE
OUTPUTS
50ms DELAY
VIA CHGIN
INSERTION
VIA CHGIN
INSERTION
ON/OFF MODE SOFT-RESET
(PwrRstCfg[3:0] = 0000, 0001)
CUSTOM BUTTON MODE
(PwrRstCfg= 0110)
POWER
SEQUENCING
POWER
SEQUENCING
30ms + tRST DELAY
34ms + tRST DELAY
ON
ON
VIA PFN 2
(10ms DEB)
SOFT-RESET
RST = LOW
KIN > 12s, OR I2C CMD
VIA PFN 1
(10ms DEB)
SHUTDOWN
RST = LOW
PASSIVELY DISCHARGE
OUTPUTS
SHUTDOWN -SYS
FLOATING RST = LOW
PASSIVELY DISCHARGE
OUTPUTS
10ms DELAY + PFN2
(10ms deb ) RELEASED
10ms DELAY
10ms DELAY
OFF
PASSIVELY DISCHARGE
OUTPUTS
POWER-ON
RESET
POWER-ON
RESET
OFF
PASSIVELY DISCHARGE
OUTPUTS
CHGIN > 30ms
OR KIN > 400ms
VIA PFN1
OR CHGIN
CUSTOM SOFT RESET
(PwrRstCfg [3:0] = 0111 )
POWER
SEQUENCING
30ms + tRST DELAY
VIA PWR _OFF_CMD
(30ms DELAY )
SHUTDOWN
RST = LOW
PASSIVELY DISCHARGE
OUTPUTS
10ms DELAY
POWER-ON
RESET
ON
KIN > 12s
SOFT-RESET
(LDOS , BUCKS ,
POWERPATH ILIM STAY
ACTIVE )
OFF
VIA CHGIN INSERTION >30ms
OR KIN >3s
10ms DELAY
Figure 1. Power Function Input Control Modes Flow Diagrams
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Maxim Integrated │ 18
MAX14690
Wearable Charge-Management Solution
Power Sequencing
Additionally, the regulators can be selected to default off
and can be turned on with an I2C command after RST is
released. Each LDO regulator can be configured to be
always-on as long as SYS or BAT is present.
The sequencing of the buck regulators and LDOs during power-on is configurable. See Table 1 for details.
Regulators can be configured to turn on at one of three
points during the power-on process: 34ms after the
power-on event, after the RST signal is released, or at
two points in between. The two points between SYS and
RST are fixed proportionally to the duration of the PowerOn Reset (POR) process, but the overall time of the reset
delay is configurable (80ms, 120ms, 220ms, 420ms). The
timing relationship is presented graphically in Figure 2.
The SYS voltage is monitored during the power-on
sequence. If an undervoltage condition is detected on
SYS during the sequencing process with a valid voltage
at CHGIN, the process repeats from the point where
SYS was enabled to allow more time for the voltage to
stabilize. If there is not a valid voltage at CHGIN, the
device returns to the off state to avoid draining the
battery. Power is also turned off if an undervoltage condition
is detected on SYS.
POWER-ON
EVENT
34ms
Smart Power Selector
tRST
The smart power selector seamlessly distributes power
from the external CHGIN input to the battery (BAT) and
the system (SYS). With both an external adapter and
battery connected, the smart power selector basic
functions are:
RST
SYS
BUCK_
LDO_
_En
% of t RST
001
100
0%
101
25%
●●
When the system load requirements are less than the
input current limit, the battery is charged with residual
power from the input.
●●
When the system load requirements exceed the
input current limit, the battery supplies supplemental
current to the load.
●●
When the battery is connected and there is no
external power input, the system is powered from the
battery.
111
100%
110
50%
Figure 2. Reset Sequence Programming
VCHG
VSYS
VBAT
CLOSED
OPEN
OPEN
`
SYS SWITCH
CLOSE
ILIM
ICHG
IBAT
ISYS
0mA
SMART POWER SELECTOR
OPERATION WITH LIMITED VB
CURRENT
CONSTANT BAT
VOLTAGE
CHARGE
DONE
Figure 3. Smart Power Selector Current/Voltage Behavior
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Maxim Integrated │ 19
MAX14690
Thermal Current Regulation
In case the die temperature exceeds the normal limit, the
MAX14690 will attempt to limit the temperature increase
by reducing the input current from CHGIN. In this condition, the system load has priority over charger current, so
the input current is first reduced by lowering the charge
current. If the junction temperature continues to rise and
reaches the maximum operating limit, no input current
is drawn from CHGIN and the battery powers the entire
system load.
System Load Switch
An internal 80mW (typ) MOSFET connects SYS to BAT
when no voltage source is available on CHGIN. When an
external source is detected at CHGIN, this switch opens
and SYS is powered from the input source through the
input current limiter. The SYS-to-BAT switch also prevents VSYS from falling below VBAT when the system load
exceeds the input current limit. If VSYS drops to VBAT due
to the current limit, the load switch turns on so the load is
supported by the battery. If the system load continuously
exceeds the input current limit the battery is not charged.
This is useful for handling loads that are nominally below
the input current limit but have high current peaks exceeding the input current limit. During these peaks, battery
energy is used, but at all other times the battery charges.
See Figure 3.
The pin EXT can drive the gate of an external pMOS connected between SYS (source, bulk) and BAT (drain) in
parallel to the internal one.
EXT voltage is the buffered version of the internal gate
command that controls the internal 80mW (typ) MOSFET.
Note: The body diode of an external pMOS connected
between BAT and SYS remains present when the device
is in off mode.
Wearable Charge-Management Solution
and downstream circuitry from high-voltage stress up to
28V and down to -5.5V. During OVL, the internal circuit
remains powered and an interrupt is sent to the host.
During OVL, the charger turns off and the system load
switch closes, allowing the battery to power SYS. CHGIN
is also invalid if it is less than VBAT, or less than the USB
undervoltage threshold. With an invalid input voltage, the
SYS-to-BAT load switch closes and allows the battery to
power SYS.
CHGIN Input Current Limit: The CHGIN input current is
limited to prevent input overload. The input current limit is
controlled by I2C.
Thermal Limiting: In case the die temperature
exceeds the normal limit (TCHG_LIM), the MAX14690
attempts to limit temperature increase by reducing
the input current from CHGIN. In this condition, the
system load has priority over the charger current, so the
input current is first reduced by lowering the charge current. If the junction temperature continues to rise and
reaches the maximum operating limit (TCHGIN_SHDN), no
input current is drawn from CHGIN and the battery powers the entire system load.
Adaptive Battery Charging: While the system is
powered from CHGIN, the charger draws power from
SYS to charge the battery. If the total load exceeds
the input current limit, an adaptive charger control loop
reduces charge current to prevent VSYS from
collapsing.
When the charge current is reduced below 50% due to
ILIM or TDIE, the timer clock operates at half speed. When
the charge current is reduced below 20% due to ILIM or
TDIE, the timer clock is paused.
Fast-Charge Current Setting
The input limiter distributes power from the external
adapter to the system load and battery charger. In addition to the input limiter’s primary function of passing power
to the system load and charger, it performs several additional functions to optimize use of available power:
The MAX14690 uses an external resistor connected
from SET to GND to set the fast-charge current. The
pre-charge and charge-termination currents are
programmed as a percentage of this value via I2C
registers. The fast-charge current resistor can be
calculated as:
RSET = KSET x VSET/IFChg
Invalid CHGIN Voltage Protection: If CHGIN is above
the overvoltage threshold, the MAX14690 enters overvoltage lockout (OVL). OVL protects the MAX14690
where KSET has a typical value of 2000A/A and VSET has
a typical value of 1V. The range of acceptable resistors for
RSET is 4kW to 400kW.
Input Limiter
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Maxim Integrated │ 20
MAX14690
Wearable Charge-Management Solution
ICHG
NO
CHARGING
VBATREG
CHARGING
T1
NO
CHARGING
T3
T2
TEMPERATURE (°C)
NO
CHARGING
T1
T4
NO
CHARGING
CHARGING
T2
T3
T4
TEMPERATURE (°C)
Figure 4a. Charging Behavior Using Thermistor Monitor
VBATREG
ICHG
NO
CHARGING
NO
CHARGING
CHARGING
T1
T3
T2
TEMPERATURE (°C)
NO
CHARGING
CHARGING
T1
T4
-150mv
-150mv
T3
T2
NO
CHARGING
T4
TEMPERATURE (°C)
Figure 4b. Charging Behavior Using JEITA Monitor
Table 2. Thermistor Monitoring/JEITA
Monitoring Enable Control
ThermEn
JEITAEn
0
—
Thermistor/JEITA Monitoring Off
1
0
Thermistor Monitoring On
1
1
JEITA Monitoring On
FUNCTION
Thermistor/JEITA Monitoring
with Charger Shutdown
The MAX14690 includes thermistor and JEITA monitoring to enhance safety when charging Li+ batteries. The
battery pack temperature is measured from a divider
formed by a pullup resistor connected to CAP and the
battery-pack thermistor. The THM pin measures the
voltage across the resistor divider and converts it to
temperature. There are five temperature zones that can
be read from the ThermStat bits in I2C. When thermistor monitoring is enabled, the charger is disabled
for temperatures below T1 or above T3, as shown
in Figure 4a. When JEITA monitoring is enabled, the
charger will be disabled for temperatures below T1
or above T4, as shown in Figure 4b. See Table 2 and
Table 3 on configuring the thermistor/JEITA monitoring.
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Table 3. Voltage and Example
Temperature Thresholds
%CAP Thresholds
on THM
Temperature Thresholds
RPU = 10k, RTHM = 10k
(β = 3380)
T1
73.9
0°C
T2
64.5
10°C
T3
32.9
45°C
T4
23.3
60°C
I2C Interface
The MAX14690 uses the two-wire I2C interface to communicate with the host microcontroller. The configuration
settings and status information provided through this
interface are detailed in the register descriptions.
I2C Addresses
The registers of the MAX14690 are accessed through
the slave address of 0101000 (0x50 for writes/0x51 for
reads).
Maxim Integrated │ 21
MAX14690
Wearable Charge-Management Solution
Thermistor Monitoring with Charger Shutdown
FROM ANY STATE
RESET CHARGE TIMER
T1 < T < T4
TDIE < TBUS_LIM
OR VBAT > VSYS
OR ChgEn = 0
CHARGE SUSPEND
CHARGER OFF
FAULT
ChgStat = 001
ChgStat = 000
ChgStat = 111
LED = 1.5s PERIOD
LED = OFF
ICHG = 0
ICHG = 0
RECOVER FROM FAULT
RESET CHARGE TIMER
LED = 0.15s PERIOD
ICHG = 0
ChgEn = 1,
AND VSYS > 4.3V
MAINTAIN
CHARGE DONE
T < T1 OR T > T4
VBAT < VBATREG - VBATRECHG
AND ChgAutoReSta = 1
PREQUAL
ChgStat = 110
ChgStat = 010
LED = OFF
LED = ON
ICHG = 0
ICHG = IPCHG
VBAT < VPCHG_R
RESET CHARGE TIMER
T < T2 OR T > T3
ICHG > ICHG_DONE and
VOLTAGE MODE = 0*
RESET CHARGE TIMER
tCHG_TIMER > tMTCHG
AND
ChgAutoStp = 1
MAINTAIN
CHARGE
FAST
CHARGE
(CONSTANT CURRENT)
ICHG = 0
tCHG_TIMER > tPCHG
PAUSE
CHARGE
TIMER
T < T1 OR T > T4
ChgStat = 011
LED = ON
ICHG = IFCHG**
ICHG > ICHG_DONE and
VOLTAGE MODE = 1*
RESET CHARGE TIMER
ChgStat = 001
LED = 1.5s PERIOD
T1 < T < T4
VBAT > VPCHG_R
RESET CHARGE TIMER
VOLTAGE MODE= 0*
T < T1 OR T > T4
PAUSE
CHARGE
T < T1 OR T > T4 TIMER PREQUAL SUSPEND
ChgStat = 001
T1 < T < T4
VOLTAGE MODE = 1*
FAST
CHARGE
(CONSTANT VOLTAGE)
FAST
CHARGE
CC SUSPEND
PAUSE
CHARGE
TIMER
T < T1 OR T > T4
LED = 1.5s PERIOD
ICHG = 0
tCHG_TIMER > tFCHG
FAST
CHARGE
CV SUSPEND
ChgStat = 101
ChgStat = 100
ChgStat = 001
LED = ON
LED = ON
LED = 1.5s PERIOD
ICHG < ICHG_DONE
ICHG < ICHG_DONE
AND VSYS > 4.55V
AND TDIE < TCHG_LIM
RESET CHARGE TIMER
T1 < T < T4
ICHG = IFCHG
ICHG = 0
NOTES:
* VOLTAGE MODE IS AN INTERNAL SIGNAL.
** CHARGE TIMER IS SLOWED BY 50% IF ICHG < IFCHG/2 AND PAUSED IF ICHG < IFCHG/5 ONLY IN FAST-CHARGE CONSTANT-CURRENT STATE.
Figure 5. Battery Charger State Diagram
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Maxim Integrated │ 22
MAX14690
Wearable Charge-Management Solution
Applications Information
Slave Address
Set the Read/Write bit high to configure the MAX14690_
to read mode (Table 4). Set the Read/Write bit low to configure the MAX14690_ to write mode. The address is the
first byte of information sent to the MAX14690_ after the
START condition.
I2C Interface
The MAX14690_ contain an I2C-compatible interface
for data communication with a host controller (SCL and
SDA). The interface supports a clock frequency of up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
Bit Transfer
One data bit is transferred on the rising edge of each SCL
clock cycle. The data on SDA must remain stable during
the high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control signals (see the Start, Stop, And Repeated Start Conditions
section). Both SDA and SCL remain high when the bus
is not active.
Start, Stop, And Repeated Start Conditions
When writing to the MAX14690_ using I2C, the master
sends a START condition (S) followed by the MAX14690_
I2C address. After the address, the master sends the register address of the register that is to be programmed. The
master then ends communication by issuing a STOP condition (P) to relinquish control of the bus, or a REPEATED
START condition (Sr) to communicate to another I2C
slave. See Figure 6.
Single-Byte Write
In this operation, the master sends an address and two
data bytes to the slave device (Figure 7). The following
procedure describes the single byte write operation:
Table 4. I2C Slave Addresses
HEX
BINARY
●● 1) The master sends a START condition
7-Bit Slave ID
0x28
0101000
Write Address
0x50
01010000
●● 2) The master sends the 7-bit slave address plus a
write bit (low)
Read Address
0x51
01010001
ADDRESS FORMAT
S
●● 3) The addressed slave asserts an ACK on the data line
●● 4) The master sends the 8-bit register address
●● 5) The slave asserts an ACK on the data line only if
the address is valid (NAK if not)
P
Sr
●● 6) The master sends 8 data bits
●● 7) The slave asserts an ACK on the data line
SCL
●● 8) The master generates a STOP condition
SDA
Figure 6. I2C START, STOP and REPEATED START Conditions
Fig
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
8 DATA BITS
A
FROM MASTER TO SLAVE
REGISTER ADDRESS
A
P
FROM SLAVE TO MASTER
Figure 7. Write Byte Sequence
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Maxim Integrated │ 23
MAX14690
Wearable Charge-Management Solution
Burst Write
Single Byte Read
In this operation, the master sends an address and multiple data bytes to the slave device (Figure 8). The slave
device automatically increments the register address after
each data byte is sent, unless the register being accessed
is 0x00, in which case the register address remains the
same. The following procedure describes the burst write
operation:
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 9). The following procedure describes the
single byte read operation:
●● 1) The master sends a START condition
●● 2) The master sends the 7-bit slave address plus a
write bit (low)
●● 1) The master sends a START condition
●● 3) The addressed slave asserts an ACK on the data
line
●● 2) The master sends the 7-bit slave address plus a
write bit (low)
●● 4) The master sends the 8-bit register address
●● 3) The addressed slave asserts an ACK on the data
line
●● 5) The slave asserts an ACK on the data line only if
the address is valid (NAK if not)
●● 4) The master sends the 8-bit register address
●● 6) The master sends a REPEATED START condition
●● 5) The slave asserts an ACK on the data line only if
the address is valid (NAK if not)
●● 7) The master sends the 7-bit slave address plus a
read bit (high)
●● 6) The master sends eight data bits
●● 8) The addressed slave asserts an ACK on the data
line
●● 7) The slave asserts an ACK on the data line
●● 8) Repeat 6 and 7 N-1 times
●● 9) The slave sends eight data bits
●● 9) The master generates a STOP condition
●● 10) The master asserts a NACK on the data line
●● 11) The master generates a STOP condition
BURST WRITE
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - N
A
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 8. Burst Write Sequence
READ SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
Sr
DEVICE SLAVE ADDRESS - R
A
8 DATA BITS
NA
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 9. Read Byte Sequence
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Maxim Integrated │ 24
MAX14690
Wearable Charge-Management Solution
Burst Read
●● 9) The slave sends eight data bits
In this operation, the master sends an address plus two
data bytes and receives multiple data bytes from the slave
device (Figure 210). The following procedure describes
the burst byte read operation:
●● 10) The master asserts an ACK on the data line
●● 11) Repeat 9 and 10 N-2 times
●● 12) The slave sends the last eight data bits
●● 1) The master sends a START condition
●● 13) The master asserts a NACK on the data line
●● 2) The master sends the 7-bit slave address plus a
write bit (low)
●● 14) The master generates a STOP condition
●● 3) The addressed slave asserts an ACK on the data
line
Acknowledge Bits
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX14690_ generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (see Figure 3a11). To generate a NACK,
leave SDA high before the rising edge of the ninth clock
pulse and leave it high for the duration of the ninth clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
●● 4) The master sends the 8-bit register address
●● 5) The slave asserts an ACK on the data line only if
the address is valid (NAK if not)
●● 6) The master sends a REPEATED START condition
●● 7) The master sends the 7-bit slave address plus a
read bit (high)
●● 8) The slave asserts an ACK on the data line
BURST READ
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
Sr
DEVICE SLAVE ADDRESS - R
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - 3
A
8 DATA BITS - N
NA
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 10. Burst Read Sequence
S
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 11. Acknowledge
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Maxim Integrated │ 25
StatusA
StatusB
StatusC
IntA
IntB
IntMaskA
IntMaskB
ILimCntl
ChgCntlA
ChgCntlB
ChTmr
Buck1Cfg
Buck1VSet
Buck2Cfg
Buck2VSet
Reserved
LDO1Cfg
0x04
0x05
0x06
0x07
0x08
0x09*
0x0A*
0x0B*
0x0C*
0x0D
0x0E
0x0F
0x10
0x11
0x12
ChipRev
0x01
0x03
ChipId
0x00
0x02
REGISTER
NAME
REGISTER
ADDRESS
I2C Register Map
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R/W
—
R/W**
R/W
R/W**
R/W
R/W**
R/W**
R/W**
R/W**
R/W
R/W
COR
COR
R
R
R
R
R
R/W
—
—
—
—
-
ChgAutoStp
—
LDO1Seq[2:0]
—
—
Buck2Seq[2:0]
—
Buck1Seq[2:0]
—
ChgAuto
ReSta
—
—
ChgStatIntM
—
—
—
ChgStatInt
—
—
—
B6
Therm
StatIntM
ThermStatInt
—
—
—
B7
B3
—
—
Buck2VSet[5:0]
LDO1En[1:0]
Buck2Md[1:0
—
B0
Thrm
LDO3IntM
ChgTmoIntM
ThrmLDO3Int
ChgTmoInt
ThrmLDO3
ChgTmo
LDO1Mode
Buck2Ind
Buck1Ind
PChgTmr[1:0]
ChgDone[1:0]
ChgEn
ILimCntl[1:0]
Thrm
LDO2IntM
Buck1Md[1:0]
Buck1VSet[5:0]
FChgTmr[1:0]
LDO1
ActDSC
Buck2En[1:0]
—
MtChgTmr[1:0]
IPChg[1:0]
BatReg[2:0]
—
Thrm
Bk0IntM
—
Thrm
LDO1IntM
UsbOkIntM
ChgThrm
RegIntM
ThrmLDO2Int
ChgThrm
RegInt
ChgThrm
SdInt
ThrmLDO1Int
ThrmLDO2
ChgThrmReg
ChgStat[2:0]
B1
ThrmLDO1
ChgThrmSd
B2
ChgThrm
SdIntM
ThrmBk0Int
UsbOkInt
ThrmBk2
UsbOk
Buck1En[1:0]
ThrmBk1IntM
UsbOVPIntM
ThrmBk1Int
UsbOVPInt
ThrmBk1
UsbOVP
ThermStat[2:0]
Chip_Rev[7:0] (Read-Only)
Chip_Id[7:1,0] (Read-Only)
B4
BatReChg[1:0]
VPChg[2:0]
—
—
ILimIntM
—
ILimInt
—
ILim
B5
MAX14690
Wearable Charge-Management Solution
Maxim Integrated │ 26
R/W
R/W**
LDO2Cfg
LDO2VSet
LDO3Cfg
LDO3VSet
ThrmCfg
MONCfg
BootCfg
0x14
0x15
0x16
0x17
0x18*
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0x19
0x1A
PwrCfg
NULL
PwrOff
0x1D
0x1E
0x1F
R
R/W
—
PFNxResEnaa
Reserved
—
—
—
—
B7
—
—
Reserved
ILim___T[2:0]
—
—
Buck2
ActDSC
—
—
—
—
Reserved
PFN1
SftRstCfg
MONHiZ
—
LDO3
ActDSC
LDO2
ActDSC
B3
PWR_OFF_CMD
Buck2FFET
—
Reserved bits must not be modified from their default states to ensure proper operation.
All R/W registers are reset to default value when entering the off state.
** R if WriteProtect enabled (Table 35).
—
—
—
B4
MONRatioCfg[1:0]
—
—
—
—
B5
PwrRstCfg[3:0]
—
—
LDO3Seq[2:0]
—
LDO2Seq[2:0]
—
B6
*Register is reset to default value upon CHGIN rising edge.
Note: COR = Clear-on-read
R/W
0x1C
R/W
R/W
PinStat
Buck1/2
Extra
0x1B
R/W
R/W
R/W**
R/W**
R/W
R/W**
LDO1VSet
0x13
R/W
REGISTER
NAME
REGISTER
ADDRESS
I2C Register Map (continued)
—
—
B1
—
—
Buck1ActDSC
MPC1
MONCtr[2:0]
JEITAEn
BootDly[1:0]
Reserved
PFN2
—
LDO3VSet[4:0]
LDO3En[1:0]
LDO2VSet[4:0]
LDO2En[1:0]
LDO1VSet[4:0]
B2
—
StayOn
Buck1FFET
MPC0
—
ThermEn
LDO3Mode
LDO2Mode
B0
MAX14690
Wearable Charge-Management Solution
Maxim Integrated │ 27
MAX14690
Wearable Charge-Management Solution
I2C Register Descriptions
Table 5. ChipId Register (0x00)
ADDRESS:
0x00
MODE:
Read-Only
BIT
7
6
5
4
NAME
Chip_Id[7:0]
3
2
1
0
2
1
0
1
0
Chip_Id[7:0]
Chip_Id[7:0] bits show information about the version of the MAX14690.
Table 6. ChipRev Register (0x01)
ADDRESS:
0x01
MODE:
Read-Only
BIT
7
6
5
NAME
Chip_Rev[7:0]
4
3
Chip_Rev[7:0]
Chip_Rev[7:0] bits show information about the revision of the MAX14690 silicon.
Table 7. StatusA Register (0x02)
ADDRESS:
0x02
MODE:
Read-Only
BIT
7
6
NAME
–
–
5
4
ThermStat[2:0]
3
2
ChgStat[2:0]
ThermStat[2:0]
Status of Thermistor Monitoring
000 = T < T1
001 = T1 < T < T2
010 = T2 < T < T3
011 = T3 < T < T4
100 = T > T4
101 = No thermistor detected (THM high due to external pullup). Note that if a parallel resistor is used for
thermistor monitoring, this mode may not function properly.
110 = NTC input disabled through ThermEn
111 = Detection disabled due to CHGIN not present.
ChgStat[2:0]
Status of Charger Mode
000 = Charger off
001 = Charging suspended due to temperature (see Figure 5)
010 = Pre-charge in progress
011 = Fast-charge, constant current mode in progress
100 = Fast-charge, constant voltage mode in progress
101 = Maintain charge in progress
110 = Maintain charger timer done
111 = Charger fault condition (see Figure 5)
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Maxim Integrated │ 28
MAX14690
Wearable Charge-Management Solution
Table 8. StatusB Register (0x03)
ADDRESS:
0x03
MODE:
Read-Only
BIT
7
6
5
4
3
2
1
0
NAME
—
—
ILim
UsbOVP
UsbOk
Chg
ThrmSd
Chg
ThrmReg
ChgTmo
ILim
CHGIN Input Current Limit
0 = CHGIN input current is within limit.
1 = CHGIN input is in current limit.
UsbOVP
Status of CHGIN OVP
0 = CHGIN OVP is not active.
1 = CHGIN OVP is active.
UsbOk
Status of CHGIN Input
0 = CHGIN Input is not present or outside of valid range.
1 = CHGIN Input is present and valid.
ChgThrmSd
Status of Thermal Shutdown
0 = Charger and input current limiter is in normal operating mode.
1 = Charger and input current limiter is in thermal shutdown.
ChgThrmReg
Status of Thermal Regulation
0 = Charger is functioning normally, or disabled.
1 = Charger is running in thermal regulation mode and charging current is being actively reduced to prevent
device overheating.
ChgTmo
Status of Time-Out Condition
0 = Charger is running normally, or disabled.
1 = Charger has reached a time-out condition. ChgStat =1 11 in this condition (see Figure 5).
Table 9. StatusC Register (0x04)
ADDRESS:
0x04
MODE:
Read-Only
BIT
7
6
5
4
3
2
1
0
NAME
—
—
—
ThrmBuck1
ThrmBuck2
ThrmLDO1
ThrmLDO2
ThrmLDO3
ThrmBuck1
0 = Buck1 NOT in Thermal Off mode
1 = Buck1 in Thermal Off Mode
ThrmBuck2
0 = Buck2 NOT in Thermal Off mode
1 = Buck2 in Thermal Off Mode
ThrmLDO1
0 = LDO1 NOT in Thermal Off mode
1 = LDO1 in Thermal Off Mode
ThrmLDO2
0 = LDO2 NOT in Thermal Off mode
1 = LDO2 in Thermal Off Mode
ThrmLDO3
0 = LDO3 NOT in Thermal Off mode
1 = LDO3 in Thermal Off Mode
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Maxim Integrated │ 29
MAX14690
Wearable Charge-Management Solution
Table 10. IntA Register (0x05)
ADDRESS:
0x05
MODE:
Clear On Read
BIT
NAME
7
6
5
4
3
2
1
0
Therm
StatInt
ChgStatInt
ILimInt
UsbOVPInt
UsbOk
Chg
ThrmSdInt
Therm
RegInt
Chg
TmoInt
ThermStatInt
Change in ThermStat caused interrupt.
ChgStatInt
Change in ChgStat caused interrupt, or first detection complete after POR.
ILimInt
Input current limit triggered caused interrupt.
UsbOVPInt
Change in UsbOVP caused interrupt.
UsbOk
Change in UsbOk caused interrupt.
ChgThrmSdInt
Change in ChgThrmSd caused interrupt.
ThermRegInt
Change in ChgThrmReg caused interrupt.
ChgTmoInt
Change in ChgTmo caused interrupt.
ThermStatInt
Change in ThermStat caused interrupt.
Table 11. IntB Register (0x06)
ADDRESS:
0x06
MODE:
Clear On Read
BIT
7
6
5
4
3
2
1
0
NAME
—
—
—
Thrm
Buck1Int
Thrm
Buck2Int
Thrm
LDO1Int
Thrm
LDO2Int
Thrm
LDO3Int
ThrmBuck1Int
Change in ThrmBuck1 caused interrupt.
ThrmBuck2Int
Change in ThrmBuck2 caused interrupt.
ThrmLDO1Int
Change in ThrmLDO1 caused interrupt.
ThrmLDO2Int
Change in ThrmLDO2 caused interrupt.
ThrmLDO3Int
Change in ThrmLDO3 caused interrupt.
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Maxim Integrated │ 30
MAX14690
Wearable Charge-Management Solution
Table 12. IntMaskA Register (0x07)
ADDRESS:
0x07
MODE:
Read/Write
BIT
NAME
7
6
5
4
3
2
1
0
Therm
StatIntM
Chg
StatIntM
ILimIntM
Usb
OVPIntM
UsbOkM
ChgThrm
SdIntM
Therm
RegIntM
Chg
TmoIntM
ThermStatIntM
ThermStatIntM masks the ThermStatInt interrupt in the IntA register (0x05).
0 = Mask
1 = Not masked
ChgStatIntM
ChgStatIntM masks the ChgStatInt interrupt in the IntA register (0x05).
0 = Mask
1 = Not masked
ILimIntM
ILimIntM masks the ILimInt interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
UsbOVPIntM
UsbOVPIntM masks the UsbOVPInt interrupt in the IntA register (0x05).
0 = Mask
1 = Not masked
UsbOkM
UsbOkM masks the UsbOk interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
ChgThrm
SdIntM
ChgThrmSdIntM masks the ChgThrmSdInt interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
ThermRegIntM
ThermRegIntM masks the ThermRegInt interrupt in the IntA register (0x05).
0 = Mask
1 = Not masked
ChgTmoIntM
ChgTmoIntM masks the ChgTmoInt interrupt in the IntA register (0x05).
0 = Mask
1 = Not masked
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Maxim Integrated │ 31
MAX14690
Wearable Charge-Management Solution
Table 13. IntMaskB Register (0x08)
ADDRESS:
0x08
MODE:
Read/Write
BIT
7
6
5
4
3
2
1
0
NAME
—
—
—
Thrm
Buck1IntM
Thrm
Buck2IntM
Thrm
LDO1IntM
Thrm
LDO2IntM
Thrm
LDO3IntM
ThrmBuck1
IntM
0 = Mask
1 = Not masked
ThrmBuck2
IntM
0 = Mask
1 = Not masked
ThrmLDO1
IntM
0 = Mask
1 = Not masked
ThrmLDO2
IntM
0 = Mask
1 = Not masked
ThrmLDO3
IntM
0 = Mask
1 = Not masked
Table 14. ILimCntl Register (0x09)
ADDRESS:
0x09
MODE:
Read/Write* or Read-Only if WriteProtect Enabled (see Table 36)
BIT
7
6
5
4
3
2
NAME
—
—
—
—
—
—
ILimCntl[1:0]
1
0
ILimCntl [1:0]
CHGIN Custom Input Current Limit
(see Electrical Characteristics for details)
00 = 0mA
01 = 100mA
10 = 500mA
11 = 1000mA
*Register is reset to default value upon CHGIN rising edge.
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Maxim Integrated │ 32
MAX14690
Wearable Charge-Management Solution
Table 15. ChgCntlA Register (0x0A)
ADDRESS:
0x0A
MODE:
Read/Write* or Ready-Only if WriteProtect Enabled (see Table 36)
BIT
NAME
7
6
ChgAuto
Stp
ChgAuto
ReSta
5
4
BatReChg[1:0]
3
2
1
BatReg[2:0]
ChgEn
ChgAutoStp
Charger Auto-Stop. Controls the transition from Maintain Charger to Maintain Charger Done.
0 = Autostop disabled.
1 = Autostop enabled.
ChgAutoReSta
Charger Auto Restart Control
0 = Charger remains in maintain charge done even when VBAT is less than charge restart threshold
(see Charger state diagram).
1 = Charger automatically restarts when VBAT drops below charge restart threshold.
BatReChg[1:0]
0
Recharge Threshold in Relation to BatReg
00 = BatReg - 70mV
01 = BatReg - 120mV
10 = BatReg - 170mV
11 = BatReg - 220mV
BatReg[2:0]
Setting the Battery Regulation Threshold
000 = 4.05V
001 = 4.10V
010 = 4.15V
011 = 4.20V
100 = 4.25V
101 = 4.30V
110 = 4.35V
111 = Reserved
ChgEn
On/Off Control for Charger (does not affect SYS node).
0 = Charger disabled.
1 = Charger enabled.
*Register is reset to default value upon CHGIN rising edge.
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Maxim Integrated │ 33
MAX14690
Wearable Charge-Management Solution
Table 16. ChgCntlB Register (0x0B)
ADDRESS:
0x0B
MODE:
Read/Write* or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
NAME
—
6
5
4
3
VPChg[2:0]
VPChg[2:0]
Precharge voltage threshold setting
000 = 2.10V
001 = 2.25V
010 = 2.40V
011 = 2.55V
100 = 2.70V
101 = 2.85V
110 = 3.00V
111 = 3.15V
IPChg[1:0]
Precharge current setting
00 = 0.05 x IFCHG
01 = 0.1 x IFCHG
10 = 0.2 x IFCHG
11 = 0.3 x IFCHG
ChgDone[1:0]
Charge done threshold setting
00 = 0.05 x IFCHG
01 = 0.1 x IFCHG
10 = 0.2 x IFCHG
11 = 0.3 x IFCHG
2
IPChg[1:0]
1
0
ChgDone[1:0]
*Register is reset to default value upon CHGIN rising edge.
Table 17. ChTmr Register (0x0C)
ADDRESS:
0x0C
MODE:
Read/Write* or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
5
NAME
—
—
MtChgTmr[1:0]
MtChgTmr
[1:0]
Maintain Charge Timer Setting
00 = 0min
01 = 15min
10 = 30min
11 = 60min
FChgTmr[1:0]
Fast-Charge Timer Setting
00 = 75min
01 = 150min
10 = 300min
11 = 600min
PChgTmr[1:0]
Precharge Timer Setting
00 = 30min
01 = 60min
10 = 120min
11 = 240min
4
3
2
FChgTmr[1:0]
1
0
PChgTmr[1:0]
*Register is reset to default value upon CHGIN rising edge.
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Maxim Integrated │ 34
MAX14690
Wearable Charge-Management Solution
Table 18. Buck1Cfg Register (0x0D)
ADDRESS:
0x0D
MODE:
Read/Write
BIT
7
NAME
6
5
Buck1Seq[2:0] (read-only)
4
3
Buck1En[1:0]
2
1
Buck1Md[1:0]
Buck1Seq[2:0]
Buck1 Enable Configuration (read only)
000 = Disabled
001 = Reserved
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Reserved
110 = Reserved
111 = Controlled by Buck1En[1:0] after 100% of Boot/POR Process Delay Control
Buck1En[1:0]
Buck1 Enable Configuration (effective only when Buck1Seq = 111)
00 = Disabled (Buck1 OUT not actively discharged unless in Hard Reset/ShutDown/Off Mode)
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
Buck1Md[1:0]
Buck1 Mode Select
00 = Burst mode
01 = Forced PWM mode
10 = Forced PWM mode when MPC0 is high (regardless of MPC1)
11 = Forced PWM mode when MPC1 is high (regardless of MPC0)
Buck1Ind
Buck1 Inductance Select
0 = inductance is 2.2µH
1 = inductance is 4.7µH
0
Buck1Ind
Table 19. Buck1VSet Register (0x0E)
ADDRESS:
0x0E
MODE:
Read/Write or Read-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
NAME
—
—
Buck1VSet
[5:0]
5
4
3
2
1
0
Buck1VSet[5:0]
Buck1 Output Voltage Setting This setting is internally latched and can change only when Buck1 is disabled.
Linear scale from 0.8V to 1.8V in 25mV increments
000000 = 0.8V
000001 = 0.825V
…
101000 = 1.8V
> 101000 = 1.8V
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Maxim Integrated │ 35
MAX14690
Wearable Charge-Management Solution
Table 20. Buck2Cfg Register (0x0F)
ADDRESS:
0x0F
MODE:
Read/Write
BIT
7
NAME
6
5
Buck2Seq[2:0] (read only)
4
3
2
Buck2En[1:0]
1
Buck2Md[1:0]
Buck2Seq[2:0]
Buck2 Enable Configuration (read only)
000 = Disabled
001 = Reserved
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Reserved
110 = Reserved
111 = Controlled by Buck2En [1:0] after 100% of Boot/POR Process Delay Control
Buck2En[1:0]
Buck2 Enable Configuration (effective only when Buck2Seq = 111)
00 = Disabled (Buck2 OUT not actively discharged unless in Hard Reset/ShutDown/Off Mode)
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
Buck2Md[1:0]
Buck2 Mode Select
00 = Burst mode
01 = Forced PWM mode
10 = Forced PWM mode when MPC0 is high (regardless of MPC1)
11 = Forced PWM mode when MPC1 is high (regardless of MPC0)
Buck2Ind
Buck2 Inductance Select
0 = inductance is 2.2µH
1 = inductance is 4.7µH
0
Buck2Ind
Table 21. Buck2VSet Register (0x10)
ADDRESS:
0x10
MODE:
Read/Write or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
NAME
—
—
Buck2VSet
[5:0]
5
4
3
2
1
0
Buck2VSet[5:0]
Buck2 Output Voltage Setting
This setting is internally latched and can change only when Buck2 is disabled.
Linear scale from 1.5V to 3.3V in 50mV increments
000000 = 1.5V
000001 = 1.55V
…
100100 = 3.3V
> 100100 = 3.3V
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Maxim Integrated │ 36
MAX14690
Wearable Charge-Management Solution
Table 22. LDO1Cfg Register (0x12)
ADDRESS:
0x12
MODE:
Read/Write
BIT
7
NAME
6
5
LDO1Seq[2:0] (read Only)
4
3
RFU
LDO1Act
DSC
2
1
0
LDO1
Mode
LDO1En[1:0]
LDO1Seq[2:0]
LDO1 Enable Configuration (read only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Disabled
110 = Disabled
111 = Controlled by LDO1En[1:0] after 100% of Boot/POR Process Delay Control
LDO1ActDSC
LDO1 Active Discharge Control
0: LDO1 output is actively discharged only in HardReset mode
1: LDO1 output is actively discharged in HardReset mode and also when its Enable goes low
LDO1En[1:0]
LDO1 Enable Configuration (effective only when LDO1Seq = 111)
00 = Disabled–LDOs OUT not actively discharged unless Hard-Reset/Shutdown/Off mode
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
LDO1Mode
LDO1 Mode Control
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully ON or OFF depending on state of LDO1En. When FET is ON, the
output is unregulated. This setting is internally latched and can change only when the LDO is disabled.
Table 23. LDO1VSet Register (0x13)
ADDRESS:
0x13
MODE:
Read/Write* or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
5
NAME
—
—
—
LDO1VSet[4:0]
4
3
2
1
0
LDO1Vset[4:0]
LDO1 Output Voltage Setting
Linear Scale from 0.8V to 3.6V in 100mV increments
00000 = 0.8V
00001 = 0.9V
…
11100 = 3.6V
> 11101 = N/A
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Maxim Integrated │ 37
MAX14690
Wearable Charge-Management Solution
Table 24. LDO2Cfg Register (0x14)
ADDRESS:
0x14
MODE:
Read/Write
BIT
7
NAME
6
5
LDO2Seq[2:0] (read only)
4
3
RFU
LDO2Act
DSC
2
1
0
LDO2
Mode
LDO2En[1:0]
LDO2Seq [2:0]
LDO2 Enable Configuration (read only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Disabled
110 = Disabled
111 = Controlled by LDO2En[1:0] after 100% of Boot/POR Process Delay Control
LDO2ActDSC
LDO2 Active Discharge Control
0 = LDO2 output will be actively discharged only in HardReset mode
1 = LDO2 output will be actively discharged in HardReset mode and also when its Enable goes Low
LDO2En [1:0]
LDO2 Enable Configuration (effective only when LDO2Seq = 111)
00 = Disabled – LDO’s OUT not actively discharged unless HardReset/ShutDown/Off Mode
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
LDO2Mode
LDO2 Mode Control
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully ON or OFF depending on state of LDO2En. When FET is ON, the
output is unregulated. This setting is internally latched and can change only when the LDO is disabled.
Table 25. LDO2VSet Register (0x15)
ADDRESS:
0x15
MODE:
Read/Write or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
5
NAME
—
—
—
LDO2VSet[4:0]
4
3
2
1
0
LDO2Vset[4:0]
LDO2 Output Voltage Setting
Linear scale from 0.8V to 3.6V in 100mV increments
00000 = 0.8V
00001 = 0.9V
…
11100 = 3.6V
> 11101 = N/A
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Maxim Integrated │ 38
MAX14690
Wearable Charge-Management Solution
Table 26. LDO3Cfg Register (0x16)
ADDRESS:
0x16
MODE:
Read/Write
BIT
7
NAME
6
5
LDO3Seq[2:0] (read-only)
4
3
RFU
LDO3Act
DSC
2
1
0
LDO3
Mode
LDO3En[1:0]
LDO3Seq[2:0]
LDO3 Enable Configuration (read only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Disabled
110 = Disabled
111 = Controlled by LDO3En[1:0] after 100% of Boot/POR Process Delay Control
LDO3ActDSC
LDO3 Active Discharge Control
0 = LDO3 output is actively discharged only in HardReset mode
1 = LDO3 output is actively discharged in HardReset modes and also when its Enable goes low.
LDO3En[1:0]
LDO3 Enable Configuration (effective only when LDO3Seq == 111)
00 = Disabled. LDO’s OUT not actively discharged unless in HardReset/ShutDown/Off mode
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
LDO3Mode
LDO3 Mode Control
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully ON or OFF depending on state of LDO3En. When FET is ON, the
output is unregulated. This setting is internally latched and can change only when the LDO is disabled.
Table 27. LDO3VSet Register (0x17)
ADDRESS:
0x17
MODE:
Read/Write or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
5
NAME
—
—
—
LDO3VSet[4:0]
4
3
2
1
0
LDO3Vset[4:0]
LDO3 Output Voltage Setting
Linear scale from 0.8V to 3.6V in 100mV increments
00000 = 0.8V
00001 = 0.9V
…
11100 = 3.6V
> 11101 = N/A
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Maxim Integrated │ 39
MAX14690
Wearable Charge-Management Solution
Table 28. ThrmCfg Register (0x18)
ADDRESS:
0x18
MODE:
Read/Write* or Ready-Only if WriteProtect Enabled (see Table 35)
BIT
7
6
5
4
3
2
1
0
NAME
—
—
—
—
—
—
JEITAEn
ThermEn
3
2
1
0
JEITAEn
Thermal or JEITA Monitoring Enable
0 = JEITA monitoring disabled
1 = JEITA monitoring enabled, only if ThermEn = 1
ThermEn
Thermal or JEITA Monitoring Selector
0 = Thermal monitoring disabled
1 = Thermal monitoring enabled
*Register is reset to default value upon CHGIN rising edge.
Table 29. MONCfg Register (0x19)
ADDRESS:
0x19
MODE:
Read/Write
BIT
7
6
NAME
—
—
5
4
MONRatioCfg[1:0]
MONtHiZ
MONRatioCfg
MON Resistive Partition Selector
00 = 4:1
01 = 3:1
10 = 2:1
11 = 1:1
MONtHiZ
MON OFF MODE condition
0 = Pulled low by 100k pulldown resistor
1 = Hi-Z
MONCtr[2:0]
MON Pin Source selection (40µs BBM after any change of MONCtr)
000 = MON is not connected to any internal node and its state depends on MONHiZ
001 = MON connected to a resistive partition of BATT
010 = MON connected to a resistive partition of SYS
011 = MON connected to a resistive partition of BUCK1 OUT
100 = MON connected to a resistive partition of BUCK2 OUT
101 = MON connected to a resistive partition of LDO1 OUT
110 = MON connected to a resistive partition of LDO2 OUT
111 = MON connected to a resistive partition of LDO3 OUT
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MONCtr[2:0]
Maxim Integrated │ 40
MAX14690
Wearable Charge-Management Solution
Table 30. BootCfg Register (0x1A)
ADDRESS:
0x1A
MODE:
Read-Only
BIT
7
6
NAME
5
4
PwrRstCfg[3:0]
3
2
SftRstCfg
PwrRstCfg
[3:0]
See Table 1
SftRstCfg
Soft Reset Register Default
0 = Registers do not reset to default values on soft reset
1 = Registers reset to default values on soft reset
BootDly[1:0]
Boot/POR Process Delay Control
00 = 80ms + 34ms
01 = 120ms + 34ms
10 = 220ms + 34ms
11 = 420ms + 34ms
1
BootDly[1:0]
0
RFU
Table 31. PinStat Register (0x1B)
ADDRESS:
0x1B
MODE:
Read/Write
BIT
7
NAME
6
5
ILim_T[2:0]
ILim_T[2:0]
Monitor of The Input limiter Current Setting
000 = Input limiter off
001 = 100mA
010 = 500mA
100 =1A
PFN1
PFN1 Input State
0 = Pin low
1 = Pin high
PFN2
PFN2 In/Out State
0 = Pin low
1 = Pin high
MPC1
MPC1 Input State
0 = Pin low
1 = Pin high
MPC0
MPC0 Input State
0 = Pin low
1 = Pin high
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4
3
2
1
0
—
PFN1
PFN2
MPC1
MPC0
Maxim Integrated │ 41
MAX14690
Wearable Charge-Management Solution
Table 32. Buck1/2Extra Control Register (0x1C)
ADDRESS:
0x1C
MODE:
Read/Write
BIT
NAME
Buck2ActDSC
Buck2FFET
Buck1ActDSC
Buck1FFET
7
6
5
4
3
2
1
0
Reserved
Reserved
Buck2
ActDSC
Buck2
FFET
Reserved
Reserved
Buck1
ActDSC
Buck1
FFET
Buck2 Active Discharge Control
0 = Buck2 output is actively discharged only in HardReset mode.
1 = Buck2 output is actively discharged in HardReset mode and also when its Enable goes low.
Buck2 Force FET scaling (it reduces IQ by lowering the nMOS power to 20% of the nominal value)
0 = FET Scaling only enabled during the Buck2 turn-on sequence.
1 = FET Scaling enabled during the Buck2 turn-on sequence and also in the Buck2 steady on state.
Buck1 Active Discharge Control
0 = Buck1 output is actively discharged only in HardReset mode.
1 = Buck1 output is actively discharged in HardReset mode and also when its Enable goes low.
Buck1 Force FET Scaling (it reduces IQ by lowering the nMOS power to 20% of the nominal value)
0 = FET Scaling only enabled during the Buck1 turn-on sequence.
1 = FET Scaling enabled during the Buck1 turn-on sequence and also in the Buck1 steady on state.
Table 33. PwrCfg Register (0x1D)
ADDRESS:
0x1D
MODE:
Read/Write
BIT
NAME
7
6
5
4
3
2
1
0
PFNx
ResEna
–
–
–
–
–
–
StayOn
PFNxResEna
PFN_ Automatic Internal Pull-Up/Pull-Down Enable
0 = No internal pullup/pulldown
1 = Automatic internal pullup/pulldown as per Table 1
StayOn
This bit is used to ensure that the processor booted correctly. This bit must be set within 5s of power-on to
prevent the part from shutting down and returning to the power-off condition. This bit has no effect after being set.
0 = Shut down 5s after power-on
1 = Stay on
Table 34. PwrOff Register (0x1F)
ADDRESS:
0x1F
MODE:
Read/Write
BIT
7
NAME
PWR_CMD
[7:0]
6
5
4
3
2
1
0
PWR_CMD[7:0]
Power-Off Command
Writing 0xB2 to this register places the part in the off mode except in PwrRstCfg[3:0] modes 0000 and 0001
when it has no effect. Writing any other code has no effect.
In PwrRstCfg[3:0] modes 0110 and 0111, the part can be turned back on by a button press or a valid voltage
applied to CHGIN. In all other modes, only a valid voltage applied to CHGIN turns the device back on. See
Figure 1 for more details.
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Maxim Integrated │ 42
Enabled
Enabled
Enabled
-120mV
ChgAutoStp
ChgAutoReSta
BatReChg[1:0]
www.maximintegrated.com
0.10 x IFChg
30min
150min
2.85V
0.10 x IFChg
0.05 x IFChg
60min
300min
30min
VPChg[2:0]
IPChg[1:0]
ChgDone[1:0]
MtChgTmr[1:0]
FChgTmr[1:0]
PChgTmr[1:0]
2.2μH
1.2V
1.8V
100mA
100mA
Buck1_Iup_SET[2:0]
Buck2_Iup_SET[2:0]
LDO
3.0V
LDO1Mode
LDO1Vset[4:0]
(Read-Only)
LDO1Seq[2:0]
LDO1En
2.2μH
2.2μH
Buck2Ind
Buck2VSet[5:0]
2.0V
LDO
Always On
100mA
100mA
1.8V
0% boot
(Read-Only)
0% boot
Buck2Seq[2:0]
1.175V
2.2μH
Buck1Ind
Buck1VSet[5:0]
(Read-Only)
25% boot
240min
3.00V
Disabled
Buck1En
Buck1Seq[2:0]
0.05 x IFChg
Disabled
Buck1En[1]
4.30V
ChgEn
Enabled
4.20V
Enabled
BatReg[2:0]
-220mV
Enabled
MAX14690B
MAX14690A
REGISTER BITS
3.1V
LDO
LDO1En
100mA
100mA
2.0V
2.2μH
25% boot
1.8V
2.2μH
Disabled
60min
300min
0min
0.10 x IFChg
0.10 x IFChg
3.00V
Disabled
Enabled
4.35V
-220mV
Enabled
Enabled
MAX14690C
Table 35. Register Bit Default Values
3.1V
LDO
0% boot
100mA
100mA
1.8V
2.2μH
Buck2En
1.3V
2.2μH
0% boot
30min
150min
0min
0.05 x IFChg
0.10 x IFChg
3.00V
Disabled
Enabled
4.20V
-220mV
Enabled
Enabled
MAX14690D
2V
LDO
Always On
100mA
100mA
2.2V
2.2μH
0% boot
1.2V
2.2μH
Buck1En
30min
600min
60min
0.05 x IFChg
0.10 x IFChg
2.85V
Disabled
Enabled
4.20V
-120mV
Enabled
Enabled
MAX14690E
1.8V
LDO
Always On
100mA
100mA
1.8V
2.2μH
25% boot
1.2V
2.2μH
25% boot
60min
300min
0min
0.10 x IFChg
0.10 x IFChg
3.00V
Disabled
Enabled
4.20V
-120mV
Enabled
Enabled
MAX14690N
3.0V
LDO
LDO1En
100mA
100mA
3.3V
2.2μH
Buck2En
1.8V
2.2μH
0% boot
60min
300min
0min
0.1 x IFChg
0.10 x IFChg
3.00V
Disabled
Enabled
4.35V
-220mV
Enabled
Enabled
MAX14690H
3.00V
Disabled
Enabled
4.35V
-120mV
Enabled
Enabled
MAX14690J
3.00V
Disabled
Enabled
4.20V
-220mV
Enabled
Enabled
MAX14690K
1.8V
LDO
LDO1En
100mA
100mA
2.85V
2.2μH
25% boot
1.2V
2.2μH
Buck1En
60min
300min
0min
0.10 x IFChg
1.8V
LDO
LDO1En
100mA
100mA
2.85V
2.2μH
25% boot
1.2V
2.2μH
Buck1En
60min
300min
0min
3.1V
LDO
0% boot
100mA
100mA
1.8V
2.2mH
Buck2En
1.3V
2.2mH
0% boot
30min
150min
0min
0.10 x IFChg 0.05 x IFChg
0.10 x IFCHg 0.10 x IFCHg 0.10 x IFCHg
3.00V
Disabled
Enabled
4.20V
-120mV
Enabled
Enabled
MAX14690I
MAX14690
Wearable Charge-Management Solution
Maxim Integrated │ 43
www.maximintegrated.com
Enabled
Stay On
Writable
Enabled
5s Turnoff
Writable
500mA
PFNxResEna
StayOn
WriteProtect
ILimCntl[1:0]
500mA
Enabled
ms
(80 + 34)ms
(120 + 34)
Reset
Hold
(Read-Only)
KIN#
KIN#
BootDly[1:0]
(Read-Only)
SftRstCfg
(Read-Only)
PwrRstCfg[3:0]
Enabled
Disabled
JEITAEn
ThermEn
Enabled
3.7V
3.7V
LDO3Vset[4:0]
Switch
Switch
LDO3En
3.2V
LDO
LDO2En
MAX14690B
LDO3Mode
(Read-Only)
LDO3En
3.7V
LDO2Vset[4:0]
LDO3Seq[2:0]
Switch
LDO2En
MAX14690A
LDO2Mode
(Read-Only)
LDO2Seq[2:0]
REGISTER BITS
500mA
Writable
Stay On
Enabled
(120 + 34)ms
Reset
Soft Reset
Enabled
Enabled
1.8V
Switch
LDO3En
1.8V
LDO
LDO2En
MAX14690C
500mA
Writable
Stay On
Enabled
(80 + 34)ms
Reset
CR Low
Enabled
Disabled
0.8V
Switch
LDO3En
0.8V
Switch
LDO2En
MAX14690D
Table 35. Register Bit Default Values (continued)
500mA
Writable
Stay On
Enabled
(80 + 34)ms
Hold
Soft Reset
Enabled
Enabled
3.7V
Switch
LDO3En
2.7V
LDO
LDO2En
MAX14690E
500mA
Writable
Stay On
Enabled
(120 + 34)ms
Hold
KIN
Enabled
Disabled
3.0V
LDO
LDO3En
3.2V
LDO
LDO2En
MAX14690N
500mA
Writable
Stay On
Enabled
(120 + 34)ms
Reset
KIN
Enabled
Enabled
3.0V
LDO
LDO3En
3.0V
LDO
LDO2En
MAX14690H
Hold
Soft Reset
Enabled
Disabled
3V
LDO
LDO3En
1.2V
LDO
LDO2En
MAX14690J
500mA
Writable
Stay On
Enabled
100mA
Writable
Stay On
Enabled
(120 + 34)ms (120 + 34)ms
Hold
Soft Reset
Enabled
Disabled
3V
LDO
LDO3En
1.2V
LDO
LDO2En
MAX14690I
500mA
Writable
Stay On
Enabled
(80 + 34)ms
Reset
Soft Reset
Enabled
Disabled
0.8V
Switch
LDO3En
0.8V
Switch
LDO2En
MAX14690K
MAX14690
Wearable Charge-Management Solution
Maxim Integrated │ 44
ChipId
ChipRev
IntMaskA
IntMaskB
ILimCntl
ChgCntlA
ChgCntlB
ChgTmr
Buck1Cfg
Buck1VSet
Buck2Cfg
Buck2VSet
Reserved
LDO1Cfg
LDO1VSet
LDO2Cfg
LDO2VSet
LDO3Cfg
LDO3VSet
ThrmCfg
MONCfg
BootCfg
Buck1/2Extra
PwrCfg
NULL
PwrOff
0x00
0x01
0x07
0x08
0x09
www.maximintegrated.com
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1C
0x1D
0x1E
0x1F
0x00
0x00
0x80
0x00
0x63
0x00
0x01
0x1D
0xE1
0x1D
0xE1
0x16
0xE0
0x24
0x06
0x40
0x10
0xE0
0x38
0x54
0xD7
0x02
0x00
0x00
0x02
0x01
0x00
0x00
0x81
0x00
0x69
0x00
0x03
0x1D
0xE1
0x18
0xE0
0x0C
0x20
0x24
0x06
0x40
0x0F
0x60
0x27
0x61
0xFB
0x02
0x00
0x00
0x02
0x01
0x00
0x00
0x81
0x00
0x7B
0x00
0x03
0x0A
0xE1
0x0A
0xE0
0x17
0xE0
0x24
0x0A
0x60
0x28
0x00
0x09
0x65
0xFD
0x02
0x00
0x00
0x03
0x01
0x00
0x00
0x81
0x00
0x59
0x00
0x01
0x00
0xE1
0x00
0xE1
0x17
0x40
0x24
0x06
0xE0
0x14
0x40
0x04
0x64
0xF7
0x02
0x00
0x00
0x02
0x01
0x01
0x03
0x00
0x00
0x02
0xD7
0x65
0x09
0x60
0x10
0x60
0x06
0x24
0x20
0x0A
0xE0
0x18
0xE0
0x16
0x01
0x00
0x63
0x00
0x81
0x00
0x00
0x01
0x03
0x00
0x00
0x02
0xD7
0x54
0x3C
0xE0
0x10
0x40
0x0E
0x24
0x20
0x0C
0xE0
0x13
0xE1
0x1D
0x03
0x00
0x71
0x00
0x81
0x00
0x00
0x00
0x00
0x81
0x00
0x6B
0x00
0x03
0x16
0xE0
0x16
0xE0
0x16
0xE0
0x24
0x24
0xE0
0x28
0x40
0x09
0x65
0xFD
0x02
0x00
0x00
0x03
0x01
0x00
0x00
0x81
0x00
0x73
0x00
0x01
0x16
0xE0
0x04
0xE0
0x0A
0xE0
0x24
0x1B
0x60
0x10
0xE0
0x09
0x65
0xD7
0x02
0x00
0x00
0x03
0x01
0x00
0x00
0x81
0x00
0x73
0x00
0x01
0x16
0xE0
0x04
0xE0
0x0A
0xE0
0x24
0x1B
0x60
0x10
0xE0
0x09
0x65
0xDD
0x01
0x00
0x00
0x02
0x01
0x00
0x00
0x81
0x00
0x79
0x00
0x01
0x00
0xE1
0x00
0xE1
0x17
0x40
0x24
0x06
0xE0
0x14
0x40
0x04
0x64
0xF7
0x02
0x00
0x00
0x02
0x01
DEFAULT VALUES
REGISTER REGISTER
ADDRESS
NAME
MAX14690A MAX14690B MAX14690C MAX14690D MAX14690E MAX14690N MAX14690H MAX14690I MAX14690J MAX14690K
Table 36. Register Default Values
MAX14690
Wearable Charge-Management Solution
Maxim Integrated │ 45
MAX14690
Wearable Charge-Management Solution
Ordering Information
PART
Chip Information
TEMP RANGE
PIN-PACKAGE
MAX14690AEWX+
-40°C to +85°C
36 WLP
MAX14690AEWX+T
-40°C to +85°C
36 WLP
MAX14690BEWX+
-40°C to +85°C
36 WLP
MAX14690BEWX+T
-40°C to +85°C
36 WLP
MAX14690CEWX+
-40°C to +85°C
36 WLP
MAX14690CEWX+T
-40°C to +85°C
36 WLP
MAX14690DEWX+
-40°C to +85°C
36 WLP
MAX14690DEWX+T
-40°C to +85°C
36 WLP
MAX14690EEWX+*
-40°C to +85°C
36 WLP
MAX14690EEWX+T*
-40°C to +85°C
36 WLP
MAX14690HEWX+
-40°C to +85°C
36 WLP
MAX14690HEWX+T
-40°C to +85°C
36 WLP
MAX14690IEWX+
-40°C to +85°C
36 WLP
MAX14690IEWX+T
-40°C to +85°C
36 WLP
MAX14690JEWX+
-40°C to +85°C
36 WLP
MAX14690JEWX+T
-40°C to +85°C
36 WLP
MAX14690KEWX+*
-40°C to +85°C
36 WLP
MAX14690KEWX+T*
-40°C to +85°C
36 WLP
MAX14690NEWX+
-40°C to +85°C
36 WLP
MAX14690NEWX+T
-40°C to +85°C
36 WLP
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
36 WLP
W362D2+1
21-0897
Refer to
Application
Note 1891
+Denotes a lead(Pb)-free package/RoHS-compliant package.
T = Tape and reel.
*Future Product—contact marketing for availability.
See Table 35 and Table 36 for the device differences.
www.maximintegrated.com
Maxim Integrated │ 46
MAX14690
Wearable Charge-Management Solution
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
12/14
Initial release
1
4/15
BUCK1 default was changed to 1.175V from 2.0V
2
4/15
Removed future product designation from MAX14690AEWX+
3
4/15
Added additional Buck Ripple specifications in Electrical Characteristics table
DESCRIPTION
—
6, 13, 15, 16, 19, 22,
40
41
5, 6
2, 11, 17-18, 22, 24,
39-42
4
5/15
Added I2C section and MAX14690C/D/N as future products
5
7/15
Removed future product designation from MAX14690DEWX+ and
MAX14690DEWX+T
6
10/15
Removed future product designation of MAX14690C and MAX14690N
2, 10, 13, 18, 29,
41-45
7
1/16
Added MAX14690I part numbers to data sheet
5, 11, 18, 43–45
8
2/16
Push Button Control diagram updated
18
9
2/16
Removed future product designation from MAX14690I
45
10
4/16
Removed future product designation from MAX14690H and added MAX14690J to
Ordering Information table
43-45
11
5/16
Added MAX14690K future product
43-45
45
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 47
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