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MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
General Description
The MAX14819/MAX14819A low-power, dual-channel,
IO-Link® master transceiver with sensor/actuator powersupply controllers is fully compliant with the latest IO-Link
and binary input standards and test specifications, IEC
61131-2, IEC 61131-9 SDCI, and IO-Link 1.1.3. This
master transceiver also includes two auxiliary digital input
(DI_) channels.
The MAX14819/MAX14819A is configurable to operate
either with external UARTs or using the integrated framers on the IC.
To ease selection of microcontroller, the master transceiver
features frame handlers with UARTs and FIFOs. These
are designed to simplify time critical control of all IO-Link
M-sequence frame types. The MAX14819/MAX14819A
also features autonomous cycle timers, reducing the need
for accurate controller timing. Integrated establish-communication sequencers also simplify wake-up management.
The device message response delay on the MAX14819A
can be disabled when using the frame handler and
the MAX14819A features higher L+ thresholds than
the MAX14819. The MAX14819A receivers also feature
increased high-frequency signal isolation compared to
the MAX14819.
The MAX14819/MAX14819A integrates two low-power
sensor supply controllers with advanced current limiting,
reverse current-blocking, and reverse polarity protection
capability to enable low-power robust solutions.
The MAX14819/MAX14819A is available in a 48-pin
(7mm x 7mm) TQFN package and is specified over the
extended -40°C to +125°C temperature range.
Applications
●● IO-Link Master Systems
●● IO-Link Gateways
19-8744; Rev 3; 3/20
Benefits and Features
●● Low-Power Architecture
• 1Ω (typ) Driver On-Resistance
• 1.9mA (typ) Total Supply Current for 2 Channels
• Current Limiters with 15mV Sense Voltage
●● Integrated IO-Link Framer Eliminates Need for
External UARTs
• Integrated Cycle Timer Relieves Microcontroller
from Timing-Critical Tasks
●● High Configurability and Integration Reduce SKUs
• Two Auxiliary Type 1/Type 3 Digital Inputs
• Supports NPN Sensors
• Dual 24V Sensor Supply Controllers Include:
• Large Capacitive Load Charge Capability
• 2A and Higher Load Currents
●● Integrated Protection Enables Robust Systems
• Reverse Polarity Protection on All Interface Pins
• Overvoltage Tolerance on All Interface Pins
• C/Q and DI Fully Compliant with IEC 61131-2
• C/Q Compliant with IO-Link 1.1.3.
• Reverse Current Blocking on L+ and C/Q
• 65V Absolute Max Ratings for TVS Flexibility
• Glitch Filters for Improved Burst Resilience
• -40°C to +125°C Operating Temperature Range
Ordering Information appears at end of data sheet.
IO-Link is a registered trademark of Profibus User Organization
(PNO).
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Typical Operating Circuit
24V
10µF
3.3V
5V
VL V5 REGEN VCC
MAX12930
µC
3.3V
SN2A G2A L+A
IRQ
5V
MAX14931
SN1A
G1A
1µF
100Ω
1µF
XI
14.7456MHz
CQA
MAX14819
MAX14819A
SPI
DIA
330pF
100Ω
XO
CLKO
CLKI
3.3V
A0 A1
TXA
TXENA
GND
RXRDYA/LD1A
RXERRA/LD2A
THE MAX14819/MAX14819A IS A DUAL-CHANNEL MASTER TRANSCEIVER. ONLY ONE CHANNEL IS SHOWN HERE. OPERATED WITH INTERNAL IOLINK FRAMER.
Functional Diagram
VL
V5
MAX14819
MAX14819A
REGEN
VCC
G1A
G1B SN1A
SN1B
SN2A
SN2B G2A
G2B
REG
XI
XO
CLKI
XTAL
OSCILLATOR
CLKO
ESTABLISH
COMM
L+ SUPPLY CONTROLLER
L+A
L+B
RXA
RXB
TXENA
CQA
TXENB
CQB
DRIVER
TXA
TXB
RXERRA/LD2A
RXERRB/LD2B
FRAME HANDLER
RXRDYA/LD1A
DIA
RXRDYB/LD1B
IRQ
SDI
SDO
SCLK
CS
DIB
SYNC
SPI
REGISTERS
A1
www.maximintegrated.com
CYCLE TIMER
A0
CHANNEL A
CHANNEL B
GND
LIB
LIA
Maxim Integrated │ 2
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Absolute Maximum Ratings
(All voltages referenced to GND, unless otherwise noted.)
VCC............................. max [(VPM - 70V), (VCQ_ - 70V)] to +65V
V5, VL.......................................................................-0.3V to +6V
REGEN.............................. -0.3V to the min(VCC + 0.3V or +6V)
CQA, CQB................................................... (VCC - 70V) to +65V
DIA, DIB, L+A, L+B..................................... (VPM - 70V) to +65V
SN1A, SN1B...........................................................-0.3V to +65V
SN2A...................................... (VSN1A - 0.3V) to (VSN1A + 0.3V)
SN2B...................................... (VSN1B - 0.3V) to (VSN1B + 0.3V)
G1A, G2A............max (-0.3V, [VSN1A - 14V]) to (VSN1A + 0.3V)
G1B, G2B............max (-0.3V, [VSN1B - 14V]) to (VSN1B + 0.3V)
XI, XO........................................................... -0.3V to (V5 + 0.3V)
Logic Inputs
CS, SDI, SCLK, A_, TXEN_, TX_, CLKI.... -0.3V to (VL + 0.3V)
Logic Outputs
SDO, IRQ, LI_, RX_, RXRDY_/LD1_,
RXERR_/LD2_, CLKO ............................ -0.3V to (VL + 0.3V)
Continuous Current Into GND and VCC.................................±2A
Continuous Current Into CQA and CQB................................±1A
Continuous Current Into V5.............................................±100mA
Continuous Current Into Any Other Pin.............................±50mA
Continuous Power Dissipation
TQFN (derate 40mW/°C above +70°C)............................3.2W
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature.......................Internally Limited
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
VPM = max (0V, VCC, DIA, DIB, SN1A, SN1B, L+A, L+B)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 48 TQFN-EP
Package Code
T4877+4C
Outline Number
21-0144
Land Pattern Number
90-0130
MULTILAYER BOARD
Junction to Ambient (θJA)
25°C/W
Junction to Case (θJC)
1°C/W
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.maximintegrated.com
Maxim Integrated │ 3
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DC Electrical Characteristics
(VCC = 9V to 36V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V, all logic inputs at VL or GND; TA = -40°C to +125°C, unless otherwise
noted. Typical values are at VCC = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
9
36
V
7
9
V
VCC POWER
VCC Supply Voltage
VCC Undervoltage-Lockout
Threshold
VCC Undervoltage-LockoutThreshold Hysteresis
VCC Supply Current
VCC
VCCUVLO
VCC rising
VCCUVLO_HYST
ICC
VCC Warning Threshold
VCC_WRN
VCC Warning Threshold
Hysteresis
VCC_WHY
340
REGEN = GND,
L+EnA = L+EnB =
1, external clock
selected, CQ_ in
push-pull
configuration,
CL[1:0] = 00, no
load on CQ_
CQ_ outputs low
0.4
mV
0.75
mA
CQ_ outputs high
0.5
16
0.85
18
500
V
mV
V5 POWER
V5 Supply Voltage
V5 Supply Current
V5
REGEN = GND
IV5
REGEN = GND,
L+EnA = L+EnB =
1, external clock
selected, CQ_ in
push-pull
configuration,
CL[1:0] = 00, no
load on CQ_
4.5
CQ_ outputs low
5
5.5
1.4
1.9
V
mA
CQ outputs high
1.4
1.9
V5 LINEAR REGULATOR
V5 Output Voltage
V5 Current Limit
V5 Load Regulation
REGEN Pullup Current
REGEN Threshold
www.maximintegrated.com
V5
REGEN unconnected, no load on V5,
CQ_ disabled, L+EnA = L+EnB = 0
4.75
ICL_V5
REGEN unconnected, CQ_ disabled,
L+EnA = L+EnB = 0
20
dVV5
REGEN unconnected, CQ_ disabled,
L+EnA = L+EnB = 0, 0mA ≤ ILOAD ≤
20mA
IREGEN
VTH_REGEN
VREGEN = 0V
5.25
mA
-0.1
5
0.2
V
1.8
mV/mA
30
μA
2.6
V
Maxim Integrated │ 4
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DC Electrical Characteristics (continued)
(VCC = 9V to 36V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V, all logic inputs at VL or GND; TA = -40°C to +125°C, unless otherwise
noted. Typical values are at VCC = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.62
5.5
V
0.4
1.5
V
VL POWER
VL Logic-Level Supply
Voltage
VL
VL Undervoltage Threshold
VLUVLO
VL Undervoltage Threshold
Hysteresis
VLUVHYS
VL Logic-Level Supply
Current
VL falling
50
mV
IL
All logic inputs at VL or GND, all logic
outputs unconnected
ROH
High-side enabled, ILOAD = -200mA
1.0
2
ROL
Low-side enabled, ILOAD = +200mA
1.0
2.2
5
µA
CQ_ DRIVER
Driver On-Resistance
Driver Current Limit
ICL
VCQ_ = (VCC - 3V)
or 3V
CL[1:0] = 00
100
150
CL[1:0] = 01
190
280
CL[1:0] = 10
280
410
CL[1:0] = 11
500
650
IEC3Th_/DiEC3Th
=0
10.5
13.0
IEC3Th_/DiEC3Th
=1
7.5
11.0
IEC3Th_/DiEC3Th
=0
8.0
11.5
IEC3Th_ /DiEC3Th
=1
6.0
8.0
Ω
mA
CQ_, DI_ RECEIVER
CQ_, DI_ Input Threshold
High
CQ_, DI_ Input Threshold
Low
CQ_, DI_ Input Threshold
Hysteresis
VTH
VTL
VHYS
CQ_ driver disabled
CQ_ driver disabled
CQ_ driver disabled
ICQ_SNK
VCQ_ > 5V,
SourceSink_ = 0
V
IEC3Th_/DiEC3Th
=0
2
IEC3Th_/DiEC3Th
=1
2
2mA pulldown
enabled
CQ_ Current Sink
V
V
2
2.5
2.75
(SinkSel_[1:0] = 10)
5mA pulldown
enabled
mA
5
5.8
6.6
(SinkSel_[1:0] = 01)
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Maxim Integrated │ 5
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DC Electrical Characteristics (continued)
(VCC = 9V to 36V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V, all logic inputs at VL or GND; TA = -40°C to +125°C, unless otherwise
noted. Typical values are at VCC = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
2mA pullup enabled
CQ_ Current Source
ICQ_SRC
(VCC - VCQ_) > 5V, (SinkSel_[1:0] = 10)
SourceSink_ = 1 5mA pullup enabled
(SinkSel_[1:0] = 01)
MIN
TYP
MAX
-2.75
-2.5
-2
UNITS
mA
-6.6
-5.8
-5
CQ_ Weak Pulldown Current
ICQ_PD
Driver disabled (DrvDis_ = 1),
SourceSink = 0, weak pulldown enabled
(SinkSel_[1:0] = 11), VCQ_ > 5V
150
250
μA
CQ_ Weak Pullup Current
ICQ_PU
Driver disabled (DrvDis_ = 1),
SourceSink = 1, weak pullup enabled
(SinkSel_[1:0] = 11), VCC - VCQ_ > 5V
-250
-150
μA
ICQ
CQ_ driver enabled (DrvDis = 0),
CQ_set to high impedance, pullup and
pulldown disabled (SinkSel_[1:0] = 00),
receiver enabled, VCC = 24V,
-1V < VCQ_ < (VCC + 1V)
-60
+400
μA
ICQ_EXT
CQ_ driver enabled (DrvDis = 0),
CQ_set to high impedance, pullup and
pulldown disabled (SinkSel_[1:0] = 00),
receiver enabled, VCC = 24V,
(VCC - 65V) < VCQ_ < 60V
-200
+500
μA
ICQ_LKG
CQ_ driver disabled (DrvDis = 1), pullup
and pulldown disabled (SinkSel_[1:0] =
00), receiver enabled, VCC = 24V,
(VCC - 65V) < VCQ_ < 60V
-100
+100
μA
CQ_ Push-Pull High
Impedance Current
ICQ_HiZ
CQ_ driver enabled (DrvDis = 0), CQ_in
push-pull, pullup and pulldown disabled
(SinkSel_[1:0] = 00), receiver enabled,
VCC = 24V, 0V < VCQ_ < 24V
-50
+50
μA
DI_ Current Sink
IDI_SNK
VDI_ > 5V, DiCSink = 1
2
2.5
3
mA
DI_ Current Source
IDI_SRC
VCC - VDI_ > 5V, DiCSource = 1
-3
-2.5
-2
mA
IDI
Pullup and pulldown disabled, DI_
receiver enabled, VCC = 24V,
-1V < VDI_ < (VCC + 1V)
-5
+50
μA
IDI_EXT
Pullup and pulldown disabled, DI_
receiver enabled, VCC = 24V,
(VCC - 65V) < VDI_ < 60V
-100
+100
μA
CQ_ Input Current
CQ_ Input Current, Extended
Range
CQ_ Leakage Current
DI_ Input Current
DI_ Input Current, Extended
Range
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Maxim Integrated │ 6
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DC Electrical Characteristics (continued)
(VCC = 9V to 36V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V, all logic inputs at VL or GND; TA = -40°C to +125°C, unless otherwise
noted. Typical values are at VCC = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.2 x VL
V
LOGIC INPUTS (CS, SDI, SCLK, A1, A0, TXENA, TXENB, TXA, TXB, CLKI)
Logic Input Voltage Low
VIL
Logic Input Voltage High
VIH
Logic Input Leakage Current
ILEAK
0.8 x VL
Logic input = GND or VL
V
-1
+1
µA
0.4
V
LOGIC OUTPUTS (SDO, IRQ, LIA, LIB, RXA, RXB, RXRDYA/LD1A, RXERRA/LD2A, RXRDYB/LD1B, RXERRB/LD2B, CLKO)
Logic Output Voltage Low
VOL
IOUT = -5mA
Logic Output Voltage High
VOH
RX_, LI_, SDO, and CLKO, IOUT = 5mA
Output Leakage Current
IOH
RXRDY_/LD1_, RXERR_/LD2_, IRQ,
output is high impedance, output is
pulled up to 5V
VL - 0.4
V
-1
+1
µA
CRYSTAL OSCILLATOR (XI, XO)
Crystal Oscillator Current
Supply
IV5_XTAL
fXTAL = 14.7456MHz, V5 supply current
increase versus external clocking
Crystal Equivalent Series
Resistance
ESRXTAL
fXTAL = 14.7456MHz (Note 2)
75
Ω
COXTAL
fXTAL = 14.7456MHz (Note 2)
8
pF
Crystal Shunt Capacitance
Input Capacitance
CIN
240
µA
XI
10
XO
10
(Notes 3, 4)
55
µA
3.686
MHz
pF
INTERNAL OSCILLATOR
Internal Oscillator Current
Consumption
IV5_OSC
EXTERNAL CLOCK INPUT (CLKI)
External Clock Frequency
fECLK
External Clock Detection
fECLK_DET
CLKI Capacitance
Minimum CLKI frequency for operation
0.5
CCLKI
2
2
MHz
pF
L+ SENSOR SUPPLIES WITH CURRENT LIMITING AND REVERSE BLOCKING (L+A, L+B)
Reverse Current Blocking
Threshold
VTH_RCB
G1_/G2_ Gate-to-Source
On-Voltage
VG_ON
VRCB = (VSN1_ -VCC)
VSN1_ > 18V
VSN1_ 14V
mV
VSN1_ 11V
V
G2_ Minimum Gate-to-Source
Voltage Under Regulation
VG2_REG
G1_ Gate Turn-Off Switch
Resistance
RG1_OFF
G1_ pulled to SN1_
50
Ω
G2_ Gate Turn-Off Switch
Resistance
RG2_OFF
G2_ pulled to SN2_
50
Ω
www.maximintegrated.com
VSN1_ 0.8V
160
V
Maxim Integrated │ 7
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DC Electrical Characteristics (continued)
(VCC = 9V to 36V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V, all logic inputs at VL or GND; TA = -40°C to +125°C, unless otherwise
noted. Typical values are at VCC = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
L+_ Current-Limit Threshold
PARAMETER
VCL_T
VCL_T = (VSN1_ - VSN2_), L+CL2X_ = 0
12.75
15
18.5
mV
L+_ Double Current-Limit
Threshold
VCL_2T
VCL_2T = (VSN1_ - VSN2_), L+CL2X_ = 1,
VCC = VSN1_ = 24V, VL+ _ > 18V
25.5
30
36
mV
SN1_ Supply Current
ISN1ACT
VL+ > 18V, L+En_ = 1, L+CL2X_ = 1
0.23
0.325
mA
+10
μA
20
μA
-50
+50
μA
MAX14819
16
18
MAX14819A
18
20
MAX14819
15.5
17.5
MAX14819A
17.5
19.5
SN2_ Input Current
L+_ Input Current
L+_ Extended Range Input
Current
ISN2
IL+
VSN2_ = VSN1_
VL+_ = 30V
IL+_EXT
VCC = VSN1_ = 24V, (VCC - 60V) < VL+_
< 60V
VTL+_R
L+_ rising
VTL+_F
L+_ falling
L+_ Power Good Threshold
L+_ Power Good Hysteresis
L+_ Dynamic Blanking
Threshold
-10
V
V
VTL+H
0.4
V
VLPDTHR
8.8
V
+135
°C
15
°C
THERMAL MANAGEMENT
Thermal-Warning Threshold
TWRN
Thermal-Warning Threshold
Hysteresis
TWRN_HYS
Die junction temperature rising,
TempW and TempWInt bits are set
Die junction temperature falling,
TempW bit cleared
CQ_ Thermal-Shutdown
Temperature
TSHUT
Driver temperature rising, temperature
at which the driver is turned off. ThShut
and ThuShutInt bits are set
+160
°C
Thermal-Shutdown
Temperature Hysteresis
TSHUT_HYS
Driver temperature falling. ThShut bit is
cleared
15
°C
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Maxim Integrated │ 8
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
AC Electrical Characteristics
(VCC = 18V to 30V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V; TA = -40°C to +125°C, unless otherwise noted. Typical values
are at VCC = 24V, V5 = 5V, VL = 3.3, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.45
0.90
UNITS
CQ_ DRIVER
Push-pull and PNP configuration, Figure 1
Driver Low-to-High Propagation
Delay
tPDLH
Driver High-to-Low Propagation
Delay
tPDHL
PNP configuration, Figure 1
(no capacitive load)
Driver Skew
tSKEW
|tPDLH - tPDHL|, Figure 1
Driver Rise Time
tRISE
Push-pull and PNP configuration, Figure 1
0.25
Driver Fall Time
tFALL
Push-pull and NPN configuration, Figure 1
0.25
Driver Enable Time High
tENH
Driver Enable Time Low
tENL
Driver Disable Time High
Driver Disable Time Low
NPN configuration, Figure 1
(no capacitive load)
μs
5
Push-pull and NPN configuration, Figure 1
0.43
0.90
μs
5
0.2
μs
0.42
0.75
μs
0.42
0.75
µs
Push-pull and PNP configuration, Figure 2
0.45
0.9
µs
Push-pull and NPN configuration, Figure 3
0.26
0.9
µs
tDISH
Push-pull and PNP configuration, Figure 2
1.9
3
µs
tDISL
Push-pull and NPN configuration, Figure 3
1.7
3
µs
MAX14819
0.28
0.5
MAX14819A
0.53
0.8
MAX14819
1.2
2
MAX14819A
1.5
2.3
MAX14819
0.25
0.5
MAX14819A
0.31
0.8
MAX14819
1.2
2
MAX14819A
1.3
2.3
CQ_ RECEIVER (Figure 4)
CQ_ Receiver Low-to-High
Propagation Delay
CQ_ Receiver High-to-Low
Propagation Delay
CQ_ Receiver Skew
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CQFilterEn_ = 0
tCPRLH
CQFilterEn_ = 1
CQFilterEn_ = 0
tCPRHL
CQFilterEn_ = 1
tCRSKEW
|tCPRLH tCPRHL|
(Note 3)
CQ
FilterEn_ = 0
MAX14819
0.1
MAX14819A
0.4
CQ
FilterEn_ = 1
MAX14819
0.1
MAX14819A
0.4
µs
µs
µs
µs
Maxim Integrated │ 9
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
AC Electrical Characteristics (continued)
(VCC = 18V to 30V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V; TA = -40°C to +125°C, unless otherwise noted. Typical values
are at VCC = 24V, V5 = 5V, VL = 3.3, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MAX14819
1.9
3
MAX14819A
1.3
3
MAX14819
2.9
4.2
MAX14819A
2.3
4.2
MAX14819
1.3
3
MAX14819A
1.0
3
MAX14819
2.3
4.2
MAX14819A
2.0
4.2
DiFilterEn_
=0
0.5
1
0.3
1
DiFilterEn_
=1
0.5
1
0.3
1
UNITS
DI_ RECEIVER (Figure 4)
DI_ Receiver Low-to-High
Propagation Delay
DI_ Receiver High-to-Low
Propagation Delay
DI_ Receiver Skew
DiFilterEn = 0
tDPRLH
DiFilterEn = 1
DiFilterEn = 0
tDPRHL
DiFilterEn = 1
tDRSKEW
|tDPRLH - tDPRHL|
µs
µs
µs
WAKE-UP PULSE
Delay Time to Wake-Up Pulse
tSU_WU
Wake-Up Pulse Duration
tWU
On-Time After Wake-Up
tON_WU
(Figure 9)
Wake-up (WU) pulse has the opposite
polarity of the CQ_ line before the WU pulse
was generated
80
75
80
µs
85
µs
Driver enabled with original polarity on
CQ_ line
2
µs
Delay between (VRCB rising > VTH_RCB)
and IGATE2_ turned off
10
μs
L+ CURRENT LIMITING
Reverse Current Blocking
Response Time
tRCB
Reverse Current Blocking
Threshold
VTH_RCB
Current-Limit Blanking Time
tL+CLBL
VRCB = (VSN1_ - VCC)
L+BL_[1:0] = 00
5
5.5
L+BL_[1:0] = 01
15
16.5
L+BL_[1:0] = 10
50
55
L+BL_[1:0] = 11
150
165
L+RT_[1:0] = 00, latched off
Current-Limit Retry Delay
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tL+CLRT
160
mV
ms
∞
L+RT_[1:0] = 01
0.5
L+RT_[1:0] = 10
4
L+RT_[1:0] = 11
10
s
Maxim Integrated │ 10
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
AC Electrical Characteristics (continued)
(VCC = 18V to 30V, V5 = 4.5V to 5.5V, VL = 1.62V to 5.5V, VGND = 0V; TA = -40°C to +125°C, unless otherwise noted. Typical values
are at VCC = 24V, V5 = 5V, VL = 3.3, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tCYCL
Actual cycle time relative to programmed
cycle time, using an external clock or crystal
with 100ppm accuracy
0
4
5
%
CYCLE TIMER
Cycle Time
SPI TIMING (CS, SCLK, SDI, SDO) (Figure 5)
1.6V ≤ VL < 2.5V
Maximum SPI Clock Frequency
SCLK Clock Period
VL ≥ 2.5V
tCH+CL
SCLK Pulse-Width High
tCH
SCLK Pulse-Width Low
tCL
CS Fall to SCLK Rise Time
tCSS
SDI Hold Time
tDH
SDI Setup Time
tDS
SDO Output Data Propagation
Delay
tDO
SDO Rise and Fall Times
tFT
Minimum CS Pulse High
tCSW
CS Hold Time
tCSH
15.6
1.6V ≤ VL < 2.5V
20
64
VL ≥ 2.5V
50
1.6V ≤ VL < 2.5V
32
VL ≥ 2.5V
25
1.6V ≤ VL < 2.5V
32
VL ≥ 2.5V
25
1.6V ≤ VL < 2.5V
10
VL ≥ 2.5V
7
1.6V ≤ VL < 2.5V
0
VL ≥ 2.5V
0
1.6V ≤ VL < 2.5V
25
VL ≥ 2.5V
23
MHz
ns
ns
ns
ns
ns
ns
1.6V ≤ VL < 2.5V
35
VL ≥ 2.5V
15
VL = 1.8V
1.4
VL ≥ 2.5V
0.7
1.6V ≤ VL < 2.5V
10
VL ≥ 2.5V
10
1.6V ≤ VL < 2.5V
32
VL ≥ 2.5V
25
ns
ns
ns
Note 1: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design.
Note 2: Includes stray capacitance or resistance. Required characteristic of the external crystal.
Note 3: Not production tested. Guaranteed by design.
Note 4: V5 supply current increases when the internal oscillator is selected.
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Maxim Integrated │ 11
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
VCC
TXEN_
TXEN_
MAX14819
MAX14819A
TX_
TX_
CQ_
3.3nF
GND
5kΩ
MAX14819
MAX14819A
5kΩ
3.3nF
GND
PUSH-PULL AND PNP MODE
CQ_
NPN MODE
(a) INVCQ_ = 0
VL
TXEN_
0V
VL
TX_
50%
50%
tPDHL
CQ_
0V
tPDLH
50%
90%
90%
10%
10%
tFALL
VCC
50%
0V
tRISE
(b) INVCQ_ = 1
VL
TXEN_
0V
VL
TX_
50%
50%
tPDHL
CQ_
0V
tPDLH
50%
90%
90%
10%
10%
tRISE
VCC
50%
0V
tFALL
Figure 1. C/Q Driver Propagation Delays and Rise/Fall Times
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Maxim Integrated │ 12
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
VCC
TXEN_
VL
TX_
MAX14819
MAX14819A
5kΩ
CQ_
3.3nF
GND
VL
TXEN_
0V
tDISH
tENL
VCC
CQ_
50%
10%
0V
Figure 2. C/Q Driver Enable Low and Disable High Timing with External Pullup Resistor (INVCQ_ = 0)
TXEN_
TX_
MAX14819
MAX14819A
CQ_
GND
3.3nF
5kΩ
VL
TXEN_
0V
tDISL
tENH
CQ_
50%
90%
VCC
0V
Figure 3. C/Q Driver Enable High and Disable Low Timing (INVCQ_ = 0)
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Maxim Integrated │ 13
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
TXEN_
CQ_
OR DI_
MAX14819
MAX14819A
GND
RX_
OR LI_
15pF
(a) INVCQ_ = 0
CQ_
OR DI_
VCC
50%
50%
0V
tPRHL
tPRLH
RX_
OR LI_
VL
50%
50%
0V
(a) INVCQ_ = 1
CQ_
OR DI_
50%
50%
0V
tPRHL
tPRLH
RX_
OR LI_
VCC
VL
50%
50%
0V
Figure 4. C/Q Receiver Propagation Delays
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Maxim Integrated │ 14
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CS
tCSS
tCSW
tCL
tCSH
tCH
SCLK
tDS
tDH
SDI
tDO
SDO
90%
90%
10%
10%
tFT
tFT
Figure 5. SPI Timing Diagram
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Maxim Integrated │ 15
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Typical Operating Characteristics
(VCC = 24V, VL = 3.3V, REGEN is unconnected, CQ_ is in push-pull configuration, TA = +25°C, unless otherwise noted.)
CQ_ ON-RESISTANCE vs
LOAD CURRENT
1.8
9
1.6
8
1.4
1.0
0.8
REGEN = OPEN
5
REGEN = GND,
V5 = EXTERNAL 5V
3
2
0.4
DRIVER IN PUSH PULL MODE
HIGHEST CURRENT LIMIT SETTING
0.2
0.0
6
4
LOW SIDE
0.6
0
100
200
300
400
500
1
0
600
0.1
1
V5 SUPPLY CURRENT vs
CQ_ DATARATE
2.0
toc03
-200
SOURCE CURRENT (mA)
1.4
I5 (mA)
1.2
1.0
0.8
REGEN = GND
CQA AND CQB ARE PUSH PULL
TXENA = TXENB
SQUARE WAVE ON TXA = TXB
NO LOAD ON CQA OR CQB
0.2
0.1
1
10
100
CL[1:0] = 10
-400
-500
CL[1:0] = 11
-600
-700
-800
1000
CQ_ IN PUSH PULL
CQ_ IS HIGH
0
5
CL[1:0] = 10
300
CL[1:0] = 01
200
CL[1:0] = 00
25
30
toc06
300
250
200
150
100
50
100
0
20
LED_ _ IS ENABLED
350
500
400
15
LED_ _ VOLTAGE vs
LED_ _ SINK CURRENT
400
LED_ _ VOLTAGE (mV)
SINK CURRENT (mA)
600
toc05
CQ_ IN PUSH PULL
CQ_ IS LOW
CL[1:0] = 11
10
CQ_ OUTPUT VOLTAGE (V)
CQ_ CURRENT LIMIT
(LOWSIDE)
700
toc04
CL[1:0] = 01
-300
CQ_ DATA RATE (kbps)
800
1000
CL[1:0] = 00
-100
1.6
0.4
100
CQ_ CURRENT LIMIT
(HIGH SIDE)
0
1.8
0.6
10
CQ_ DATA RATE (kbps)
LOAD CURRENT (mA)
0.0
toc02
CQA AND CQB ARE PUSH PULL
TXENA = TXENB
SQUARE WAVE ON TXA = TXB
NO LOAD ON CQA OR CQB
7
HIGH SIDE
1.2
VCC SUPPLYCURRENT vs
CQ_ DATARATE
10
ICC (mA)
ON-RESISTANCE (Ω)
2.0
toc01
0
5
10
15
20
CQ_ OUTPUT VOLTAGE (V)
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25
30
0
0
5
10
15
20
25
30
35
LED_ _ SINK CURRENT (mA)
40
Maxim Integrated │ 16
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Typical Operating Characteristics (continued)
(VCC = 24V, VL = 3.3V, REGEN is unconnected, CQ_ is in push-pull configuration, TA = +25°C, unless otherwise noted.)
VCC = 30V
L+CL2x_ = 1
L+EN_ = 1
165ms blanking time enabled
1mF capacitor on L+_
toc07
L+_
20V/div
0V
ILOAD
1A/div
(SN1_ - SN2_) THRESHOLD (mV)
L+_ SHORT CIRCUIT
RESPONSE TIME
0A
4ms/div
0
-2
G1_ OUTPUT VOLTAGE vs
TEMPERATURE
toc09
0
REFERENCED TO SN1_
L+_ ENABLED
-2
(VG2_-VSNS2_) (V)
-6
-8
-12
-12
18
-40 -25 -10 5
-14
20 35 50 65 80 95 110 125
TEMPERATURE (ºC)
L+_ INPUT CURRENT vs
TEMPERATURE
toc11
10
L+_ = 24V
8
16
6
14
4
12
2
10
8
G2_ OUTPUT VOLTAGE vs
TEMPERATURE
toc10
REFERENCED TO SN2_
L+_ ENABLED
-4
-6
2
-8
www.maximintegrated.com
20 35 50 65 80 95 110 125
TEMPERATURE (ºC)
20 35 50 65 80 95 110 125
TEMPERATURE (ºC)
SN2_ INPUT CURRENT vs
TEMPERATURE
toc12
L+En_ = 1
SN1_ = SN2_
0
4
-40 -25 -10 5
-40 -25 -10 5
-2
6
0
20 35 50 65 80 95 110 125
TEMPERATURE (ºC)
-8
-10
20
-40 -25 -10 5
-6
-10
-14
(SN1_ - SN2_) VOLTAGE vs
TEMPERATURE
toc08
-4
ISNS2_ (µA)
(VG1_ -VSNS1_) (V)
-4
IL+_ (µA)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
-10
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (ºC)
Maxim Integrated │ 17
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
G2B
SN2B
SN1B
VCC
G1B
LIB
RXB
TXENB
TXB
TXA
RXA
TOP VIEW
TXENA
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
LIA
37
24 L+B
A0
38
23 DIB
A1
39
22 N.C.
VL
40
21 N.C.
XI
41
20 CQB
MAX14819
MAX14819A
19 N.C.
XO
42
CLKI
43
CLKO
44
17 CQA
18 N.C.
SDI
45
16 N.C.
SDO
46
15 N.C.
SCLK
47
CS
48
+
14 DIA
6
7
IRQ
RXERRA/LD2A
RXRDYB/LD1B
RXERRB/LD2B
V5
REGEN
8
9
10 11 12
G2A
5
SN2A
4
SN1A
3
VCC
2
G1A
1
RXRDYA/LD1A
13 L+A
TQFN
(7mm x 7mm)
Pin Description
PIN
NAME
1
IRQ
2
RXRDYA/LD1A
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FUNCTION
REFERENCE
Open-drain Interrupt Output. Connect a pullup resistor to IRQ. IRQ asserts
whenever a bit that has been enabled in the InterruptEn register is set in the
Interrupt register. See the Register Description for more information.
GND
Channel A Configurable Open-Drain Receive Data Ready Output/LD1A Driver.
Set the RxRdyEnA bit to 1 in the LEDCtrl register to enable RXRDYA/LD1A as
an interrupt output. In this configuration, RXRDYA/LD1A asserts when the RxDataEnRdyA interrupt bit is set in the Interrupt register. Set the RxRdyA bit to 0
to configure RXRDYA/LD1A as an open-drain LED driver. When configured as
an LED driver, RXRDYA/LD1A is controlled by the LEDEn1A bit in the LEDCtrl
register. Connect a resistor in series to limit the LED current. See the Register
Description for more information.
GND
Maxim Integrated │ 18
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
REFERENCE
RXERRA/LD2A
Channel A Configurable Open-Drain Receive Error Output/LD2A Driver. Set
the RxErrEnA bit in the LEDCtrl register to enable RXERRA/LD2A as an
interrupt output. In this configuration, RXERRA/LD2A asserts when the
RxErrorA bit in the Interrupt register is set. Set the RxErrEnA bit to 0 to
configure RXERRA/LD2A as an open-drain LED driver. When configured as
a LED driver, RXERRA/LD2A is controlled by the LEDEn2A bit in the LEDCtrl
register. Connect a resistor in series to limit the LED current. See the Register
Description for more information.
GND
RXRDYB/LD1B
Channel B Configurable Open-Drain Receive Data Ready Output/LD1B Driver.
Set the RxRdyEnB bit to 1 in the LEDCtrl register to enable RXRDYB/LD1B
as an interrupt output. In this configuration, RXRDYB/LD1B asserts when the
RxDataRdyB interrupt bit is set in the Interrupt register. Set the RxRdyEnB bit to
0 to configure RXRDYB/LD1B as an open-drain LED driver. When configured as
an LED driver, RXRDYB/LD1B is controlled by the LEDEn1B bit in the LEDCtrl
register. Connect a resistor in series to limit the LED current. See the Register
Description for more information.
GND
RXERRB/LD2B
Channel B Configurable Open-Drain Receive Error Output/LD2B Driver. Set
the RxErrEnB bit in the LEDCtrl register to enable RXERRB/LD2B as an interrupt output. In this configuration, RXERRB/LD2B asserts when the RxErrorB bit
in the Interrupt register is set. Set the RxErrEnB bit to 0 to configure RXERRB/
LD2B as an open-drain LED driver. When configured as an LED driver, RXERRB/LD2B is controlled by the LEDEn2B bit in the LEDCtrl register. Connect a
resistor in series to limit the LED current. See the
Register Description for more information.
GND
6
V5
5V Supply Input/Linear Regulator Voltage Output. Connect a 1μF bypass
capacitor as close as possible to the IC. Apply an external 5V supply to V5 if the
internal 5V regulator is disabled (REGEN = GND). 5V must be present on V5 at
all times for normal operation.
GND
7
REGEN
5V Linear Regulator Enable Input. Leave REGEN unconnected to enable the
internal 5V regulator. Connect REGEN to GND to disable the internal 5V
regulator.
GND
8, 29
VCC
VCC Supply Input. Bypass VCC to GND with a 1μF capacitor as close as
possible to the device.
GND
9
G1A
Channel A Gate Drive Output 1. Connect G1A to the gate of the external
PMOS1A to control the external reverse-current-blocking transistor of sensor
supply A (L+A). Leave G1A unconnected if the external PMOS1A is not used.
SN1A
10
SN1A
Channel A Sense Input 1/PMOS1A Source Connection. Connect a currentlimiting resistor between SN1A and SN2A. Leave SN1A unconnected when the
channel A supply controller is not used.
GND
11
SN2A
Channel A Sense Input 2/PMOS2A Source Connection. Connect a currentlimiting resistor between SN1A and SN2A. Connect SN2A to SN1A when
current sensing is not used.
SN1A, GND
12
G2A
Channel A Gate Drive Output 2. Connect G2A to the gate of the external
PMOS2A for the channel A sensor supply (L+A). Leave G2A unconnected if the
external PMOS2A is not used.
SNA1, GND
3
4
5
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Maxim Integrated │ 19
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
REFERENCE
13
L+A
Channel A L+ Sensor Supply Monitoring Input. Connect L+A to the drain of the
external PMOS2A current-limiting transistor. Bypass L+A to GND with 0.47μF.
Connect a 100Ω resistor in series with L+A (see Typical Operating Circuit).
Connect L+A to GND or leave unconnected if not used.
14
DIA
Channel A Auxiliary Digital Input. Connect a 100Ω resistor in series with DIA
(see Typical Operating Circuit).
15, 16,
18 ,19,
21, 22
N.C.
No Connection. Not internally connected.
—
17
CQA
Channel A C/Q Transceiver Input/Output
VCC, GND
20
CQB
Channel B C/Q Transceiver Input/Output
VCC, GND
23
DIB
Channel B Auxiliary Digital Input. Connect a 100Ω resistor in series with DIB
(see Typical Operating Circuit).
GND
24
L+B
Channel B L+ Sensor Supply Monitoring Input. Connect L+B to the drain of the
external PMOS2B transistor to limit the load current sourced by the channel
B source supply. Bypass L+B to GND with 0.47μF. Connect a 100Ω resistor in
series with L+B (see Typical Operating Circuit). Connect L+B to VCC or GND, or
leave unconnected if not used.
GND
25
G2B
Channel B Gate Drive Output 2. Connect G2B to the gate of the external
PMOS2B for the channel B sensor supply (L+B). Leave G2B unconnected if the
external PMOS2B is not used.
SN1B
SN1B
GND
GND
26
SN2B
Channel B Sense Input 2/PMOS2B Drain Connection. Connect a currentlimiting resistor between SN1B and SN2B. Connect SN2B to SN1B or leave
unconnected when current sensing is not used.
27
SN1B
Channel B Sense Input 1/PMOS1B Source Connection. Connect a current-limiting resistor between SN1B and SN2B. Leave SN1B unconnected when supply
controller B is not used.
VCC
28
G1B
Channel B Gate Drive Output 1. Connect G1B to the gate of the external
PMOS1B to control the external reverse-current-blocking transistor of sensor
supply B (L+B). Leave G1B unconnected if the external PMOS1B is not used.
SN1B
30
LIB
Channel B Logic Output of the Digital Input (DIB). LIB is the logic inverse of the
signal on DIB.
VL, GND
31
RXB
Channel B Logic Output of the CQB Receiver. RXB is the logic inverse of the
signal on CQB (when InvCQB = 0).
VL, GND
32
TXENB
Channel B CQB Transmitter Output Enable. Drive TXENB high to enable the
CQB driver. Drive TXENB low at power-up.
VL, GND
33
TXB
Channel B CQB Transmitter Logic Input. CQB is the logic inverse of the signal
on TXB (when InvCQB = 0 ).
VL, GND
34
TXA
Channel A CQA Transmitter Logic Input. CQA is the logic inverse of the signal
on TXA (when InvCQA = 0).
VL, GND
35
TXENA
Channel A CQA Transmitter Output Enable. Drive TXENA high to enable the
CQA driver. Drive TXENA low at power-up.
VL, GND
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Maxim Integrated │ 20
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Pin Description (continued)
PIN
NAME
36
RXA
Channel A Logic Output of the CQA Receiver. RXA is the logic inverse of the
signal on CQA (when InvCQA = 0).
VL, GND
37
LIA
Channel A Logic Output of the Digital Input (DIA). LIA is the logic inverse of the
signal on DIA.
VL, GND
A0
SPI Chip Address Input A0. The MAX14819/MAX14819A is designed to allow
up to 4 transceivers on the SPI at one time with a shared CS signal. Connect A1
and A0 high or low to set the individual IC SPI address. Do not leave A0
unconnected.
VL, GND
39
A1
SPI Chip Address Input A1. The MAX14819/MAX14819A is designed to allow
up to 4 transceivers on the SPI at one time with a shared CS signal.
Connect A1 and A0 high or low to set the individual IC SPI address.
Do not leave A1 unconnected.
VL, GND
40
VL
Logic Level Supply Input. VL sets the logic level of all logic inputs and outputs
(TXEN_, TX_, RX_, LI_, and the SPI interface). Bypass VL to GND with a 0.1μF
capacitor as close as possible to the device.
GND
41
XI
Crystal Oscillator Input for Internal Framer Operation. Connect a crystal between XI and XO to use crystal clocking. Leave XI unconnected if crystal clocking is not used.
V5, GND
42
XO
Crystal Oscillator Output for Internal Framer Operation. Connect a crystal
between XI and XO to use crystal clocking. Leave XO unconnected if crystal
clocking is not used.
V5, GND
43
CLKI
Logic Clock Input for Internal Framer Operation. When not using a crystal for
framer operation, connect a 3.686MHz clock signal to CLKI. Connect CLKI to
GND when not used.
V5, GND
44
CLKO
Logic Clock Output for Internal Framer Operation. CLKO outputs a 3.686MHz
clock signal when enabled (ClkOEn = 1). When using multiple MAX14819/
MAX14819A ICs on a board, these can be clocked with a single crystal by
connecting the CLKO output of one device to the CLKI inputs of the other(s).
V5, GND
45
SDI
SPI Data Input. Connect SDI to the MOSI output of the microcontroller.
V5, GND
46
SDO
SPI Data Output. Connect SDO to the MISO input of the microcontroller.
V5, GND
47
SCLK
SPI Clock Input. Connect SCLK to the CLK output of the microcontroller.
V5, GND
48
CS
SPI Chip-Select Input. The SPI cycle begins when CS is driven low and ends
when CS is driven high. Up to 4 MAX14819/MAX14819A ICs can share a single
SPI bus and CS input using the A1 and A0 address inputs.
V5, GND
EP
―
38
www.maximintegrated.com
FUNCTION
Exposed Pad. Connect to GND.
REFERENCE
GND
Maxim Integrated │ 21
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Detailed Description
5V Linear Regulator
The MAX14819/MAX14819A low-power dual-channel
industrial IO-Link master transceiver is fully compliant
with the latest SDCI/ IO-Link standards and test specifications. The MAX14819/MAX14819A features two integrated framers but can alternatively operate with external
UARTs.
The MAX14819/MAX14819A includes an integrated regulator to generate 5V (V5). To enable the internal regulator,
leave REGEN unconnected and connect a 1μF bypass
capacitor between V5 and ground as close as possible to
the device. The internal V5 regulator is capable of driving
external loads up to 20mA.
The MAX14819/MAX14819A features a high-speed SPI
interface for system-side data and control interfacing.
Integrated IO-Link message frame handlers and FIFOs
simplify time critical control and cycle time management of all IO-Link M-sequence communication, easing
data link layer control. Autonomous cycle timers also
reduce the need for accurate controller timing. Integrated
establish-communication sequencers simplify wake-up
management.
When the internal 5V linear regulator is not used, V5 is the
supply input for the internal analog and digital functions and
must be supplied externally. Connect REGEN to ground to
disable the internal regulator when applying an external 5V
to V5. Ensure that V5 is present for normal operation.
The MAX14819/MAX14819A further includes two sensor supply controllers (L+A, L+B) with current limiting
and reverse current blocking. The current limit is set with
external sense resistors.
POWER
Power-Up
The CQ_ driver outputs are high impedance when the
VCC supply, V5, and VL voltages are below their respective undervoltage thresholds during power-up.
The drivers are automatically disabled when the VCC
voltage falls below the 9V (typ) UVLO threshold. The SPI
interface remains active while V5 and VL are present.
VCC Low Voltage and Undervoltage Detection
The MAX14819/MAX14819A monitors the VCC supply
for low-voltage and undervoltage conditions. Low-voltage
warnings are reported in the Status register and can be
configured to generate an interrupt on the IRQ output.
When VCC falls below the 18V (max) low-voltage warning threshold, the VCCWarn and VCCWarnCOR bits in
the Status register are set. If VCCWarnCOR in the Clock
register is set, a StatusInt interrupt is generated and IRQ
asserts.
When VCC falls below the 9V (max) undervoltage-lockout
(UVLO) threshold, the VCCUV and VCCUVCOR bits in the
Status register are set. A StatusInt interrupt is generated
and IRQ asserts.
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An internal undervoltage lockout comparator detects
when the V5 voltage falls below the 3.5V (typ) V5_UVLO
threshold. When the V5 voltage drops below this level,
the device is under reset: SPI registers are reset to their
power-up state, the CQ_ outputs and L+_ supplies are
disabled, internal pullups/pulldowns are turned off, the
CQ_ and DI_ receivers are disabled, and the LED outputs
are high impedance. When the V5 voltage rises above the
UVLO threshold, the MAX14819/MAX14819A restarts in
the default power-on configuration.
The internal V5 regulator output is not protected against
short circuits.
Logic Supply (VL)
The VL input is the logic-level supply for all the digital I/
Os. Apply a voltage between 1.62V and 5.5V to VL for
normal operation.
Internal UVLO circuitry monitors the VL supply. If VL falls
below the 0.7V (typ) VL UVLO threshold, all the digital
I/Os referred to VL are ignored and either set to high
impedance or are low.
L+ Sensor Supply Controllers
The MAX14819/MAX14819A includes one sensor/actuator
supply controller for each IO-Link channel, L+A and L+B.
Each sensor supply is configurable through the SPI interface and must be enabled by setting the L+En_ bit in the
L+Cnfg_ register. Using external pMOS transistors, these
controllers provide active current limiting, reverse current
blocking, and undervoltage detection. The 24V VCC field
supply input is tolerant to reverse voltage and the L+A/L+B
output is negative voltage capable down to VCC - 60V.
Maxim Integrated │ 22
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Setting the L+_ Current Limit
CQ_ Current Limit and Thermal Protection
The L+_ sensor supply current is limited by placing a
sense resistor between the SN1_ and SN2_ currentsense inputs. When the voltage across the resistor
reaches the VCL_T (15mV, typ) threshold, the gate of the
pMOS (G2_) is actively controlled to limit the load current
such that:
The MAX14819/MAX14819A features a selectable current
limit for both CQ_ drivers ranging from 100mA to 500mA.
Set the CL[1:0] bits in the DrvrCurrLim register to select the
current limit for the drivers.
ILIM = VCL_T/RSENSE
If the L+_ voltage is pulled below ground (< -3V), the
current limit is reduced to about 10% of normal value to
reduce the power dissipated in the external pMOS.
L+_ Blanking Time and Autoretry Functionality
The L+_ controllers have programmable variables (set in
the L+Cnfg_ registers) that allow the system to optimize
turn-on and charging large loads while protecting the
pMOS FETs in cases of shorts and challenging load conditions.
If the load current is in current limiting for a period exceeding the set blanking time, the gate drive (G2_) is turned
off. The sensor supply is then either turned off until the
controller reenables it, or is turned on again following the
autoretry delay.
To further reduce the power dissipated in the pMOS transistors during turn-on of loads that require large inrush
currents (e.g., capacitive loads), the current limiter includes
a dynamic blanking time mode that reduces the blanking
time when the voltage across the pMOS is high, limiting
the pulse energy during the initial turn-on phase. Dynamic
blanking time mode is operational when the L+_ output
voltage is below 18V and must be enabled by setting the
L+DynBl_ bit in the L+Cnfg_ register.
The MAX14819/MAX14819A current-limit circuitry also
includes the option to double the L+_ load current when the L+_
supply voltage is above 18V. This functionality is enabled by
setting the L+CL2x_ bit in the L+Cnfg_ register.
Bypassing the L+_ Sensor Supplies
When the internal L+_ supply controllers are not used,
leave all the associated pins (G1_, G2_, SN1_, SN2_,
L+_) unconnected. L+_ can also be connected to GND.
CQ_ Transceivers
The CQA and CQB drivers are independently configurable as push-pull, NPN, PNP mode outputs in the
SPI registers. Set the bits in the CQCfgA and CQCfgB
registers to configure the drivers, enable or disable
internal pullup and pulldown current sources on the CQ_
I/Os, and to set the digital input thresholds. The CQ_
drivers can also be enabled/disabled in these registers.
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The CQ_ drivers are independently thermally protected.
If one output driver temperature rises above the 160°C
threshold, that output is disabled until the temperature
drops below 145°C.
CQ_ Driver Fault Detection
The MAX14819/MAX14819A senses a fault condition
on the CQ_ driver when an overcurrent event exists
for longer than the blanking time. Both the current limit
and blanking time can be configured in the DrvrCurrLim
register.
When a short-circuit fault occurs on CQ_, the CQFault_
and CQFaultCOR_ bits in the ChanStat_ register are set
and can trigger an interrupt.
When an overcurrent event occurs on CQ_, the driver can
either be set to continue supplying the selected current
until the device enters thermal shutdown (autoretry is disabled), or to enter autoretry mode. In autoretry mode, the
driver is automatically disabled after the current blanking
time and is then reenabled.
CQ_ Reverse-Polarity Protection
The CQ_ outputs are protected against reverse polarity
vs. ground. If CQ_ is connected to a negative voltage,
the driver is automatically disabled and CQ_ is set to high
impedance.
When CQ_ is shorted to a voltage above VCC, the driver
is automatically disabled and the output is set to high
impedance.
During a reverse condition, positive or negative, when no
fault is detected on CQ_ but the internal diode begins to
overheat, the L+_ supply is immediately disabled (turning
off the external transistors) to protect the device.
Reverse conditions do not generate a fault or interrupt.
CQ_ Current Sources/Sinks
The MAX14819/MAX14819A features programmable
internal 2.5mA/5.8mA pullup/pulldown current sources
on the CQ_ receivers. Select the pullup/pulldown current
for each CQ_ I/O by setting the SinkSel_[1:0] bits in the
CQCfg_ register. The internal pullup/pulldown currents
are automatically disabled when the CQ_ output is driven
(i.e., push-pull not in high-impedance state, NPN mode is
set low, or NPN mode is set high).
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MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQ_ Receiver Output (RXA/RXB)
RX_ is the output of the CQ_ receiver. By default, the RX_
output is the inverse logic of the CQ_ input. Setting the
InvCQ_ bit in the MsgCtrl_ register inverts CQ_ so that
the RX_ output is the same logic of the CQ_ input. RX_
cannot be disabled/three-stated.
CQ_ Receiver Threshold
The CQ_ receiver thresholds are compliant with the
IO-Link standard by default. The receiver thresholds are
also configurable to be compatible with the IEC 61131-2
type 1 and type 2/3 digital inputs. Set the IEC3Th_ bit
in the CQCfg_ register to select the input thresholds for
each receiver.
CQ_ Receiver Deglitch
The CQ_ receivers feature a selectable glitch filter
for improved noise immunity. Enable/disable this filter
by setting the CQFilterEn_ bit in the CQCfg_ register.
Transients longer than 1.3µs (typ) are ignored when the
glitch filter is enabled.
DI_ Receiver
The MAX14819/MAX14819A includes two auxiliary digital
inputs: DIA and DIB. These inputs are protected against
reverse polarity (referred to VCC and/or GND).
DI_ inputs are configurable in the IOStCfg_ registers. Set
the DiCSource__ bit to enable the internal 2.4mA source
on the DI_ input. Set the DiCSink_ bit to enable the 2.4mA
sink on the input.
Each DI_ input also features a selectable glitch filter for
improved noise immunity. Transients longer than 1.3µs
(typ) are ignored when the glitch filter is enabled. Set the
DiFilterEn_ bit to enable or disable this filter. When the
glitch filter is enabled, signal pulses less than 1μs are
ignored on the DI_ input.
The DI_ receiver thresholds are configurable to be
compatible with the IEC 61131-2 type 1, and type 2/3
digital inputs. Set the DiEC3Th_ bit in the IOStCfg_ register
to select the input thresholds for each receiver.
SPI Interface
The MAX14819/MAX14819A is connected to a microcontroller or SPI-host through an SPI-compatible serial interface. The interface has three inputs: clock (SCLK), chip
select (CS), and data in (SDI), and one output, data out
(SDO). SDO is high impedance when CS is high, allowing
multiple SPI slave devices to share a common bus. The
SPI is not daisy-chainable. The maximum SPI clock rate
is 20MHz when VL > 2.5V.
The SPI interface logic complies with SPI clock
polarity (CPOL = 0) and clock phase (CPHA = 0). The SPI
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interface supports both byte-by-byte cycle and burst
mode read and write.
In both read and write cycles, the SDO signals the IRQ
status, as well as the receive-data-ready and receive-dataerror for both receivers A and B (Figure 6 and Figure 7).
The SPI interface is not available when the VL voltage
is below the 0.7V (typ) VL UVLO threshold or when 5V
is not present on V5. The SPI registers are reset to their
default state when the V5 voltage falls below the 3.5V V5
UVLO threshold.
SPI Chip Address (A1, A0)
The MAX14819/MAx14819A is designed to allow up to four
master transceivers on a single bus with a single/shared CS.
This is accomplished using SPI-addressable devices with
logic address inputs A1 and A0. See Table 1. Do not leave
the A1 or A0 address input unconnected. Each chip on the
SPI bus should be assigned an individual chip address.
The MAX14819/MAX14819A monitors the SPI address in
each read/write cycle and responds when the SPI address
matches the pin-programmed address for that IC.
SPI trigger commands are global and are not filtered by the
chip address. All MAX14819/MAX14819A devices connected to the SPI bus will react to a received trigger command.
SPI In-Band IRQ Interrupt
The addressed MAX14819/MAX14819A sends out an
IRQ bit on SDO in every SPI cycle (both in single cycle as
well as burst mode), beginning on the third SPI clock. This
bit is equivalent to the IRQ interrupt output pin logic, but
inverted (active high). The IRQ bit is set when the IRQ pin
is asserted. Similarly, when the IRQ output is high impedance, the IRQ bit is 0. See Figure 6 and Figure 7.
The IRQ bit cannot be masked.
SPI In-Band Device-Message-Ready Signaling
In addition to sending IRQ status, the addressed
MAX14819/MAX14819A can be enabled to also send out
2 bits per channel in every SPI cycle that provide information, whether the IO-Link device answer message was
received correctly (RRDY_) or in error (RERR_) (Figure 6
and Figure 7). Set the RMessgRdy_ bits in the MesgCrtl_
register to enable this functionality.
Table 1. SPI MAX14819/MAX14819A Chip
Address Select
A1
A0
DEVICE ADDRESS
LOW
LOW
00
LOW
HIGH
01
HIGH
LOW
10
HIGH
HIGH
11
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MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CS
SCLK
SDI
W
A1
A0
SDO
R4
R3
R2
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
0
A1
A0
R4
R3
R2
R1
R0
IRQ RERRB RRDYB RERRA RRDYA D7
D6
D5
D4
IRQ RERRB RRDYB RERRA RRDYA
A_ = Chip Address
R_ = Register Address
D_ = Data Bit
IRQ = IRQ Bit
RRDY_ = Receive Data Ready Interrupt
RERR_ = Receive Data Error Interrupt
= Clock Edge upon which SDI data is latched
= Clock Edge upon which SDO is generated
Figure 6. SPI Byte-by-Byte Write Cycle
CS
SCLK
SDI
R
SDO
A1
A0
R4
R3
R2
R1
R0
D3
D2
D1
D0
A_ = Chip Address
R_ = Register Address
D_ = Data Bit
IRQ = IRQ Bit
RRDY_ = Receive Data Ready Interrupt
RERR_ = Receive Data Error Interrupt
= Clock Edge upon which SDI data is latched
= Clock Edge upon which SDO is generated
Figure 7. SPI Byte-by-Byte Read Cycle
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Maxim Integrated │ 25
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
The RRDY_ bits are equivalent to the DtaRdy_ hardware
outputs. Similarly, the RERR_ bits are the equivalent to
the RxErr_ hardware outputs. The SDO bit logic is the
inverse of the pin logic: when the pin output is low, the
associated bit is set to 1, and when the pin output is high,
the associated bit is 0.
The SPI clock must continue clocking throughout the
burst access cycle. Only the initial register address is
sent, followed by multiple bytes of data. The burst cycle
ends when the SPI master pulls CS high. See Figure 8.
When performing a burst read or write of/to the TxRxData_
registers, the register address remains the same, allowing
fast loading of a master message into the TxFIFO_ and
reading of the device message out of the RxFIFO_.
The RRDY_ bits and the RXRDY_ pins are cleared automatically when the device message is read out of the
RxFIFO_.
When burst reading or writing of registers having a
higher address than the TxRxData_ registers, the register
address is automatically incremented, allowing reading
and writing of a consecutive register block by only defining the initial register address in the SPI command byte.
SPI Burst Access
Burst access allows SPI reading/writing of two or more
bytes in a single SPI cycle. The chip-select input (CS)
must be held low during the entire burst write/read cycle.
IC AND
REGISTER ADDRESS
SPI BURST WRITE
CS
SDI
COMND
SDO
Data0
Data1
Data2
Data3
Data(N-1)
DataN
COMND
Data1
Data2
Data(N-2)
Data(N-1)
Data(N-1)
DataN
SPI BURST READ
CS
SDI
COMND
SDO
Data0
Data1
IC AND
REGISTER ADDRESS
Data2
Data3
SPI BYTE-BY-BYTE WRITE
CS
SDI
COMND
SDO
Data0
Data1
COMND
COMND
Data0
Data2
COMND
COMND
Data0
Data3
COMND
SPI BYTE-BY-BYTE READ
CS
SDI
COMND
SDO
Data0
COMND
Data1
Data0
COMND
Data2
Data0
Data3
Figure 8. SPI Burst Read/Write and Byte-by-Byte Read/Write Overview
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Maxim Integrated │ 26
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Wake-Up Pulse Generation
The MAX14819/MAX14819A can automatically generate
a wake-up pulse to initiate IO-Link communication. Set
the CQ_ driver into receive mode (TXEN = low or TxEn_
= 0), and drive TX_ low or set the Tx_ bit to 0 before the
wake-up sequence begins. Set the WuPuls_ bit to begin
the wake-up sequence. When the WuPuls_ bit is set, the
MAX14819/MAX14819A samples the CQ_ voltage level
and then automatically enables the CQ_ driver. A 500mA
current pulse of opposite polarity is applied to the CQ_ line
for 80μs (typ). During the wake-up pulse, the CQ_ current
limit is temporarily set above 500mA internally, although
the CL_ register bits are not changed. The driver remains
enabled, the line returns to the original polarity, and after a
100μs (typ) delay the MAX14819/MAX14819A CQ_ driver
is set to high impedance (Figure 9). The WuPuls_ bit is
automatically cleared after the tON_WU delay.
Microcontroller Data Interface
The MAX14819/MAX14819A offers two interface options
for IO-Link communication. When used as a transceiver,
external UARTs are required in the microcontroller and
these are interfaced to the TX_, RX_ and TXEN_ pins.
If the IO-Link framers in the MAX14819/MAX14819A are
used, then the SPI is used for interfacing to the microcontroller.
Framer Communication
The MAX14819/MAX14819A includes two independent
IO-Link framers with UARTs, one for each CQ_ channel. Each
framer operates in a Master-message (TX)/Device-message
WuPuls_ Bit
0
(RX) doublet, verifying communication timing and data
transmitted/received. After a channel has completed transmission of a master message, the framer is
automatically switched into receive mode. When the
expected number of bytes has been received, the framer
automatically exits from receive mode and any further
received data is ignored.
Shortly before, during, and after the frame handler sends
and receives messages, its transmitter must be disabled.
Disable the transmitter by either driving the associated
TXEN_ pin low, or by setting the TXTXENDis bit to 1. Note
that the TXTXENDis bit is global and acts on both channels.
UART Framing
The UART frame is made up of one start bit, 8 data bits
with 1 even parity bit and 1 STOP bit. When transmitting,
the idle time between the STOP bit and the following
START bit is less than 1 bit interval.
Frame Handler FIFOs (TxRxFIFOA/TxRxFIFOB)
Each IO-Link channel on the MAX14819/MAX14819A
(CQA and CQB) has a transmit and receive FIFO for
buffering the IO-Link M-sequence messages that are
sent and received. These FIFOs have a depth (66 bytes)
to buffer the largest M-sequence, Type 2.V, in addition to
the two length bytes.
Transmit/Receive FIFO Data Structure
To ensure proper communication, the message from the
SPI master to the TxFIFO_ must follow the sequence
shown in Figure 10.
1
WAKE-UP PULSE
tWU
CQ_ VOLTAGE
tSU_WU
tON_WU
Figure 9. Wake-Up Timing
SDI
RxBytes
TxBytes
TxData-1
(MC)
TxData-2
(CKT)
TxData-n
Figure 10. Transmit SPI Data Write Sequence
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Maxim Integrated │ 27
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
RxBytes is the number of octets the IO-Link device
is expected to reply with after it receives this master
message. TxBytes is the number of bytes that the master will send to the device in this message (the master
message length).
The IO-Link device answers with the device message,
which is stored in the RxFIFO_. When the RxFIFO_ on the
MAX14819/MAX14819A is read, the data is formatted as
shown in Figure 11. RxBytesAct is the actual number of
bytes received from the device and available for readout
from the RxFIFO_. This may differ from the expected number of receive bytes (RxBytes).
Loading the Transmit FIFO (TxFIFO_)
The master message is loaded into the transmit
FIFO (TxFIFO_) through the SPI interface. The SPI
master needs to send three pieces of information to the
TxRxData_ register for a complete master message
(Figure 12):
1) A byte describing the expected number of bytes of
the IO-Link device reply message. This is RxBytes.
2) A byte describing the number of bytes in the master
message (the length that will be transmitted). This is
TxBytes.
3) The data for the master message.
The TxBytes byte signals the number of octets in the
master message and the RxBytes indicates the number of octets expected from the device in the response
message.
SDO
Set the TSizeEn_ bit in the MsgCtrl_ register to compare
the TxBytes information to the number of octets loaded
in the TxFIFO_ and verify that the full message has been
received by the SPI master. The TSizeEn_ functionality
can be used either for byte-by-byte FIFO loading or for
burst loading. When a size error is detected, a TSizeErr_
interrupt is generated.
The TxFIFO_ can be written to using byte-by-byte write
or a burst write. When loading the TxFIFO_ with byteby-byte writing, the CQ_ transmission can be started
before the complete master message is loaded into the
TxFIFO_ (transmission and TxFIFO_ loading can be
done in parallel). In this case, the SPI controller must set
the InsChks bit in the MsgCtrl_ register to 0 and include
the 6-bit checksum in the master message CKT octet,
since the MAX14819/MAX14819A cannot calculate it. The
MAX14819/MAX14819A can only generate a TChkSmEr_
interrupt after the whole message is loaded into the
TxFIFO_; if transmission is started before the full message was loaded, it is possible that the IO-Link device will
receive a message with a checksum in error.
When transmission starts after the TxFIFO_ is completely loaded, the MAX14819/MAX14819A can calculate
and insert the checksum (when InsChk_= 1) into the
CKT octet. Alternatively, the SPI master can insert the
checksum in the master message and the MAX14819/
MAX14819A will verify the data (SPIChks_ = 1). If a
checksum error is detected, a TChksmEr_ interrupt is
generated and the MAX14819/MAX14819A does one of
RxByte-1
RxBytesAct
RxBytes-m
(CKS)
RxByte-2
Figure 11. Receive SPI Data Read Sequence
MASTER
MESSAGE
DEVICE
RESPONSE
UART
FRAME
UART
FRAME
t1
UART
FRAME
t1
UART
FRAME
UART
FRAME
tA
t2
UART
FRAME
t2
tM-sequence
Figure 12. Message Timing
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Maxim Integrated │ 28
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
two things, depending on the state of the TxErDestroy_ bit
in the MsgCtrl_ register:
●● If TxErDestroy = 1: The MAX14819/MAX14819A will
not send the message, so the SPI master must reload
the message into the TxFIFO_ in time for the cycle
time.
●● If TxErDestroy = 0: The MAX14819/MAX14819A
sends the message with the error.
Initiating Transmission
Transmission on CQ_ is initiated either by setting the
CQSend_ bit in the CQCtrl_ register or by using a trigger
command (see the TrigAssgn_ register for more information). Transmission can also be initiated cyclically when
the internal cycle time is enabled (CyclTmrEn_=1).
When SPI burst write mode is used, transmission
must be initiated after the TxFIFO_ is loaded or the
MAX14819/MAX14819A generates a cycle error interrupt
(TCycleErr_ = 1).
When using byte-by-byte SPI write mode, transmission
can be initiated before the complete master message is
loaded. When using this mode, ensure that the TxFIFO_
always has at least 1 data byte stored in it to avoid any
idle time or errors. The TxFIFO_ transmission is halted
and the CQ_ transceiver is configured to receive mode as
soon as the TxFIFO_ is empty.
During transmission, the CQ_ transmitter is set to pushpull mode. CQ_ is restored to the previous state when
transmission is complete.
Transmit Loopback Check
The internal framers automatically verify transmitted
data through a loopback check. During transmission, the
signal at CQ_ is automatically routed to the receiver and the
message sent is checked against the data sent out. If
inconsistencies are detected (e.g., when a CQ_ line is
shorted), the TransmErr_ bit is set and a TxError_ interrupt
can be generated.
Receiving the Device Message
When the MAX14819/MAX14819A completes transmission of the master message to the IO-Link
device, the CQ_ transmitter is set to receive mode
within 3μs (typ) and the master waits for the device
reply message. The MAX14819/MAX14819A waits for
9 to 24 bit times (set by the DDelay_ bits in the DeviceDly_
register) for a valid START from the device.
From the RxBytes data in the master message, the
MAX14819/MAX14819A already knows the number of
bytes expected to be returned from the device. If the number
of bytes received is not the expected number, a RSizeErr_
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interrupt is generated. The receiver stops reception when
the number of received bytes equals the value in RxBytes
and any further data sent from the device is ignored.
Reception is also terminated when less bytes are received
than expected. The MAX14819/MAX14819A determines
this to be the case when no START bit occurs within 2 to
5 bit times (as set in the BDelay_ bits in the DeviceDly_
register) after the last character’s STOP bit.
When the device message is received successfully (without any errors), an RxDataRdy_ interrupt is
signaled to the host SPI controller by asserting the IRQ pin
(if (RDaRdyIntEn = 1) and/or by asserting the RXRDY_/
LD1_ pin when the received data (device message) is
ready for readout from the RxFIFO_. The host controller
can read out the message from the RxFIFO_ in byte-bybyte mode or in a single-burst SPI cycle. The IRQ and/or
RXRDY/LD1_ interrupts are automatically cleared when
the first byte of the message is read out of the RxFIFO_, or
alternatively, by reading the Interrupt register.
If the device message is not received successfully (i.e.,
received with an error), an RxError_ interrupt is signaled to
the host controller by asserting the IRQ pin (if RxErrIntEn_
= 1) and/or by asserting the RXERR_/LD2_ pin. Detected
errors in the received data can include checksum, parity,
UART framing, or size deviations. The RxError_ interrupt is
cleared only when the Interrupt register is read.
Monitoring Message Timing
The IO-Link standard requires that the device reply
message must be fully received within a time of
tM-sequence after the start of the communication cycle:
tM-sequence = (m+n) x 11 x TBIT + tA
+ (m-1) x t1 + (n-1) x t2
where m is the number of octets in the master message,
n is the number of octets in the device message, TBIT is
the bit time at the present COM data rate, tA (max) is 10
bits, t1 is a maximum of 1 bit, and t2 is a maximum of 3
bits (Figure 12).
The MAX14819/MAX14819A can be set to generate an
error if the device message is not completely received in
the expected tM-sequence window. Set the RspnsTmrEn_
bit in the DeviceDly_ register to enable the internal message timing monitor.
While the IO-Link standard specifies tM-sequence as the
longest allowable delay, actual IO-Link devices may
exhibit longer delays (e.g., a longer delay can occur
when tA exceeds more than 10 x TBIT). The MAX14819/
MAX14819A can be set to allow for these tolerances. Set
the BDelay_[1:0] and DDelay_[3:0] bits in the DeviceDly_
register to add additional delay. For IO-Link compliance, set
BDelay_[1:0] = 01b and DDelay_[3:0] = 0001b. If a device
Maxim Integrated │ 29
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
message is not received or not completely received in this
time, the RxErr_ interrupt is signaled.
Response Time Checking (MAX14819A Only)
When the RspnsTmrEn bit is 0 (RspnsTmrEn = 0), the
MAX14819A does not check the message response delay
(TA) cycle time. This response time checking is not done
whether the cycle timer is enabled or disabled. When
RspnsTmrEn = 0, the receive FIFO waits for a device to
answer the message with no time limit on the response. If
the IO-Link device does not reply, the MAX14819A does
not send a new message after the cycle timer expires (if
the cycle timer is enabled). When this occurs, the SPI master must reset the RxFIFO by setting the RxFIFORst bit
(RxFIFORst = 1). Setting RxFIFORst = 1 puts the receiver
in idle mode and resumes normal cyclic operation.
Checksum Calculation and Checking
The MAX14819/MAX14819A can perform standard
IO-Link 6-bit checksum calculation and checksum verification. This can be used to generate the master message
checksum automatically, to check the integrity of the master message from the SPI master to the TxFIFO_, and to
check the received device message.
Set the InsChks_ bit in the MsgCtrl_ register to enable
master-message checksum generation. When enabled,
the checksum bits from the SPI master are ignored and the
MAX14819/MAX14819A inserts the calculated checksum
bits into the CKT octet before transmission. The master
message must be completely loaded into the TxFIFO_
before transmission for the MAX14819/MAX14819A to
insert the calculated checksum into the message.
Set the SPIChks_ bit in the MsgCtrl_ register to enable
the MAX14819/MAX14819A to verify the current checksum in the CKT octet in the TxFIFO_ with the calculated master-message checksum. If a difference is
detected, a TChksmEr_ interrupt is generated. When the
TxErDestroy_ bit in the MsgCtrl_ register is set, the master message is deleted in the TxFIFO_ and is not sent to
the IO-Link device. In SPI byte-by-byte write mode, the
master message is deleted only if the complete master
message has been loaded into the TxFIFO before transmission is initiated.
Establish-Communication Sequencer
The MAX14819/MAX14819A features an integrated
IO-Link establish-communication sequencer to autonomously perform the IO-Link establish-communication
wake-up sequence. The wake-up sequence is the prerequisite for placing the device in IO-Link pre-operate and
operate modes. Set the EstCom_ bit in the CQCtrl_ register to begin the autonomous establish-communication
sequencer.
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When the EstCom_ bit is set, the MAX14819/MAX14819A
generates an 80μs (typ) wake-up pulse on the CQ_ line
and then autonomously determines the COM rate and
minimum cycle time of the attached IO-Link device. During
this time, the microcontroller should not initiate driver activity on the CQ_ interface until the establish communication
sequence is complete. Once the sequence is successfully
completed, the COM rate of the IO-Link device is stored
in the ComRt_ bits of the CQCtrl_ register. Similarly , the
minimum cycle time of the device is stored in the CyclTmr_
register.
If the first establish-communication sequence fails, the
MAX14819/MAX14819A repeats the sequence again
after a 30ms delay. If the sequence fails again, a third
attempt is made. If the third attempt fails, the MAX14819/
MAX14819A stops attempting to establish communication
with the device and a WURQInt interrupt is generated, the
EstCom_ bit is reset, and the CQ_ driver is returned to
SIO mode after 300ms (max). A new establish-communication sequence can then be initiated by the SPI controller by setting the EstCOM_ bit.
Transmitter Synchronization
The start of master-message transmission can be
synchronized on multiple IO-Link ports, so that ports that
operate with the same cycle time receive the master
message simultaneously. Triggering allows synchronization
of master ports on one or many MAX14819/MAX14819A
devices being driven by a common SPI. Assign the same
trigger value to ports that will be synchronized in the
TrigAssgn_ registers and enable synchronization by setting
the TrigEn_ bit.
Write an SPI trigger value to the Trigger register to initiate immediate transmission of the data in the TxFIFOs
assigned to that trigger value. Trigger is a global SPI
command and is not filtered by the SPI address bits, making it possible to synchronize the transmitters of multiple
MAX14819/MAX14819A devices on a single SPI bus with a
single trigger command.
Trigger functionality can also be used with the internal
cycle timer. When configured for this, the cycle timer is
immediately started when its trigger value is received.
Trigger Delay and Synchronization Accuracy
The delay between the time when the MAX14819/
MAX14819A receives a trigger command and the time
when the associated CQ_ transmitter starts transmission is made up of a fixed and a variable component,
which depends on the UART data rate. The time (tTRIG)
between the last rising edge of the serial clock (SCLK)
and the beginning of the CQ_ START bit is:
Maxim Integrated │ 30
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
• COM3: 0.813μs ≤ tTRIG ≤ 1.085μs
• COM2: 4.881μs ≤ tTRIG ≤ 6.508μs
• COM1: 39.060μs ≤ tTRIG ≤ 52.080μs
trigger accuracy equation for a single transmitter output.
Calculate the CQ_ transmitter output skew using the following equation:
The reference point is the time when the trigger command
is received by the MAX14819/MAX14819A. This occurs on
the final (i.e., the 16th) SPI clock’s low-to-high transition
(Figure 13).
When synchronizing multiple CQ transmitters, the trigger
delay skew of the CQ_ transmitter outputs is based on the
triggering delays of each transmitter (see Figure 14). This
skew has a baud-rate-dependent component, similar to the
tTRIG_SKEW (max) ≤ (4BTS - 3BTF) / 16
Where BT is the bit time of the CQ_ data (= 1/COM rate),
BTS is the bit time of the lower bit rate (e.g., COM1), and
BTF is the bit time of the faster bit rate.
When synchronizing ports that use the internal cycle
timers, the skew between channels will be larger, ranging
from 0μs to (BT/16 + 101μs).
UNCERTAINTY
INTERVAL
SCLK
tTRIG_MIN
CQ_
tTRIG_MAX
Figure 13. Trigger Delay
SCLK
CQn
tCQn_MIN
tCQn_MAX
CQy
tCQy_MIN
tCQy_MAX
tTRIGSKEW
Figure 14. Master-Message Trigger Skew
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Maxim Integrated │ 31
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Cycle Timer
The MAX14819/MAX14819A features two cycle timers
(one for each CQ_ transceiver) that autonomously send
the master message from the TxFIFO_ at predefined time
intervals. The bits in the CyclTmr_ register set the time
interval. The smallest cycle time supported by the cycle
timer is 400μs.
The minimum cycle time of the attached IO-Link device is
automatically determined during the establish-communication sequence and is stored in the CyclTmr_ register. If
the device returns a minimum cycle time value of 0x03 or
less, then this will be shown in the associated CycleTmr_
register, however the actual cycle time will be set to
400µs. The SPI master can overwrite these values with
the cycle time required by the application.
Set the RspnsTmrEn bit to 1 (RspnsTmrEn = 1) for
normal cycle timer operation. See the Response Time
Checking (MAX14819A Only) section to operate the cycle
timer without checking the message response delay, TA.
To start the cycle timer sending the first master message,
either send its trigger value or set the CQSend_ bit in the
CQCtrl_ register.
At the start of each cycle, the CQ_ transmitter is enabled
and the master message sent. The CQ_ transceiver is then
automatically switched to receive mode (within 1 bit interval) and the MAX14819/MAX14819A waits for the IO-Link
device response message. When the complete device
message is received, an RxDataRdy_ interrupt is triggered.
When the data ready interrupt is triggered, the SPI
master must read out the device message from the RxFIFO.
The following master message must then be written into
the TxFIFO, if the TxKeepMsg_ bit is not set. A TxError_
interrupt is generated due to TCycleErr_ if the SPI master
does not load the next master message in time.
Clocking
If external UARTs of a microcontroller are used, external
clock sources are not required since the MAX14819/
MAX14819A has adequate internal clocking. If the internal
framers are used instead of external UARTs, external clockXtalEn
XO
XI
CLKI
CLKO
CRYSTAL
OSCILLATOR
ClkDiv1
ClkDiv0
DIVIDER
ExtClock
ing from a crystal or clock source is required to achieve the
timing accuracy required for IO-Link communication (Figure
15). Set the ClkDiv[1:0] bits in the Clock register to select the
input (crystal or clock) frequency: 3.686MHz, 7.372MHz, or
14.745MHz. Set the ComRt_[1:0] bits in the CQCtrl_
register to determine the COM rate on the CQ_ interface.
Set the ExtClockEn bit in the Clock register to enable clocking
from an external clock source on the CLKI input. Set the
XtalEn bit and clear the ExtClkEn bit if a crystal is used for
clocking.
Set the ClkOEn bit in the Clock register to enable the
clock signal on the CLKO output. When ClkOEn is set,
a 3.6864MHz clock output is routed to CLKO, allowing
multiple MAX14819/MAX14819A transceivers to operate
from a single crystal oscillator.
An internal oscillator is used for basic functionality when
both the crystal oscillator and the external clock are
disabled. SPI read/write functionality is also available
when no valid external clock source is present.
LED Control
The MAX14819/MAX14819A features four logic outputs
that can be used for driving LEDs: LD1A, LD1B, LD2A, LD2B.
LED functionality is controlled by setting the bits in the
LEDCtrl register.
Thermal Protection
Thermal Shutdown
The CQ_ drivers are automatically disabled when the driver
temperature exceeds the +160°C (typ) thermal-shutdown
threshold. Drivers are automatically switched on when
the driver temperature falls below the thermal-shutdown
threshold plus hysteresis. The MAX14819/MAX14819A
generates a thermal-shutdown interrupt (ThShdnCOR = 1)
in the Status register when thermal shutdown occurs.
Overtemperature Warning
When the junction temperature exceeds the +135°C (typ)
overtemperature-warning threshold, the TempWarn bit in
the Status register is set.
The TempWarn bit is cleared when the die temperature
falls to +120°C (typ).
ComRtA1 ComRtA0 ComRtB1 ComRtB0
BAUD-RATE
GENERATOR A
UART A
BAUD-RATE
GENERATOR B
UART B
Figure 15. Clock Generation
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Maxim Integrated │ 32
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Register Map
REGISTER
NAME
CH/
GLOBAL
REG
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxRxDataA
A
0x00
DataA7
DataA6
DataA5
DataA4
DataA3
DataA2
DataA1
DataA0
TxRxDataB
B
0x01
DataB7
DataB6
DataB5
DataB4
DataB3
DataB2
DataB1
DataB0
Interrupt
G
0x02
StatusInt
WURQInt
TxErrorB
TxErrorA
RxErrorB
RxErrorA
RxDataRdyB
RxDataRdyA
InterruptEn
B
0x03
StatusIntEn
WURQIntEn
TxErrIntEnB
TxErrIntEnA
RxErrIntEnB
RxErrIntEnA
RDaRdyIntEnB
RxDaRdyIntEnA
RxFIFOLvlA
A
0x04
FifoLvlA7
FifoLvlA6
FifoLvlA5
FifoLvlA4
FifoLvlA3
FifoLvlA2
FifoLvlA1
FifoLvlA0
RxFIFOLvlB
B
0x05
FifoLvlB7
FifoLvlB6
FifoLvlB5
FifoLvlB4
FifoLvlB3
FifoLvlB2
FifoLvlB1
FifoLvlB0
CQCtrlA
A
0x06
ComRtA1
ComRtA0
EstComA
WuPulsA
TxFifoRstA
RxFifoRstA
CycleTmrEnA
CQSendA
CQCtrlB
B
0x07
ComRtB1
ComRtB0
EstComB
WuPulsB
TxFifoRstB
RxFifoRstB
CycleTmrEnB
CQSendB
CQErrA
A
0x08
TransmErrA
TCyclErrA
TChksmErA
TSizeErrA
RChksmErA
RSizeErrA
FrameErrA
ParityErrA
CQErrB
B
0x09
TransmErrB
TCyclErrB
TChksmErB
TSizeErrB
RChksmErB
RSizeErrB
FrameErrB
ParityErrB
MsgCtrlA
A
0x0A
TxErDestroyA
SPIChksA
InsChksA
TSizeEnA
TxKeepMsgA
RChksEnA
RMessgRdyEnA
InvCQA
MsgCtrlB
B
0x0B
TxErDestroyB
SPIChksB
InsChksB
TSizeEnB
TxKeepMsgB
RChksEnB
RMessgRdyEnA
InvCQB
ChanStatA
A
0x0C
RstA
FramerEnA
L+CLimCORA
UVL+CORA CQFaultCORA
L+CLimA
UVL+A
CQFaultA
ChanStatB
B
0x0D
RstB
FramerEnB
L+CLimCORB
UVL+CORB CQFaultCORB
L+CLimB
UVL+B
CQFaultB
LEDCtrl
G
0x0E
LEDEn2B
RxErrEnB
LEDEn1B
RxRdyEnB
LEDEn2A
RxErrEnA
LEDEn1A
RxRdyEnA
Trigger
G
0x0F
*
*
*
*
TrigInit3
TrigInit2
TrigInit1
TrigInit0
CQCfgA
A
0x10
IEC3ThA
SourceSinkA
SinkSelA1
SinkSelA0
NPNA
PushPulA
DrvDisA
CQFilterEnA
CQCfgB
B
0x11
IEC3ThB
SourceSinkB
SinkSelB1
SinkSelB0
NPNB
PushPulB
DrvDisB
CQFilterEnB
CyclTmrA
A
0x12
TCyclBsA1
TCyclBsA0
TCyclMA5
TCyclMA4
TCyclMA3
TCyclMA2
TCyclMA1
TCyclMA0
CyclTmrB
B
0x13
TCyclBsB1
TCyclBsB0
TCyclMB5
TCyclMB4
TCyclMB3
TCyclMB2
TCyclMB1
TCyclMB0
DeviceDlyA
A
0x14
DelayErrA
BDelayA1
BDelayA0
DDelayA3
DDelayA2
DDelayA1
DDelayA0
RspnsTmrEnA
DeviceDlyB
B
0x15
DelayErrB
BDelayB1
BDelayB0
DDelayB3
DDelayB2
DDelayB1
DDelayB0
RspnsTmrEnB
TrigAssgnA
A
0x16
TrigA3
TrigA2
TrigA1
TrigA0
*
*
*
TrigEnA
TrigAssgnB
B
0x17
TrigB3
TrigB2
TrigB1
TrigB0
*
*
*
TrigEnB
L+CnfgA
A
0x18
L+RTA1
L+RTA0
L+DynBLA
L+BLA1
L+BLA0
L+CL2xA
L+CLimDisA
L+EnA
L+CnfgB
B
0x19
L+RTB1
L+RTB0
L+DynBLB
L+BLB1
L+BLB0
L+CL2xB
L+ClimDisB
L+EnB
IOStCfgA
A
0x1A
DiLevelA
CQLevelA
TxEnA
TxA
DiFilterEnA
DiEC3ThA
DiCSourceA
DiCSinkA
IOStCfgB
B
0x1B
DiLevelB
CQLevelB
TxEnB
TxB
DiFilterEnB
DiEC3ThB
DiCSourceB
DiCSinkB
DrvrCurrLim
G
0x1C
CL1
CL0
CLDis
CLBL1
CLBL0
TAr1
TAr0
ArEn
Clock
G
0x1D
VCCWarnEn
TXTXENDis
ExtClkMis
ClkOEn
ClkDiv1
ClkDiv0
ExtClkEn
XtalEn
Status
G
x01E
ThShdnCOR
ThWarnCOR
VCCUVCOR
VCCWarnCOR
ThShdn
TempWarn
VCCUV
VCCWarn
RevID
G
0x1F
*
*
*
*
ID3
ID2
ID1
ID0
*Bit is unused.
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Maxim Integrated │ 33
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Register Description
TxRxDataA Register [0x00]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
DataA7
DataA6
Data5
DataA4
DataA3
DataA2
DataA1
DataA0
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
X
X
X
X
X
X
X
X
RESET UPON READ
N
N
N
N
N
N
N
N
The TxRxDataA register allows writing data into the channel A TxFIFOA and reading data received out of the channel
A RxFIFOA. Data can be written into the TxFIFOA and read out of the RxFIFOA in either byte-by-byte mode or burst
mode. When using SPI burst mode, multiple bytes can be written to/read from the FIFOs in a single SPI cycle. Reading
the RxFIFOA after it is empty results in random values.
RxFIFOA and TxFIFOA are available when framer A is enabled by setting the FramerEnA bit in the ChanStatA register.
BIT
NAME
7:0
DataA
DESCRIPTION
Channel A TxFIFO/RxFIFO data
TxRxDataB Register [0x01]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
DataB7
DataB6
DataB5
DataB4
DataB3
DataB2
DataB1
DataB0
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
X
X
X
X
X
X
X
X
RESET UPON READ
N
N
N
N
N
N
N
N
The TxRxDataB register allows writing data into the channel B TxFIFOB and reading data received out of the channel
B RxFIFOB. Data can be written into the TxFIFOB and read out of the RxFIFOB in either byte-by-byte mode or burst
mode. When using SPI burst mode, multiple bytes can be written to/read from the FIFOs in a single SPI cycle. Reading
the RxFIFOB after it is empty results in random values. Reading the RxFIFOB after it is empty results in random values.
RxFIFOB and TxFIFOB are available when framer B is enabled by setting the FramerEnB bit in the ChanStatB register.
BIT
NAME
7:0
DataB
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DESCRIPTION
Channel B TxFIFO/RxFIFO data
Maxim Integrated │ 34
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Interrupt Register [0x02]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
StatusInt
WURQInt
TxErrorB
TxErrorA
RxErrorB
RxErrorA
RxDataRdyB
RxDataRdyA
READ/WRITE
R
R
R
R
R
R
R
R
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
Y
Y
Y
Y
Y
Y
N
N
BIT
NAME
DESCRIPTION
7
StatusInt
Status Error Interrupt
This bit is set when a supply error or thermal error L+ supply error, or CQ_ driver
error occurs. See Figure 16.
6
WURQInt
Wake-Up Request Interrupt
This bit is set when the establish-communication sequencer is either
successfully or unsuccessfully completed after an EstCom_ sequence is
initiated. See the CQCntrl register for more information.
5
TxErrorB
Channel B Transmitter Error Interrupt
This bit is set when an error is detected on the channel B transmitter (CQB).
Details on the type of error can be read out of the CQErrB register. See Figure 17.
4
TxErrorA
Channel A Transmitter Error Interrupt
This bit is set when an error is detected on the channel A transmitter (CQA).
Details on the type of error can be read out of the CQErrA register. See Figure 17.
3
RxErrorB
2
RxErrorA
1
0
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Channel B Receiver Error Interrupt
This bit is set when a receive error is detected on CQB. Details on the receive
error can be read out of the CQErrB or DevicDelyB register. Optionally, the status
of the RxErrorB bit can be made available on the RXERRB/LD2B pin. Set the
RxErrEnB bit in the LEDCtrl register to 1 to assert the RXERRB/LD2B pin when
RxErrorB is set. See Figure 18.
Channel A Receiver Error Interrupt
This bit is set when a receive error is detected on CQA. Details on the receive
error can be read out of the CQErrA register. Optionally, the status of the RxErrorA
bit can be made available on the RXERRA/LD2A pin. Set the RxErrEnB bit in the
LEDCtrl register to 1 to assert the RXERRA/LD2A pin when RxErrorA is set. See
Figure 18.
RxDataRdyB
Channel B Receiver Data Ready Interrupt
RxDataRdyB is set when the first byte of data is received by the channel B
RxFIFO. The RxDataRdyB interrupt is set when the RxFIFOB level changes from
empty to at least one received word. If RMessgRdyEnB = 1, RxDataRdyB is set
when a complete M-sequence frame was received correctly and is ready for SPI
readout from TxRxDataB. Set the RxRdyEnB bit in the LEDCtrl register to 1 to
assert the RXRDYB/LD1B pin when RxDataRdyB is set.
RxDataRdyB is cleared when the TxRxDataB register is read.
RxDataRdyA
Channel A Receiver Data Ready Interrupt
RxDataRdyaA is set when the first byte of data is received by the channel A
RxFIFO. The RxDataRdyA interrupt is set when the RxFIFOA level changes from
empty to at least one received word. If RMessageRdyEnA = 1, RxDataRdyA is
set when a complete M-sequence frame was received correctly and is ready for
SPI readout from TxRxDataA. Set the RxRdyEnA bit in the LEDCtrl register to 1 to
assert the RXRDYA/LD1A pin when RxDataRdyA is set.
RxDataRdyA is cleared when TxRxDataA is read.
Maxim Integrated │ 35
STATUS
REGISTER
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
VCCUVCOR
VCCWarnCOR
ThShdnCOR
ThWarnCOR
CHANSTAT_
REGISTER
StatusInt
L+CLimCOR_
UVL+COR_
CQFaultCOR_
Figure 16. StatusInt Interrupt Triggers
CQErr_
REGISTER
TransmErr_
TCyclErr_
TChkSmEr_
TxError_
TSizeErr_
Figure 17. TxError_ Triggers
CQError_
REGISTERS
ParityErr_
FrameErr_
RSizeErr_
DeviceDly_
REGISTERS
RChkSmErr_
REGISTER BITS: RxError_
SDO READ BITS: ERRA_
PINS: RXRDY_/LD1_
DelayErr_
Figure 18. RxError_Triggers
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Maxim Integrated │ 36
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
InterruptEn Register [0x03]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
StatusIntEn
WURQIntEn
TxErrIntEnB
TxErrIntEnA
RxErrIntEnB
RxErrIntEnA
RDaRdyIntEnB
RDaRdyIntEnA
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
7
6
5
4
3
NAME
DESCRIPTION
StatusIntEn
Status Interrupt Enable
Set the StatIntEn bit to 1 to assert the IRQ output when a StatusInt interrupt is generated.
Clear the StatusIntEn bit to disable/mask the IRQ output when a StatusInt interrupt is
generated.
WURQIntEn
Wake-Up Request Interrupt Enable
Set the WURQIntEn bit to 1 to assert the IRQ output when a WURQInt interrupt is
generated.
Clear the WURQIntEn bit to disable/mask the IRQ output when a WURQInt interrupt is
generated.
TxErrIntEnB
Channel B Transmitter Error Interrupt Enable
Set the TxErrIntEnB bit to 1 to assert the IRQ output when a TxErrorB interrupt is
generated.
Clear the TxErrIntEn bit to disable/mask the IRQ output when a TxErrorB interrupt is
generated.
TxErrIntEnA
Channel A Transmitter Error Interrupt Enable
Set the TxErrIntEnA bit to 1 to assert the IRQ output when a TxErrorA interrupt is
generated.
Clear the TxErrIntEn bit to disable/mask the IRQ output when a TxErrorA einterrupt is
generated.
RxErrIntEnB
Channel B Receiver Error Interrupt Enable
Set the RxErrIntEnB bit to 1 to assert the IRQ output when a RxErrorB interrupt is
generated.
Clear the RxErrIntEnB bit to disable/mask the IRQ output when a RxErrorB interrupt is
generated. .
The RxErrIntEnB bit does not mask or enable the RXERRB/LD2B pin.
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Maxim Integrated │ 37
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
InterruptEn Register [0x03] (continued)
BIT
NAME
2
DESCRIPTION
Channel A Receiver Error Interrupt Enable
Set the RxErrIntEnA bit to 1 to assert the IRQ output when a RxErrorA interrupt is
generated.
Clear the RxErrIntEnA bit to disable/mask the IRQ output when a RxErrorA interrupt is
generated.
The RxErrIntEnA bit does not mask or enable the RXERRA/LD2A pin.
RxErrIntEnA
1
0
RDaRdyIntEnB
Channel B Receiver Data Ready Interrupt Enable
Set the RDaRdyIntEnB bit to 1 to assert the IRQ output when a RxDataRdyB interrupt is
generated.
Clear the RDaRdyIntEnB bit to disable/mask the IRQ output when a RxDataRdyB
interrupt is generated.
The RDaRdyIntEnB bit does not mask or enable the RXRDYB/LD1B pin.
RDaRdyIntEnA
Channel A Receiver Data Ready Interrupt Enable
Set the RDaRdyIntEnA bit to 1 to assert the IRQ output when a RxDataRdyA interrupt is
generated.
Clear the RDaRdyIntEnA bit to disable/mask the IRQ output when a RxDataRdyA
interrupt is generated.
The RDaRdyIntEnA bit does not mask or enable the RXRDYA/LD1A pin.
RxFIFOLvlA Register [0x04]
BIT
BIT NAME
READ/WRITE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FifoLvlA7
FifoLvlA6
FifoLvlA5
FifoLvlA4
FifoLvlA3
FifoLvlA2
FifoLvlA1
FifoLvlA0
R
R
R
R
R
R
R
R
POR STATE
0
0
0
0
0
0
0
1
RESET UPON READ
N
N
N
N
N
N
N
N
The RxFIFOLvlA register shows the current number of device message bytes in the RxFIFOA. This changes as data is read out of
the RxFIFOA and as the RxFIFOA fills up. The MAX14819/MAX14819A adds one byte, at the start of the RxFIFOA data, which is
the number of device message bytes that were received; the RxFIFOLvlA value does not include this added byte.
Note: Due to the limitations of simultaneous access, the value read from the RxFIFOLvlA register may be off by ±1 word while the
receiver is receiving data. The value read from RxFIFOLvlA is correct while the receiver is not receiving data.
BIT
NAME
7:0
FifoLvlA
www.maximintegrated.com
DESCRIPTION
Channel A Receive FIFO Device Message Level
Maxim Integrated │ 38
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
RxFIFOLvlB Register [0x05]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
FifoLvlB7
FifoLvlB6
FifoLvlB5
FifoLvlB4
FifoLvlB3
FifoLvlB2
FifoLvlB1
FifoLvlB0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
N
N
N
N
N
N
N
N
READ/WRITE
POR STATE
RESET UPON READ
The RxFIFOLvlB register shows the current number of device message bytes in the RxFIFOB. This changes as data is read out of
the RxFIFOB and as the RxFIFOB fills up. The MAX14819/MAX14819A adds one byte, at the start of the RxFIFOB data, which is
the number of device message bytes that were received; the RxFIFOLvlB value does not include this added byte.
Note: Due to the limitations of simultaneous access, the value read from the RxFIFOLvlB register may be off by ±1 word while the
receiver is receiving data. The value read from RxFIFOLvlB is correct while the receiver is not receiving data.
BIT
NAME
DESCRIPTION
7:0
FifoLvlB
Channel B Receive FIFO Device Message Level
CQCtrlA Register [0x06]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
ComRtA1
ComRtA0
EstComA
WuPulsA
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
[7:6]
www.maximintegrated.com
NAME
ComRtA1,
ComRtA0
TxFifoRstA RxFifoRstA CycleTmrEnA CQSendA
R/W
DESCRIPTION
Channel A CQ (CQA) COM Rate Setting
The ComRtA[1:0] bits set the COM data rate on the CQA interface.
Once the establish-communication sequence, intiated with EstComA, is
successfully completed, the COM rate of the IO-link device will be stored
in these bits as follows:
00: Detection failure (230.4kbps)
01: COM1 = 4.8kbps
10: COM2 = 38.4kbps
11: COM3 = 230.4kbps
Maxim Integrated │ 39
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQCtrlA Register [0x06] (continued)
BIT
5
4
NAME
DESCRIPTION
EstComA
Channel A Establish-Communication Sequence Enable
Set the EstComA to 1 to initiate an IO-Link establish-communication sequence on CQA. After successful completion of the establish
communication sequence, a WURQInt interrupt is generated and the
EstComA bit changes to 0. During the generated wake-up pulse, the CQA
current limit is temporarily set above 500mA internally, although the CL_
register bits are not changed. The COM rate of the IO-Link device is then
reflected by the ComRt0A and ComRt1A bits and the device cycle time
can be read out of the CyclTimeA register.
If the establish-communication sequence was not successful, a WURQInt
interrupt is generated and EstComA is 0 and the ComRt1A and ComRt0A
bits both = 0. The FramerEnA bit must be 1 to use the EstComA function.
WuPulsA
Channel A Wake-Up Pulse Generate
Set WuPulsA to 1 to immediately generate a wake-up pulse/request
(WURQ) on CQA. Following the wake-up request, the CQA transceiver is
set into receive mode. WuPulsA is reset to 0 after the WURQ is completed.
WuPulsA is used when the microcontroller manages the establish
communication sequence and the EstComA funciton is not used.
3
TxFifoRstA
Channel A TX FIFO (TxFIFOA) Reset
Set TxFifoRstA to reset the TxFIFOA. This may be necessary if an SPI
transmission error is detected when filling the TxFIFOA or if a CQA
transmission error is detected.
2
RxFifoRstA
Channel A RX FIFO (RxFIFOA) Reset
Set RxFifoRstA to reset the RxFIFOA. This may be necessary if an
RSizeErrA event occurs.
1
0
CycleTmrEnA
CQSendA
Channel A Cycle Timer Enable
Set CyclTmrEnA to 1 to enable the channel A cycle time. CyclTmrEnA
does not start the cycle timer. Cycle timer A starts when the CQSendA bit
is set to 1 (after the timer is enabled) or an associated trigger command is
received.
Set CyclTmrEnA to 0 to stop the cycle timer. The timer can be stopped at
any time, even if the current cycle is not yet complete.
Channel A Initiate Master Message
Set CQSendA to 1 to initiate transmission of the master message in the
channel A transmit FIFO (TxFIFOA). The CQA transceiver is put into
transmit mode and sends the master message/data in the TxFIFOA. When
the master message is complete/TxFIFOA is empty, the CQA transceiver
is set to receive mode to receive device messages.
If CyclTmrEnA = 1, setting CQSendA to 1 also starts cycle timer A.
CQSendA is automatically cleared.
www.maximintegrated.com
Maxim Integrated │ 40
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQCtrlB Register [0x07]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT NAME
ComRtB1
ComRtB0
EstComB
WuPulsB
TxFifoRstB
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
[7:6]
5
4
www.maximintegrated.com
NAME
ComRtB1, ComRtB0
BIT 2
BIT 1
RxFifoRstB CycleTmrEnB
BIT 0
CQSendB
DESCRIPTION
Channel B CQ (CQB) COM Rate Setting
The ComRtB[1:0] bits set the COM data rate on the CQB interface.
Once the establish-communication sequence, intiated with EstComB, is
successfully completed, the COM rate of the IO-link device will be stored
in these bits as follows:
00: Detection failure (230.4kbps)
01: COM1 = 4.8kbps
10: COM2 = 38.4kbps
11: COM3 = 230.4kbps
EstComB
Channel B Establish-Communication Sequence
Set the EstComB to 1 to initiate an IO-Link establish-communication
sequence on CQB. After successful completion of the establish
communication sequence, a WURQInt interrupt is generated and the
EstComB bit changes to 0. During the generated wake-up pulse, the CQB
current limit is temporarily set above 500mA internally, although the CL_ register bits are not changed. The COM rate of the IO-Link device is then
reflected by the ComRt0A and ComRt1A bits and the device cycle time can
be read out of the CyclTimeB register.
If the establish-communication sequence was not successful, a WURQInt
interrupt is generated and EstComB is 0 and the ComRt1B and ComRt0B
bits both = 0. The FramerEnB bit must be 1 to use the EstComB function.
WuPulsB
Channel B Wake-Up Pulse Generate
Set WuPulsB to 1 to immediately generate a wake-up pulse/request
(WURQ) on CQB. Following the wake-up request, the CQB transceiver is
set into receive mode. WuPulsB is reset to 0 after the WURQ is completed.
WuPulsA is used when the microcontroller manages the establishcommunication sequence and the EstComB function is not used.
Maxim Integrated │ 41
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQCtrlB Register [0x07] (continued)
BIT
NAME
DESCRIPTION
Channel B TX FIFO (TxFIFOA) Reset
3
TxFifoRstB
2
RxFifoRstB
1
CyclTmrEnB
Set TxFifoRstB to reset the TxFIFOB. This may be necessary if an
SPI transmission error is detected when filling the TxFIFOB or if a
CQB transmission error is detected.
Channel B RX FIFO (RxFIFOA) Reset
Set RxFifoRstA to reset the RxFIFOA. This may be necessary if
an RSizeErrA event occurs.
Channel B Cycle Timer Enable
Set CyclTmrEnB to 1 to enable the channel B cycle time.
CyclTmrEnB does not start the cycle timer. Cycle timer B starts
when the CQSendB bit is set to 1 (after the timer is enabled) or an
associated trigger command is received.
Set CyclTmrEnB to 0 to stop the cycle timer. The timer can be
stopped at any time, even if the current cycle is not yet complete.
Channel B Initiate Master Message
0
CQSendB
Set CQSendB to 1 to initiate transmission of the master message
in the channel B transmit FIFO (TxFIFOB). The CQB transceiver
is put into transmit mode and sends the master message/data in
the TxFIFOB. When the master message is complete/TxFIFOB
is empty, the CQB transceiver is set to receive mode to receive
device messages.
If CyclTmrEnB = 1, setting CQSendB to 1 also starts cycle timer
B.
CQSendB is automatically cleared.
CQErrA Register [0x08]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
TransmErrA
TCyclErrA
TChksmErA
TSizeErrA
RChksmErA
RSizeErrA
FrameErrA
ParityErrA
READ/WRITE
R
R
R
R
R
R
R
R
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
Y
Y
Y
Y
Y
Y
Y
Y
BIT
7
www.maximintegrated.com
NAME
TransmErrA
DESCRIPTION
Channel A Transmission Error
This bit is set when the message sent on Channel A was not properly sent.
The bit is cleared when the CQErrA register is read.
Maxim Integrated │ 42
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQErrA Register [0x08] (continued)
BIT
6
5
4
3
2
1
0
www.maximintegrated.com
NAME
DESCRIPTION
TCyclErrA
Channel A Transmission Cycle Error
This bit is set when when no data is loaded into the TxFIFOA before the start
of the master message transmission. At least one octet must be loaded into
TxFIFOA at the start of the transmission cycle. This bit is only active when
the internal cycle timer is used (CycTmrEnA = 1). The bit is cleared when the
CQErrA register is read.
TChksmErA
Channel A Transmitter Checksum Error
This bit is set when the checksum calculated by the MAX14819/MAX14819A
on the master message is different to the checksum written in the TxFIFOA by
the SPI master. A checksum error indicates an SPI transmission error. This bit
is only active when SPIChksA = 1. If TChksmErA = 1, the master message is
not sent to the device when the autonomous cycle timer A is enabled. The bit
is cleared when the CQErrA register is read.
TSizeErrA
Channel A Transmitter Size Error
This bit is set when the number of octets in the master message differs from the
TxBytes value written into the TxFIFOA. This can occur as a result of
slow SPI master writing of the master message into TxFIFOA while CQA
transmission has started, so that the master message cannot be sent in the
allocated time. When this error occurs, it is recommended that the controller
delete the TxFIFOA (TxFIFORstA = 1) and repeat the master message
transmission. The bit is cleared when the CQErrA register is read.
RChksmErA
Channel A Receiver Checksum Error
This bit is set when a 6-bit checksum calculated by the MAX14819/
MAX14819A differs from the checksum in the received device message.
The bit is cleared when the CQErrA register is read.
RSizeErrA
Channel A Receiver Size Error
This bit is set when the number of octets received for the device differs from
RxBytes previously loaded into TxFIFOA. The bit is cleared when the CQErrA
register is read.
FrameErrA
Channel A Frame Error
This bit is set when a UART frame error is detected on the data received on
the CQA receiver. A FrameErrA error triggers a RxErrorA interrupt. The bit is
cleared when the CQErrA register is read.
ParityErrA
Channel A Parity Error
This bit is set when a UART parity error is detected on a word received by the
CQA receiver. A ParityErrA interrupt triggers an RxErrorA interrupt in the Interrupt register. The bit is cleared when the CQErrA register is read.
Maxim Integrated │ 43
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQErrB Register [0x09]
BIT
BIT 7
BIT 6
BIT NAME
TransmErrB
TCyclErrB
READ/WRITE
R
R
R
R
R
R
R
R
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
Y
Y
Y
Y
Y
Y
Y
Y
BIT
NAME
7
TransmErrB
6
5
4
www.maximintegrated.com
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
TChksmErB TSizeErrB RChksmErB RSizeErrB FrameErrB
BIT 0
ParityErrB
DESCRIPTION
Channel B Transmission Error
This bit is set when the message sent on Channel B was not properly
sent. The bit is cleared when the CQErrB register is read.
TCyclErrB
Channel B Transmission Cycle Error
This bit is set when when no data is loaded into the TxFIFOB before the
start of the master message transmission. At least one octet must be
loaded into TxFIFOB at the start of the transmission cycle. This bit is only
active when the internal cycle timer is used (CyclTmrEnB = 1). The bit is
cleared when the CQErrB register is read.
TChksmErB
Channel B Transmitter Checksum Error
This bit is set when the checksum calculated by the MAX14819/
MAX14819A on the master message is different to the checksum written in the TxFIFOB by the SPI master. A checksum error indicates an
SPI transmission error. This bit is only active when SPIChksB = 1. If
TChksmErB = 1, the master message is not sent to the device when the
autonomous cycle timer B is enabled. The bit is cleared when the CQErrB
register is read.
TSizeErrB
Channel B Transmitter Size Error
This bit is set when the number of octects in the master message differs
from the TxBytes value written into the TxFIFOB. This can occur as a
result of slow SPI master writing of the master message into TxFIFOB
while CQB transmission has started, so that the master message cannot
be sent in the allocated time. When this error occurs, it is recommended
that the controller delete the TxFIFOB (TxFIFORstB = 1) and repeat
the master message transmission. The bit is cleared when the CQErrB
register is read.
Maxim Integrated │ 44
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQErrB Register [0x09] (continued)
BIT
NAME
3
RChksmErB
2
1
0
DESCRIPTION
Channel B Receiver Checksum Error
This bit is set when a 6-bit checksum calculated by the MAX14819/
MAX14819A differs from the checksum in the received device message.
The bit is cleared when the CQErrB register is read.
RSizeErrB
Channel B Receiver Size Error
This bit is set when the number of octets received for the device differs
from RxBytes previously loaded inot TxFIFOB. The bit is cleared when
the CQErrB register is read.
FrameErrB
Channel B Frame Error
This bit is set when a UART frame error is detected on the data received
on the CQB receiver. A FrameErrB error triggers a RxErrorB interrupt. The
bit is cleared when the CQErrBregister is read.
ParityErrB
Channel B Parity Error
This bit is set when a UART parity error is detected on a word received by
the CQB receiver. A ParityErrB interrupt triggers an RxErrorB interrupt in
the Interrupt register. The bit is cleared when the CQErrB register is read.
MsgCtrlA Register [0x0A]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT NAME
TxErDestroyA
SPIChksA
InsChksA
TSizeEnA
READ/WRITE
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
BIT
7
www.maximintegrated.com
NAME
TxErDestroyA
BIT 3
BIT 2
BIT 1
BIT 0
RMessgRdyEnA
InvCQA
R/W
R/W
R/W
0
0
0
N
N
N
TxKeepMsgA RChksEnA
DESCRIPTION
Channel A TxFIFOA Message Delete on Error
Set TxErDestroyA = 1 to instruct the MAX14819 to automatically delete the
message in the TxFIFOA (reset TxFIFOA) when a checksum or size error
is detected in the message. This is only possible when a complete master
message is loaded in the the TxFIFOA before transmission starts.
Maxim Integrated │ 45
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
MsgCtrlA Register [0x0A] (continued)
BIT
6
5
4
3
2
1
0
www.maximintegrated.com
NAME
DESCRIPTION
SPIChksA
Channel A SPI Checksum Verify
Set SPIChksA = 1 to enable checking of the SPI checksum that the SPI
master wrote into the CKT octet compared to the calculated checksum.
This bit is independent of InsChksA. When a checksum disparity is found,
the TChksmErA bit is set in the CQErrA register.
InsChksA
Channel A Insert Checksum
Set InsChksA = 1 to instruct the MAX14819/MAX14819A to calculate the
6-bit checksum on the master message residing in TxFIFOA and insert this
into the CKT byte. The bits written by the SPI master into these 6 bits are
replaced.
TSizeEnA
Channel A TxFIFOA Size Check Enable
Set TSizeEnA = 1 to require the MAX14819/MAX14819A to verify that the
number of bytes in the TxFIFOA is equal to the TxBytes value written into
the TxFIFOA. If the master message is loaded before transmission starts,
a TxErrA interrupt is generated and the message can be deleted by the
MAX14819/MAX14819A (when TxErDestroyA = 1). If the transmission has
started before the whole message is loaded, then the message cannot be
automatically deleted.
TxKeepMsgA
Channel A Keep TxFIFO Message Enable
Set TxKeepMsgA = 1 to stop the MAX14819/MAX14819A from clearing the
TxFIFOA after the message has been sent. This allows sending the same
master message on the following cycle. When TxKeepMsgA = 0, the data in
the TxFIFOA is automatically cleared after the message has been sent.
RChksEnA
Channel A Device Message Checksum Enable
Set RChksEnA = 1 to enable the MAX14819/MAX14819A to check the device message checksum in the RxFIFOA. If an error is detected during
the checksum check, the RChksmErA bit is set.
RMessgRdyEnA
Channel A Received Message Ready
Set RMessgRdyEnA = 1 to generate a RxDataRdyA interrupt when the
complete device response message is received and has no errors. When
RMessgRdyEnA = 0, a RxDataRdyA interrupt is generated as soon as the
first word is received in the RxFIFOA.
InvCQA
Channel A Logic Invert
Set InvCQA = 1 to switch the polarity of the CQA output for transmission and
reception. when InvCQA = 0, TXA and RXA are logic inverts of CQA. When
InvCQA = 1, TXA and RXA follow CQA, logically.
Maxim Integrated │ 46
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
MsgCtrlB [0x0B]
BIT
BIT 7
BIT 6
BIT 5
BIT NAME
TxErDestroyB
SPIChksB
InsChksB
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
7
6
5
4
www.maximintegrated.com
BIT 4
BIT 3
BIT 2
BIT 1
TSizeEnB TxKeepMsgB RChksEnb RMessgRdyEnb
BIT 0
InvCQB
NAME
DESCRIPTION
TxErDestroyB
Channel B TxFIFOB Message Delete on Error
Set TxErDestroyB = 1 to instruct the MAX14819/MAX14819A to automatically delete the message in the TxFIFOB (reset TxFIFOB) when a checksum or size error is detected in the message. This is only possible when a
complete master message is loaded in the the TxFIFO before transmission
starts.
SPIChksB
Channel B SPI Checksum Verify
Set SPIChksB = 1 to enable checking of the SPI checksum that the SPI
master wrote into the CKT octet compared to the calculated checksum.
This bit is independent of InsChksB. When a checksum disparity is found,
the TChksmErB bit is set in the CQErrB register.
InsChksB
Channel B Insert Checksum
Set InsChksB = 1 to instruct the MAX14819/MAX14819A to calculate the
6-bit checksum on the master message residing in TxFIFOB and inster this
into the CKT byte. The bits written by the SPI master into these 6 bits are
replaced.
TSizeEnB
Channel B TxFIFOB Size Check Enable
Set TSizeEnB = 1 to require the MAX14819/MAX14819A to verify that the
number of bytes in the TxFIFOB is equal to the TxBytes value written into
the TxFIFOB. If the master message is loaded before transmission starts,
a TxErrB interrupt is generated and the message can be deleted by the
MAX14819/MAX14819A (when TxErDestroyB = 1). If the transmission has
started before the whole message is loaded, then the message cannot be
automatically deleted.
Maxim Integrated │ 47
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
MsgCtrlB [0x0B] (continued)
BIT
3
2
1
0
www.maximintegrated.com
NAME
DESCRIPTION
TxKeepMsgB
Channel B Keep TxFIFO Message Enable
Set TxKeepMsgB = 1 to stop the MAX14819/MAX14819A from clearing the
TxFIFOB after the message has been sent. This allows sending the same
master message on the following cycle. When TxKeepMsgB = 1, the TxFIFOB must be cleared by setting the TxFIFORstB bit. When TxKeepMsgB =
0, the data in the TxFIFOB is automatically cleared after the message has
been sent.
RChksEnB
Channel B Device Message Checksum Enable
Set RChksEnB = 1 to enable the MAX14819/MAX14819A to check the
device message checksum in the RxFIFOB. If an error is detected during
the checksum check, the RChksmErB bit is set.
RMessgRdyEnB
Channel B Received Message Ready
Set RMessgRdyEnB = 1 to generate a RxDataRdyB interrupt when the
complete device response message is received and has no errors. When
RMessgRdyEnB = 0, a RxDataRdyB interrupt is generated as soon as the
first word is received by the RxFIFOB.
InvCQB
Channel B Logic Invert
Set InvCQB = 1 to switch the polarity of the CQB output for transmission
and reception. when InvCQB = 0, TXB and RXB are logic inverts of CQB.
When InvCQB = 1, TXB and RXB follow CQB, logically.
Maxim Integrated │ 48
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
ChanStatA Register [0x0C]
BIT
BIT 7
BIT NAME
RstA
READ/WRITE
R/W
R/W
R
R
R
POR STATE
0
0
X
X
0
RESET UPON READ
N
N
Y
Y
Y
BIT
7
6
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
FramerEnA L+CLimCORA UVL+CORA CQFaultCORA L+CLimA
NAME
RstA
FramerEnA
5
L+CLimCORA
4
UVL+CORA
3
2
1
0
www.maximintegrated.com
BIT 1
BIT 0
UVL+A
CQFaultA
R
R
R
X
X
0
N
N
N
DESCRIPTION
Channel A Register Reset
Set RstA = 1 to reset all channel A register bits, the TxFIFOA, and
RxFIFOA. Channel B registers and global register bits are not affected.
RstA is cleared automatically when the channel A registers have been
reset.
Channel A Framer Enable
Set FramerEnA = 1 to enable the internal message handler, RxFIFOA,
and TxFIFOA. When an external UART is used (the internal framer is not
used), set FramerEnA = 0 and connect the external UART to the TXENA,
TXA, and RXA pins.
Channel A L+A Current Limit Latched
Clear-on-read flag of the L+ClimA bit. This bit is set only when the
L+CLimA bit transitions from 0 to 1. This bit can generate a StatusInt
interrupt.
Channel A L+A UnderVoltage Latched
Clear-on-read flag of the UVL+A bit. This bit is set only when the UVL+A
bit transitions from 0 to 1. This bit can generate a StatusInt interrupt.
CQFaultCORA
Channel A CQ Driver Fault Latched
Clear-on-read flag of the CQFaultA bit. This bit is set only when the
CQFaultA bit transitions from 0 to 1. This bit can generate a StatusInt
interrupt.
L+CLimA
Channel A L+A Current Limit Real Time
This bit is set when the L+A sensor supply load current exceeds the
current-limit threshold set by the sense resistor for longer than the
programmed current-limit blanking time (see the L+CnfgA register for
more information). L+CLimA is cleared when the L+A supply exits
autoretry current limiting.
UVL+A
Channel A L+A Undervoltage Real Time
This bit is set when the L+A supply voltage falls below the L+ power-good
falling threshold. The bit is cleared when the L+A voltage rises above the
L+ power-good rising threshold.
CQFaultA
Channel A CQ Driver Fault Real Time
This bit is set when a fault is detected on the CQA driver. The fault can be
an overload condition, for example an overcurrent of thermal-shutdown
event.
Maxim Integrated │ 49
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
ChanStatB Register [0x0D]
BIT
BIT 7
BIT 6
BIT NAME
RstB
FramerEnB
READ/WRITE
R/W
R/W
R
R
R
POR STATE
0
0
X
X
0
RESET UPON READ
N
N
Y
Y
Y
BIT
7
NAME
RstB
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UVL+B
CQFaultB
R
R
R
X
X
0
N
N
N
L+CLimCORB UVL+CORBr CQFaultCORB L+CLimB
DESCRIPTION
Channel B Register Reset
Set RstB = 1 to reset all channel B register bits, the TxFIFOB, and
RxFIFOB. Channel A registers and global register bits are not affected.
RstB is cleared automatically when the channel B registers have been
reset.
6
FramerEnB
Channel B Framer Enable
Set FramerEnB = 1 to enable the internal UARTB, message handler,
RxFIFOB, and TxFIFOB. When an external UART is used (the internal
framer is not used), set FramerEnA = 0 and connect the external UART to
the TXENA, TXA, and RXA pins.
5
L+CLimCORB
Channel B L+B Current Limit Latched
Clear-on-read flag of the L+ClimB bit. This bit is set when the L+CLimB bit
transitions from 0 to 1. This bit can generate a StatusInt interrupt.
4
UVL+CORB
Channel B L+B UnderVoltage Latched
Clear-on-read flag of the UVL+B bit. This bit is set only when the UVL+B bit
transitions from 0 to 1. This bit can generate a StatusInt interrupt.
3
CQFaultCORB
Channel B CQ Driver Fault Latched
Clear-on-read flag of the CQFaultB bit. This bit is set only when the CQFaultB bit transitions from 0 to 1. This bit can generate a StatusInt interrupt.
2
1
0
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L+CLimB
Channel B L+B Current Limit Real Time
This bit is set when the L+B sensor supply load current exceeds the
current-limit threshold set by the sense resistor for longer than the programmed current-limit blanking time (see the LpCfgB register for more
information). L+CLimB is cleared when the L+B supply exits autoretry
current limiting.
UVL+B
Channel B L+B Undervoltage Real Time
This bit is set when the L+B supply voltage falls below the L+ power-good
falling threshold. The bit is cleared when the L+B voltage rises above the
the L+ power-good rising threshold.
CQFaultB
Channel B CQ Driver Fault Real Time
This bit is set when a fault is detected on the CQB driver. The fault can be
an overload condition, for example an overcurrent of thermal-shutdown
event.
Maxim Integrated │ 50
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
LEDCtrl Register [0x0E]
BIT
BIT 7
BIT 6
BIT 5
BIT NAME
LEDEn2B
RxErrEnB
LEDEn1B
READ/WRITE
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
RESET UPON READ
N
N
N
N
BIT
7
6
5
4
3
www.maximintegrated.com
NAME
LEDEn2B
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxErrEnA
LEDEn1A
RxRdyEnA
R/W
R/W
R/W
R/W
0
0
0
0
N
N
N
N
RxRdyEnB LEDEn2A
DESCRIPTION
Channel B LD2B LED Driver Control
Set LEDEn2B = 1 to turn on a LED connected to RXERRB/LD2B. Set
LEDEn2B = 0 to turn the LED off. LEDEn2B is only active when
RxErrEnB = 0.
RxErrEnB
Channel B RXERRB/LD2B Pin Function Select
Set RxErrEnB = 1 to enable the receiver-error (RxErrorB) interrupt
functionality on the RXERRB/LD2B pin. In this mode, RXERRB/LD2B
asserts when the RxErrorB bit is set. The RXERRB/LD2B pin functionality
is not affected by the RxErrIntEnB interrupt mask.
Set RxErrEnB = 0 to enable the LED driver function on the ERRB/LD2B
output.
LEDEn1B
Channel B LD1B LED Driver Control
Set LEDEn1B = 1 to turn on a LED connected to RXRDYB/LD1B. Set
LEDEn1B = 0 to turn the LED off. LEDEn1B is only active when
RxRdyEnB = 0.
RxRdyEnB
Channel B RXRDYB/LD1B Pin Function Select
Set RxRdyEnB = 1 to enable the receiver-error (RxErrorB) interrupt
functionality on the RXRDYB/LD1B pin. In this mode, RXRDYB/LD1B
asserts when the RcDaRdyB bit is set. The RXRDYB/LD1B pin
functionality is not affected by the RxDaRdyIntEnB interrupt mask.
Set RxRdyEnB = 0 to enable the LED driver function on the
RXRDYB/LD1B pin.
LEDEn2A
Channel A LD2A LED Driver Control
Set LEDEn2A = 1 to turn on a LED connected to RXERRA/LD2A. Set
LEDEn2A = 0 to turn the LED off. LEDEn2A is only active when RxErrEnA
= 0.
Maxim Integrated │ 51
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
LEDCtrl Register [0x0E] (continued)
BIT
NAME
DESCRIPTION
RxErrEnA
Channel A RXERRA/LD2A Pin Function Select Bit
Set RxErrEnA = 1 to enable the receiver-error (RxErrorA) interrupt
functionality on the RXERRA/LD2A pin. In this mode, RXERRA/LD2A
asserts when the RxErrorA bit is set. The RXERRA/LD2A pin functinoality
is not affected by the RxErrIntEnA interrupt mask.
Set RxErrEnA = 0 to enable the LED driver functiona on RXERRA/LD2A.
LEDEn1A
Channel A LD1A LED Driver Control Bit
Set LEDEn1A = 1 to turn on a LED connected to the RXRDYA/LD1A
pin. Set LEDEn1A = 0 to turn the LED off. LEDEn1A is only active when
RxRdyEnA = 0.
RxRdyEnA
Channel A RXRDYA/LD1A Pin Function Select Bit
Set RxRdyEnA = 1 to enable the receiver-data-ready interrupt
functionality on the RXRDYA/LD1A pin. In this mode, RXRDYA/LD1A
asserts when the RDataRdyA bit is set. The RXRDYA/LD1A pin is not
affected by the RxDaRdyIntEnA interrupt mask.
Set RxRdyEnA = 0 to enable the LED driver function on RXRDYA/LD1A.
2
1
0
Trigger Register [0x0F]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
—
—
—
—
Trigger3
Trigger2
Trigger1
Trigger0
READ/WRITE
—
—
—
—
W
W
W
W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
—
—
—
—
N
N
N
N
BIT
NAME
7:4
—
3:0
www.maximintegrated.com
Trigger[3:0]
DESCRIPTION
These bits are not used.
SPI Trigger Start Transmission Bits
When the SPI master writes a vlue into the trigger register that matches the
assigned value in the TrigAssignA/TrigAssignB registers, the MAX14819/
MAX14819A immediately starts the cycle timer for the matching channel(s)
(if enabled), and starts sending the master message.
Note that writing to the trigger register is a global SPI write. Data written to
the trigger register is not filtered by the SPI address and is written into the
trigger reigster of each MAX14819/MAX14819A device connected to the
common SPI bus.
Maxim Integrated │ 52
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQCfgA Register [0x10]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
IEC3ThA
SourceSinkA
SinkSelA1
SinkSelA0
NPNA
PushPulA
DrvDisA
CQFilterEnA
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
7
NAME
DESCRIPTION
IEC3ThA
Channel A IEC61131-2 Type2/3 Threshold Select
Set IEC3ThA = 0 for IO-Link operation and to select IEC61131-2 type 1
thresholds in SIO digital input mode. Set IEC3ThA = 1 to enable type 2/3
thresholds on receiver CQA, if desired for SIO digital input operation.
SourceSinkA
Channel A CQ Current Sink or Source Select
Set SourceSinkA = 1 to enable the internal current source on CQA. Set
SourceSinkA = 0 to enable the internal current sink on CQA. Select the
current level with the SinkSelA[1:0] bits.
5:4
SinkSelA[1:0]
Channel A CQ Sink/Source Current Level Select
Set the SinkSelA[1:0] bits to enable/disable and select the current level of
the internal current sink or source on CQA:
00: Current sink/source OFF
01: 5mA
10: 2mA
11: 150μA
3
NPNA
Channel A CQ Driver NPN/PNP Mode Select
Set NPNA = 1 to configure the CQA driver in NPN mode. Set NPNA = 0 to
configure the CQA driver in PNP mode. NPNA is ignored if PushPulA = 1.
2
PushPulA
Channel A CQ Driver Push-Pull Mode Select
Set PushPulA = 1 to configure the CQA driver in push-pull mode required
for IO-Link operation. Set PushPulA = 0 for open-drain operation (NPN or
PNP) on the CQA driver.
1
DrvDisA
Channel A CQ Driver Disable
Set DrvDisA = 1 to disable the CQA driver. CQA is high impedance when
disabled. Set DrvDisA = 0 to enable the CQA driver.
CQFilterEnA
Channel A CQ Glitch Filter Enable
Set CQFilterEnA = 1 to enable the glitch filter on the CQA receiver. This
is useful for burst filtering. Transients longer than 1.3µs (typ) are ignored
when the glitch filter is enabled.
6
0
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Maxim Integrated │ 53
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CQCfgB Register [0x11]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
IEC3ThB
SourceSinkB
SinkSelB1
SinkSelB0
NPNB
PushPulB
DrvDisB
CQFilterEnB
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
7
NAME
IEC3ThB
DESCRIPTION
Channel B IEC61131-2 Type2/3 Threshold Select
Set IEC3ThB = 0 for IO-Link operation and to select IEC61131-2 type 1
thresholds in SIO digital input mode. Set IEC3ThB = 1 to enable type 2/3
thresholds on receiver CQB, if desired for SIO digital input operation.
SourceSinkB
Channel B CQ Current Sink or Source Select
Set SourceSinkB = 1 to enable the internal current source on CQB. Set
SourceSinkB = 0 to enable the internal current sink on CQB. Select the
current level with the SinkSelB[1:0] bits.
5:4
SinkSelB[1:0]
Channel B CQ Sink/Source Current Level Select
Set the SinkSelB[1:0] bits to enable/disable and select the current level of
the internal current sink or source on CQB:
00: Current sink/source OFF
01: 5mA
10: 2mA
11: 150μA
3
NPNB
Channel B CQ Driver NPN/PNP Mode Select
Set NPNB = 1 to configure the CQB driver in NPN mode. Set NPNB = 0 to
configure the CQB driver in PNP mode. NPNB is ignored if PushPulB = 1.
2
PushPulB
Channel B CQ Driver Push-Pull Mode Select
Set PushPulB = 1 to configure the CQB driver in push-pull mode required
for IO-Link operation. Set PushPulB = 0 for open-drain operation (NPN or
pnp) on the CQB driver.
1
DrvDisB
Channel B CQ Driver Disable
Set DrvrDisB = 1 to disable the CQB driver. CQB is high impedance when
disabled. Set DrvrDisB = 0 to enable the CQB driver.
6
0
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CQFilterEnB
Channel B CQ Glitch Filter Enable
Set CQFilterEnB = 1 to enable the glitch filter on the CQB receiver. This
is useful for burst filtering. Transients longer than 1.3µs (typ) are ignored
when the glitch filter is enabled.
Maxim Integrated │ 54
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CyclTmrA Register [0x12]
BIT
BIT 7
BIT 6
BIT 5
BIT NAME
TCyclBsA1
TCyclBsA0
TCyclMA5
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
BIT 4
BIT 3
BIT 2
BIT 1
TCyclMA4 TCyclMA3 TCyclMA2 TCyclMA1
NAME
BIT 0
TCyclMA0
DESCRIPTION
7:6
TCyclBsA[1:0]
Channel A Cycle Time-Base Select
Set the TCyclBsA[1:0] bits to select the cycle time base for channel A
IO-Link communication. The cycle timer is enabled by setting the
CyclTmrEnA bit in the CQCntrlA register. See Table 2.
5:0
TCyclMA[5:0]
Channel A Cycle Time Multipler
Set the TCyclMA bits to select the cycle time multiplier for channel A
communication. ee Table 2.
Table 2. Cycle Time-Base Selection
TCyclBs_[1:0]
TIME BASE
CALCULATION
CYCLE TIME
00
0.1ms
TCyclMA x Time Base
0.4ms to 6.3ms
01
0.4ms
6.4ms + TCyclMA x Time Base
6.4ms to 31.6ms
10
1.6ms
32ms + TCyclMA x Time Base
32ms to 132.8ms
11
N/A
N/A
N/A
www.maximintegrated.com
Maxim Integrated │ 55
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
CyclTmrB Register [0x13]
BIT
BIT 7
BIT 6
BIT 5
BIT NAME
TCyclBsB1
TCyclBsB0
TCyclMB5
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
BIT 4
BIT 3
BIT 2
BIT 1
TCyclMB4 TCyclMB3 TCyclMB2 TCyclMB1
NAME
BIT 0
TCyclMB0
DESCRIPTION
Channel B Cycle Time-Base Select
7:6
TCyclBsB[1:0]
5:0
TCyclMB[5:0]
Set the TCyclBsB[1:0] bits to select the cycle time base for channel B
communication. The cycle timer is enabled by setting the CyclTmrEnB bit in the
CQCntrlB register. See Table 2.
Channel B Cycle Time Multipler
Set the TCyclMB bits to select the cycle time multiplier for channel B communication. See Table 2.
DeviceDlyA Register [0x14]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
DelayErrA
BDelayA1
BDelayA0
DDelayA3
READ/WRITE
DDelayA2
DDelayA1
DDelayA0
RspnsTmrEnA
R
R/W
R/W
R/W
POR STATE
R/W
R/W
R/W
R/W
0
0
0
0
RESET UPON READ
0
0
0
0
Y
N
N
N
N
N
N
N
BIT
7
6:5
4:1
0
www.maximintegrated.com
NAME
DESCRIPTION
DelayErrA
Channel A Delay Error
This bit is set when the device message is not received within the
programmed delay time. DelayErrA triggers a RxErrorA interrupt when set.
This bit is cleared when the DevDlyA register is read.
BDelayA[1:0]
Channel A Additional Byte Delay
Set the BDelayA[1:0] bits to allow additional time between the device UART
bytes, on top of the worst case delay defined by the IO-Link standard. The
maximum additional delay is 3 bit intervals.
DDelayA[3:0]
Channel A Additional Device Message Delay
Set the DDelayA[3:0] bits to allow additional time to the expected device
message response delay, on top of the worst case delay defined in the
IO-Link standard of 10 bits. The maximum additional delay is 15 bit intervals.
Set DDelayA = 1 for IO-Link compliance.
RspnsTmrEnA
Channel A Response Timer Enable
Set RspnsTmrEnA = 1 to enable monitoring of the device message delay
from the last stop bit of the message transmitted by the master. If the delay
is longer than the expected delay, an RxErrorA interrupt is generated.
DelayErrA is set if the IO-Link device takes a longer than usual response
time or interpacket delay.
Set RspnsTmrEnA = 0 to disable this device message delay monitoring.
When RspnsTmrEnA = 0, DelayErrA is always 0.
Maxim Integrated │ 56
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DeviceDlyB Register [0x15]
BIT
BIT 7
BIT 6
BIT NAME
DelayErrB
BDelayB1
READ/WRITE
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
Y
N
N
N
N
N
N
N
BIT
7
6:5
4:1
0
www.maximintegrated.com
NAME
BIT 5
BIT 4
BDelayB0 DDelayB3
BIT 3
DDelayB2
BIT 2
BIT 1
BIT 0
DDelayB1 DDelayB0 RspnsTmrEnB
DESCRIPTION
DelayErrB
Channel B Delay Error
This bit is set when the device message is not received within the programmed delay time. DelayErrB triggers a RxErrorB interrupt when set.
This bit is cleared when the DevDlyB register is read.
BDelayB[1:0]
Channel B Additional Byte Delay
Set the BDelayB[1:0] bits to allow additional time b etween the device
UART bytes, on top of the worst case delay defined by the IO-Link standard. The maximum additional delay is 3 bit intervals.
DDelayB[3:0]
Channel B Additional Device Message Delay
Set the DDelayB[3:0] bits to allow additional time to the expected device
message response delay, on top of the worst case delay defined in the
IO-Link standard of 10 bits. The maximum additional delay is 15 bit
intervals.
Set DDelayB = 1 for Io-Link compliance.
RspnsTmrEnB
Channel B Response Timer Enable
Set RspnsTmrEnB = 1 to enable monitoring of the device message delay
from the last stop bit of the message transmitted by the master. If the delay is longer than the expected delay, an RxErrorB interrupt is generated.
DelayErrB is set if the IO-Link device takes a longer than usual response
time or interpacket delay.
Set RspnsTmrEnB = 0 to disable this device message delay monitoring.
When RspnsTmrEnB = 0, DelayErrB is always 0.
Maxim Integrated │ 57
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
TrigAssgnA Register [0x16]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
TrigA3
TrigA2
TrigA1
TrigA0
—
—
—
TrigEnA
READ/WRITE
R/W
R/W
R/W
R/W
R
R
R
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
—
—
—
N
BIT
7:4
NAME
TrigA[3:0]
DESCRIPTION
Channel A Transmission Trigger
Set the TrigA[3:0] bits to assign one of 16 possible trigger values to the
CQA transmitter. When the same trigger value is subsequently written by
the SPI master to the trigger register, the master message is immediately
sent from TxFIFOA and the cycle timer is started (if previously enabled).
Trigger 0000 is a global trigger value and is associated with both CQA
and CQB by default, this cannot be changed.
6:1
0
www.maximintegrated.com
—
TrigEnA
These bits are not used
Channel A Tranmission Triggering Enable
Set TrigEnA = 1 to enable SPI based master message triggering/
synchronization on Channel A. Set TrigEnA = 0 to disable transmitter
triggering. When TrigEnA = 0, the bits in TrigA[3:0] are ignored.
Maxim Integrated │ 58
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
TrigAssgnB Register [0x17]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
TrigB3
TrigB2
TrigB1
TrigB0
—
—
—
TrigEnB
READ/WRITE
R/W
R/W
R/W
R/W
R
R
R
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
—
—
—
N
BIT
NAME
7:4
DESCRIPTION
Channel B Transmission Trigger
Set the TrigB[3:0] bits to assign one of 16 possible trigger values to the
CQB transmitter. When the same trigger value is subsequently written by
the SPI master to the trigger register, the master message is immediately
sent from TxFIFOB and the cycle timer is started (if previously enabled).
TrigB[3:0]
Trigger 0000 is a global trigger value and is associated with both CQA
and CQB by default, this cannot be changed.
6:1
These bits are not used.
—
0
Channel B Tranmission Triggering Enable
Set TrigEnB = 1 to enable SPI based master message triggering/
synchronization on Channel B. Set TrigEnB = 0 to disable transmitter
triggering. When TrigEnB = 0, the bits in TrigB[3:0] are ignored.
TrigEnB
L+CnfgA Register [0x18]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT NAME
L+RTA1
L+RTA0
L+DynBLA
L+BLA1
L+BLA0
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
7:6
NAME
L+RTA[1:0]
BIT 2
BIT 1
L+CL2xA L+CLimDisA
BIT 0
L+EnA
R/W
DESCRIPTION
Channel A L+ Sensor Supply Current-Limit Autoretry Period
Set the L+RTA[1:0] bits to select the current-limit autoretry period:
00: Latchoff, no autoretry
01: 400ms
10: 4s
11: 12s
Latchoff is used for controller-managed timing.
www.maximintegrated.com
Maxim Integrated │ 59
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
L+CnfgA Register [0x18] (continued)
BIT
5
4:3
NAME
DESCRIPTION
L+DynBLA
Channel A L+ Dynamic Blanking Time Enable/Disable
Set L+DynBLA = 1 to enable the blanking time reduction when the L+A
voltage is below the L+ power-good falling threshold. This option allows
the circuit to reduce the energy dissipated in the external PMOS2 in case
of a shorted output, keeping the current constant.
The dynamic blanking time is limited, dependent on the L+ voltage:
• Blanking time is reduced to 1/2 programmed time when
9V (typ) ≤ VL+ ≤ 17V (typ)
• Blanking time is reduced to 1/4 programmed time when
VL+ < 9V (typ)
L+BLA[1:0]
Channel A L+ Sensor Supply Current Blanking Time
Set the L+BLA[1:0] bits to set the current-limit blanking time for the L+A
sensor supply:
00: 5.5ms
01: 16.5ms
10: 55ms
11: 165ms
Longer blanking times allow for charging of larger capacitive loads.
When selecting the blanking time, consider the power ratings of the
external PMOS2 transistors used in the L+A supply line. The VDS on
these transistors linearly reduces during capacitive load charge-up. The
time to charge a capacitive load is proportional to the maximum current
during blanking time.
2
1
0
www.maximintegrated.com
L+CL2xA
L+CLimDisA
L+EnA
Channel A L+Double Current Limit Enable/Disable
Set L+CL2xA = 1 to enable twice the current set by the current-limit
resistor when the L+A voltage is higher than 18V. Set L+CL2xA = 0 to
operate the L+A sensor supply with the normal current-limit threshold.
Channel A L+Supply Current Limit Enable/Disable
Set L+CLimDisA = 1 to disable current limiting on the L+A sensor supply.
This disables the internal current-sense amplifier.
Set L+CLimDisA = 0 to enable current limiting on L+A. The current limit is
set by the sense resistor connected between the Channel A pMOSFETs.
Channel A L+Supply Enable
Set the L+EnA = 1 to enable the L+A sensor supply. This turns on the
PMOS2 G2A gate driver.
When L+EnA is set to 0, the current-limit timers (autoretry, latchoff, and
blanking timers) are reset. Set L+EnA = 0 long enough to allow the
external PMOS to cool, if needed.
Short pulses on L+EnA (less than 200μs) are ignored.
Maxim Integrated │ 60
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
L+CnfgB Register [0x19]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT NAME
L+RTB1
L+RTB0
L+DynBLB
L+BLB1
L+BLB0
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
7:6
NAME
L+RTB[1:0]
BIT 2
BIT 1
L+CL2xB L+CLimDisB
BIT 0
L+EnB
DESCRIPTION
Channel B L+ Sensor Supply Current-Limit Autoretry Period
Set the L+RTB[1:0] bits to select the current-limit autoretry period:
00: Latchoff, no autoretry
01: 400ms
10: 4s
11: 12s
Latchoff is used for controller-managed timing.
5
4:3
L+DynBLB
L+BLB[1:0]
Channel B L+ Dynamic Blanking Time Enable/Disable
Set L+DynBLB = 1 to enable the blanking time reduction when the L+B
voltage is below the L+ power-good falling threshold. This option allows
the circuit to reduce the engery dissipated in the external PMOS2 in case
of a shorted output, keeping the current constant.
The dynamic blanking time is limited, dependent on the L+ voltage:
• Blanking time is reduced to 1/2 programmed time when
9V (typ) ≤ VL+ ≤ 17V (typ)
• Blanking time is reduced to 1/4 programmed time when
VL+ < 9V (typ)
Channel B L+ Sensor Supply Current Blanking Time
Set the L+BLB[1:0] bits to set the current-limit blanking time for the L+B
sensor supply:
00: 5.5ms
01: 16.5ms
10: 55ms
11: 165ms
Longer blanking times allow for charging of larger capacitive loads.
When selecting the blanking time, consider the power ratings of the
external PMOS2 transistors used in the L+B supply line. The VDS on
these transistors linearly reduces during capacitive load charge-up. The
time to charge a capacitive load is proportional to the maximum current
during blanking time.
www.maximintegrated.com
Maxim Integrated │ 61
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
L+CnfgB Register [0x19] (continued)
BIT
2
1
0
www.maximintegrated.com
NAME
DESCRIPTION
L+CL2xB
Channel B L+ Double Current-Limit Enable/Disable Set L+CL2xB = 1
to enable twice the current set by the current-limit resistor when the L+B
voltage is higher than 18V. Set L+CL2xB = 0 to operate the L+B sensor
supply with the normal current-limit threshold.
L+CLimDisB
Channel B L+ Supply Current-Limit Enable/Disable
Set L+CLimDisB = 1 to disable current limiting on the L+B sensor supply.
This disables the internal current-sense amplifier.
Set L+CLimDisB = 0 to enabled current limiting on L+B. The current limit
is set by the sense resistor connected between the Channel B
pMOSFETs.
L+EnB
Channel B L+ Supply Enable
Set the L+EnB = 1 to enable the L+B sensor supply. This turns on the
G2B gate driver.
When L+EnB is set to 0, the current-limit timers (autoretry, latchoff, and
blanking timers) are reset. Set L+EnB = 0 long enough to allow the
external PMOS to cool, if needed.
Short pulses on L+EnB (less than 200μs) are ignored.
Maxim Integrated │ 62
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
IOStCfgA Register [0x1A]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT NAME
DiLevelA
CQLevelA
TxEnA
TxA
BIT 3
BIT 2
BIT 1
READ/WRITE
R
R
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
DiFilterEnA DiEC3ThA DiCSourceA
BIT
NAME
7
DiLevelA
Channel A DIA Logic Level
This bit is set when DIA = high. This bit is 0 when DIA = low.
6
CQLevelA
Channel A CQA Logic Level
This bit is set when CQA = high. This bit is 0 when CQA = low.
5
TxEnA
4
TxA
BIT 0
DiCsinkA
DESCRIPTION
Channel A CQ Transmitter Enable Input
When TXTXENDis = 1, this bit has the same functionality as the TXENA
input. When TXTXENDis = 0, this bit is ignored.
Channel A CQ Transmitter Input
When TXTXENDis = 1, this bit has the same functionality as the TXA
input. When TXTXENDis = 0, this bit is ignored.
3
DiFilterEnA
Channel A DI Glitch Filter Enable/Disable
Set DiFilterEnA = 1 to enable the glitch filter on DIA. Set DiFilterEnA = 0
to disable the glitch filter. Transients longer than 1.3µs (typ) are ignored
when the glitch filter is enabled.
2
DiEC3ThA
Channel A IEC61131-2 Type2/3 Threshold Select
Set DiEC3ThA = 1 to enable type 2/3 thresholds on the DIA receiver. Set
DiEC3ThA = 0 to enable type 1 threholds on the DIA receiver.
1
DiCSourceA
Channel A DI Current Source Enable/Disable
Set DiCSourceA = 1 to enable the 2mA (typ) current source on DIA. Set
DiCSourceA = 0 to disable the current source.
0
DiCSinkA
www.maximintegrated.com
Channel A DI Current Sink EnableDisable
Set DiCSinkA = 1 to enable the 2mA (typ) current sink on DIA. Set
DiCSinkA = 0 to disable to current sink.
Maxim Integrated │ 63
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
IOStCfgB Register [0x1B]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT NAME
DiLevelB
CQLevelB
TxEnB
TxB
BIT 3
BIT 2
BIT 1
READ/WRITE
R
R
R/W
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
DiFilterEnA DiEC3ThA DiCSourceA
BIT
NAME
7
DiLevelB
Channel A DIA Logic Level
This bit is set when DIB = high. This bit is 0 when DIB = low.
6
CQLevelB
Channel A CQA Logic Level
This bit is set when CQB = high. This bit is 0 when CQB = low.
5
TxEnB
4
TxB
BIT 0
DiCsinkB
DESCRIPTION
Channel A CQ Transmitter Enable Input
When TXTXENDis = 1, this bit has the same functionality as the TXENB
input. When TXTXENDis = 0, this bit is ignored.
Channel B CQ Transmitter Input
When TXTXENDis = 1, this bit has the same functionality as the TXB
input. When TXTXENDis = 0, this bit is ignored.
3
DiFilterEnB
Channel B DI Glitch Filter Enable/Disable
Set DiFilterEnB = 1 to enable the glitch filter on DIB. Set DiFilterEnB = 0
to disable the glitch filter. Transients longer than 1.3µs (typ) are ignored
when the glitch filter is enabled.
2
DiEC3ThB
Channel B IEC61131-2 Type2/3 Threshold Select
Set DiEC3ThB = 1 to enable type 2/3 thresholds on the DIB receiver. Set
DiEC3ThB = 0 to enable type 1 thresholds on the DIB receiver.
1
DiCSourceB
Channel B DI Current Source Enable/Disable
Set DiCSourceB = 1 to enable the 2mA (typ) current source on DIB. Set
DiCSourceB = 0 to disable the current source.
0
DiCSinkB
www.maximintegrated.com
Channel B DI Current Sink EnableDisable
Set DiCSinkB = 1 to enable the 2mA (typ) current sink on DIB. Set
DiCSinkB = 0 to disable to current sink.
Maxim Integrated │ 64
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
DrvrCurrLim Register [0x1C]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
CL1
CL0
CLDis
CLBL1
CLBL0
TAr1
TAr0
ArEn
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
BIT
7:6
5
4:3
NAME
DESCRIPTION
CL[1:0]
CQA and CQB Driver Current-Limit Selection
Set the CL[1:0] bits to set the current limit for the CQA and CQB drivers
when CLDis = 0:
00: 100mA
01: 200mA
10: 300mA
11: 500mA
CLDis
CQA and CQB Driver Current Enable/Disable
Set CLDis = 1 to disable current limiting on the CQA and CQB drivers.
Set CLDis = 0 to enable current limiting on the CQA and CQB driver.
When CLDis = 0, the CQA and CQB driver current limit is set by the
CL[1:0] bits.
CLBL[1:0]
Blanking Time Selection
Set the CLBL[1:0] bits to set the blanking time on the CQA and CQB
drivers before a fault is indicated:
00: 128μs
01: 500μs
10: 1ms
11: 5ms
The blanking time affects the maximum capacitive and incandescent lamp
load that can be driven without triggering the fault signal. In order to drive
very large capacitive or lamp loads, increase the blanking time and/or
disable the autoretry timeout.
2:1
0
www.maximintegrated.com
TAr[1:0]
Autoretry Timeout Selection
When a fault is detected on a driver output, the driver is disabled for the
autoretry timeout. The driver is reenabled following the autoretry timeout.
Set the TAr[1:0] bits to select the autoretry timeout:
00: 50ms
01: 100ms
10: 200ms
11: 500ms
ArEn
Autoretry Enable/Disable
Set ArEn = 1 to enable autoretry functionality when a fault condition occurs
on CQA or CQB. When a fault is detected on a driver, the driver is disabled
for the autoretry fixed off time (set in the TAr[1:0] bits). The driver is
reenabled and, following the blanking time, is rechecked. If the fault
persists, the fault bit is left set and the driver is disabled again.
When the fault is removed, the status bit is reset and the driver returns to
normal operation.
Maxim Integrated │ 65
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Clock Register [0x1D]
BIT
BIT NAME
READ/WRITE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VCCWarnEn
TXTXENDis
ExtClkMis
ClkOEn
ClkDiv1
ClkDiv0
ExtClkEn
XtalEn
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
NAME
DESCRIPTION
VCCWarnEn
VCC Warning Interrupt Enable
Set VCCWarnEn = 1 to enable the StatusInt interrupt when VCC drops
below the 18V (typ) VCC warning threshold. When VCCWarnEn = 0,
the VCCWarn bit in the Status register is active, but does not generate
a StatErrInt interrupt when the VCC voltage drops below 18V (typ).
TXTXENDis
CQ_ Pin Control Enable/Disable
Set TXTXENDis = 1 to disable the external TX_ and TXEN_ input pins
and to enable control of the CQ_ outputs through the Tx_ and TxEn_
bits in the IOStCfgA and IOStCfgB registers.
5
ExtClkMis
This bit is set when the external clock or crystal oscillator is not operational. When the external clock source (either crystal oscillator or the
external clock on CLKI) fails, the internal clock takes over and the ExtClkMis bit is set. Wait 100ms after startup before reading ExtClkMis.
4
ClkOEn
Clock Output Pin (CLKO) Enable/Disable
Set ClkOEn = 1 to enable the 3.686MHz output clock on the CLKO pin.
ClkDiv[1:0]
External Crystal Frequency Divider
Set the ClkDiv[1:0] bits to select the frequency divider quotient related
to the external crystal frequency:
00: 14.745MHz
01: 7.373MHz
10 and 11: 3.686MHz
ExtClkEn
External Clock Input Enable/Disable
Set ExtClkEn = 1 to enable clocking from the CLKI input. XtalEn must
be set to 0 when ExtClkEn is 1.
Set ExtClkEn = 0 and XtalEn = 0 when the internal framer and neither
the external clock, nor external crystal, are not used.
XtalEn
Crystal Oscillator Enable/Disable
Set XtalEn = 1 to enable the internal crystal oscillator. ExtClkEn must
be set to 0 when XtalEn is 1.
Set XtalEn = 0 and ExtClkEn = 0 when the internal framer and neither
the external clock, nor external crystal, are not used.
7
6
3:2
1
0
www.maximintegrated.com
Maxim Integrated │ 66
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Status Register [0x1E]
BIT
BIT NAME
BIT 7
BIT 6
BIT 5
BIT 4
ThShdnCOR ThWarnCOR VCCUVCOR VCCWarnCOR
BIT 3
BIT 2
BIT 1
BIT 0
ThShdn
ThWarn
VCCUV
VCCWarn
READ/WRITE
R
R
R
R
R
R
R
R
POR STATE
0
0
0
0
0
0
0
0
RESET UPON READ
Y
Y
Y
Y
N
N
N
N
BIT
7
6
5
4
NAME
DESCRIPTION
ThShdnCOR
Clear-On-Read Thermal Shutdown
Clear-on-read version of the ThShdn bit. This bit is set only when the
ThShdn bit transitions from 0 to 1. A StatusInt interrupt is generated when
this bit is set.
This bit is cleared when Status register is read.
ThWarnCOR
Clear-On-Read Die Temperature Warning
Clear-on-read version of the ThWarn bit. This bit is set only when the
ThWarn bit transitions from 0 to 1. A StatusInt interrupt is generated when
this bit is set.
This bit is cleared when the Status register is read.
VCCUVCOR
Clear-On-Read VCC Undervoltage Warning
Clear-on-read version of the VCCUV bit. This bit is set only when the
VCCUV bit transitions from 0 to 1. A StatusInt interrupt is generated when
this bit is set.
This bit is cleared when the Status register is read.
VCCWarnCOR
Clear-On-Read VCC Supply Voltage Warning
Clear-on-read version of the VCCWarn bit. This bit is set only when the
VCCWarn bit transitions from 0 to 1. A StatusInt interrupt is generated
when this bit is set, if enabled by setting the VccWarnEn bit.
This bit is cleared when the Status register is read.
ThShdn
Thermal Shutdown
This bit is set when the die temperature reaches 150°C and the die enters
thermal shutdown. This bit is cleared when the die temperature falls and
the part is no longer in thermal shutdown.
2
ThWarn
Die Temperature Warning
This bit is set when the die junction temperature exceeds the 135°C
warning threshold. This bit is cleard when the die temperature falls below
120°C.
1
VCCUV
VCC Undervoltage
This bit is set when the VCC voltage falls below 9V (typ). It is cleared when
the VCC voltage rises above 9V (typ).
0
VCCWarn
3
www.maximintegrated.com
VCC Supply Voltage Warning
This bit is set when the VCC voltage falls below 18V (max). It is cleared
when the VCC voltage rises above 15.5V (min).
Maxim Integrated │ 67
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
RevID Register [0x1F]
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT NAME
—
—
—
—
ID3
ID2
ID1
ID0
READ/WRITE
R
R
R
R
R
R
R
R
POR STATE (MAX14819)
0
0
0
0
1
0
1
0
POR STATE (MAX14819A)
0
0
0
0
1
1
1
0
RESET UPON READ
N
N
N
N
N
N
N
N
BIT
NAME
[7:4]
—
[3:0]
DESCRIPTION
These bits are not used.
CHIP ID Bits
These bits are ready only. They reflect the current revision of the MAX14819/
MAX14819A. The RevID register is meant for use during system/chip
initialization and should not be used during IO-Link communication, since a
byte may be lost in the RxFIFOA. The RevID register is 0b00001010 for the
MAX14819 and 0b00001110 for the MAX14819A.
ID[3:0]
The MAX14819/MAX14819A continues to operate normally
unless the die temperature reaches the +160°C (typ) thermalshutdown threshold, at which time the device enters
thermal shutdown.
Applications Information
The Microcontroller Interface
Logic-Level I/Os
The logic levels of the microcontroller interface I/Os are
defined by VL. Apply a supply voltage between 1.62V
and 5.5V to VL for normal operation. Logic outputs are
supplied by VL.
Efficient Microcontroller Interface Management
When the MAX14819/MAX14819A receives the device
responsemessage completely and error-free, an SPI
CYCLE TIMER
RxDataRdy_ interrupt is generated and IRQ asserts. If
enabled, the hardware interrupt (RXRDY_/LD1_) also
asserts. When the SPI master receives the interrupt and
then reads out the device message from the RxFIFO_, the
RxDataRdy_ bit and RXRDY_/LD1_ pin interrupts are then
automatically cleared.
If the device message is received by the MAX14819/
MAX14819A with errors or not in time, then an RxError_
interrupt occurs (IRQ asserts) and optionally, the RXERR_/
LD2_ hardware interrupt also asserts if enabled. The
MAX14819/MAX14819A can be configured to delete the
device message under these circumstances and resend
the master message with the SPI controller managing
the process. The SPI controller is required only when the
device message is ready and the MAX14819/MAX14819A
is ready for the next master message (Figure 19).
START CYCLE
(N+1)
START CYCLE
N
MASTER MESSAGE ON CQ_
DEVICE RESPONSE ON CQ_
TxFIFO
Write
RxFIFO
TxFIFO
READ
WRITE
CONTROLLER SPI ACTIVITY
RxDataRdy_
INTERRUPT
Figure 19. IO-Link Cycle Timing
www.maximintegrated.com
Maxim Integrated │ 68
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Quartz Crystal Selection
The crystal should have a frequency of either 3.6864MHz,
7.3728MHz, or 14.7456MHz. Select a crystal with an
equivalent series resistance (ESR), including stray resistances, less than 75Ω (max).
as a result of L+ output short-circuit for the length of the
programmed blanking time.
Because the PMOS1_ transistor is not a part of the
current-limiting circuitry, it does not dissipate as much
heat as PMOS2_ during a short-circuit event.
The crystal oscillator drives the crystal with a power limited
to 70μW (max) power dissipation in the crystal based on a
14.7456MHz frequency, 8pF (max) shunt capacitance, and
75Ω equivalent series resistance.
Ensure that the PMOS1_ and PMOS2_ FETs have gatesource threshold voltages less than 0.8V (VGS(th) <
-0.8V).
The input capacitance of the MAX14819/MAX14819A XIN
and XOUT pins is 10pF, so no external capacitors are
needed if the crystal’s load capacitance is in this range. If
the selected crystal requires higher load capacitance, connect capacitors at XIN and XOUT to GND to make up for
the difference.
Transient Protection
Selecting the pMOS Transistors for
the L+A/L+B Supplies
Select PMOS1_ and PMOS2_ transistors whose drain-tosource current (IDS) carrying capability is higher than the
maximum load current. The maximum load current for an
application is set by the selected current limit resistor and
the L+CL2x_ bits.
It is important to select pMOS FETs with low RDS(ON) to
minimize the I2R heat generation in the module. When
turned on, the PMOS1_ and PMOS2_ gate-to-source voltage (VGS) is driven to -12.5V (typ). Use this bias condition
for selecting the RDS(ON) of the pMOS.
The pMOS transistors need to support the minimum and
maximum voltages expected at the VCC and L+_ terminals. Select the transistor such that the drain-to-source
voltage (VDS) of PMOS1_ FET is able to support the most
negative VCC voltage, while the L+_ supply maintains a
positive voltage (e.g., 28V) due to capacitance on the
line. Similarly, ensure that the VDS of the PMOS2_ FET is
large enough to support the maximum VCC voltage while
L+_ is shorted to the most negative voltage.
When the L+ supply output is shorted to ground or a
negative voltage, the PMOS2_ FET dissipates the maximum heat. The heat energy is determined by the currentlimit current, the on-to-off duty cycle (i.e., blanking time/
autoretry time), and the VDS voltage. Select a PMOS2_
transistor with a low thermal impedance to efficiently
conduct away the heat.
The IO-Link specification requires the L+ sensor supply
be able to supply a minimum of 400mA load current for
50ms after L+ supply turn-on. Hence the blanking time
should be programmed to 55ms or larger. PMOS2 must
be able to dissipate the transient heat pulse produced
www.maximintegrated.com
Examples of suitable pMOS FETs (depending on desired
current limits) are NVMFS5113PL, NTTFS5116PL, and
Si7415DN.
Inductive Loads
Both the CQ_ drivers and the L+_ supplies can drive
and switch inductive loads. External TVS/zener-clamping
diodes are required to clamp the kickback voltage and
absorb energy when inductive loads are driven and fast
turn-off is needed. The clamping voltage must be less
than the Absolute Maximum voltage ratings of the CQA
and CQB pins. In some cases, the EMC protection devices
may be adequate for this purpose.
Surge, Burst, and ESD Protection
The CQ_, DI_, L+, and VCC pins need to be protected
against electrostatic discharge (ESD), electrical fast transients (EFT), and possible surges. The Absolute Maximum
Ratings for these pins is (VCC - 70V) to +65V, providing
significant headroom to allow the use of physically small
protection diodes and higher protection voltages. For standard ESD and burst protection demanded by the IO-Link
specification, small package TVS (like the uClamp3603T
or the SPT01-335) can be used to protect the CQ_, DI,
and L+_ lines. If higher level surge ratings need to be
achieved, such as IEC 61000-4-5 ±1kV/42Ω, PDFN3-32,
SPT02-236, or SMCJ48A, TVS protectors can be used on
CQ_, DI_ and L+. 48V TVS diodes allow for high negative
voltages, making these pins tolerant to negative short circuits and reverse polarity.
For ±500V/2Ω IEC 61000-4-5 surge protection on the
VCC input, Maxim recommends the SM30TY47AY and
SM30TY33AY.
Using a Step-Down Regulator with
the 5V Regulator
To decrease power dissipation in the MAX14819/
MAX14819A, V5 can be powered by an external stepdown regulator. Connect the external regulator’s output
to the V5 input and disable the internal 5V regulator by
connecting REGEN to ground (Figure 20).
Maxim Integrated │ 69
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
24V
1µF
EN/UVLO VIN
1µF
MAX15062B LX
VOUT
33µH
1µF
VCC
GND
5V
10µF
10µF
3.3V
PMOS1A
PMOS2A
VL V5
VCC
G1A
SN1A
1μF
100Ω
0.1µF
SN2A G2A L+A
IRQ
µC
SPI
14.7456MHz
MAX14819
MAX14819A
XI
XO
CQA
330pF
DIA
100Ω
REGEN
CLKO
CLKI A0 A1
5V
TXA
TXENA
GND
RXRDYA/LD1A
RXERRA/LD2A
THE MAX14819/MAX14819A IS A DUAL-CHANNEL MASTER TRANSCEIVER. ONLY ONE CHANNEL IS SHOWN HERE.
OPERATED WITH INTERNAL FAMER.
Figure 20. Using an External 5V Step-Down Regulator
Ordering Information
PART
TEMP RANGE
Chip Information
PIN-PACKAGE
MAX14819ATM+
-40°C to +125°C
48 TQFN-EP*
MAX14819ATM+T
-40°C to +125°C
48 TQFN-EP*
MAX14819AATM+
-40°C to +125°C
48 TQFN-EP*
MAX14819AATM+T
-40°C to +125°C
48 TQFN-EP*
PROCESS: BiCMOS
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
www.maximintegrated.com
Maxim Integrated │ 70
MAX14819/MAX14819A
Dual IO-Link Master Transceiver with Integrated
Framers and L+ Supply Controllers
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/17
PAGES
CHANGED
DESCRIPTION
Initial release
—
1
8/17
Updated/corrected figures and text
1, 2, 8, 23, 26,
28, 39, 40, 45,
46, 52, 53, 62,
63, 69
2
8/18
Updated Absolute Maximum Ratings section, Electrical Characteristics table,
Pin Description table, Framer Communication section, Establish-Communication
Sequencer section, Cycle Timer section, Register Map, and registers
3, 8, 19, 26, 29,
31, 52, 53, 58–
60, 65, 66, 68
2.1
3
Corrected typos
3/30
22
Updated title and added the MAX14819A to all part references in text and figures;
updated General Description, Functional Diagram, Electrical Characteristics, Figure
1, Figure 2, Figure 3, Figure 4, Figure 5, Pin Description, Detailed Description, VCC
Low Voltage and Undervoltage Detection, 5V Linear Regulator, L+ Sensor Supply
Controllers, L+_ Blanking Time and Autoretry Functionality, CQ_ Current Limit and
Thermal Protection, CQ_ Current Sources/Sinks, DI_ Receiver, SPI Interface, SPI
Chip Address (A1, A0), SPI Interface, SPI Chip Address (A1, A0), SPI In-Band IRQ
Interrupt, SPI In-Band Device-Message-Ready Signaling, Table 1, Wake-Up Pulse
Generation, Microcontroller Data Interface, Framer Communication, Frame Handler
FIFOs (TxRxFIFOA/TxRxFIFOB), Transmit/Receive FIFO Data Structure, Loading
the Transmit FIFO (TxFIFO_), Initiating Transmission, Transmit Loopback Check,
Receiving the Device Message, Monitoring Message Timing, Checksum Calculation
and Checking, Establish-Communication Sequencer, Transmitter Synchronization,
Trigger Delay and Synchronization Accuracy, Cycle Timer, Clocking, LED Control,
Thermal Protection, sections; Added Response Time Checking (MAX14819A Only),
and Applications Information, Efficient Microcontroller Interface Management, Quartz
Crystal Selection, Surge, Burst, and ESD Protection, Using a Step-Down Regulator
with the 5V Regulator section, replaced Figure 20 and the Typical Operating Circuit;
added the Response Time Checking (MAX14819A Only); updated Registers
RxFIFOLvlA Register [0x04], RxFIFOLvlB Register [0x05],CQErrA Register [0x08],
CQErrB Register [0x09], MsgCtrlB [0x0B], ChanStatA Register [0x0C], ChanStatB
Register [0x0D], Trigger Register [0x0F], DeviceDlyB Register [0x15], L+CnfgA
Register [0x18], L+CnfgB Register [0x19] and RevID Register [0x1F]
1–71
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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