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MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
General Description
Benefits and Features
The MAX14827A integrates the high-voltage functions
commonly found in industrial sensors, including drivers and regulators. The MAX14827A features two ultra
low-power drivers with active reverse-polarity protection.
Operation is specified for normal 24V supply voltages up
to 60V. Transient protection is simplified due to high voltage tolerance allowing the use of micro TVS.
The device features a flexible control interface. Pincontrol logic inputs allow for operation with switching sensors that do not use a microcontroller. For sensors that
use a microcontroller, an SPI interface is available with
extensive diagnostics. For IO-Link operation, a three-wire
UART interface is provided, allowing interfacing to the
microcontroller UART. Finally, a multiplexed UART/SPI
option allows using one serial microcontroller interface for
shared SPI and UART interfaces.
The device includes on-board 3.3V and 5V linear regulators for low-noise analog/logic supply rails.
The MAX14827A is available in a (4mm x 4mm) 24-pin
TQFN package and a (2.5mm x 2.5mm) 25-pin waferlevel package (WLP) and is specified over the extended
-40°C to +125°C temperature range.
●● Low Power Dissipation for Small Sensors
• 2.3Ω/2.7Ω (typ) Driver On-Resistance
• 70mW (typ) Power Dissipation at 100mA (When
Both C/Q and DO Drivers Are Driving)
●● High Configurability and Integration Reduce SKUs
• Auxiliary 24V Digital Output and Input
• Selectable Driver Current: 50mA to 250mA
• SPI/Pin-Control Interface for Configuration and
Monitoring
• Multiplexed SPI/UART Interface Option
• 5V and 3.3V Linear Regulators
• Optional External Transistor Supports Higher
Regulator Load Capability
• Integrated LED Driver
●● Selectable Driver Integrated Protection Enables
Robust Communication
• 65V Absolute Maximum Ratings on Interface and
Supply Pins Allows for Flexible TVS Protection
• 9V to 60V Specified Operation
• Glitch Filters for Improved Burst Resilience and
Noise
• Thermal Shutdown Auto-Retry Cycling
• Hot-Plug Supply Protection
• Reverse Polarity Protection of All Sensor Interface
Inputs/Outputs
• -40°C to +125°C Operating Temperature Range
Applications
●● Industrial sensors
●● IO-Link sensors and actuators
●● Safety applications
Ordering Information appears at end of data sheet.
Typical Operating Circuit
5V
1µF
3.3V
1µF
10kΩ
VCC
VL
V33
V5
SPI/PIN
GPIO
IRQ/OC
GPO
LED1IN
0.1µF
L+
IRQ
WU
RX
RX
TX
TX
RTS
MAX14827A
GND
TXEN
UARTSEL
LED1
DI/DO
DO
DI
IO-Link is a registered trademark of Profibus User Organization (PNO).
SPI is a trademark of Motorola, Inc.
19-8592; Rev 2; 3/19
V24
SPI
MICROCONTROLLER
GND
REG
C/Q
1kΩ
1
2
4
3
C/Q
L-
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Functional Diagram
LED1 LED2*
LED1IN
VL
V33
3.3V
LDO
LED DRIVER
SPI/PIN
IRQ/OC
CS/PP
SDI/TX/NPN
CLK/TXEN/200MA
SDO/RX/THSH
RX
REG
V5
MAX14827A
V24
5V REG
REV POL
PROTECTION
UVLO
VDRV
CONTROL
AND
MONITOR
PROTECTION
Transceiver
C/Q
TX
TXEN
UARTSEL
WU
WAKE-UP DETECT
LI
DI
VDRV
LO
DRIVER
PROTECTION
DO
GND
* WLP PACKAGE ONLY
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Maxim Integrated │ 2
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Absolute Maximum Ratings
(All voltages referenced to GND, unless otherwise noted.)
V24..........................................................................-70V to +65V
REG...............................................................-0.3V to (V5 + 16V)
V5, VL.......................................................................-0.3V to +6V
V33...............................................................-0.3V to (V5 + 0.3V)
C/Q, DO, DI.................... MIN: larger of -70V and (V24 - 70V) to
MAX: the lower of +70V and (V24 + 70V)
Logic Inputs:
CS/PP, TXEN, TX, LED1IN, LI,
UARTSEL, CLK/TXEN/200MA, SPI/PIN,
SDI/TX/NPN...............................................-0.3V to (VL + 0.3V)
Logic Outputs:
RX, LI, LO WU, SDO/RX/THSH................. -0.3V to (VL + 0.3V)
IRQ/OC...................................................................-0.3V to +6V
LED1, LED2................................................... -0.3V to (V5+0.3V)
Continuous Current Into GND and V24.................................±1A
Continuous Current Into C/Q and DO.............................±500mA
Continuous Current Into V5 and REG.............................±100mA
Continuous Current Into Any Other Pin.............................±50mA
Continuous Power Dissipation
TQFN (derate 27.8mW/°C above +70°C)..................2222mW
WLP (derate 22.7mW/°C above +70°C).....................1816mW
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature.......................Internally Limited
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow, TQFN and WLP)............ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 24 TQFN
Package Code
T2444+4
Outline Number
21-0139
Land Pattern Number
90-0022
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
36°C/W
Junction to Case (θJC)
3°C/W
PACKAGE TYPE: 25 WLP
Package Code
W252L2+1
Outline Number
21-0787
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
44°C/W
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For
detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.maximintegrated.com
Maxim Integrated │ 3
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
DC Electrical Characteristics
(V24 = 9V to 60V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
V24 Supply Voltage
V24 Undervoltage-Lockout
Threshold
V24 Undervoltage-LockoutThreshold Hysteresis
V24 Supply Current
V24 Low-Voltage Warning
Threshold
V5 Supply Voltage
V5 Undervoltage-Lockout
Threshold
V5 Supply Current
SYMBOL
V24
V24UVLO
CONDITIONS
V24 rising
V24 falling
MIN
9
6
6
V24UVLO_HYST
I24
I5_IN
V5 powered externally, REG is
unconnected
VL
VLUVLO
VL Logic-Level Supply Current
IL
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UNITS
V
V
mV
C/Q and DO disabled (CQ_Dis = 1,
DO_Dis = 1)
0.14
0.5
C/Q and DO in pushpull configuration,
CL[10] = 11, C/Q and
DO high, no load on
C/Q or DO
1.1
1.75
C/Q and DO in pushpull configuration,
CL[10] = 11, C/Q and
DO low, no load on
C/Q or DO
1.4
1.8
14.5
16.5
18
V
4.5
2.8
2.8
5.5
4.5
4.5
V
3.5
3.45
0.64
0.9
1.37
1.75
1.41
1.8
1.7
5.5
2.4
V
V
0.25
3
µA
V5 rising
V5 falling
C/Q and DO disabled (CQ_Dis = 1,
DO_Dis = 1), V33
disabled (V33_Dis
= 1)
C/Q and DO in pushpull configuration,
External 5V applied
CL[10] = 11, C/Q
to V5, REG is unconand DO high, V33
nected, no load on
enabled, no load on
LED1 or LED2
C/Q, DO, or V33
C/Q and DO in pushpull configuration,
CL[10] = 11, C/Q
and DO low, V33
enabled, no load on
C/Q, DO, or V33
VL Logic-Level Supply Voltage
VL Undervoltage Threshold
7.8
7.2
MAX
60
9
9
570
V24W
V5UVLO
TYP
All logic inputs at VL or GND, all logic
outputs unconnected
2.5
0.9
mA
V
mA
Maxim Integrated │ 4
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
DC Electrical Characteristics (continued)
(V24 = 9V to 60V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
5V LINEAR REGULATOR/CONTROLLER (V5)
V5 Output Voltage
V5
Load Regulation
ΔV5_LDR
Line Regulation
ΔV5_LNR
REG Output Current
IREG
V24 REG Dropout Voltage
ΔVREG
REG Open Voltage
VREG_OPN
V5 Capacitance
CV5
3.3V LINEAR REGULATOR (V33)
V33 Output Voltage
V33
V33 Load Regulation
V33_LDR
V33 Capacitance
CV33
CONDITIONS
MIN
TYP
MAX
UNITS
REG = V5, no load on V5, 9V ≤ V24 ≤ 60V
REG = V5, 0mA < ILOAD < 30mA, V24 = 24V
REG = V5, ILOAD = 1mA, V24 from 9V to 60V
Internal regulator or external NPN
V24 = 9V, V5 = 4.5V, IREG = 5mA
V24 = 60V, V5 = 4.5V, no load on REG
Allowed capacitance on V5, REG connected to V5 (Note 2)
4.75
5.00
0.02
0.01
5.25
0.2
4
30
No load on V33
0mA < ILOAD < 30mA
Allowed capacitance on V33, V33 enabled (Note 2)
10
2.35
13
16
V
%
mV/V
mA
V
V
0.8
1
2
µF
3.1
0
3.3
0.4
3.5
0.8
V
%
0.8
1
µF
C/Q, DO DRIVER
Driver On-Resistance
Driver Current Limit
Driver Peak Current
C/Q Leakage Current
ROH
ROL
ICL
ICL_PEAK
High-side enabled, V24 = 24V,
CL[10] = 11, ILOAD = -200mA (Note 2)
Low-side enabled, V24 = 24V,
CL[10] = 11, ILOAD = +200mA (Note 2)
CL[10] = 00
SPI/PIN = high, VDRIVCL[10] = 01
ER = (V24 – 3V) or 3V,
CL[10] = 10
CL_Dis = 0
CL[10] = 11
CLK/TXEN/
SPI/PIN = low, VDRIVER 200MA = low
= (V24 – 3V) or 3V
CLK/TXEN/
200MA = high
DC current
C/Q driver is disabled (C/Q_Dis = 1), RX
disabled (Rx_Dis = 1), V24 = 24V, (V24 65V) ≤ VC/Q ≤ +60V
ILEAK_CQ
C/Q driver enabled
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2.65
4.6
2.3
4.45
50
100
200
250
65
120
230
290
80
150
275
350
100
120
150
200
230
275
490
-70
Ω
mA
mA
+10
NPN mode, set to
high impedance (TX
= low), VC/Q = 24V
17.4
PNP mode, set to
high impedance (TX
= high) VC/Q = 0V
0
PNP mode, set to
high impedance (TX
= 0) VC/Q = 24V
22.9
PNP mode, set to
high impedance (TX
= 0) VC/Q = 0V
-43.5
µA
Maxim Integrated │ 5
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
DC Electrical Characteristics (continued)
(V24 = 9V to 60V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
DO Leakage Current
SYMBOL
ILEAK_DO
CONDITIONS
DO driver is disabled (DO_Dis =1), V24 =
24V, (V24 -65V) ≤ VDO ≤ +60V
DO driver enabled
MIN
TYP
-10
MAX
UNITS
+10
NPN mode, set to
high impedance (LO
= low) , VDO = 24V
6.0
PNP mode, set to
high impedance (LO
= high) VDO = 0V
0
µA
PNP mode, set to
high impedance (CQDOPAR = 1, TXEN =
0), VDO = 24V
PNP mode, set to
high impedance (CQDOPAR = 1, TXEN =
0), VDO = 0V
11.6
-42.4
C/Q Output Reverse Current
IREV_CQ
C/Q driver enabled and in push-pull configuration, V24 = 30V, VC/Q = (V24 + 5V)
or (VGND - 5V)
-60
+1000
μA
DO Output Reverse Current
IREV_DO
DO driver enabled and in push-pull configuration, V24 = 30V, VDO = (V24 + 5V)
or (VGND - 5V)
-60
+1000
μA
Weak Pulldown Current
IPD
VDRIVER = 5V,
CQ_WPD = 1,
DO_WPD = 1,
SPI/PIN = high, driv- CQ_WPU = 0,
er disabled (CQ_Dis DO_WPU = 0
= 1, DO_Dis =1)
VDRIVER = 24V,
CQ_WPD = 1,
DO_WPD = 1,
CQ_WPU = 0,
DO_WPU = 0
Weak Pullup Current
IPU
SPI/PIN = high, driver
disabled (CQ_Dis = 1,
DO_Dis = 1),
VDRIVER = V24 - 5V
C/Q, DI RECEIVER
Input Voltage Range
VIN
For valid RX/LI logic
C/Q, DI Input Threshold High
VTH
C/Q, DI Input Threshold Low
VTL
C/Q, DI Input Hysteresis
C/Q Input Capacitance
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VHYS_CQ
CIN_CQ
CQ_WPU = 1,
DO_WPU = 1,
CQ_WPD = 0,
DO_WPD = 0,
V24 > 18V
C/Q driver disabled
V24 < 18V
V24 > 18V
C/Q driver disabled
V24 < 18V
V24 > 18V
C/Q driver disabled
V24 < 18V
Driver disabled, weak pull-up and pulldown disabled, f = 100kHz
200
300
400
μA
200
470
1000
-400
-300
-200
μA
+65
12.5
72
10.5
63
V
V
% of V24
V
% of V24
V
% of V24
V24 – 65
11
59
9
45
11.8
65.5
9.8
54.5
2
11
50
pF
Maxim Integrated │ 6
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
DC Electrical Characteristics (continued)
(V24 = 9V to 60V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
DI Input Capacitance
C/Q Input Current
DI Leakage Current
SYMBOL
CIN_DI
IIN_CQ
ILEAK_DI
CONDITIONS
f = 100kHz
C/Q driver disabled
-5V ≤ VC/Q ≤ (V24 + 5V)
(CQ_Dis = 1), C/Q
receiver enabled,
(V24 - 65V)≤ VC/Q
V24 = 24V
≤ +60V
DI receiver disabled (DI_Dis = 1), V24 =
24V, (V24 - 65V) ≤ VDI ≤ +60V
MIN
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MAX
-10
+30
-70
+70
-40
+150
-5V ≤ VDI ≤ (V24 + 5V)
-10
DI receiver enabled,
V24 = 24V
(V24 - 65V) ≤ VDI ≤
-40
+60V
LOGIC INPUTS (CS/PP, TXEN, TX, LO, LED1IN, CLK/TXEN/200MA, SPI/PIN, SDI/TX/NPN)
Logic Input Voltage Low
VIL
Logic Input Voltage High
VIH
0.8 x VL
Logic Input Leakage Current
ILEAK
Logic input = GND or VL
-1
LOGIC OUTPUTS (RX, LI, WU, IRQ/OC, SDO/RX/THSH)
Logic Output Voltage Low
VOL
IOUT = -5mA
Logic Output Voltage High
VOH
IOUT = 5mA
VL - 0.4
IRQ/OC Open-Drain Leakage
IRQ/OC high impedance,
ILK_OD
-1
Current
IRQ/OC = GND or VL
SPI/PIN = high, CS/PP = high, SDO/RX/
SDO Leakage Current
ILK_SDO
-1
THSH = GND or VL
SPI/PIN = high, DI_Dis = 1,
RX, LI Leakage Current
ILK_RXLI
-1
RX_Dis = 1, RX/LI = GND or VL
LED DRIVERS (LED1, LED2)
LED Output Voltage Low
VLEDOL
IOUT = -5mA
LED Output Voltage High
VLEDOH
IOUT = 10mA
V5 – 0.4
THERMAL MANAGEMENT
Die junction temperature rising,
Thermal Warning Threshold
TWRN
TempW and TempWInt bits are set
Thermal Warning Threshold
Die junction temperature falling,
TWRN_HYS
Hysteresis
TempW bit cleared
Per-Driver Thermal Shutdown
Driver temperature rising, temperature at
TSHUT_D
Temperature
which the driver is turned off
Per-Driver Thermal Shutdown
TSHUT_DHYS Driver temperature falling
Temperature Hysteresis
Die temperature rising, ThShut and
IC Thermal Shutdown
TSHUT_IC
ThuShutInt bits are set
IC Thermal-Shutdown HysDie temperature falling, ThShut bit is
TSHUT_ICHYS
teresis
cleared
DI Input Current
TYP
10
+35
IIN_DI
+200
0.2 x VL
+1
UNITS
pF
µA
µA
µA
V
V
µA
0.4
V
V
+1
μA
+1
µA
+1
µA
0.4
V
V
+140
°C
15
°C
+160
°C
15
°C
+170
°C
15
°C
Maxim Integrated │ 7
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
AC Electrical Characteristics
(V24 = 18V to 30V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Push-pull and PNP configuration, Figure1
0.16
0.4
NPN configuration, Figure 1
0.16
Push-pull and NPN configuration, Figure1
0.28
PNP configuration, Figure 1
0.28
UNITS
C/Q, DO DRIVER
Driver Low-to-High Propagation
Delay
tPDLH_PP
Driver High-to-Low Propagation
Delay
tPDHL_PP
Driver Skew
tSKEW
Push-pull configuration, Figure 1
| tPDLH - tPDHL |
Driver Rise Time
tRISE
Push-pull and PNP configuration, Figure 1
Driver Fall Time
tFALL
Driver Enable Time High
-0.3
0.4
μs
μs
+0.3
μs
0.12
0.4
μs
Push-pull and NPN configuration, Figure 1
0.12
0.4
µs
tENH
Push-pull and PNP configuration, CQDOPar = 1 for DO, Figure 2
0.15
0.4
µs
Driver Enable Time Low
tENL
Push-pull and NPN configuration, CQDOPar = 1 for DO, Figure 3
0.27
0.4
µs
Driver Disable Time High
tDISH
Push-pull and PNP configuration, CQDOPar = 1 for DO, Figure 2
1.8
3
µs
Driver Disable Time Low
tDISL
Push-pull and NPN configuration, CQDOPar = 1 for DO, Figure 3
1.5
3
µs
C/Q, DI RECEIVER (Figure 4)
SPI/PIN = high or low, CQFil = 0
0.85
1.3
2.1
SPI/PIN = high, CQFil = 1
0.2
0.3
0.5
SPI/PIN = high or low, CQFil = 0
0.85
1.3
2.1
SPI/PIN = high, CQFil = 1
0.2
0.3
0.5
tPRLH_DI
1.3
2.2
3.5
µs
tPRHL_DI
1.3
2.2
3.5
µs
C/Q Receiver Low-to-High
Propagation Delay
tPRLH_CQ
C/Q Receiver High-to-Low
Propagation Delay
tPRHL_CQ
DI Receiver Low-to-High Propagation Delay
DI Receiver High-to-Low Propagation Delay
DRIVER CURRENT LIMITING
Blanking Time
tCL_ARBL
SPI/PIN = high
CL_BL[10] = 00
0.128
CL_BL[10] = 01
0.5
CL_BL[10] = 10
1
CL_BL[10] = 11
5
SPI/PIN = low
Autoretry Period
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tCL_ARP
SPI/PIN = high,
ArEn = 1 (Note 3)
µs
µs
ms
0.128
TAr[10] = 00
50
TAr[10] = 01
100
TAr[10] = 10
200
TAr[10] = 11
500
ms
Maxim Integrated │ 8
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
AC Electrical Characteristics (continued)
(V24 = 18V to 30V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
55
66
75
µs
85
95
110
µs
100
200
300
ΜS
WAKE-UP DETECTION (Figure 5)
Wake-Up Input Minimum Pulse
Width
tWUMIN
Wake-Up Input Maximum Pulse
Width
tWUMAX
WU Output Low Time
tWUL
CL = 3nF
Valid wake-up condition on C/Q
SPI TIMING (CS/PP, CLK/TXEN/200MA,SDI,TX/NPN, SDO/RX/THSH) (Figure 6)
Maximum SPI Clock Frequency
12.5
MHz
CLK/TXEN/200MA Clock Period
tCH+CL
80
ns
CLK/TXEN/200MA Pulse-Width
High
tCH
40
ns
CLK/TXEN/200MA Pulse-Width
Low
tCL
40
ns
CS/PP Fall to CLK/TXEN/200MA
Rise Time
tCSS
20
ns
CLK/TXEN/200MA Rise to CS/
PP Rise Hold Time
tCSH
40
ns
SDI/TX/NPN Hold Time
tDH
10
ns
SDI/TX/NPN Setup Time
tDS
25
ns
Output Data Propagation Delay
tDO
20
ns
SDO/RX/THSH Rise and Fall
Times
tFT
20
ns
tCSW
10
ns
Minimum CS/PP Pulse
Note 1: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design.
Note 2: Not production tested. Guaranteed by design.
Note 3: Autoretry functionality is not available in pin-mode.
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Maxim Integrated │ 9
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
V24
TXEN
TXEN
TX, LO
MAX14827A
TX, LO
C/Q, DO
3.3nF
GND
5kΩ
MAX14827A
5kΩ
3.3nF
GND
PUSH-PULL AND PNP MODE
C/Q, DO
NPN MODE
VL
TXEN
0V
VL
TX, LO
50%
50%
tPDHL
90%
C/Q, DO
0V
tPDLH
50%
V24
90%
10%
50%
10%
0V
tFALL
tRISE
Figure 1. C/Q and LO Driver Propagation Delays and Rise/Fall Times
V24
TXEN
VL
TX
MAX14827A
GND
5kΩ
C/Q
3.3nF
VL
TXEN
0V
tDISH
tENL
V24
C/Q
50%
10%
0V
Figure 2. C/Q Driver Enable Low and Disable High Timing with External Pullup Resistor
www.maximintegrated.com
Maxim Integrated │ 10
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
TXEN
TX
MAX14827A
C/Q
GND
3.3nF
5kΩ
VL
TXEN
0V
tDISL
tENH
C/Q
V24
90%
50%
0V
Figure 3. C/Q Driver Enable High and Disable Low Timing
TXEN
MAX14827A
C/Q, DI
GND
RX, LI
15pF
V24
C/Q, DI
50%
50%
0V
tPRHL
tPRLH
RX, LI
VL
50%
50%
0V
Figure 4. C/Q and DI Receiver Propagation Delays
www.maximintegrated.com
Maxim Integrated │ 11
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
TXEN
WU
MAX14827A
TX
C/Q
GND
TXEN
TX
< tWUMIN
NO WAKE-UP
C/Q
tWUMIN < tWU < tWUMAX
WU
tWUL
Figure 5. Wake-Up Detection Timing
CS/PP
tCSH
tCSS
tCL
tCSH
tCH
CLK/TXEN/200MA
tDS
tDH
SDI/TX/NPN
tDO
SDO/RX/THSH
Figure 6. SPI Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 12
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Typical Operating Characteristics
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q and DO in push-pull configuration, TA = +25°C, unless otherwise noted.)
I24 SUPPLY CURRENT
vs. V24 SUPPLY VOLTAGE
3.0
toc01
TA = +125ºC
I24 SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
TA = +25ºC
TA = -40ºC
1.5
1.0
0.0
8
1nF LOAD
7
6
5
4
NO LOAD
3
2
0.5
C/Q AND DO ARE PUSH-PULL
NO SWITCHING: C/Q = HIGH, DO = LOW
6
12
18
24
30
36
42
48
54
C/Q IN PUSH-PULL
DO DISABLED
1
0
60
0
50
SUPPLY VOLTAGE (V)
toc03
OUTPUT VOLTAGE HIGH (V)
I24 SUPPLY CURRENT (mA)
TA = +25ºC
23.5
23.4
0.50
TA = +125ºC
23.3
C/Q IN PUSH-PULL
DO DISABLED
REG UNCONNECTED
V5 = 5V
0.25
50
100
150
200
23.2
23.1
250
23.0
C/Q HIGH-SIDE ENABLED
0
25
50
C/Q SWITCHING RATE (kbps)
C/Q DRIVER OUTPUT LOW
vs. SINK CURRENT
1.0
DO DRIVER OUTPUT HIGH
vs. LOAD CURRENT
24.0
23.9
0.7
toc06
TA = -40ºC
23.8
OUTPUT VOLTAGE HIGH (V)
OUTPUT VOLTAGE LOW (V)
toc05
0.8
23.7
TA = +125ºC
23.6
0.6
TA = +25ºC
0.5
TA = +125ºC
23.5
23.4
0.4
23.3
0.3
0.2
TA = -40ºC
0.1
0.0
75 100 125 150 175 200 225 250
LOAD CURRENT (mA)
C/Q LOW-SIDE ENABLED
0.9
toc04
23.6
NO LOAD
0
250
TA = -40ºC
23.7
1nF LOAD
0.75
200
24.0
23.8
1.00
150
C/Q DRIVER OUTPUT HIGH
vs. LOAD CURRENT
23.9
1.25
0.00
100
C/Q SWITCHING RATE (kbps)
V5 SUPPLY CURRENT
vs. C/Q SWITCHING RATE
1.50
toc02
9
2.5
2.0
I24 SUPPLY CURRENT
vs. C/Q SWITCHING RATE
10
0
25
50
75 100 125 150 175 200 225 250
LOAD CURRENT (mA)
www.maximintegrated.com
TA = +25ºC
23.2
23.1
23.0
DO HIGH-SIDE ENABLED
0
25
50
75 100 125 150 175 200 225 250
LOAD CURRENT (mA)
Maxim Integrated │ 13
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Typical Operating Characteristics (continued)
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q and DO in push-pull configuration, TA = +25°C, unless otherwise noted.)
DO DRIVER OUTPUT LOW
vs. SINK CURRENT
1.00
toc07
0.90
OUTPUT VOLTAGE LOW (V)
0.80
SINK CURRENT (mA)
TA = +125ºC
0.70
0.60
TA = +25ºC
0.50
0.40
0.30
0.20
0.00
300
CL[10] = 11
250
CL[10] = 10
200
150
25
50
CL[10] = 01
100
0
0
75 100 125 150 175 200 225 250
CL[10] = 00
0
6
LOAD CURRENT (mA)
C/Q CURRENT LIMIT
CL[10] = 00
-100
CL[10] = 01
SOURCE CURRENT (mA)
-50
toc09
CL[10] = 10
-250
CL[10] = 11
-300
-350
6
12
18
24
OUTPUT VOLTAGE LOW (V)
toc11
TA = -40ºC
-30
-40
C/Q driver disabled
-10
0
10
20
30
40
50
60
C/Q WEAK PULL-DOWN CURRENT
vs. C/Q VOLTAGE
toc12
900
800
6
PULL-DOWN CURRENT (µA)
LEAKAGE CURRENT (µA)
TA = +25ºC
C/Q VOLTAGE (V)
8
TA = +125ºC
4
2
0
-2
TA = -40ºC and +25ºC
-4
700
600
400
200
0
0
10
20
30
DO VOLTAGE (V)
www.maximintegrated.com
40
50
60
TA = +25ºC
100
-100
-10
TA = -40ºC
300
-8
DO driver disabled
TA = +125ºC
500
-6
-10
toc10
TA = +125ºC
-20
-60
30
DO DRIVER LEAKAGE CURRENT
vs. DO VOLTAGE
10
-10
-50
C/Q IN PUSH-PULL
C/Q IS HIGH
0
30
0
-150
-200
12
18
24
OUTPUT VOLTAGE LOW (V)
C/Q DRIVER LEAKAGE CURRENT
vs. C/Q VOLTAGE
10
LEAKAGE CURRENT (µA)
0
toc08
C/Q IN PUSH-PULL
C/Q IS LOW
50
TA = -40ºC
0.10
C/Q CURRENT LIMIT
350
DO HIGH-SIDE ENABLED
-200
CQ_Dis = 1
CQ_WPD = 1
-10
0
10
20
30
40
50
60
C/Q VOLTAGE (V)
Maxim Integrated │ 14
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Typical Operating Characteristics (continued)
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q and DO in push-pull configuration, TA = +25°C, unless otherwise noted.)
C/Q WEAK PULL-UP CURRENT
vs. C/Q VOLTAGE
500
toc13
40
300
200
TA = +125ºC
100
INPUT CURRENT (µA)
PULL-UP CURRENT (mA)
400
TA = +25ºC
0
-100
TA = -40ºC
-200
-300
-10
0
10
20
30
40
50
60
TA = -40ºC
20
10
TA = +25ºC
0
-20
C/Q receiver enabled
-10
0
10
C/Q VOLTAGE (V)
INPUT CURRENT (µA)
60
30
40
C/Q DRIVER SWITCHING
INTO 1nF LOAD
toc15
50
60
toc16
TX
2V/div
0V
TA = +125ºC
50
VOUTN
40
VINSIDE
TA = +25ºC
30
C/Q
5V/div
VBACKUP
20
10
TA = -40ºC
0
-10
20
INPUT VOLTAGE (V)
DI RECEIVER INPUT
CURRENT vs. INPUT VOLTAGE
70
toc14
TA = +125ºC
30
-10
CQ_Dis = 1
CQ_WPU = 1
-400
-500
C/Q RECEIVER INPUT
CURRENT vs. INPUT VOLTAGE
50
0V
-10
0
10
20
30
40
50
60
INPUT VOLTAGE (V)
C/Q DRIVER SWITCHING
INTO 4.7nF LOAD
C/Q IS PUSH-PULL 10µs/div
CLOAD = 1nF
WAKE-UP DETECTION
toc17
toc18
TX
2V/div
0V
C/Q
5V/div
VOUTN
C/Q
10V/div
VINSIDE
0V
VBACKUP
WU
2V/div
10µs/div
www.maximintegrated.com
0V
0V
TXEN = VL
TX = GND
40µs/div
Maxim Integrated │ 15
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Typical Operating Characteristics
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q and DO in push-pull configuration, TA = +25°C, unless otherwise noted.)
V5 LINEAR REGULATOR
LOAD REGULATION
0.000
toc19
5.058
-0.020
5.056
LOAD REGUIATION (%)
V5 VOLTAGE (V)
-0.010
-0.030
TA = -40ºC
-0.040
-0.050
TA = +125ºC
TA = +25ºC
-0.060
5.052
5.050
5.048
5.046
-0.080
5.044
-0.090
5.042
-0.100
5.040
5
10
15
20
25
30
EXTERNAL NPN TRANSISTOR
CONNECTED TO V5 AND REG
ILOAD = 10mA ON V5
10
20
30
V33 LINEAR REGULATOR
LOAD REGULATION
0.0
toc21
-0.3
LED1 OR LED2 VOLTAGE (V)
LOAD REGUIATION (%)
60
toc22
5.0
-0.2
TA = -40ºC
-0.4
-0.5
TA = +25ºC
-0.6
-0.7
TA = +125ºC
-0.8
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
10
15
20
25
0.0
30
0
2
4
6
LED DRIVER OUTPUT LOW
VOLTAGE vs SINK CURRENT
200
toc23
5.07
V5 VOLTAGE (V)
5.08
140
120
100
80
5.02
20
5.01
www.maximintegrated.com
18
20
toc24
5.04
5.03
6
8 10 12 14
LOAD CURRENT (mA)
16
5.05
40
4
14
5.06
60
2
12
5.09
160
0
10
V5 VOLTAGE vs TEMPERATURE
5.10
LED DRIVER TURNED OFF
180
8
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LED1 OR LED2 VOLTAGE (mV)
50
LED DRIVER OUTPUT HIGH
VOLTAGE vs LOAD CURRENT
5.5
-0.1
0
40
V24 VOLTAGE (V)
LOAD CURRENT (mA)
-0.9
toc20
5.054
-0.070
0
V5 LINEAR REGULATOR
LINE REGULATION
5.060
16
18
20
5.00
ILOAD = 20mA
-45
-20
5
30
55
80
TEMPERATURE (ºC)
105
130
Maxim Integrated │ 16
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
WU
LO
UARTSEL
LI
VL
V33
Pin Configuration
18
17
16
15
14
13
TOP VIEW
LED1IN
19
IRQ/OC
20
SDO/RX/THSH
21
CLK/TXEN/200MA
22
SPI/PIN
23
* EP
MAX14827A
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
A
C/Q
V24
GND
DO
DI
B
V5
REG
LED1
V33
VL
C
TX
TXEN
LED2
UART
SEL
LI
D
RX
SPI/PIN
SDO/RX/
THSH
WU
LO
E
CS/PP
SDI/TX/
NPN
CLK/TXEN/
200MA
IRQ/OC
LED1IN
+
12
DI
11
DO
10
GND
9
V24
8
C/Q
7
LED1
+
4
5
6
V5
REG
RX
3
TX
2
TXEN
1
CS/PP
24
SDI/TX/NPN
WLP
2.5mm x 2.5mm
TQFN
4mm x 4mm
Pin Description
PIN
TQFN
FUNCTION
WLP
NAME
PIN DESCRIPTION
PARALLEL MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = high
SPI chip-select and
UART signal select
input. When CS/PP is
high, the SPI interface
is disabled and UART
interface mode is enabled on the SDO/RX/
THSH, SDI/TX/NPN,
and CLK/TXEN/200MA
logic pins.
1
E1
CS/PP
CS/PP Logic
Input
SPI active-low chipselect input. Drive
CS/PP low to start
the SPI read/write
cycle. Drive CS/PP
high to end the SPI
cycle. UART interface is enabled on
RX, TX, and TXEN.
2
D1
RX
C/Q Receiver
Logic Output
RX is the inverse logic of C/Q. RX can be disabled with the SPI interface. RX is high impedance when Rx_Dis = 1.
www.maximintegrated.com
PIN MODE
(SPI/PIN = Low)
Push-pull select input.
Drive CS/PP high to enable push-pull mode for
the C/Q and DO drivers.
Drive CS/PP low to select
PNP or NPN operation for
the drivers.
RX is the inverse logic of
C/Q. RX is always active.
Maxim Integrated │ 17
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Pin Description (continued)
PIN
TQFN
3
4
FUNCTION
WLP
C2
C1
NAME
TXEN
TX
PIN DESCRIPTION
PARALLEL MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = high
Drive TXEN high
to enable the C/Q
driver. See Table 1.
With CS/PP low and
ENMPX = 0, drive
TXEN high to enable
C/Q.
Drive TXEN high to enable the C/Q driver. Drive
TXEN low to disable the
C/Q driver and enable the
C/Q receiver.
C/Q Driver Communication Input
The logic on the C/Q
output is the inverse
logic level of the signal on the TX input.
See Table 1.
With CS/PP low and
ENMPX = 0, the logic
on the C/Q output is the
inverse logic level of the
signal on the SDI/TX/
NPN input. Signals on
TX are ignored. See the
Mode Selection table.
The logic on the C/Q
output is the inverse logic
level of the signal on the
TX input when TXEN is
high.
C/Q Driver Enable Logic Input
PIN MODE
(SPI/PIN = Low)
5
B1
V5
5V Power-Supply Input/Output
5V must be present on V5 for normal operation. Bypass V5 to GND with a
1μF capacitor. V5 can be supplied by the internal 5V linear regulator or by an
external regulator. To use the internal regulator, connect V5 to REG, or to the
emitter of an external NPN transistor. To bypass the internal regulator, connect
an external 5V supply directly to V5.
6
B2
REG
5V Regulator
Control Output
To use the internal linear regulator, connect REG to V5 or connect REG to the
base of an external NPN pass transistor. Leave REG unconnected and connect V5 to an external 5V supply to bypass the internal regulator.
7
—
B3
C3
LED1
LED2
www.maximintegrated.com
LED Driver
Output 1
LED1 is a 5V logic output. Connect a currentlimiting resistor in series between LED1 and
the LED to limit the LED current. LED1 can be
controlled by driving the LED1IN high or low,
of through the SPI interface. Set the LED1b bit
high to turn on the LED, clear the LED1b bit to
turn off the LED. Alternatively, drive the LED1IN
input high to turn on the LED, drive LED1IN low
to turn off the LED. See Table 2.
LED1 is a 5V logic output.
Connect a current-limiting
resistor in series between
LED1 and the LED to limit
the LED current. Drive the
LED1IN input high to turn
on the LED, drive LED1IN
low to turn off the LED.
LED Driver
Output 2
LED2 is a 5V logic output. Connect a currentlimiting resistor in series between LED2 and the
LED to limit the LED current. Set the LED2b bit
high to turn on the LED, clear the LED2b bit to
turn off the LED.
LED2 cannot be controlled in pin-mode. LED2
is off.
Maxim Integrated │ 18
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Pin Description (continued)
PIN
TQFN
FUNCTION
WLP
NAME
PIN DESCRIPTION
8
A1
C/Q
C/Q Transceiver
Output/
Input
9
A2
V24
Power-Supply
Input
10
A3
GND
11
12
A4
A5
DO
DI
PARALLEL MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = high
PIN MODE
(SPI/PIN = Low)
Drive TXEN high to enable the C/Q driver. The
The C/Q driver can be controlled and monitored
logic on the C/Q output is
with the logic input/output pins or through the
the inverse logic-level of
SPI interface. Drive TXEN high to enable the
the signal in the TX input.
C/Q driver. The logic on the C/Q output is the
RX is the logic inverse of
inverse logic-level of the signal in the TX input.
C/Q.
RX is the logic inverse of C/Q.
Configure the C/Q driver
with the pin-mode inputs.
Bypass V24 to GND with a 0.1μF ceramic capacitor as close to the device as
possible.
Ground
DO Driver
Output
DO is the inverse logic level of the LO input. The
DO driver can be enabled/disabled, configured,
controlled, and monitored with the logic input/
output pins or through the SPI interface.
DO is the inverse logic
level of the LO input.
Configure the DO driver
with the pin-mode inputs.
DO cannot be disabled in
pin-mode.
DI Receiver
Input
The DI receiver can be monitored on the LI output
or through the SPI interface. The LI output is the
inverse logic-level of the signal on the DI input.
Connect a 1kΩ resistor in series with the DI pin.
The LI output is the inverse
logic-level of the signal on
the DI input. The DI receiver
cannot be disabled in pinmode. Connect a 1kΩ resistor in series with the DI pin.
Bypass V33 to GND with a 1μF capacitor as
close to the IC as possible. The V33 regulator can
be disabled through the SPI interface.
Bypass V33 to GND with
a 1μF capacitor as close
to the IC as possible. V33
cannot be disabled in pinmode.
13
B4
V33
3.3V Linear Regulator Output
14
B5
VL
Logic-Level
Supply Input
VL defines the logic levels on all of the logic inputs and outputs. Apply a voltage
from 2.5V to 5.5V on VL. Bypass VL to GND with a 0.1μF ceramic capacitor.
DI Receiver
Logic Output
The LI output is the inverse logic-level of the signal on the DI input. Disable the LI output through
the SPI interface. LI is high impedance when the
DI_Dis bit is set.
15
16
C5
C4
LI
UARTSEL
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UART Interface
Select Logic Input
Drive UARTSEL
low to use RX, TX,
and TXEN for UART
signaling.
When CS/PP is high,
use SDO/RX/THSH,
SDI/TX/NPN, and CLK/
TXEN/200MA for UART
signaling.
The LI output is the
inverse logic-level of the
signal on the DI input.
LI cannot be disabled in
pin-mode.
UARTSEL is inactive
when SPI/PIN is low.
Maxim Integrated │ 19
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Pin Description (continued)
PIN
TQFN
FUNCTION
WLP
NAME
PIN DESCRIPTION
PARALLEL MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = high
PIN MODE
(SPI/PIN = Low)
The logic on the DO
output is the inverse logiclevel of the signal on the
LO input. Configure the
DO driver with the pinmode inputs.
17
D5
LO
DO Driver Logic
Input
The logic on the DO output is the inverse logiclevel of the signal on the LO input. Configure,
control, and monitor the DO output through the
logic pins or through the SPI interface.
18
D4
WU
Wake-Up Request Push-Pull
Output
WU asserts low for 200μs when an IO-Link 80μs wake-up condition is detected on the C/Q line.
LED1IN
LED1 Driver
Logic Input
Drive LED1IN high or low to enable/disable the
LED1 driver. The LED1 driver can also be controlled through the SPI interface. See Table 2.
Drive LED1IN high to turn
on the LED connected to
LED1. Drive LED1IN low
to turn the LED driver off.
IRQ/OC
Open-Drain
Interrupt/
Over-current
Output
IRQ/OC asserts when any bit in the INTERRUPT register is set. IRQ/OC deasserts when
the INTERRUPT register is read.
IRQ/OC asserts low when
the load current on the
C/Q or DO output exceeds
the set current limit.
SDO/
RX/
THSH
SPI Serial Data
Output/
RX Logic Output/
Thermal Shutdown Indicator
19
20
21
E5
E4
D3
www.maximintegrated.com
SPI serial data output
When CS/PP is high,
the SPI interface is disabled and UART interface mode is enabled.
SDO/RX/THSH is the
logic inverse of C/Q.
SDO/RX/THSH asserts
low when the IC enters
thermal shutdown. SDO/
RX/THSH deasserts
when the device returns
to normal operation.
Maxim Integrated │ 20
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Pin Description (continued)
PIN
TQFN
FUNCTION
WLP
NAME
PIN DESCRIPTION
23
D2
SPI/PIN
SPI or Pin-Mode
Select Input
SPI Serial Data
Input/
TX Logic Input/
NPN Driver
Mode Select
Input
EP
-
EP
www.maximintegrated.com
UARTSEL = high
When CS/PP is high,
the SPI interface is
disabled and UART
interface mode is
enabled. Drive CLK/
TXEN/200MA high to
enable the C/Q driver.
Drive CLK/TXEN/200MA
high to enable a 200mA
current limit on the C/Q
and DO driver outputs.
Drive CLK/TXEN/200MA
low to set the current limit
for the driver outputs to
100mA.
Drive SPI/PIN high for SPI or UART interface operation. Drive SPI/PIN low for
pin-mode operation.
E3
SDI/TX/
NPN
UARTSEL = Low
PIN MODE
(SPI/PIN = Low)
SPI clock input
22
E2
MULTIPLEXED MODE
(SPI/PIN = High)
SPI Clock Input/
UART TXEN
Input/
Current Limit
Setting Input
CLK/
TXEN/
200MA
24
PARALLEL MODE
(SPI/PIN = High)
SPI serial data input
When CS/PP is high,
the SPI interface is disabled and UART interface mode is enabled.
Drive SDI/TX/NPN to
switch C/Q. C/Q is the
logic inverse of the
SDI/TX/NPN input.
Drive SDI/TX/NPN high to
set the C/Q and DO driver
outputs in NPN mode.
Drive SDI/TX/NPN low to
set the driver outputs in
PNP mode. SDI/TX/NPN
is ignored when the CS/
PP input is high.
Exposed pad. Connect to ground. Not intended as the main ground connection.
Maxim Integrated │ 21
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Table 1. C/Q and DO Control
SPI/PIN
TXEN
L
L
H
L
TX OR CQ_DIS OR CQ_Q OR
LO
DO_DIS
DO_Q
X
PNP MODE
PP MODE
C/Q
DO
C/Q
DO
C/Q
DO
Z
Z
H
Z
H
L
-
-
Z
H
-
-
Z
L
Z
Z
Z
L
L
-
-
Z
Z
H
H
H
H
H
-
-
L
L
Z
Z
L
L
L
0
0
Z
Z
Z
H
Z
H
L
0
1
Z
Z
H
H
H
H
H
0
0
Z
L
Z
Z
Z
L
H
0
1
Z
Z
H
H
H
H
L
0
0
Z
Z
H
H
H
H
L
0
1
Z
Z
H
H
H
H
H
0
0
L
L
Z
Z
L
L
H
0
1
Z
Z
H
H
H
H
X
1
X
Z
Z
Z
Z
Z
Z
H
H
NPN MODE
X = Don’t care, Z = High impedance
Table 2: LED1 Configuration
LED1IN
L
H
LED1B BIT
LED1 DRIVER STATUS
0
OFF
1
ON
0
ON
1
ON
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Table 3. Driver NPN, PNP, PP Selection in
Pin-Mode
C/Q AND DO DRIVER MODE
SPI/PIN
CS/PP
L
L
L
PNP
L
L
H
NPN
L
H
L
PUSH-PULL
L
H
H
PUSH-PULL
H
X
X
C/Q and DO Modes
are set with the SPI
interface
SDI/TX/NPN
Maxim Integrated │ 22
MAX14827A
Detailed Description
The MAX14827A is an industrial sensor output driver/
IO-Link device transceiver. The IC integrates the high voltage functions commonly found in sensors, including two
24V line driver and two on-board linear regulators (LDOs).
The MAX14827A can be configured and monitored either
through the SPI interface or by setting logic interface pins.
The MAX14827A features multiple programmable functions that allow the user to optimize operation and power
dissipation for various loads and application scenarios.
The integrated 3.3V and 5V LDOs provide the power
needed for low noise analog and logic supply rails.
SPI, UART, or Pin-Mode Interface
Pin-Mode
The MAX14827A provides a selectable SPI or pin interface to configure and monitor device operation. Drive the
SPI/PIN input high to use the SPI. Drive SPI/PIN low to
use the pin interface (pin-mode control).
When operating in pin mode, the following functionality is
set and cannot be changed:
• RX and DI are enabled (cannot be disabled)
• RX deglitch filter is enabled
• Weak pull-ups/pull-downs on C/Q and DO are
disabled
• Autoretry functionality is disabled
• The blanking time on C/Q and DO is 128μs
SPI Operation (Parallel Operating Mode)
When the MAX14827A is operated in SPI mode, an external UART can be connected to separate UART interface
pins (TX, RX, TXEN). This is called the parallel SPI/UART
operating mode. This is the common approach used when
the microcontroller offers a UART and a separate SPI port
in the Typical Operating Circuit. Drive UARTSEL low for
operation in parallel mode.
SPI Operation (Multiplexed Mode)
In cases where only one microcontroller serial port is available with both SPI and UART functions, the MAX14827A
can be operated in multiplexed SPI/UART mode. This is
feasible in IO-Link operation due to the defined idle times
in the IO-Link cycle time. In multiplexed mode, the UART
and SPI pins are shared. Two operating modes are available in multiplexed mode, as selected by the ENMPX bit.
When ENMPX = 0, UART and SPI operation are selected
by setting the CS/PP input. In this mode the SPI interface
is active when CS/PP is low and UART operation when
CS/PP is high.
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
When ENMPX = 1, UART and SPI operations are selected by setting the UARTSEL input. To avoid glitches on
C/Q, CLK/TXEN/200MA and SDI/TX/NPN are sampled
on the falling edge of UARTSEL in this mode. See Mode
Selection Table for more information.
When entering multiplexed mode, set TXEN low and TX
high to disable the driver.
IRQ/OC is active in both multiplexed modes during UART
communication.
24V Interface
The MAX14827A features an IO-Link transceiver interface
capable of operating with voltages up to 60V. This is the
24V interface and includes the C/Q input/output, the logiclevel digital output (DO), the logic-level digital input (DI),
and the V24 supply.
The MAX14827A features selectable push-pull, high-side
(PNP), or low-side (NPN) switching drivers at C/Q and DO.
Configurable Drivers (Pin-Mode)
In pin-mode, use SDI/TX/NPN and CS/PP inputs to configure the C/Q and DO drivers in push-pull, PNP, or NPN
modes (Table 3) In this mode, toggle TXEN, TX, and LO
to switch the C/Q and DO outputs.
Configurable Drivers (SPI Mode)
In SPI operation, the C/Q and DO drivers can be configured independently. Set the bits in the CQConfig register
to configure the C/Q driver, enable/disable the weak
pull-up and pull-down currents on C/Q. Set the bits in the
DIOConfig register to configure the DO driver and enable/
disable the weak pull-up and pull-down currents on DO.
The C/Q and DO drivers can be disabled by setting the
CQ_Dis and DO_Dis bits. Driver outputs are high impedance and power dissipation is reduced when these bits
are set. See the Register Functionality section for more
information on configuring the drivers.
For IO-Link operation, TX, TXEN, and RX are the UART
interface to control C/Q communication. Set CQ_Dis =
CQ_Q = 0 and drive TX and TXEN inputs for C/Q driver
control.
For lower rate switching on the C/Q and DO drivers,
register bits can be used for C/Q and DO control. For bit
control, drive TXEN, TX, and LO high and use the CQ_Q
and DO_Q bits to control the C/Q and DO driver states.
The CQ_Dis and DO_Dis bits are used to enable/disable
the drivers in this mode.
IO-Link is a registered trademark of Profibus User Organization (PNO).
SPI is a trademark of Motorola, Inc.
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Maxim Integrated │ 23
MAX14827A
C/Q Driver Enable/Disable
In pin-mode, the C/Q driver is enabled/disabled with the
TXEN input. Drive TXEN high to enable the C/Q driver.
C/Q is the logic inverse of the TX input.
In SPI mode, the C/Q driver can also be enabled/disabled,
configured, and controlled in the CQConfig register.
C/Q Current Limit
The C/Q driver is optimized for driving large capacitive
loads and dynamic impedances like incandescent lamps.
In pin-mode, the driver current limit is selectable by setting the CLK/TXEN/200MA input high or low. Set CLK/
TXEN/200MA low for 100mA maximum load current. Set
CLK/TXEN/200MA high for a 200mA maximum load current.
In SPI operation, the maximum driver current limit is
selectable as 50mA, 100mA, 200mA, or 250mA by setting
the CL1 and CL0 bits in the CURRLIM register.
C/Q Driver Fault Detection
The MAX14827A senses a fault condition on the C/Q driver when it detects a short circuit for longer than the blanking time. A short condition exists when the C/Q driver’s
load current exceeds the current limit. In SPI mode, both
the current limit and blanking time may be configured.
In pin-mode, the IRQ/OC output asserts low when a short
circuit fault occurs on C/Q or DO. In SPI mode, the
C/QFault and C/QFaultInt bits are set and IRQ/OC
asserts.
When a short-circuit event occurs on C/Q, the driver
can either be set to continue supplying the selected current until the device enters thermal shutdown or to enter
autoretry mode when an overcurrent event occurs. In
autoretry mode the driver is automattically disabled after
the current blanking time and is then re-enabled.
C/Q Receiver Output (RX)
RX is the output of the C/Q receiver. RX is the inverse logic
of the C/Q input.
In pin-control mode, the C/Q receiver is always on.
In SPI mode, the receiver can be disabled by setting the
Rx_Dis bit in the CQConfig register. RX is high impedance
when Rx_Dis is set. Note that the CQLvl bit in the Status
register is invalid when the Rx_Dis bit is set.
When operating in multiplexed mode, SDO/RX/THSH is
the output of the C/Q receiver. In this mode, SDO/RX/
THSH is high impedance when CS/PP is high and Rx_Dis
bit is set.
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Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
C/Q Receiver Threshold
The IO-Link standard defines device operation with a
sensor supply between 18V and 30V. Industrial sensors,
however, commonly operate with supply voltages as low
as 9V. The MAX14827A C/Q receiver supports operation
with lower supply voltages by scaling the receiver thresholds when V24 is less than 18V (V24 < 18V).
DO Driver
In pin-mode, the DO driver is always enabled. DO is the
logic inverse of the LO input.
In SPI mode, the DO driver can be enabled/disabled,
configured, and controlled in the DIOConfig register.
DO Current Limit
The DO driver is optimized for driving large capacitive
loads and dynamic impedances like incandescent lamps.
In pin-control mode, the driver current limit is selectable
by setting the CLK/TXEN/200MA input high or low. Set
CLK/TXEN/200MA low for 100mA maximum load current.
Set CLK/TXEN/200MA high for a 200mA maximum load
current.
In SPI operation, the maximum driver current limit is
selectable as 50mA, 100mA, 200mA, or 250mA by setting
the CL1 and CL0 bits in the CURRLIM register.
DO Fault Detection
The MAX14827A senses a fault condition on the DO
output when it detects a short circuit for longer than
the blanking time. A short condition exists when the DO
driver’s load current exceeds the current limit. In SPI
mode, both the current limit and blanking time may be
configured.
In pin-mode, the IRQ/OC output asserts low when a
short circuit fault occurs on C/Q or DO. In SPI mode, the
DoFault and DoFaultInt bits are set and IRQ/OC asserts.
When a short-circuit event occurs on DO, the driver can
either be set to continue supplying the selected current
until the device enters thermal shutdown or to enter
autoretry mode when an overcurrent event occurs. In
autoretry mode the driver is automattically disabled after
the current blanking time and is then re-enabled.
DO and C/Q Tracking
In SPI mode, the DO driver can be configured to track the
C/Q driver. Set the CQDOPar bit in the CQConfig register
to enable this functionality. When the DO driver is set to
track C/Q, both C/Q and DO switch as a function of the
TX and TXEN inputs or CQ_Q bit.
In pin-mode, or when CQDOPar is 0, C/Q and DO operate
independently.
Maxim Integrated │ 24
MAX14827A
Reverse-Polarity Protection
The MAX14827A is protected against reverse-polarity
connections on V24, C/Q, DO, DI, and GND. Any combination of these pins can be connected to DC voltages up
to 65V (max), resulting in a current flow of less than 1mA.
Ensure that the maximum voltage between any of these
pins does not exceed 65V.
Driver Short-Circuit Detection
The MAX14827A monitors the DO and C/Q driver outputs
for overcurrent and driver overheating conditions.
In pin-mode, the driver short-circuit current limit is set with
the CLK/TXEN/200mA input. IRQ/OC asserts when an
overcurrent or overheating condition occurs on either the
C/Q or DO driver. IRQ/OC deasserts when the overcurrent or overheating condition is removed.
In SPI mode, the DO and C/Q are independently monitored. Driver current limits for both drivers are set using
the CL1 and CL0 bits in the CURRLIM register. When
an overcurrent or overheating condition occurs on C/Q,
the CQFault and CQFaultInt bits are set and IRQ/OC
asserts. When an overcurrent or overheating condition
occurs on DO, the DOFault and DOFaultInt bits are set.
The CQFault and DOFault bits are cleared as soon as
the overcurrent or overheating conditions on the C/Q
and DO drivers are removed. IRQ/OC deasserts and the
CQFaultInt and DOFaultInt bits are cleared only when the
INTERRUPT register is read.
5V and 3.3V Linear Regulators
The MAX14827A includes two internal regulators to generate 5V (V5) and 3.3V (V33).
The V5 regulator is capable of driving external loads up to
30mA, including device and 3.3V LDO current consumption. To drive larger loads, use an external pass transistor to generate the required 5V. When using an external
transistor, connect REG to the base of the transistor to
regulate the voltage and connect V5 to the emitter (Figure
10 ).
When the internal 5V linear regulator is not used, V5 is
the supply input for the internal analog and digital functions and must be supplied externally. Ensure that V5 is
present for normal operation.
The 3.3V regulator is capable of driving external loads
up to 30mA. In SPI mode, the 3.3V LDO can be enabled/
disabled by setting the V33Dis bit in the Mode register.
V5 and V33 are not protected against short circuits.
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Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Power-Up
The C/Q and DO driver outputs are high impedance when
V24, V5, VL, and/or V33 voltages are below their respective undervoltage thresholds during power-up.
The drivers are automatically disabled if V24, V5, or VL
falls below its threshold.
Low Voltage and Undervoltage Detection
In SPI mode, the device monitors the V24 supply for low
voltage and undervoltage conditions. Low-voltage warnings must be enabled in the MODE register.
When V24 falls below the 16V (typ) low-voltage warning
threshold, the V24W bit in the STATUS register is set. If
V24WEn is set to 1, the V24WInt interrupt bit is also set
and IRQ/OC asserts.
When V24 falls below the 7.4V (typ) undervotlage lockout
(UVLO) threshold, the UV24 bit in the STATUS register is
set. Similarly, the UV24Int bit in the INTERRUPT register
is set and IRQ/OC asserts. UVLO monitoring and interrupts cannot be disabled.
Wake-Up Detection
The MAX14827A detects an IO-Link wake-up condition
on the C/Q line in push-pull, high-side (PNP), or low-side
(NPN) operation modes. A wake-up condition is detected
when the C/Q output is shorted for 80µs (typ). WU pulses
low for 200µs (typ) when the device detects a wake-up
pulse on C/Q (Figure 5).
In SPI mode, the WuInt bit in the INTERRUPT registeris
set and IRQ/OC asserts when an IO-Link wake-up event
is detected.
Wake-up detection can be disabled in SPI mode by setting the WU_Dis bit in the MODE register to 1. Wake-up
detection cannot be disabled in pin-mode.
The device includes a wake-up detection algorithm to
avoid false wake-up detection on C/Q. The false wake-up
blanking time is defined by the current limit blanking time.
In pin-mode, this is 128μs. In SPI-mode, this is set by the
CL_BL0 and CL_BL1 bits in the CURRLIM reigster.
Thermal Protection and Considerations
The internal LDOs and drivers can generate more power
than the package for the devices can safely dissipate.
Ensure that the driver and LDO loading is less than the
package can dissipate. Total power dissipation for the
device is calculated using the following equation:
PTOTAL = PC/Q + PDO + PV5 + P33 + P24 +
(2 x PPU) + (2 x PPD)
Maxim Integrated │ 25
MAX14827A
where PC/Q is the power generated in the C/Q driver, PDO
is the power dissipated by the DO driver, PV5 and PV33
are the power generated by the LDOs, P24 is the quiescent power generated by the device, and PPU and PPD
are the power generated in the C/Q and DO weak pullup/
pulldown current sources/sinks, respectively.
Ensure that the total power dissipation is less than the
limits listed in the Absolute Maximum Ratings section.
Use the following to calculate the power dissipation (in
mW) due to the C/Q driver:
PC/Q = [IC/Q(max)]2 × RO
where RO driver on-resistance.
Calculate the internal power dissipation of the DO driver
using the following equation:
PDO = [IDO(max)]2 x RO
where RO driver on-resistance.
Calculate the power dissipation in the 5V LDO, V5, using
the following equation:
P5 = (V24 - V5) × I5
where I5 includes the I33 current sourced from V33.
Calculate the power dissipated in the 3.3V LDO, V33,
using the following equation:
P33 = 1.7V × ILOAD33
Calculate the quiescent power dissipation in the device
using the following equation:
P24 = I24(max) × V24(max)
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Overtemperature Warning
In SPI mode, the device generates interrupts when the
junction temperature of any of the drivers (C/Q or DO)
exceeds +140°C (typ) warning threshold. The TempW bit
in the STATUS register is set and the TempWInt in the
INTERRUPT register is set and IRQ/OC asserts under
these conditions.
The TempW bit is cleared when the die temperature falls
to +125°C. The INTERRUPT register must be read to
clear the TempWInt bit and deassert IRQ/OC.
The device continues to operate normally unless the
die temperature reaches the +165°C thermal shutdown
threshold, when the device enters thermal shutdown.
The device does not generate overtemperature warnings
when operating in pin-mode.
Thermal Shutdown
The C/Q and DO drivers, and the V5 and V33 regulators
are automatically switched off when the junction temperature exceeds the +165°C (typ) thermal shutdown threshold. SPI communication and and the internal regulators
are not disabled during thermal shutdown. In SPI mode,
the ThShut bit in the STATUS register and the ThShutInt
in the INTERRUPT register are set.
Regulators are automatically switched on when the internal die temperature falls below the thermal shutdown
threshold plus hysteresis. If the internal V5 regulator is
used, the internal registers return to their default state
when the V5 regulator is switched back on.
If the weak current sinks/sources are enabled, calculate
their associated power dissipation as:
PPD = IPD(max) × VC/Q (max)
PPU = IPU(max) × [V24 - VC/Q](max)
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Maxim Integrated │ 26
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Mode Selection Table
OPERATING
MODE
PIN
PARALLEL UART
+ SPI
SPI/
PIN
L
H
UARTSEL
X
L
ENMPX
BIT
X
0
CS/PP
LOW
OR
HIGH
LOW
OR
HIGH
L
MULTIPLEXED
UART/SPI
H
H
0
H
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PIN NAME
PIN
FUNCTION
FUNCTION
SDI/TX/NPN
NPN
Parallel configuration/monitoring
SDO/RX/THSH
THSH
Parallel configuration/monitoring
CLK/TXEN/200MA
200MA
Parallel configuration/monitoring
CS/PP
PP
Parallel configuration/monitoring
IRQ/OC
OC
RX
C/Q RX
TX
C/Q TX
TXEN
C/Q TXEN
Parallel configuration/monitoring
Parallel configuration/monitoring/
UART communication
Parallel configuration/monitoring/
UART communication
Parallel configuration/monitoring/
UART communication
SDI/TX/NPN
SDI
SPI configuration/monitoring
SDO/RX/THSH
SDO
SPI configuration/monitoring
CLK/TXEN/200MA
CLK
SPI configuration/monitoring
CS/PP
CS
SPI configuration/monitoring
IRQ/OC
IRQ
SPI configuration/monitoring
RX
C/Q RX
UART communication
TX
C/Q TX
UART communication
TXEN
C/Q TXEN
UART communication
SDI/TX/NPN
SDI
SPI configuration/monitoring
SDO/RX/THSH
SDO
SPI configuration/monitoring
CLK/TXEN/200MA
CLK
SPI configuration/monitoring
CS/PP
LOW
SPI configuration/monitoring
IRQ/OC
IRQ
SPI configuration/monitoring
RX
C/Q RX
UART communication
TX
C/Q TX
UART communication
TXEN
C/Q TXEN
UART communication
SDI/TX/NPN
C/Q TX
UART communication
SDO/RX/THSH
C/Q RX
UART communication
CLK/TXEN/200MA
C/Q TXEN
UART communication
CS/PP
HIGH
IRQ/OC
IRQ
SPI configuration/monitoring
RX
C/Q RX
Active
TX
C/Q TX
Ignored
TXEN
C/Q TXEN
Ignored
Maxim Integrated │ 27
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Mode Selection Table (continued)
OPERATING
MODE
SPI/
PIN
UARTSEL
ENMPX
BIT
CS/PP
0
MULTIPLEXED
UART/SPI
H
1
1
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LOW
OR
HIGH
PIN NAME
PIN
FUNCTION
FUNCTION
SDI/TX/NPN
SDI
SPI configuration/monitoring
SDO/RX/THSH
SDO
SPI configuration/monitoring
CLK/TXEN/200MA
CLK
SPI configuration/monitoring
CS/PP
CS
SPI configuration/monitoring
IRQ/OC
IRQ
SPI configuration/monitoring
RX
Active
TX
Ignored
TXEN
Ignored
SDI/TX/NPN
C/Q TX
UART communication
SDO/RX/THSH
C/Q RX
UART communication
CLK/TXEN/200MA
C/Q TXEN
UART communication
Not used
CS/PP
IRQ/OC
IRQ
SPI monitoring
RX
Active
TX
Ignored
TXEN
Ignored
Maxim Integrated │ 28
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Register Functionality
The devices have four 8-bit-wide registers for configuration and monitoring (Table 1).
Table 4. Register Summary
REGISTER ADD R/W
INTERRUPT 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
ThShutInt
WuInt
DoFaultInt
CQFaultInt
V24WInt
UV24Int
-
TempWInt
STATUS
01h
R
ThShut
DiLvl
DoFault
CQFault
V24W
UV24
CQLvl
TempW
MODE
02h
R/W
RST
WU_Dis
V33_Dis
ENMPX
V24WEn
CQFil
LED2b
LED1b
CURRLIM
03h
R/W
CL1
CL0
CLDis
CL_BL1
CL_BL0
TAr1
TAr0
ArEn
CQConfig
04h
R/W
Rx_Dis
CQ_WPD
CQ_WPU
CQDOPar
CQ_NPN
CQ_PP
CQ_Q
CQ_Dis
DIOConfig
05h
R/W
DI_Dis
DO_WPD
DO_WPU
DO_AV
DO_NPN
DO_PP
DO_Q
DO_Dis
INTERRUPT Register [A2, A1, A0] = [000]
Bit
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ThShutInt
WuInt
DoFaultInt
CQFaultInt
V24WInt
UV24Int
-
TempWInt
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
The INTERRUPT register reflects current state of various fault conditions. The IRQ/OC output asserts when any of the
bits in the INTERRUPT register is set. INTERRUPT register bits are latched and are not cleared when the initiating
condition is removed. Reading the INTERRUPT register clears all the bits and deasserts IRQ/OC. IRQ/OC reasserts
only when another fault condition occurs.
BIT
7
6
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NAME
DESCRIPTION
ThShutInt
Thermal Shutdown Interrupt
1: This bit is set when the MAX14827A has entered thermal shutdown mode. Once set,
this bit is not cleared until the register is read. The current status of the thermal
shutdown condition can be read in the Status register.
0: The MAX14827A is not in thermal shutdown.
WuInt
Wake-Up Event Interrupt
1: This bit is set when an IO-Link wake-up condition is detected on the C/Q line.
0: No wake-up condition is detected.
The wake-up interrupt can be disabled by setting the WuDis bit to 1.
Maxim Integrated │ 29
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
INTERRUPT Register [A2, A1, A0] = [000] (continued)
BIT
NAME
DESCRIPTION
DoFaultInt
DO Driver Fault Interrupt
1: This bit is set when a fault occurs on the DO driver (over current or over heating).
Once set, this bit is not cleared until the register is read. The current status of the
thermal shutdown condition can be read in the Status register.
0: No fault on the DO driver.
CQ_FaultInt
C/Q Driver Fault Interrupt
1: This bit is set when a fault occurs on the C/Q driver (over current or over heating).
Once set, this bit is not cleared until the register is read. The current status of the
thermal shutdown condition can be read in the Status register.
0: No fault on the C/Q driver.
V24WInt
V24 Low Voltage Warning Interrupt
1: This bit is set when V24 falls below the IO-Link low-voltage warning threshold fault
(V24 < V24W). Once set, this bit is not cleared until the register is read. The current
status of the thermal shutdown condition can be read in the Status register.
0: V24 is greater than the low-voltage warning threshold.
2
UV24Int
V24 Supply Undervoltage Interrupt
1: This bit is set when V24 falls below the UVLO threshold (V24 < V24UVLO). Once set,
this bit is not cleared until the register is read. The current status of the thermal shutdown condition can be read in the Status register.
0: V24 is greater than the UVLO threshold.
1
5
4
3
0
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TempWInt
This bit is not used.
Overtemperature Warning Interrupt
1: This bit is set when the die temperature exceeds the warning threshold (TJ > TWRN).
Once set, this bit is not cleared until the register is read. The current status of the
thermal shutdown condition can be read in the Status register.
0: The die temperature has not exceeded the overtemperature warning threshold.
Maxim Integrated │ 30
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
STATUS Register [A2, A1, A0] = [001]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ThShut
DiLvl
DoFault
CQFault
V24W
UV24
CQLvl
TempW
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
Bit Name
The Status register reflects current state of various IC functions.
BIT
NAME
DESCRIPTION
7
ThShut
6
DiLvl
5
DoFault
DO Driver Fault Status
1: This bit is set when a fault occurs on the DO driver (over current or over heating).
0: This bit is cleared automatically when the fault on DO is removed.
4
CQ_Fault
C/Q Driver Fault Status
1: This bit is set when a fault occurs on the C/Q driver (over current or over heating).
0: This bit is cleared automatically when the fault on C/Q is removed.
Thermal Shutdown Status
1: This bit is set when the MAX14827A has entered thermal shutdown mode.
0: This bit is cleared automatically when the device exits thermal shutdown.
DI Logic Level
1: This bit is set when the DI voltage is a logic high (VDI < VTL).
0: This bit is clear when the DI voltage is a logic low (VDI > VTH).
3
V24W
V24 Low Voltage Warning Status
1: This bit is set when V24 falls below the IO-Link low-voltage warning threshold (V24 <
V24W).
0: This bit is cleared automatically when V24 rises above the low-voltage warning
threshold.
2
UV24
V24 Supply Status
1: This bit is set when V24 falls below the UVLO threshold (V24 < V24UVLO).
0: This bit is cleared automatically when V24 rises above the UVLO threshold.
1
CQLvl
C/Q Logic Level
1: This bit is set when the C/Q voltage is a logic high (VC/Q < VTL).
0: This bit is clear when the C/Q voltage is a logic low (VC/Q > VTH).
0
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TempW
Overtemperature Warning
1: This bit is set when the die temperature exceeds the warning threshold (TJ > TWRN).
0: This bit is cleared automatically when the when the die temperature falls below the
warning threshold and hysteresis (TJ < TWRN - TWRN_HYST).
Maxim Integrated │ 31
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
MODE Register [A2, A1, A0] = [010]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
RST
WU_Dis
V33_Dis
ENMPX
V24WEn
CQFil
LED2b
LED1b
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset upon Read
N
N
N
N
N
N
N
N
Use the Mode register to configure the MAX14827A and manage the 3.3V LDO.
BIT
NAME
DESCRIPTION
Register Reset
1: Reset all registers to their default power-up state. The Status register is
cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts are not
generated while RST = 1.
0: Normal operation.
7
RST
6
WU_Dis
Wake-Up Interrupt Disable/Enable
1: Wake-up detection is disabled.
0: Enable IO-Link wake-up detection.
5
V33_Dis
V33 Enable/Disable
1: Disable the V33 linear regulator.
0: Enable the V33 linear regulator.
ENMPX
Enable/Disable SPI/UART Multiplexing
1: Enable UART multiplexing on SPI interface pins. See the Mode Selection
Table for more information.
0: Disable UART multiplexing on SPI interface pins.
3
V24WEn
V24 Undervoltage Warning Enable
1: Enable the V24 undervoltage warning interrupt. V24WInt is set when V24 falls
below the UVLO threshold.
0: Disable the V24 undervoltage warning interrupt.
2
CQFil
C/Q Deglitch Filter Enable/Disable
1: Deglitch filter is disabled on RX.
0: Deglitch filter is enabled on RX.
1
LED2b
LED2 Driver Logic
1: Set the LED2 output high.
0: Set the LED2 output low.
0
LED1b
LED1 Driver Logic.
1: Set the LED1 output high.
0: LED1 output is driven by the LED1IN logic input.
4
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Maxim Integrated │ 32
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
CURRLIM Register [A2, A1, A0] = [011]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
CL1
CL0
CL_Dis
CL_BL1
CL_BL0
TAr1
TAr0
ArEN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
The CURRLIM register sets the C/Q and DO driver current limits and the fixed off-time once the drivers have exceeded
their individual thermal shutdown thresholds.
BIT
NAME
DESCRIPTION
CL1
Driver Current Limit
Set the CL1 and CL0 bits to select the active current limit for the C/Q and DO drivers
when CL_Dis = 0.
6
CL0
00:
01:
10:
11:
5
CL_Dis
Driver Current Limit Disable/Enable
1: Disable the driver current limit for the C/Q and DO drivers.
0: Enable the driver current limit (as set by the CL1 and CL0 bits).
CL_BL1
Current Limit Blanking Time
Set the CL_BL1 and CL_BL0 bits to select the minimum blanking time to signal a current limit or thermal fault.
CL_BL0
00:
01:
10:
11:
7
4
3
2
1
0
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Driver current limit is set to 50mA
Driver current limit is set to 100mA
Driver current limit is set to 200mA
Driver current limit is set to 250mA
Blanking time is 128μs
Blanking time is 500μs
Blanking time is 1ms
Blanking time is 5ms
TAr1
Auto-Retry Fixed Off-Time
Set the TAr1 and TAr0 bits to select the fixed driver off-time after a fault has been
generated when auto-retry functionality is enabled (ArEn = 1). The driver is re-enabled
automatically after the fixed off-delay.
TAr0
00:
01:
10:
11:
ArEN
Auto-Retry Fixed Off-Time Enable/Disable
1: Fixed off-time functionality is enabled. C/Q and DO drivers are disabled for a fixed
time after an overcurrent or thermal fault occurs. The driver is re-enabled automatically after the fixed off-delay.
0: Fixed off-time functionality is disabled. The driver is re-enabled after temperature falls
below the thermal hysteresis.
Fixed off-time is 50ms
Fixed off-time is 100ms
Fixed off-time is 200ms
Fixed off-time is 500ms
Maxim Integrated │ 33
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
CQConfig Register [A2, A1, A0] = [100]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX_Dis
CQ_WPD
C/Q_WPU
C/QDOPar
C/Q_NPN
CQ_PP
CQ_Q
CQ_Dis
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
1
Reset Upon Read
N
N
N
N
N
N
N
N
Bit Name
Use the CQConfig register to control the C/Q driver and receiver parameters. All bits in the CQConfig register are
read-write.
BIT
NAME
7
RX_Dis
6
CQ_WPD
C/Q Weak Pull-Down Enable
1: Enable the weak pull-down current sink on the C/Q driver.
0: Disable the weak pull-down current sink on the C/Q driver.
5
CQ_WPU
C/Q Weak Pull-Up Enable
1: Enable the weak pull-up current source on the C/Q driver.
0: Disable the weak pull-up current source on the C/Q driver.
CQDOPar
C/Q and DO Driver Tracking
1: Enable C/Q and DO tracking. In this mode, both C/Q and DO switch as a
function of the TX input or the CQ_Q bit.
0: C/Q and DO operate independently.
3
CQ_NPN
C/Q Driver NPN/PNP Mode
1: Enable NPN operation (when CQ_PP = 0) on the C/Q driver.
0: Enable PNP operation (when CQ_PP = 0) on the C/Q driver.
CQ_NPN is ignored when CQ_PP = 1.
2
CQ_PP
C/Q Driver Push-Pull Mode
1: Enable push-pull operation on the C/Q driver.
0: Enable open-drain (PNP or NPN mode) operation on the C/Q driver.
CQ_Q
C/Q Driver Output Logic
1: Set the C/Q driver high (push-pull mode), set the C/Q PNP switch on (PNP
mode), or set the C/Q NPN switch off (NPN mode). See Table 1.
0: CQ is high impedance when CQ_Q = 0 and TXEN is low (or CQ_Dis = 1).
CQ logic is the inverse of TX logic when TXEN is high (and CQ_Dis = 0)
and CQ_Q = 0. See Table 1.
CQ_Dis
C/Q Driver Disable/Enable
1: Disable the C/Q driver, regardless of the state of the TXEN input. The driver
is high impedance in this mode.
0: Status of the C/Q driver is determined by the TXEN input or CQ_Q bit.
4
1
0
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DESCRIPTION
Receiver Disable/Enable
1: The RX receiver output is disabled. RX is high impedance when disabled.
0: RX is enabled.
Maxim Integrated │ 34
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
DIOConfig Register [A2, A1, A0] = [101]
Bit
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DI_Dis
DO_WPD
DO_WPU
DO_AV
DO_NPN
DO_PP
DO_Q
DO_Dis
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
1
Reset Upon Read
N
N
N
N
N
N
N
N
Use the DIOConfig register to control the DI and DO interfaces. All bits in the DIOConfig register are read-write.
BIT
NAME
DESCRIPTION
DI Receiver Enable/Disable
1: The DI receiver is disabled. LI is high impedance when the DI
receiver is disabled.
0: DI receiver is enabled.
7
DI_Dis
6
DO_WPD
DO Weak Pulldown Enable
1: Enable the weak pull-down current sink on the DO driver.
0: Disable the weak pull-down current sink on the DO driver.
5
DO_WPU
DO Weak Pullup Enable
1: Enable the weak pull-up current source on the DO driver.
0: Disable the weak pull-up current source on the DO driver.
4
DO_AV
DO Antivalent Operation
1: Enable antivalent operation on the C/Q and DO outputs. In this
mode, DO switches as a function of the LO input or the DO_Q bit, but
with opposite logic. If CQDOPar = 1, both C/Q and DO switch as a
function of TX and/or CQ_Q, but with opposite logic.
0: C/Q and DO switch with normal polarity.
DO Driver NPN/PNP Mode
1: Enable NPN operation (when DO_PP = 0) on the DO driver.
0: Enable PNP operation (when DO_PP = 0) on the DO driver.
DO_NPN is ignored when DO_PP = 1.
3
DO_NPN
2
DO_PP
DO Driver Push-Pull Mode
1: Enable push-pull operation on the DO driver.
0: Enable open-drain (PNP or NPN mode) operation on the DO driver.
1
DO_Q
DO Driver Output Logic
1: Set the DO driver high (push-pull mode), set the DO PNP switch on
(PNP mode), or set the DO NPN switch off (NPN mode). See Table 1.
0: DO logic is the inverse of LO logic when DO_Dis = 0 and DO_Q = 0.
See Table 1.
0
DO_Dis
DO Driver Disable/Enable
1: Disable the DO driver. DO is high impedance when disabled.
0: State of the DO driver is determined by the LO input or the DO_Q bit.
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Maxim Integrated │ 35
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
SPI Interface
polarity CPOL = 0 and clock phase CPHA = 0 (see Figure 7
and Figure 8).
The device communicates through an SPI-compatible
4-wire serial interface. The MAX14827A supports burst
read/write access. The maximum SPI clock rate for the
device is 12MHz. The SPI interface complies with clock
The SPI interface is not available when V5 or VL are not
present.
CS/PP
CLK/
TXEN/
200MA
SDI/TX/
NPN
W
0
0
0
0
A2
A1
A0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 2
BIT 1
BIT 0
A_ = REGISTER ADDRESS
BIT_ = DATA BIT
= CLOCK EDGE THAT INTIATES LATCHING OF SDI DATA
Figure 7. SPI Write Cycle
CS/PP
CLK/
TXEN/
200MA
SDI/TX/
NPN
X
R
0
0
0
0
A2
A1
SDO/RX/
THSH
X
A0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
A_ = REGISTER ADDRESS
BIT_ = DATA BIT
= CLOCK EDGE THAT INTIATES LATCHING OF SDI DATA
= CLOCK EDGE THAT INTIATES WRITING OF SDO DATA
Figure 8. SPI Read Cycle
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Maxim Integrated │ 36
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
SPI Burst Access
Burst access allows writing or reading in one block, by
only defining the initial register address in the SPI command byte. Once the initial SPI address is received, the
MAX14827A automatically increments the register after
each SPI data byte. Efficient programming of multiple
consecutive registers is thus possible. Chip select, CS/
PP, must be kept low during the whole write/read cycle.
The SPI clock continues clocking throughout the burst
access cycle. The burst cycle ends when the SPI master
pulls CS/PP high.
Applications Information
Microcontroller Interfacing
The logic levels of the microcontroller interface I/Os are
defined by VL. Apply a voltage from 2.5V to 5.5V to VL for
normal operation. Logic outputs are supplied by VL.
The device can be configured for simultaneous or multiplexed UART communication. When configured for a
multipexed UART interface, the SPI interface and UART
interface pins are shared. See the Mode Selection Table
for more information.
Transient Protection
Inductive load switching, ESD, bursts, and surges create
high transient voltages. V24, C/Q, DI, and DO should
be protected against high overvoltage and undervoltage
transients. Positive voltage transients on V24, C/Q, DO,
and DI must be limited to +70V relative to GND. Negative
voltage transients must be limited to -70V relative to V24.
Use protection diodes on C/Q, DO, and DI as shown in
Figure 9.
For standard ESD and burst protection demanded by the
IO-Link specification, small package TVS can be used (like
the uClamp3603T or the SPT01-335). If higher level surge
ratings need to be achieved (IEC 61000-4-5 ±1kV/ 42Ω),
SMAJ33A or SMBJ36A TVS protectors can also be used.
Using an External Transistor with the 5V
Regulator
V24
MAX14827A DO
C/Q
DI
GND
Figure 9. MAX14827A Operating Circuit with TVS Protection
load currents or to shunt the power dissipation away from
the MAX14827A, an external NPN transistor can be connected as shown in Figure 10.
Select an NPN transistor with high VCE voltage to support the max L+ supply voltage. In order to protect the
NPN transistor against reverse polarity of the L+/L- supply
terminals, connect a silicon or a Schottky diode in series
with the NPN transistor’s collector that has a reverse voltage capability large enough for reverse connected L+/L-.
A 1µF capacitor on the V5 is required for stability.
Using an Step-Down Regulator with the 5V
Regulator
To decrease power dissipation in the MAX14827A, V5
can be powered by an external step-down regulator.
Connect the external regulator’s output to the V5 input
and leave REG unconnected. (Figure 11)
The internal 5V regulator (V5) can provide up to 30mA
of total load current (including the current on to the V33
LDO) when V5 is connected to REG. To achieve larger
www.maximintegrated.com
Maxim Integrated │ 37
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
L+
1µ F
V24
REG
V5
MAX14827A
GND
L-
Figure 10. Using an External NPN Transistor with the 5V Regulator
MAX17552
5V
1µF
3.3V
VL
V33
V5
SPI/PIN
GPIO2
GPO
IRQ/OC
UARTSEL
SS
SCLK/RTS
MISO/RX
MOSI/TX
CS
CLK/TXEN
SDO/RX
SDI/TX
MICROCONTROLLER
GND
GPO
IN
FB
EN
GND
1µF
VCC
LX
WU
LED1
LED2
REG
V24
0.1µF
L+
MAX14827A
DI/DO
DO
DI
GND
1kΩ
1
2
4
3
C/Q
L-
C/Q
Figure 11. Using an External Step-Down with the 5V Regulator
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Maxim Integrated │ 38
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Shared SPI/UART Interface
Figure 12 is an example of the use of a minimum pincount microcontroller. A microcontroller serial port, which
supports both UART and SPI functions, is used for managing both transceiver control (SPI) and IO-Link data
communication (UART). The microcontroller’s shared
UART and SPI interface pins are multiplexed. The transceiver’s SPI is typically only used for configuration at
power-up and occasionally afterwards for reconfiguration, and diagnostics. During an IO-Link master-device
communication cycle, the idle time on the C/Q interface
can be used for SPI activity. This is possible by slightly
increasing the IO-Link device’ minimum cycle time.
5V
1µF
3.3V
1µF
VCC
VL
V33
V5
SPI/PIN
GPIO2
GPO
IRQ/OC
UARTSEL
SS
SCLK/RTS
MISO/RX
MOSI/TX
CS
CLK/TXEN
SDO/RX
SDI/TX
MICROCONTROLLER
GND
GPO
WU
LED1
LED2
REG
V24
0.1µF
L+
MAX14827A
DI/DO
DO
DI
GND
1kΩ
1
2
4
3
C/Q
L-
C/Q
Figure 12. Multiplexed SPI/UART Mode Configuration
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Maxim Integrated │ 39
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX14827AATG+
PART
-40°C to +125°C
24 TQFN-EP*
MAX14827AATG+T
-40°C to +125°C
24 TQFN-EP*
MAX14827AAWA+
-40°C to +125°C
25 WLP
MAX14827AAWA+T
-40°C to +125°C
25 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape & Reel.
Chip Information
PROCESS: BiCMOS
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Maxim Integrated │ 40
MAX14827A
Low-Power, Ultra-Small, Dual Driver,
IO-Link Device Transceiver
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/16
Initial release
1
9/16
Added DI_Dis information
3/19
Updated the Typical Application Circuit, Pin Description and Wake-Up Detection sections,
and Figures 11 and 12
2
PAGES
CHANGED
DESCRIPTION
—
30, 36
1, 20, 26,
39–40
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc. │ 41
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