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MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
General Description
Benefits and Features
The MAX14828 integrates the high-voltage functions
commonly found in industrial sensors. The MAX14828
features one ultra low-power driver (C/Q) with active
reverse-polarity protection. An auxiliary digital input is
provided to allow firmware updates through a UART
interface. Transient protection is simplified due to high
voltage tolerance allowing the use of micro TVS.
The device features a flexible control interface. Pin-control
logic inputs allow for operation with switching sensors
that do not use a microcontroller. For sensors that use a
microcontroller, an SPI interface is available with extensive
diagnostics. For IO-Link operation, a UART interface is
provided, allowing interfacing to the microcontroller UART.
Finally, a multiplexed UART/SPI option allows using one
serial microcontroller interface for shared SPI and UART
interfaces.
The device includes on-board 3.3V and 5V linear
regulators for low-noise analog/logic supply rails.
The MAX14828 is available in a (4mm x 4mm) 24-pin
TQFN package and a (2.5mm x 2.5mm) wafer-level
package (WLP) and is specified over the extended -40°C
to +125°C temperature range.
●● Low Power Dissipation for Small Sensors
• 1.2Ω (typ) Driver On-Resistance
• 50mW (typ) Power Dissipation When Driving
100mA Load
●● High Configurability and Integration Reduce SKUs
• Auxiliary 24V Digital Input
• Selectable Driver Current: 50mA to 250mA
• SPI or Pin-Control Interface for Configuration and
Monitoring
• Multiplexed SPI/UART Interface Option
• 5V and 3.3V Linear Regulators
• Optional External Transistor Supports Higher
Regulator Loads
• Integrated LED Drivers
• Pin and Software Compatible to MAX14827A
●● Robust Communication
• 65V Absolute Maximum Ratings on Interface and
Supply Pins Allows for Flexible TVS Protection
• Glitch Filters for Improved Burst Resilience and
Noise
• Thermal Shutdown
• Hot-Plug Supply Protection
• Reverse Polarity Protection of All Sensor Interface
Inputs/Outputs
• -40°C to +125°C Operating Temperature Range
Applications
●● Industrial sensors
●● IO-Link sensors and actuators
●● Safety applications
Ordering Information appears at end of data sheet.
Typical Operating Circuit
5V
1µF
3.3V
1µF
10kΩ
VCC
VL
V33
V5
SPI/PIN
GPIO
0.1µF
L+
IRQ
WU
RX
RX
TX
TX
RTS
MAX14828
DI
GND
TXEN
UARTSEL
LED1
IO-Link is a registered trademark of Profibus User Organization (PNO).
SPI is a trademark of Motorola, Inc.
19-100001; Rev 1; 2/19
V24
IRQ/OC
SPI
MICROCONTROLLER
GND
REG
C/Q
1
2
L-
3
4
C/Q
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Functional Diagram
LED1 LED2*
LED1IN
SPI/PIN
IRQ/OC
CS/PP
SDI/TX/NPN
CLK/TXEN/200MA
SDO/RX/THSH
LED DRIVER
VL
V33
REG
V5
3.3V
LDO
MAX14828
V24
5V REG
REV POL
PROTECTION
UVLO
VDRV
CONTROL
AND
MONITOR
RX
TRANSCEIVER
REV POL
PROTECTION
C/Q
TX
TXEN
UARTSEL
WU
WAKE-UP DETECT
LI
DI
GND
* AVAILABLE ON WLP PACK AGE ONLY
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Maxim Integrated │ 2
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Absolute Maximum Ratings
(All voltages referenced to GND, unless otherwise noted.)
V24..........................................................................-70V to +65V
REG...............................................................-0.3V to (V5 + 16V)
V5, VL.......................................................................-0.3V to +6V
V33...............................................................-0.3V to (V5 + 0.3V)
C/Q, DI.......................... MIN: Larger of -70V and (V24 - 70V) to
MAX: the lower of +70V and (V24 + 70V)
Logic Inputs:
CS/PP, TXEN, TX, LED1IN,
UARTSEL, CLK/TXEN/200MA, SPI/PIN,
SDI/TX/NPN...............................................-0.3V to (VL + 0.3V)
Logic Outputs:
RX, LI, WU, SDO/RX/THSH...................... -0.3V to (VL + 0.3V)
IRQ/OC...................................................................-0.3V to +6V
LED1, LED2................................................... -0.3V to (V5+0.3V)
Continuous Current Into GND and V24.................................±1A
Continuous Current Into C/Q...........................................±500mA
Continuous Current Into V5 and REG.............................±100mA
Continuous Current Into Any Other Pin.............................±50mA
Continuous Power Dissipation
TQFN (derate 27.8mW/°C above +70°C)..................2222mW
WLP (derate 22.7mW/°C above +70°C).....................1816mW
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature.......................Internally Limited
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow, TQFN and WLP)............ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 24 TQFN
Package Code
T2444+4
Outline Number
21-0139
Land Pattern Number
90-0022
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
36°C/W
Junction to Case (θJC)
3°C/W
PACKAGE TYPE: 25 WLP
Package Code
W252L2+1
Outline Number
21-0787
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
44°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 3
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
DC Electrical Characteristics
(V24 = 9V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
V24 Supply Voltage
SYMBOL
V24
V24 Undervoltage Lockout
Threshold
V24UVLO
V24 Undervoltage Lockout
Threshold Hysteresis
V24UVLO_HYST
V24 Supply Current
V24 Low-Voltage Warning
Threshold
CONDITIONS
I24
9
VL Logic-Level Supply
Voltage
VL Undervoltage Threshold
VL Logic-Level Supply
Current
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V
V24 falling
6
7.2
9
570
V5 powered
externally, REG is
unconnected
mV
0.14
0.5
C/Q in push-pull
configuration,
CL[10] = 11,
C/Q is high,
no load on C/Q
0.5
0.75
C/Q in push-pull
configuration,
CL[10] = 11,
C/Q is low,
no load on C/Q
0.58
0.85
16.5
18
V
5.5
V
mA
14.5
V5 rising
2.8
3.5
4.5
V5 falling
2.8
3.45
4.5
0.54
0.85
0.93
1.4
1.0
1.4
External 5V
applied to
V5, REG is
unconnected, no
load on LED1 or
LED2
V
C/Q disabled
(CQ_Dis = 1)
C/Q in push-pull
configuration,
CL[10] = 11,
C/Q is high,
V33 enabled, no load
on C/Q or V33
C/Q in push-pull
configuration,
CL[10] = 11,
C/Q is low,
V33 enabled, no load
on C/Q or V33
VL
2.5
VLUVLO
IL
36
9
4.5
I5_IN
UNITS
7.8
V24W
V5UVLO
MAX
6
C/Q disabled
(CQ_Dis = 1),
V33 disabled
(V33_Dis = 1)
V5 Supply Current
TYP
V24 rising
V5 Supply Voltage
V5 Undervoltage Lockout
Threshold
MIN
0.9
All logic inputs at VL or GND, all logic
outputs unconnected
V
mA
5.5
V
1.7
2.4
V
0.25
3
µA
Maxim Integrated │ 4
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
DC Electrical Characteristics (continued)
(V24 = 9V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
5V LINEAR REGULATOR/CONTROLLER (V5)
V5 Output Voltage
V5
CONDITIONS
MIN
TYP
MAX
UNITS
REG = V5, no load on V5, 9V ≤ V24 ≤ 60V
4.75
Load Regulation
ΔV5_LDR
REG = V5, 0mA < ILOAD < 30mA,
V24 = 24V
Line Regulation
ΔV5_LNR
REG = V5, ILOAD = 1mA, V24 from 9V
to 60V
REG Output Current
V24 REG Dropout Voltage
REG Open Voltage
V5 Capacitance
IREG
Internal regulator or external NPN
ΔVREG
V24 = 9V, V5 = 4.5V, IREG = 5mA
VREG_OPN
5.00
5.25
V
0.02
0.2
%
0.01
4
mV/V
30
mA
2.35
V
V24 = 60V, V5 = 4.5V, no load on REG
10
13
16
V
CV5
Allowed capacitance on V5, REG
connected to V5 (Note 2)
0.8
1
2
µF
V33
No load on V33
3.1
3.3
3.5
V
0
0.4
0.8
%
0.8
1
3.3V LINEAR REGULATOR (V33)
V33 Output Voltage
V33 Load Regulation
V33 Capacitance
V33_LDR
0mA < ILOAD < 30mA
CV33
Allowed capacitance on V33, V33
enabled (Note 2)
ROH
High-side enabled, V24 = 24V,
CL[10] = 11, ILOAD = -200mA (Note 2)
1.25
2.4
ROL
Low-side enabled, V24 = 24V,
CL[10] = 11, ILOAD = +200mA (Note 2)
1.2
2.45
µF
C/Q DRIVER
Driver On-Resistance
Driver Current Limit
ICL
SPI/PIN = high,
VDRIVER = (V24
– 3V) or 3V,
CL_Dis = 0
SPI/PIN = low,
VDRIVER = (V24
– 3V) or 3V
Driver Peak Current
ICL_PEAK
CL[10] = 00
50
65
82
CL[10] = 01
100
120
150
CL[10] = 10
200
230
275
CL[10] = 11
250
290
350
CLK/TXEN/200MA
= low
100
120
150
CLK/TXEN/200MA
= high
200
230
275
DC current
490
C/Q driver is disabled (C/Q_Dis = 1),
RX disabled (Rx_Dis = 1), V24 = 24V,
(V24 - 65V) ≤ VC/Q ≤ +60V
C/Q Leakage Current
C/Q Output Reverse Current
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ILEAK_CQ
IREV_CQ
Ω
C/Q driver
enabled
-70
19.2
PNP mode, set to
high impedance (TX
= high), VC/Q = 0V
0
-100
mA
+10
NPN mode, set to
high impedance (TX
= low), VC/Q = 24V
C/Q driver enabled and in push-pull
configuration, V24 = 30V,
VC/Q = (V24 + 5V) or (VGND - 5V)
mA
μA
+1000
μA
Maxim Integrated │ 5
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
DC Electrical Characteristics (continued)
(V24 = 9V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Weak Pulldown Current
SYMBOL
IPD
CONDITIONS
SPI/PIN = high,
driver disabled
(CQ_Dis = 1)
IPU
SPI/PIN = high,
driver disabled
(CQ_Dis = 1),
VDRIVER = V24
- 5V
Input Voltage Range
VIN
For valid RX logic
C/Q, DI Input Threshold High
VTH
C/Q driver
disabled
C/Q, DI Input Threshold Low
VTL
C/Q driver
disabled
C/Q, DI Input Hysteresis
VHYS_CQ
C/Q driver
disabled
C/Q Input Capacitance
CIN_CQ
DI Input Capacitance
Weak Pullup Current
MIN
TYP
MAX
UNITS
VDRIVER = 5V,
CQ_WPD = 1, CQ_
WPU = 0
200
300
400
VDRIVER = 24V,
CQ_WPD = 1, CQ_
WPU = 0
200
470
1000
CQ_WPU = 1, CQ_
WPD = 0
-400
-300
-200
μA
+65
V
μA
C/Q, DI RECEIVER
C/Q Input Current
DI Leakage Current
DI Input Current
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V24 65
V24 > 18V
11
11.8
12.5
V
V24 < 18V
59
65.5
72
% of
V24
V24 > 18V
9
9.8
10.5
V
V24 < 18V
45
54.5
63
% of
V24
V24 > 18V
2
V
V24 < 18V
11
% of
V24
Driver disabled, weak pullup and
pulldown disabled, f = 100kHz
90
pF
CIN_DI
f = 100kHz
10
pF
IIN_CQ
C/Q driver
disabled
(CQ_Dis = 1),
C/Q receiver
enabled, V24 =
24V
ILEAK_DI
IIN_DI
-5V ≤ VC/Q ≤ (V24
+ 5V)
+30
µA
(V24 - 65V) ≤ VC/Q
≤ +60V
-70
+70
-40
+150
-5V ≤ VDI ≤ (V24
+5V)
-10
+35
(V24 - 65V) ≤ VDI ≤
+60V
-40
+200
DI receiver disabled (DI_Dis = 1),
V24 = 24V, (V24 - 65V) ≤ VDI ≤ +60V
DI receiver
enabled,
V24 = 24V
-10
µA
µA
Maxim Integrated │ 6
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
DC Electrical Characteristics (continued)
(V24 = 9V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V; REG unconnected, all logic inputs at VL or GND; TA = -40°C to
+125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.2 x VL
V
LOGIC INPUTS (CS/PP, TXEN, TX, LED1IN, CLK/TXEN/200MA, SPI/PIN, SDI/TX/NPN)
Logic Input Voltage Low
VIL
Logic Input Voltage High
VIH
Logic Input Leakage Current
ILEAK
0.8 x VL
Logic input = GND or VL
LOGIC OUTPUTS (RX, LI, WU, IRQ/OC, SDO/RX/THSH)
Logic Output Voltage Low
VOL
IOUT = -5mA
Logic Output Voltage High
VOH
IOUT = 5mA
V
-1
+1
µA
0.4
V
VL - 0.4
V
IRQ/OC Open-Drain Leakage
Current
ILK_OD
IRQ/OC high impedance,
IRQ/OC = GND or VL
-1
+1
μA
SDO Leakage Current
ILK_SDO
SPI/PIN = high, CS/PP = high, SDO/
RX/THSH = GND or VL
-1
+1
µA
ILK_RX
SPI/PIN = high, DI_Dis = 1, RX_Dis =
1, RX/LI = GND or VL
-1
+1
µA
LED Output Voltage Low
VLEDOL
IOUT = -5mA
0.4
V
LED Output Voltage High
VLEDOH
IOUT = 10mA
RX, LI Leakage Current
LED DRIVERS (LED1, LED2)
V5 - 0.4
V
THERMAL MANAGEMENT
Thermal Warning Threshold
TWRN
Thermal Warning Threshold
Hysteresis
TWRN_HYS
Per-Driver Thermal
Shutdown Temperature
TSHUT_D
Per-Driver Thermal
Shutdown Temperature
Hysteresis
TSHUT_DHYS
Die junction temperature rising,
TempW and TempWInt bits are set
Die junction temperature falling,
TempW bit cleared
Driver temperature rising, temperature
at which the driver is turned off
Driver temperature falling
+140
°C
15
°C
+160
°C
15
°C
IC Thermal Shutdown
TSHUT_IC
Die temperature rising, ThShut and
ThuShutInt bits are set
+170
°C
IC Thermal-Shutdown
Hysteresis
TSHUT_ICHYS
Die temperature falling, ThShut bit is
cleared
15
°C
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Maxim Integrated │ 7
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
AC Electrical Characteristics
(V24 = 18V to 30V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V, REG unconnected, all logic inputs at VL or GND, TA = -40°C
to +125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Push-pull and PNP configuration, Figure1
0.21
0.45
NPN configuration, Figure 1
0.16
Push-pull and NPN configuration, Figure1
0.47
PNP configuration, Figure 1
0.28
UNITS
C/Q DRIVER
Driver Low-to-High Propagation
Delay
tPDLH_PP
Driver High-to-Low Propagation
Delay
tPDHL_PP
Driver Skew
tSKEW
Push-pull configuration, Figure 1
| tPDLH - tPDHL |
Driver Rise Time
tRISE
Push-pull and PNP configuration, Figure 1
Driver Fall Time
tFALL
Driver Enable Time High
Driver Enable Time Low
-0.4
0.7
µs
µs
+0.4
µs
0.17
0.4
µs
Push-pull and NPN configuration, Figure 1
0.17
0.4
µs
tENH
Push-pull and PNP configuration, Figure 2
0.19
0.5
µs
tENL
Push-pull and NPN configuration, Figure 3
0.44
0.7
µs
Driver Disable Time High
tDISH
Push-pull and PNP configuration, Figure 2
1.8
3
µs
Driver Disable Time Low
tDISL
Push-pull and NPN configuration, Figure 3
1.5
3
µs
C/Q, DI RECEIVER (Figure 4)
SPI/PIN = high or low, CQFil = 0
0.85
1.3
2.1
SPI/PIN = high, CQFil = 1
0.2
0.3
0.5
SPI/PIN = high or low, CQFil = 0
0.85
1.3
2.1
SPI/PIN = high, CQFil = 1
0.2
0.3
0.5
tPRLH_DI
1.3
2.2
3.5
tPRHL_DI
1.3
2.2
3.5
C/Q Receiver Low-to-High
Propagation Delay
tPRLH_CQ
C/Q Receiver High-to-Low
Propagation Delay
tPRHL_CQ
DI Receiver Low-to-High
Propagation Delay
DI Receiver High-to-Low
Propagation Delay
µs
µs
µs
DRIVER CURRENT LIMITING
Blanking Time
tCL_ARBL
SPI/PIN = high
CL_BL[10] = 00
0.128
CL_BL[10] = 01
0.5
CL_BL[10] = 10
1
CL_BL[10] = 11
5
SPI/PIN = low
Autoretry Period
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tCL_ARP
SPI/PIN = high,
ArEn = 1 (Note 3)
ms
0.128
TAr[10] = 00
50
TAr[10] = 01
100
TAr[10] = 10
200
TAr[10] = 11
500
ms
Maxim Integrated │ 8
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
AC Electrical Characteristics (continued)
(V24 = 18V to 30V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, VGND = 0V, REG unconnected, all logic inputs at VL or GND, TA = -40°C
to +125°C, unless otherwise noted. Typical values are at V24 = 24V, V5 = 5V, VL = 3.3V, and TA = +25°C, unless otherwise noted.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
55
66
75
µs
85
95
110
µs
100
200
300
µs
WAKE-UP DETECTION (Figure 5)
Wake-Up Input Minimum Pulse
Width
tWUMIN
Wake-Up Input Maximum Pulse
Width
tWUMAX
WU Output Low Time
tWUL
CL = 3nF
Valid wake-up condition on C/Q
SPI TIMING (CS/PP, CLK/TXEN/200MA, SDI/TX/NPN, SDO/RX/THSH) (Figure 6)
Maximum SPI Clock Frequency
12.5
MHz
CLK/TXEN/200MA Clock Period
tCH+CL
80
ns
CLK/TXEN/200MA Pulse-Width
High
tCH
40
ns
CLK/TXEN/200MA Pulse-Width
Low
tCL
40
ns
CS/PP Fall to CLK/TXEN/200MA
Rise Time
tCSS
20
ns
CLK/TXEN/200MA Rise to CS/
PP Rise Hold Time
tCSH
40
ns
SDI/TX/NPN Hold Time
tDH
10
ns
SDI/TX/NPN Setup Time
tDS
25
ns
Output Data Propagation Delay
tDO
20
ns
tFT
20
ns
tCSW
10
ns
SDO/RX/THSH Rise and Fall Times
Minimum CS/PP Pulse
Note 1: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design.
Note 2: Not production tested. Guaranteed by design.
Note 3: Autoretry functionality is not available in pin-mode.
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Maxim Integrated │ 9
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
V24
TXEN
TX
TXEN
MAX14828
MAX14828
TX
C/Q
3.3nF
GND
5kΩ
5kΩ
3.3nF
GND
PUSH-PULL AND PNP MODE
C/Q
NPN MODE
VL
TXEN
0V
VL
TX
50%
50%
tPDHL
C/Q
0V
tPDLH
50%
90%
90%
10%
10%
tFALL
V24
50%
0V
tRISE
Figure 1. C/Q Driver Propagation Delays and Rise/Fall Times
V24
TXEN
VL
TX
MAX14828
GND
5kΩ
C/Q
3.3nF
VL
TXEN
0V
tDISH
tENL
V24
C/Q
50%
10%
0V
Figure 2. C/Q Driver Enable Low and Disable High Timing with External Pullup Resistor
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Maxim Integrated │ 10
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
TXEN
TX
MAX14828
C/Q
GND
3.3nF
5kΩ
VL
TXEN
0V
tDISL
tENH
C/Q
V24
90%
50%
0V
Figure 3. C/Q Driver Enable High and Disable Low Timing
TXEN
MAX14828
C/Q, DI
GND
RX, LI
15pF
V24
C/Q, DI
50%
50%
0V
tPRHL
tPRLH
RX, LI
VL
50%
50%
0V
Figure 4. C/Q and DI Receiver Propagation Delays
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Maxim Integrated │ 11
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
TXEN
WU
MAX14828
C/Q
TX
GND
TXEN
TX
< tWUMI N
NO WAKE-UP
C/Q
tWUMI N < tWU < tWUMA X
WU
tWUL
Figure 5. Wake-Up Detection Timing
CS/PP
tCSH
tCSS
tCL
tCSH
tCH
CLK/TXEN/200MA
tDS
tDH
SDI/TX/NPN
tDO
SDO/RX/THSH
Figure 6. SPI Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 12
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Typical Operating Characteristics
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q in push-pull configuration, TA = +25°C, unless otherwise noted.)
toc01
20
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.75
1.50
1.25
TA = +25ºC
1.00
0.75
TA = +125ºC
TA = -40ºC
0.50
0.00
6
12
18
24
30
36
42
48
54
toc02
1.8
16
1.6
14
1nF LOAD
12
10
8
4
SUPPLY VOLTAGE (V)
24.0
0
50
100
150
200
toc04
OUTPUT VOLTAGE LOW (V)
OUTPUT VOLTAGE HIGH (V)
23.6
23.5
23.4
23.3
0.0
75 100 125 150 175 200 225 250
0
25
50
75 100 125 150 175 200 225 250
LOAD CURRENT (mA)
toc06
C/Q CURRENT LIMIT
0
C/Q IN PUSH-PULL
C/Q IS LOW
-50
CL[10] = 00
-100
CL[10] = 01
SOURCE CURRENT (mA)
SINK CURRENT (mA)
toc05
0.3
LOAD CURRENT (mA)
200
toc07
-150
150
-200
CL[10] = 01
100
CL[10] = 10
-250
CL[10] = 00
50
0
250
0.4
0.1
CL[10] = 10
200
0.5
0.2
250
150
0.6
23.1
CL[10] = 11
100
0.7
23.2
C/Q CURRENT LIMIT
50
1.0
0.8
300
0
C/Q DRIVER OUTPUT LOW
vs. SINK CURRENT
23.7
350
C/Q IN PUSH-PULL
REG UNCONNECTED
V5 = 5V
C/Q SWITCHING RATE (kbps)
0.9
50
NO LOAD
0.8
0.0
250
23.8
25
1.0
0.2
C/Q IN PUSH-PULL
23.9
0
1.2
C/Q SWITCHING RATE (kbps)
C/Q DRIVER OUTPUT HIGH
vs. SOURCE CURRENT
23.0
1nF LOAD
1.4
0.4
NO LOAD
2
0
toc03
0.6
6
60
V5 SUPPLY CURRENT
vs. C/Q SWITCHING RATE
2.0
18
C/Q IN PUSH-PULL
NO SWITCHING
C/Q = HIGH
0.25
I24 SUPPLY CURRENT
vs. C/Q SWITCHING RATE
SUPPLY CURRENT (mA)
I24 SUPPLY CURRENT
vs. V24 SUPPLY VOLTAGE
2.00
CL[10] = 11
-300
0
6
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12
18
24
OUTPUT VOLTAGE LOW (V)
30
-350
C/Q IN PUSH-PULL
C/Q IS HIGH
0
6
12
18
24
OUTPUT VOLTAGE LOW (V)
30
Maxim Integrated │ 13
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Typical Operating Characteristics (continued)
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q in push-pull configuration, TA = +25°C, unless otherwise noted.)
C/Q DRIVER LEAKAGE CURRENT
vs. C/Q VOLTAGE
10
toc8
TA = +125ºC
-20
TA = -40ºC
-30
TA = +25ºC
-40
600
TA = +125ºC
500
400
TA = -40ºC
300
200
100
-10
0
10
20
30
40
50
-200
60
C/Q RECEIVER INPUT
CURRENT vs. INPUT VOLTAGE
30
40
50
toc11
CQ_Dis = 1
CQ_WPU = 1
-400
-500
60
-10
0
10
TA = -40ºC
20
10
TA = +25ºC
0
-10
0
10
20
30
40
50
60
INPUT VOLTAGE (V)
C/Q DRIVER SWITCHING
INTO 1nF LOAD
VOUTN
www.maximintegrated.com
60
toc12
40
TA = +25ºC
30
20
TA = -40ºC
-10
-10
0
10
20
30
40
50
60
INPUT VOLTAGE (V)
C/Q DRIVER SWITCHING
INTO 4.7nF LOAD
toc13
toc14
TX
2V/div
0V
TX
2V/div
0V
C/Q
5V/div
C/Q
5V/div
0V
C/Q IS PUSH-PULL 10µs/div
CLOAD = 1nF
50
TA = +125ºC
VINSIDE
VBACKUP
40
50
0
C/Q receiver enabled
30
DI_Dis = 0
10
-10
20
DI RECEIVER INPUT
CURRENT vs. INPUT VOLTAGE
70
TA = +125ºC
30
TA = -40ºC
C/Q VOLTAGE (V)
INPUT CURRENT (µA)
INPUT CURRENT (µA)
20
TA = +25ºC
0
-300
60
40
-20
10
TA = +125ºC
100
C/Q VOLTAGE (V)
C/Q VOLTAGE (V)
50
0
200
-200
CQ_Dis = 1
CQ_WPD = 1
-10
300
-100
TA = +25ºC
-100
C/Q driver disabled
toc10
400
700
0
-50
C/Q WEAK PULLUP CURRENT
vs. C/Q VOLTAGE
500
PULL-UP CURRENT (mA)
-10
PULL-DOWN CURRENT (µA)
LEAKAGE CURRENT (µA)
900
toc9
800
0
-60
C/Q WEAK PULLDOWN CURRENT
vs. C/Q VOLTAGE
10µs/div
0V
Maxim Integrated │ 14
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Typical Operating Characteristics (continued)
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q in push-pull configuration, TA = +25°C, unless otherwise noted.)
V5 LINEAR REGULATOR
LOAD REGULATION
toc15
VOUTN
0.000
5.058
-0.020
5.056
LOAD REGUIATION (%)
TA = -40ºC
-0.040
0V
-0.050
VBACKUP
WU
2V/div
0V
TXEN = VL
TX = GND
40µs/div
TA = +125ºC
TA = +25ºC
-0.060
5.052
5.050
5.048
5.046
-0.080
5.044
-0.090
5.042
-0.100
5.040
5
10
15
20
25
30
EXTERNAL NPN TRANSISTOR
CONNECTED TO V5 AND REG
ILOAD = 10mA ON V5
10
20
0.0
toc18
LED1 OR LED2 VOLTAGE (V)
-0.3
TA = -40ºC
-0.4
-0.5
TA = +25ºC
-0.6
-0.7
TA = +125ºC
-0.8
50
60
toc19
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
10
15
20
25
0.0
30
0
2
4
6
LED DRIVER OUTPUT LOW
VOLTAGE vs SINK CURRENT
200
toc20
5.07
V5 VOLTAGE (V)
5.08
140
120
100
80
5.02
20
5.01
0
5.00
www.maximintegrated.com
18
20
toc21
5.04
5.03
6
8 10 12 14
LOAD CURRENT (mA)
16
5.05
40
4
14
5.06
60
2
12
5.09
160
0
10
V5 VOLTAGE vs TEMPERATURE
5.10
LED DRIVER TURNED OFF
180
8
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LED1 OR LED2 VOLTAGE (mV)
40
5.0
-0.2
LOAD REGUIATION (%)
LED DRIVER OUTPUT HIGH
VOLTAGE vs LOAD CURRENT
5.5
-0.1
-0.9
30
V24 VOLTAGE (V)
LOAD CURRENT (mA)
V33 LINEAR REGULATOR
LOAD REGULATION
toc17
5.054
-0.070
0
V5 LINEAR REGULATOR
LINE REGULATION
5.060
-0.010
-0.030
C/Q
10V/div
VINSIDE
toc16
V5 VOLTAGE (V)
WAKE-UP DETECTION
16
18
20
ILOAD = 20mA
-45
-20
5
55
80
30
TEMPERATURE (ºC)
105
130
Maxim Integrated │ 15
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Typical Operating Characteristics (continued)
(V24 = 24V, VL = V33, REG is shorted to V5, C/Q in push-pull configuration, TA = +25°C, unless otherwise noted.)
V5 LOAD REGULATION
V5 LINE REGULATION
toc22
ILOAD
10mA/div
V24
10V/div
0mA
0V
V5
AC-Coupled
50mV/div
V5
AC-Coupled
200mV/div
40µs/div
40µs/div
V33 LOAD REGULATION
V33 LINE REGULATION
toc24
ILOAD
10mA/div
0V
V33
AC-Coupled
2V/div
V33
AC-Coupled
20mV/div
www.maximintegrated.com
toc25
V5
2V/div
0mA
40µs/div
toc23
40µs/div
Maxim Integrated │ 16
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
WU
I.C.
UARTSEL
LI
VL
V33
Pin Configuration
18
17
16
15
14
13
TOP VIEW
LED1IN
19
IRQ/OC
20
SDO/RX/THSH
21
CLK/TXEN/200MA
22
SPI/PIN
23
* EP
MAX14828
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
A
C/Q
V24
GND
C/Q
DI
B
V5
REG
LED1
V33
VL
C
TX
TXEN
LED2
UART
SEL
LI
D
RX
SPI/PIN
SDO/RX/
THSH
WU
I.C.
E
CS/PP
SDI/TX/
NPN
CLK/TXEN/
200MA
IRQ/OC
LED1IN
+
12
DI
11
C/Q
10
GND
9
V24
8
C/Q
7
LED1
+
3
4
5
6
TX
V5
REG
2
TXEN
1
RX
24
CS/PP
SDI/TX/NPN
WLP
2.5mm x 2.5mm
TQFN
4mm x 4mm
Pin Description
PIN
TQFN
FUNCTION
WLP
NAME
PIN
DESCRIPTION
PARALLEL
MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = High
SPI chip-select and
UART signal select
input. When CS/PP is
high, the SPI interface
is disabled and UART
interface mode is
enabled on the SDO/
RX/THSH, SDI/TX/NPN,
and CLK/TXEN/200MA
logic pins.
1
E1
CS/PP
CS/PP Logic
Input
SPI active-low
chip-select input.
Drive CS/PP
low to start the
SPI read/write
cycle. Drive CS/
PP high to end
the SPI cycle.
UART interface is
enabled on RX,
TX, and TXEN.
2
D1
RX
C/Q Receiver
Logic Output
RX is the inverse logic of C/Q. RX can be
disabled with the SPI interface. RX is high
impedance when Rx_Dis = 1.
www.maximintegrated.com
PIN MODE
(SPI/PIN = Low)
Push-pull select input. Drive
CS/PP high to enable pushpull mode for the C/Q and
DO drivers. Drive CS/PP
low to select PNP or NPN
operation for the drivers.
RX is the inverse logic of
C/Q. RX is always active.
Maxim Integrated │ 17
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Pin Description (continued)
PIN
TQFN
3
4
FUNCTION
WLP
C2
PARALLEL
MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = High
C/Q Driver
Enable Logic
Input
Drive TXEN high
to enable the C/Q
driver. See Table
1.
With CS/PP low and
ENMPX = 0, drive TXEN
high to enable C/Q.
Drive TXEN high to enable
the C/Q driver. Drive TXEN
low to disable the C/Q
driver and enable the C/Q
receiver.
TX
C/Q Driver
Communication
Input
The logic on the
C/Q output is the
inverse logic level
of the signal on
the TX input. See
Table 1.
With CS/PP low and
ENMPX = 0, the logic
on the C/Q output is the
inverse logic level of the
signal on the SDI/TX/
NPN input. Signals on
TX are ignored. See the
Mode Selection table.
The logic on the C/Q output
is the inverse logic level of
the signal on the TX input
when TXEN is high.
5V must be present on V5 for normal operation. Bypass V5 to GND with a
1μF capacitor. V5 can be supplied by the internal 5V linear regulator or by
an external regulator. To use the internal regulator, connect V5 to REG, or
to the emitter of an external NPN transistor. To bypass the internal regulator,
connect an external 5V supply directly to V5.
NAME
TXEN
C1
PIN
DESCRIPTION
5
B1
V5
5V PowerSupply Input/
Output
6
B2
REG
5V Regulator
Control Output
7
—
B3
C3
LED1
LED2
www.maximintegrated.com
PIN MODE
(SPI/PIN = Low)
To use the internal linear regulator, connect REG to V5 or connect REG to
the base of an external NPN pass transistor. Leave REG unconnected and
connect V5 to an external 5V supply to bypass the internal regulator.
LED Driver
Output 1
LED1 is a 5V logic output. Connect a currentlimiting resistor in series between LED1 and
the LED to limit the LED current. LED1 can be
controlled by driving the LED1IN high or low,
or through the SPI interface. Set the LED1b
bit high to turn on the LED, clear the LED1b
bit to turn off the LED. Alternatively, drive the
LED1IN input high to turn on the LED, drive
LED1IN low to turn off the LED. See Table 2.
LED1 is a 5V logic output.
Connect a current-limiting
resistor in series between
LED1 and the LED to limit
the LED current. Drive the
LED1IN input high to turn
on the LED, drive LED1IN
low to turn off the LED.
LED Driver
Output 2
LED2 is a 5V logic output. Connect a currentlimiting resistor in series between LED2 and
the LED to limit the LED current. Set the
LED2b bit high to turn on the LED, clear the
LED2b bit to turn off the LED.
LED2 cannot be controlled
in pin-mode. LED2 is off.
Maxim Integrated │ 18
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Pin Description (continued)
PIN
TQFN
FUNCTION
WLP
NAME
PIN
DESCRIPTION
8, 11
A1,
A4
C/Q
C/Q Transceiver
Output/
Input
9
A2
V24
Power-Supply
Input
10
A3
GND
12
A5
DI
UARTSEL = High
The C/Q driver can be controlled and
monitored with the logic input/output pins or
through the SPI interface. Drive TXEN high to
enable the C/Q driver. The logic on the C/Q
output is the inverse logic-level of the signal
in the TX input. RX is the logic inverse of C/Q.
Connect the two C/Q pins together.
Drive TXEN high to enable
the C/Q driver. The logic
on the C/Q output is the
inverse logic-level of the
signal in the TX input. RX is
the logic inverse of C/Q.
Configure the C/Q driver
with the pin-mode inputs.
Connect the two C/Q pins
together.
Bypass V24 to GND with a 0.1μF ceramic capacitor as close to the device as
possible.
DI Receiver
Input
The LI output is the inverse
logic-level of the signal on
the DI input. The DI receiver
cannot be disabled in
pin-mode. Connect a 1kΩ
resistor in series with the
DI pin.
Bypass V33 to GND with a 1μF capacitor as
close to the IC as possible. The V33 regulator
can be disabled through the SPI interface.
Bypass V33 to GND with
a 1μF capacitor as close
to the IC as possible. V33
cannot be disabled in pinmode.
V33
3.3V Linear
Regulator Output
14
B5
VL
Logic-Level
Supply Input
LI
DI Receiver
Logic Output
16
C4
UARTSEL
UART Interface
Select Logic
Input
17
D5
I.C.
Internally
Connected
www.maximintegrated.com
UARTSEL = Low
PIN MODE
(SPI/PIN = Low)
The DI receiver can be monitored on the LI
output or through the SPI interface. The LI
output is the inverse logic-level of the signal on
the DI input. Connect a 1kΩ resistor in series
with the DI pin.
B4
C5
MULTIPLEXED MODE
(SPI/PIN = High)
Ground
13
15
PARALLEL
MODE
(SPI/PIN = High)
VL defines the logic levels on all of the logic inputs and outputs. Apply a
voltage from 2.5V to 5.5V on VL. Bypass VL to GND with a 0.1μF ceramic
capacitor.
The LI output is the inverse logic-level of
the signal on the DI input. Disable the LI
output through the SPI interface. LI is high
impedance when the DI_Dis bit is set.
The LI output is the inverse
logic-level of the signal on
the DI input. LI cannot be
disabled in pin-mode.
Drive UARTSEL
low to use
RX, TX, and
TXEN for UART
signaling.
UARTSEL is inactive when
SPI/PIN is low.
When CS/PP is high,
use SDO/RX/THSH,
SDI/TX/NPN, and CLK/
TXEN/200MA for UART
signaling.
Internally connected. Connect to GND or VL.
Maxim Integrated │ 19
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Pin Description (continued)
PIN
TQFN
18
19
20
21
FUNCTION
WLP
D4
E5
E4
D3
NAME
PIN
DESCRIPTION
PARALLEL
MODE
(SPI/PIN = High)
MULTIPLEXED MODE
(SPI/PIN = High)
UARTSEL = Low
UARTSEL = High
PIN MODE
(SPI/PIN = Low)
WU
Wake-Up
Request PushPull Output
LED1IN
LED1 Driver
Logic Input
Drive LED1IN high or low to enable/disable
the LED1 driver. The LED1 driver can also
be controlled through the SPI interface. See
Table 2.
Drive LED1IN high to turn
on the LED connected to
LED1. Drive LED1IN low to
turn the LED driver off.
IRQ/OC
Open-Drain
Interrupt/
Over-current
Output
IRQ/OC asserts when any bit in the
INTERRUPT register is set. IRQ/OC
deasserts when the INTERRUPT register is
read.
IRQ/OC asserts low when
the load current on the C/Q
or DO output exceeds the
set current limit.
SDO/
RX/
THSH
SPI Serial Data
Output/
RX Logic
Output/
Thermal
Shutdown
Indicator
22
E3
CLK/
TXEN/
200MA
SPI Clock Input/
UART TXEN
Input/
Current Limit
Setting Input
23
D2
SPI/PIN
SPI or Pin-Mode
Select Input
SPI Serial Data
Input/
TX Logic Input/
NPN Driver
Mode Select
Input
24
E2
SDI/TX/
NPN
EP
—
EP
www.maximintegrated.com
WU asserts low for 200μs when an IO-Link 80μs wake-up condition is
detected on the C/Q line.
SPI serial data
output
When CS/PP is high, the
SPI interface is disabled
and UART interface mode
is enabled. SDO/RX/THSH
is the logic inverse of C/Q.
SDO/RX/THSH asserts low
when the IC enters thermal
shutdown. SDO/RX/THSH
deasserts when the device
returns to normal operation.
SPI clock input
When CS/PP is high, the
SPI interface is disabled
and UART interface mode
is enabled. Drive CLK/
TXEN/200MA high to
enable the C/Q driver.
Drive CLK/TXEN/200MA
high to enable a 200mA
current limit on the C/Q and
DO driver outputs. Drive
CLK/TXEN/200MA low to
set the current limit for the
driver outputs to 100mA.
Drive SPI/PIN high for SPI or UART interface operation. Drive SPI/PIN low
for pin-mode operation.
SPI serial data
input
When CS/PP is high, the
SPI interface is disabled
and UART interface mode
is enabled. Drive SDI/TX/
NPN to switch C/Q. C/Q
is the logic inverse of the
SDI/TX/NPN input.
Drive SDI/TX/NPN high to
set the C/Q and DO driver
outputs in NPN mode.
Drive SDI/TX/NPN low to
set the driver outputs in
PNP mode. SDI/TX/NPN
is ignored when the CS/PP
input is high.
Exposed pad. Connect to ground. Not intended as the main ground connection.
Maxim Integrated │ 20
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Table 1. C/Q Control
SPI/PIN
L
TX
CQ_Dis
CQ_Q
L
X
—
—
Z
Z
Z
L
—
—
Z
H
H
H
—
—
L
Z
L
X
0
0
Z
Z
Z
X
0
1
Z
H
H
H
L
H
C/Q OUTPUT
TXEN
H
X
NPN MODE
PNP MODE
PP MODE
L
0
X
Z
H
H
H
0
0
L
Z
L
H
0
1
Z
H
H
X
1
X
Z
Z
Z
X = Don’t care, Z = High impedance
Table 2. LED1 Configuration
LED1IN
L
H
LED1b BIT
LED1 DRIVER STATUS
0
OFF
1
ON
0
ON
1
ON
www.maximintegrated.com
Table 3. Driver NPN, PNP, PP Selection in
Pin Mode
SPI/PIN
CS/PP
SDI/TX/NPN
C/Q DRIVER MODE
L
L
L
PNP
L
L
H
NPN
L
H
L
PUSH-PULL
L
H
H
PUSH-PULL
H
X
X
C/Q mode is set with
the SPI interface
Maxim Integrated │ 21
MAX14828
Detailed Description
The MAX14828 is an industrial sensor output driver/IOLink device transceiver. The IC integrates the high voltage
functions commonly found in sensors, including a single
24V line driver and two on-board linear regulators (LDOs).
The MAX14828 can be configured and monitored either
through the SPI interface or by setting logic interface pins.
The MAX14828 features multiple programmable functions
that allow the user to optimize operation and power
dissipation for various loads and application scenarios.
The integrated 3.3V and 5V LDOs provide the power
needed for low noise analog and logic supply rails.
SPI, UART, or Pin-Mode Interface
Pin Mode
The MAX14828 provides a selectable SPI or pin interface
to configure and monitor device operation. Drive the SPI/
PIN input high to use the SPI. Drive SPI/PIN low to use the
pin interface (pin-mode control).
When operating in pin mode, the following functionality is
set and cannot be changed:
•
•
•
•
RX and DI are enabled (cannot be disabled)
RX deglitch filter is enabled
Weak pull-ups/pull-downs on C/Q are disabled
Autoretry functionality is disabled
• The blanking time on C/Q is 128μs
SPI Operation (Parallel Operating Mode)
When the MAX14828 is operated in SPI mode, an external
UART can be connected to separate UART interface pins
(TX, RX, TXEN). This is called the parallel SPI/UART
operating mode. This is the common approach used when
the microcontroller offers a UART and a separate SPI port
in the Typical Operating Circuit. Drive UARTSEL low for
operation in parallel mode.
SPI Operation (Multiplexed Mode)
In cases where only one microcontroller serial port
is available with both SPI and UART functions, the
MAX14828 can be operated in multiplexed SPI/UART
mode. This is feasible in IO-Link operation due to the
defined idle times in the IO-Link cycle time. In multiplexed
mode, the UART and SPI pins are shared. Two operating
modes are available in multiplexed mode, as selected by
the ENMPX bit.
When ENMPX = 0, UART and SPI operation are selected
by setting the CS/PP input. In this mode the SPI interface
is active when CS/PP is low and UART operation when
CS/PP is high.
Low-Power, Ultra-Small IO-Link
Device Transceiver
When ENMPX = 1, UART and SPI operations are
selected by setting the UARTSEL input. To avoid glitches
on C/Q, CLK/TXEN/200MA and SDI/TX/NPN are sampled
on the falling edge of UARTSEL in this mode. See Mode
Selection Table for more information.
When entering multiplexed mode, set TXEN low and TX
high to disable the driver.
IRQ/OC is active in both multiplexed modes during UART
communication.
24V Interface
The MAX14828 features an IO-Link transceiver interface
tolerant of voltages from (V24-70V) to +65V. This is the 24V
interface and includes the C/Q input/output (C/Q), the logiclevel digital input (DI), and the V24 supply.
The MAX14828 features a selectable push-pull, high-side
(PNP), or low-side (NPN) switching driver at C/Q.
Configurable Drivers (Pin Mode)
In pin mode, use SDI/TX/NPN and CS/PP inputs to
configure the C/Q driver in push-pull, PNP, or NPN modes
(Table 3). In this mode, toggle TXEN and TX to switch the
C/Q output.
Configurable Drivers (SPI Mode)
Set the bits in the CQConfig register to configure the C/Q
driver, enable/disable the weak pull-up and pull-down
currents on C/Q. The C/Q driver can be disabled by setting
the CQ_Dis bit. The driver output is high impedance and
power dissipation is reduced when this bit is set. See the
Register Functionality section for more information on
configuring the C/Q driver.
For IO-Link operation, TX, TXEN, and RX are the UART
interface to control C/Q communication. Set CQ_Dis =
CQ_Q = 0 and drive TX and TXEN inputs for C/Q driver
control.
Register bits can also be used to control the C/Q driver
for lower rate switching. For bit control, drive TXEN and
TX high and use the CQ_Q bit to control the C/Q driver
state. The CQ_Dis bit is used to enable/disable the driver
in this mode.
C/Q Driver Enable/Disable
In pin-mode, the C/Q driver is enabled/disabled with the
TXEN input. Drive TXEN high to enable the C/Q driver.
C/Q is the logic inverse of the TX input.
In SPI mode, the C/Q driver can also be enabled/disabled,
configured, and controlled in the CQConfig register.
IO-Link is a registered trademark of Profibus User Organization (PNO).
SPI is a trademark of Motorola, Inc.
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Maxim Integrated │ 22
MAX14828
C/Q Current Limit
The C/Q driver is optimized for driving large capacitive
loads and dynamic impedances like incandescent
lamps. In pin-mode, the driver current limit is selectable
by setting the CLK/TXEN/200MA input high or low. Set
CLK/TXEN/200MA low for 100mA maximum load current.
Set CLK/TXEN/200MA high for a 200mA maximum load
current.
In SPI operation, the maximum driver current limit is
selectable as 50mA, 100mA, 200mA, or 250mA by setting
the CL1 and CL0 bits in the CURRLIM register.
C/Q Driver Fault Detection
The MAX14828 senses a fault condition on the C/Q driver
when it detects a short-circuit for longer than the blanking
time. A short condition exists when the C/Q driver’s load
current exceeds the current limit. In SPI mode, both the
current limit and blanking time may be configured.
In pin-mode, the IRQ/OC output asserts low when a short
circuit fault occurs on C/Q. In SPI mode, the C/QFault and
C/QFaultInt bits are set and IRQ/OC asserts.
When a short-circuit event occurs on C/Q, the driver can
either be set to continue supplying the selected current
until the device enters thermal shutdown or to enter
autoretry mode when an overcurrent event occurs. In
autoretry mode the driver is automattically disabled after
the current blanking time and is then re-enabled.
C/Q Receiver Output (RX)
RX is the output of the C/Q receiver. RX is the inverse logic
of the C/Q input.
In pin-control mode, the C/Q receiver is always on.
In SPI mode, the receiver can be disabled by setting the
Rx_Dis bit in the CQConfig register. RX is high impedance
when Rx_Dis is set. Note that the CQLvl bit in the Status
register is invalid when the Rx_Dis bit is set.
When operating in multiplexed mode, SDO/RX/THSH is the
output of the C/Q receiver. In this mode, SDO/RX/THSH is
high impedance when CS/PP is high and Rx_Dis bit is set.
C/Q Receiver Threshold
The IO-Link standard defines device operation with a
sensor supply between 18V and 30V. Industrial sensors,
however, commonly operate with supply voltages as low as
9V. The MAX14828 C/Q receiver supports operation with
lower supply voltages by scaling the receiver thresholds
when V24 is less than 18V (V24 < 18V).
Low-Power, Ultra-Small IO-Link
Device Transceiver
Reverse-Polarity Protection
The MAX14828 is protected against reverse-polarity
connections on V24, C/Q, DI, and GND. Any combination
of these pins can be connected to DC voltages up to 65V
(max), resulting in a current flow of less than 1mA.
Ensure that the maximum voltage between any of these
pins does not exceed 65V.
Driver Short-Circuit Detection
The MAX14828 monitors the C/Q driver output for
overcurrent and driver overheating conditions.
In pin-mode, the driver short-circuit current limit is set
with the CLK/TXEN/200mA input. IRQ/OC asserts when
an overcurrent or overheating condition occurs on the
C/Q driver. IRQ/OC deasserts when the overcurrent or
overheating condition is removed.
In SPI mode, the current limit for the driver is set using
the CL1 and CL0 bits in the CURRLIM register. When an
overcurrent or overheating condition occurs on C/Q, the
CQFault and CQFaultInt bits are set and IRQ/OC asserts.
The CQFault bit is cleared as soon as the overcurrent or
overheating condition on the C/Q driver is removed. IRQ/
OC deasserts and the CQFaultInt bit is cleared only when
the INTERRUPT register is read.
5V and 3.3V Linear Regulators
The MAX14828 includes two internal regulators to
generate 5V (V5) and 3.3V (V33).
The V5 regulator is capable of driving external loads
up to 30mA, including device and 3.3V LDO current
consumption. To drive larger loads, use an external
pass transistor to generate the required 5V. When using
an external transistor, connect REG to the base of the
transistor to regulate the voltage and connect V5 to the
emitter (Figure 10).
When the internal 5V linear regulator is not used, V5 is the
supply input for the internal analog and digital functions
and must be supplied externally. Ensure that V5 is present
for normal operation.
The 3.3V regulator is capable of driving external loads up
to 30mA. In SPI mode, the 3.3V LDO can be enabled/
disabled by setting the V33Dis bit in the Mode register.
V5 and V33 are not protected against short circuits.
Power-Up
The C/Q driver output is high impedance when V24,
V5, VL, and/or V33 voltages are below their respective
undervoltage thresholds during power-up.
The drivers are automatically disabled if V24, V5, or VL
falls below its threshold.
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Maxim Integrated │ 23
MAX14828
Low Voltage and Undervoltage Detection
In SPI mode, the device monitors the V24 supply for
low voltage and undervoltage conditions. Low voltage
warnings must be enabled in the MODE register.
When V24 falls below the 16V (typ) low-voltage warning
threshold, the V24W bit in the STATUS register is set. If
V24WEn is set to 1, the V24WInt interrupt bit is also set
and IRQ/OC asserts.
When V24 falls below the 7.4V (typ) undervotlage lockout
(UVLO) threshold, the UV24 bit in the STATUS register is
set. Similarly, the UV24Int bit in the INTERRUPT register is
set and IRQ/OC asserts. UVLO monitoring and interrupts
cannot be disabled.
Wake-Up Detection
The MAX14828 detects an IO-Link wake-up condition
on the C/Q line in push-pull, high-side (PNP), or low-side
(NPN) operation modes. A wake-up condition is detected
when the C/Q output is shorted for 80µs (typ). WU pulses
low for 200µs (typ) when the device detects a wake-up
pulse on C/Q (Figure 5).
In SPI mode, the WuInt bit in the INTERRUPT register is
set and IRQ/OC asserts when an IO-Link wake-up event
is detected.
Wake-up detection can be disabled in SPI mode by setting
the WU_Dis bit in the MODE register to 1. Wake-up
detection cannot be disabled in pin-mode.
The device includes a wake-up detection algorithm to
avoid false wake-up detection on C/Q. The false wake-up
blanking time is defined by the current limit blanking time.
In pin-mode, this is 128μs. In SPI-mode, this is set by the
CL_BL0 and CL_BL1 bits in the CURRLIM reigster.
Thermal Protection and Considerations
The internal LDOs and the driver can generate more power
than the package for the device can safely dissipate.
Ensure that the driver and LDO loading is less than the
package can dissipate. Total power dissipation for the
device is calculated using the following equation:
PTOTAL = PC/Q + PV5 + P33 + P24 + PPU + PPD
where PC/Q is the power generated in the C/Q driver, PV5
and PV33 are the power generated by the LDOs, P24 is
the quiescent power generated by the device, and PPU
and PPD are the power generated in the C/Q weak pullup/
pulldown current source/sink, respectively.
Ensure that the total power dissipation is less than the
limits listed in the Absolute Maximum Ratings section.
Use the following to calculate the power dissipation (in
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Low-Power, Ultra-Small IO-Link
Device Transceiver
mW) due to the C/Q driver:
PC/Q = [IC/Q(max)]2 × RO
where RO driver on-resistance.
Calculate the power dissipation in the 5V LDO, V5, using
the following equation:
P5 = (V24 - V5) × I5
where I5 includes the I33 current sourced from V33.
Calculate the power dissipated in the 3.3V LDO, V33,
using the following equation:
P33 = 1.7V × ILOAD33
Calculate the quiescent power dissipation in the device
using the following equation:
P24 = I24(max) × V24(max)
If the weak current sinks/sources are enabled, calculate
their associated power dissipation as:
PPD = IPD(max) × VC/Q (max)
PPU = IPU(max) × [V24 - VC/Q](max)
Overtemperature Warning
In SPI mode, the device generates interrupts when the
junction temperature of the C/Q driver exceeds +140°C
(typ) warning threshold. The TempW bit in the STATUS
register is set and the TempWInt in the INTERRUPT
register is set and IRQ/OC asserts under these conditions.
The TempW bit is cleared when the die temperature falls
to +125°C. The INTERRUPT register must be read to
clear the TempWInt bit and deassert IRQ/OC.
The device continues to operate normally unless the
die temperature reaches the +165°C thermal shutdown
threshold, when the device enters thermal shutdown.
The device does not generate overtemperature warnings
when operating in pin-mode.
Thermal Shutdown
The C/Q driver and the V5 and V33 regulators are
automatically switched off when the junction temperature
exceeds the +165°C (typ) thermal shutdown threshold.
SPI communication and and the internal regulators are
not disabled during thermal shutdown. In SPI mode, the
ThShut bit in the STATUS register and the ThShutInt in the
INTERRUPT register are set.
Regulators are automatically switched on when the
internal die temperature falls below the thermal shutdown
threshold plus hysteresis. If the internal V5 regulator is
used, the internal registers return to their default state
when the V5 regulator is switched back on.
Maxim Integrated │ 24
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Mode Selection Table
OPERATING
MODE
PIN
PARALLEL UART
+ SPI
SPI/
PIN
L
H
UARTSEL
X
L
ENMPX
BIT
X
0
LOW
OR
HIGH
LOW
OR
HIGH
L
MULTIPLEXED
UART/SPI
H
H
0
H
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SDI/TX/NPN
PIN
FUNCTION
NPN
Parallel configuration/monitoring
SDO/RX/THSH
THSH
Parallel configuration/monitoring
CLK/TXEN/200MA
200MA
Parallel configuration/monitoring
CS/PP
PP
Parallel configuration/monitoring
IRQ/OC
OC
Parallel configuration/monitoring
RX
C/Q RX
TX
C/Q TX
TXEN
C/Q TXEN
SDI/TX/NPN
SDI
SPI configuration/monitoring
SDO/RX/THSH
SDO
SPI configuration/monitoring
CLK/TXEN/200MA
CLK
SPI configuration/monitoring
CS/PP
CS
SPI configuration/monitoring
IRQ/OC
IRQ
SPI configuration/monitoring
RX
C/Q RX
UART communication
TX
C/Q TX
UART communication
TXEN
C/Q TXEN
UART communication
SDI/TX/NPN
SDI
SPI configuration/monitoring
SDO/RX/THSH
SDO
SPI configuration/monitoring
CLK/TXEN/200MA
CLK
SPI configuration/monitoring
CS/PP
LOW
SPI configuration/monitoring
IRQ/OC
IRQ
SPI configuration/monitoring
RX
C/Q RX
UART communication
TX
C/Q TX
UART communication
TXEN
C/Q TXEN
UART communication
SDI/TX/NPN
C/Q TX
UART communication
SDO/RX/THSH
C/Q RX
UART communication
CLK/TXEN/200MA
C/Q TXEN
UART communication
CS/PP
HIGH
IRQ/OC
IRQ
SPI configuration/monitoring
RX
C/Q RX
Active
TX
C/Q TX
Ignored
TXEN
C/Q TXEN
Ignored
CS/PP
PIN NAME
FUNCTION
Parallel configuration/monitoring/
UART communication
Parallel configuration/monitoring/
UART communication
Parallel configuration/monitoring/
UART communication
Maxim Integrated │ 25
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Mode Selection Table (continued)
OPERATING
MODE
SPI/
PIN
UARTSEL
ENMPX
Bit
CS/PP
0
MULTIPLEXED
UART/SPI
H
1
1
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LOW
OR
HIGH
PIN NAME
PIN
FUNCTION
FUNCTION
SDI/TX/NPN
SDI
SPI configuration/monitoring
SDO/RX/THSH
SDO
SPI configuration/monitoring
CLK/TXEN/200MA
CLK
SPI configuration/monitoring
CS/PP
CS
SPI configuration/monitoring
IRQ/OC
IRQ
SPI configuration/monitoring
RX
Active
TX
Ignored
TXEN
Ignored
SDI/TX/NPN
C/Q TX
UART communication
SDO/RX/THSH
C/Q RX
UART communication
CLK/TXEN/200MA
C/Q TXEN
UART communication
Not used
CS/PP
IRQ/OC
IRQ
SPI monitoring
RX
Active
TX
Ignored
TXEN
Ignored
Maxim Integrated │ 26
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Register Functionality
The MAX14828 has seven 8-bit-wide registers for configuration and monitoring (Table 4).
Table 4. Register Summary
REGISTER ADD R/W
INTERRUPT 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
ThShutInt
WuInt
—
CQFaultInt
V24WInt
UV24Int
-
TempWInt
STATUS
01h
R
ThShut
DiLvl
—
CQFault
V24W
UV24
CQLvl
TempW
MODE
02h
R/W
RST
WU_Dis
V33_Dis
ENMPX
V24WEn
CQFil
LED2b
LED1b
CURRLIM
03h
R/W
CL1
CL0
CLDis
CL_BL1
CL_BL0
TAr1
TAr0
ArEn
CQConfig
04h
R/W
Rx_Dis
CQ_WPD
CQ_WPU
—
CQ_NPN
CQ_PP
CQ_Q
CQ_Dis
DIOConfig
05h
R/W
DI_Dis
—
—
—
—
—
—
—
CQInvert
06h
R/W
CQInv
—
—
—
—
—
—
—
INTERRUPT Register [A2, A1, A0] = [000]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ThShutInt
WuInt
—
CQFaultInt
V24WInt
UV24Int
—
TempWInt
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
Y
Y
Y
Y
Y
Y
Y
Y
Bit Name
The INTERRUPT register reflects current state of various fault conditions. The IRQ/OC output asserts when any of the
bits in the INTERRUPT register is set. INTERRUPT register bits are latched and are not cleared when the initiating
condition is removed. Reading the INTERRUPT register clears all the bits and deasserts IRQ/OC. IRQ/OC reasserts
only when another fault condition occurs.
BIT
7
6
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NAME
ThShutInt
WuInt
DESCRIPTION
Thermal Shutdown Interrupt
1: This bit is set when the MAX14828 has entered thermal shutdown mode. Once set,
this bit is not cleared until the register is read. The current status of the thermal
shutdown condition can be read in the STATUS register.
0: The MAX14828 is not in thermal shutdown.
Wake-Up Event Interrupt
1: This bit is set when an IO-Link wake-up condition is detected on the C/Q line.
0: No wake-up condition is detected.
The wake-up interrupt can be disabled by setting the WuDis bit to 1.
Maxim Integrated │ 27
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
INTERRUPT Register [A2, A1, A0] = [000] (continued)
BIT
NAME
5
DESCRIPTION
This bit is not used.
CQ_FaultInt
C/Q Driver Fault Interrupt
1: This bit is set when a fault occurs on the C/Q driver (over current or over heating).
Once set, this bit is not cleared until the register is read. The current status of the
thermal shutdown condition can be read in the STATUS register.
0: No fault on the C/Q driver.
V24WInt
V24 Low Voltage Warning Interrupt
1: This bit is set when V24 falls below the IO-Link low-voltage warning threshold fault
(V24 < V24W). Once set, this bit is not cleared until the register is read. The current
status of the thermal shutdown condition can be read in the STATUS register.
0: V24 is greater than the low-voltage warning threshold.
2
UV24Int
V24 Supply Undervoltage Interrupt
1: This bit is set when V24 falls below the UVLO threshold (V24 < V24UVLO). Once
set, this bit is not cleared until the register is read. The current status of the thermal
shutdown condition can be read in the STATUS register.
0: V24 is greater than the UVLO threshold.
1
4
3
0
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TempWInt
This bit is not used.
Overtemperature Warning Interrupt
1: This bit is set when the die temperature exceeds the warning threshold (TJ > TWRN).
Once set, this bit is not cleared until the register is read. The current status of the
thermal shutdown condition can be read in the STATUS register.
0: The die temperature has not exceeded the overtemperature warning threshold.
Maxim Integrated │ 28
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
STATUS Register [A2, A1, A0] = [000]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ThShut
DiLvl
—
CQFault
V24W
UV24
CQLvl
TempW
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
Bit Name
The STATUS register reflects current state of various IC functions.
BIT
NAME
7
ThShut
6
DiLvl
5
4
CQ_Fault
DESCRIPTION
Thermal Shutdown Status
1: This bit is set when the MAX14828 has entered thermal shutdown mode.
0: This bit is cleared automatically when the device exits thermal shutdown.
DI Logic Level
1: This bit is set when the DI voltage is a logic-low (VDI < VTL)
0: This bit is clear when the DI voltage is a logic-high (VDI > VTH).
This bit is not used.
C/Q Driver Fault Status
1: This bit is set when a fault occurs on the C/Q driver (overcurrent or overheating).
0: This bit is cleared automatically when the fault on C/Q is removed.
3
V24W
V24 Low Voltage Warning Status
1: This bit is set when V24 falls below the IO-Link low-voltage warning threshold (V24 <
V24W).
0: This bit is cleared automatically when V24 rises above the low-voltage warning
threshold.
2
UV24
V24 Supply Status
1: This bit is set when V24 falls below the UVLO threshold (V24 < V24UVLO).
0: This bit is cleared automatically when V24 rises above the UVLO threshold.
1
CQLvl
C/Q Logic Level
1: This bit is set when the C/Q voltage is a logic-low (VC/Q < VTL) (CQInv = 0 or 1)
0: This bit is clear when the C/Q voltage is a logic-high (VC/Q > VTH) (CQInv = 0 or 1).
TempW
Overtemperature Warning
1: This bit is set when the die temperature exceeds the warning threshold (TJ > TWRN).
0: This bit is cleared automatically when the when the die temperature falls below the
warning threshold and hysteresis (TJ < TWRN - TWRN_HYST).
0
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Maxim Integrated │ 29
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
MODE Register [A2, A1, A0] = [010]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
RST
WU_Dis
V33_Dis
ENMPX
V24WEn
CQFil
LED2b
LED1b
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset upon Read
N
N
N
N
N
N
N
N
Use the mode register to configure the MAX14828 and manage the 3.3V LDO.
BIT
NAME
DESCRIPTION
Register Reset
1: Reset all registers to their default power-up state. The Status register is
cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts are not
generated while RST = 1.
0: Normal operation.
7
RST
6
WU_Dis
Wake-Up Interrupt Disable/Enable
1: Wake-up detection is disabled.
0: Enable IO-Link wake-up detection.
5
V33_Dis
V33 Enable/Disable
1: Disable the V33 linear regulator.
0: Enable the V33 linear regulator.
ENMPX
Enable/Disable SPI/UART Multiplexing
1: Enable UART multiplexing on SPI interface pins. See the Mode Selection
Table for more information.
0: Disable UART multiplexing on SPI interface pins.
3
V24WEn
V24 Undervoltage Warning Enable
1: Enable the V24 undervoltage warning interrupt. V24WInt is set when V24 falls
below the UVLO threshold.
0: Disable the V24 undervoltage warning interrupt.
2
CQFil
C/Q Deglitch Filter Enable/Disable
1: Deglitch filter is disabled on RX.
0: Deglitch filter is enabled on RX.
1
LED2b
LED2 Driver Logic
1: Set the LED2 output high.
0: Set the LED2 output low.
0
LED1b
LED1 Driver Logic.
1: Set the LED1 output high.
0: LED1 output is driven by the LED1IN logic input.
4
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Maxim Integrated │ 30
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
CURRLIM Register [A2, A1, A0] = [011]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
CL1
CL0
CL_Dis
CL_BL1
CL_BL0
TAr1
TAr0
ArEN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
The CURRLIM register sets the C/Q driver current limit and the fixed off-time once the driver has exceeded the thermal
shutdown threshold.
BIT
NAME
7
CL1
DESCRIPTION
Driver Current Limit
Set the CL1 and CL0 bits to select the active current limit for the C/Q driver when
CL_Dis = 0.
00:
01:
10:
11:
Driver current limit is set to 50mA
Driver current limit is set to 100mA
Driver current limit is set to 200mA
Driver current limit is set to 250mA
6
CL0
5
CL_Dis
Driver Current Limit Disable/Enable
1: Disable the driver current limit for the C/Q driver.
0: Enable the driver current limit (as set by the CL1 and CL0 bits).
4
CL_BL1
Current Limit Blanking Time
Set the CL_BL1 and CL_BL0 bits to select the minimum blanking time to signal a
current limit or thermal fault.
3
2
1
0
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CL_BL0
TAr1
TAr0
ArEN
00:
01:
10:
11:
Blanking time is 128μs
Blanking time is 500μs
Blanking time is 1ms
Blanking time is 5ms
Auto-Retry Fixed Off-Time
Set the TAr1 and TAr0 bits to select the fixed driver off-time after a fault has been
generated when auto-retry functionality is enabled (ArEn = 1). The driver is re-enabled
automatically after the fixed off-delay.
00:
01:
10:
11:
Fixed off-time is 50ms
Fixed off-time is 100ms
Fixed off-time is 200ms
Fixed off-time is 500ms
Auto-Retry Fixed Off-Time Enable/Disable
1: Fixed off-time functionality is enabled. C/Q driver is disabled for a fixed time after an
overcurrent or thermal fault occurs. The driver is re-enabled automatically after the
fixed off-delay.
0: Fixed off-time functionality is disabled. The driver is re-enabled after temperature falls
below the thermal hysteresis.
Maxim Integrated │ 31
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
CQConfig Register [A2, A1, A0] = [100]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX_Dis
CQ_WPD
C/Q_WPU
—
C/Q_NPN
CQ_PP
CQ_Q
CQ_Dis
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
1
Reset Upon Read
N
N
N
N
N
N
N
N
Bit Name
Use the CQConfig register to control the C/Q driver and receiver parameters. All bits in the CQConfig register are readwrite.
BIT
NAME
DESCRIPTION
7
RX_Dis
6
CQ_WPD
C/Q Weak Pull-Down Enable
1: Enable the weak pull-down current sink on the C/Q driver.
0: Disable the weak pull-down current sink on the C/Q driver.
5
CQ_WPU
C/Q Weak Pull-Up Enable
1: Enable the weak pull-up current source on the C/Q driver.
0: Disable the weak pull-up current source on the C/Q driver.
4
Receiver Disable/Enable
1: The RX receiver output is disabled. RX is high impedance when disabled.
0: RX is enabled.
This bit is not used.
C/Q Driver NPN/PNP Mode
1: Enable NPN operation (when CQ_PP = 0) on the C/Q driver.
0: Enable PNP operation (when CQ_PP = 0) on the C/Q driver.
CQ_NPN is ignored when CQ_PP = 1.
3
CQ_NPN
2
CQ_PP
C/Q Driver Push-Pull Mode
1: Enable push-pull operation on the C/Q driver.
0: Enable open-drain (PNP or NPN mode) operation on the C/Q driver.
CQ_Q
C/Q Driver Output Logic
1: Set the C/Q driver high (push-pull mode), set the C/Q PNP switch on (PNP
mode), or set the C/Q NPN switch off (NPN mode). See Table 1.
0: CQ is high impedance when CQ_Q = 0 and TXEN is low (or CQ_Dis = 1).
CQ logic is the inverse of TX logic when TXEN is high (and CQ_Dis = 0)
and CQ_Q = 0. See Table 1.
CQ_Dis
C/Q Driver Disable/Enable
1: Disable the C/Q driver, regardless of the state of the TXEN input. The driver
is high impedance in this mode.
0: Status of the C/Q driver is determined by the TXEN input or CQ_Q bit.
1
0
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Maxim Integrated │ 32
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
DIOConfig Register [A2, A1, A0] = [101]
Bit
Bit Name
Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DI_Dis
—
—
—
—
—
—
Bit 0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
Use the DIOConfig register to enable or disable the DI receiver input.
BIT
NAME
7
DI_Dis
6:0
DESCRIPTION
DI Receiver Enable/Disable
1: The DI receiver is disabled. LI is high-impedance when the DI receiver is
disabled.
0: DI receiver is enabled.
These bits are not used.
CQInvert Register [A2, A1, A0] = [110]
Bit
Bit Name
Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CQInv
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
Reset Upon Read
N
N
N
N
N
N
N
N
Use the CQInvert register to control the polarity of the C/Q driver.
BIT
NAME
DESCRIPTION
7
CQInv
CQ Invert Enable/Disable
1: The CQ driver logic follows the TX input logic (if driver is enabled). RX logic
follows the CQ driver/receiver logic.
0: The CQ driver logic is the inverse of the TX input logic (if driver is enabled).
RX logic is the inverse of the CQ driver/receiver logic.
6:0
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These bits are not used.
Maxim Integrated │ 33
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
SPI Interface
polarity CPOL = 0 and clock phase CPHA = 0 (see Figure
7 and Figure 8).
The device communicates through an SPI-compatible
4-wire serial interface. The MAX14828 supports burst
read/write access. The maximum SPI clock rate for the
device is 12MHz. The SPI interface complies with clock
The SPI interface is not available when V5 or VL are not
present.
CS/PP
CLK/
TXEN/
200MA
SDI/TX/
NPN
W
0
0
0
0
A2
A1
A0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 2
BIT 1
BIT 0
A_ = REGISTER ADDRESS
BIT_ = DATA BIT
= CLOCK EDGE THAT INTIATES LATCHING OF SDI DATA
Figure 7. SPI Write Cycle
CS/PP
CLK/
TXEN/
200MA
SDI/TX/
NPN
X
R
0
0
0
0
A2
A1
SDO/RX/
THSH
X
A0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
A_ = REGISTER ADDRESS
BIT_ = DATA BIT
= CLOCK EDGE THAT INTIATES LATCHING OF SDI DATA
= CLOCK EDGE THAT INTIATES WRITING OF SDO DATA
Figure 8. SPI Read Cycle
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Maxim Integrated │ 34
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
SPI Burst Access
Burst access allows writing or reading in one block,
by only defining the initial register address in the SPI
command byte. Once the initial SPI address is received,
the MAX14828 automatically increments the register after
each SPI data byte. Efficient programming of multiple
consecutive registers is thus possible. Chip select, CS/
PP, must be kept low during the whole write/read cycle.
The SPI clock continues clocking throughout the burst
access cycle. The burst cycle ends when the SPI master
pulls CS/PP high.
Applications Information
Microcontroller Interfacing
The logic levels of the microcontroller interface I/Os are
defined by VL. Apply a voltage from 2.5V to 5.5V to VL for
normal operation. Logic outputs are supplied by VL.
The device can be configured for simultaneous or
multiplexed UART communication. When configured for a
multipexed UART interface, the SPI interface and UART
interface pins are shared. See the Mode Selection Table
for more information.
Transient Protection
Inductive load switching, ESD, bursts, and surges create
high transient voltages. V24, C/Q, and DI should be
protected against high overvoltage and undervoltage
transients. Positive voltage transients on V24, C/Q, and DI
must be limited to +70V relative to GND. Negative voltage
transients must be limited to -70V relative to V24. Use
protection diodes on C/Q and DI as shown in Figure 9.
For standard ESD and burst protection demanded by the
IO-Link specification, small package TVS can be used (like
the uClamp3603T or the SPT01-335). If higher level surge
ratings need to be achieved (IEC 61000-4-5 ±1kV/ 42Ω),
SMAJ33A or SMBJ36A TVS protectors can also be used.
Note that these are recommended protection components.
Results may vary based on layout.
Using an External Transistor with the 5V
Regulator
V24
MAX14828
C/Q
DI
GND
Figure 9. MAX14828 Operating Circuit with TVS Protection
load currents or to shunt the power dissipation away
from the MAX14828, an external NPN transistor can be
connected as shown in Figure 10.
Select an NPN transistor with high VCE voltage to support
the max L+ supply voltage. In order to protect the NPN
transistor against reverse polarity of the L+/L- supply
terminals, connect a silicon or a Schottky diode in series
with the NPN transistor’s collector that has a reverse
voltage capability large enough for reverse connected
L+/L-. A 1µF capacitor on the V5 is required for stability.
Using an Step-Down Regulator with the 5V
Regulator
To decrease power dissipation in the MAX14828, V5 can
be powered by an external step-down regulator. Connect
the external regulator’s output to the V5 input and leave
REG unconnected (Figure 11).
The internal 5V regulator (V5) can provide up to 30mA
of total load current (including the current on to the V33
LDO) when V5 is connected to REG. To achieve larger
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Maxim Integrated │ 35
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
L+
1µ F
V24
REG
V5
MAX14828
GND
L-
Figure 10. Using an External NPN Transistor with the 5V Regulator
MAX17552
LX
5V
FB
1µF
3.3V
VL
V33
V5
SPI/PIN
GPIO2
MICROCONTROLLER
SS
SCLK/RTS
MISO/RX
MOSI/TX
GND
GPO
EN
GND
1µF
VCC
IN
REG
V24
0.1µF
IRQ/OC
CS
CLK/TXEN
SDO/RX
SDI/TX
WU
L+
MAX14828
DI
GND
1kΩ
1
2
L-
3
4
C/Q
LED1
LED2
C/Q
Figure 11. Using an External Step-Down with the 5V Regulator
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Maxim Integrated │ 36
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Shared SPI/UART Interface
Figure 12 is an example of the use of a minimum pincount microcontroller. A microcontroller serial port,
which supports both UART and SPI functions, is used
for managing both transceiver control (SPI) and IOLink data communication (UART). The microcontroller’s
shared UART and SPI interface pins are multiplexed. The
transceiver’s SPI is typically only used for configuration at
power-up and occasionally afterwards for reconfiguration,
and diagnostics. During an IO-Link master-device
communication cycle, the idle time on the C/Q interface
can be used for SPI activity. This is possible by slightly
increasing the IO-Link device’ minimum cycle time.
5V
1µF
3.3V
1µF
VCC
VL
V33
V5
SPI/PIN
REG
V24
0.1µF
UARTSEL
GPIO2
SS
SCLK/RTS
MISO/RX
MOSI/TX
MICROCONTROLLER
GND
GPO
IRQ/OC
CS
CLK/TXEN
SDO/RX
SDI/TX
WU
L+
MAX14828
DI
GND
1kΩ
1
2
L-
3
4
C/Q
LED1
LED2
C/Q
Figure 12. Multiplexed SPI/UART Mode Configuration
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Maxim Integrated │ 37
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX14828ATG+
PART
-40°C to +125°C
24 TQFN-EP*
MAX14828ATG+T
-40°C to +125°C
24 TQFN-EP*
MAX14828AWA+
-40°C to +125°C
25 WLP
MAX14828AWA+T
-40°C to +125°C
25 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and Reel.
Chip Information
PROCESS: BiCMOS
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Maxim Integrated │ 38
MAX14828
Low-Power, Ultra-Small IO-Link
Device Transceiver
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
6/17
Initial release
1
2/19
Updated the Pin Description, Wake-Up Detection section, Figure 11, and Figure 12
DESCRIPTION
—
19, 24,
36–37
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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