EVALUATION KIT AVAILABLE
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
General Description
The MAX15014–MAX15017 combine a step-down DC-DC
converter and a 50mA, low-quiescent-current low-dropout
(LDO) regulator. The LDO regulator is ideal for powering
always-on circuitry. The DC-DC converter input voltage
range is 4.5V to 40V for the MAX15015/MAX15016, and
7.5V to 40V for the MAX15014/MAX15017.
The DC-DC converter output is adjustable from 1.26V
to 32V and can deliver up to 1A of load current. These
devices utilize a feed-forward voltage-mode-control
scheme for good noise immunity in the high-voltage
switching environment and offer external compensation
allowing for maximum flexibility with a wide selection
of inductor values and capacitor types. The switching
frequency is internally fixed at 135kHz and 500kHz,
depending on the version chosen. Moreover, the switching frequency can be synchronized to an external clock
signal through the SYNC input. Light-load efficiency
is improved by automatically switching to a pulse-skip
mode. The soft-start time is adjustable with an external
capacitor. The DC-DC converter can be disabled independent of the LDO, thus reducing the quiescent current
to 47μA (typ).
The LDO linear regulators operate from 5V to 40V and
deliver a guaranteed 50mA load current. The devices
feature a preset output voltage of 5V (MAX1501_A) or
3.3V (MAX1501_B). Alternatively, the output voltage
can be adjusted from 1.5V to 11V by using an external
resistive divider. The LDO section also features a RESET
output with adjustable timeout period.
Protection features include cycle-by-cycle current limit,
hiccup-mode output short-circuit protection, and thermal
shutdown. All devices are available in a space-saving,
high-power (2.86W), 36-pin TQFN package and are rated
for operation over the -40°C to +125°C automotive temperature range.
Applications
●● Mobile Radios
●● Navigation Systems
Features
●● Combined DC-DC Converters and Low-QuiescentCurrent LDO Regulators
●● 1A DC-DC Converters Operate from 4.5V to 40V
(MAX15015/MAX15016) or 7.5V to 40V
(MAX15014/MAX15017)
●● Switching Frequency of 135kHz
(MAX15014/MAX15016) or 500kHz
(MAX15015/MAX15017)
●● 50mA LDO Regulator Operates from 5V to 40V
Independent of the DC-DC Converter
●● 47μA Quiescent Current with DC-DC Converter
Off and LDO On
●● 6μA System Shutdown Current
●● Frequency Synchronization Input
●● Shutdown/Enable Inputs
●● Adjustable Soft-Start Time
●● Active-Low Open-Drain RESET Output with
Programmable Timeout Delay
●● Thermal Shutdown and Output Short-Circuit
Protection
●● Space-Saving (6mm x 6mm) Thermally Enhanced
36-Pin TQFN Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX15014AATX+
-40°C to +125°C
36 TQFN-EP*
MAX15014BATX+
-40°C to +125°C
36 TQFN-EP*
MAX15015AATX+
-40°C to +125°C
36 TQFN-EP*
MAX15015BATX+
-40°C to +125°C
36 TQFN-EP*
MAX15016AATX+
-40°C to +125°C
36 TQFN-EP*
MAX15016BATX+
-40°C to +125°C
36 TQFN-EP*
MAX15017AATX+
-40°C to +125°C
36 TQFN-EP*
MAX15017BATX+
-40°C to +125°C
36 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
19-0734; Rev 1; 11/14
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Absolute Maximum Ratings
IN_SW, IN_LDO, DRAIN, EN_SYS, EN_SW
to SGND.............................................................-0.3V to +45V
IN_LDO to IN_SW.................................................-0.3V to +0.3V
LX to SGND.........................................-0.3V to (VIN_SW + 0.3V)
LX to PGND.........................................-0.3V to (VIN_SW + 0.3V)
BST to SGND........................................-0.3V to (VIN_SW + 12V)
BST to LX...............................................................-0.3V to +12V
PGND to SGND.....................................................-0.3V to +0.3V
REG, DVREG, SYNC, RESET, CT to SGND........-0.3V to +12V
FB, COMP_SW, SS to SGND.................-0.3V to (VREG + 0.3V)
SET_LDO, LDO_OUT to SGND............................-0.3V to +12V
C+ to PGND
(MAX15015/MAX15016 only).............(VDVREG - 0.3V) to 12V
C- to PGND
(MAX15015/MAX15016 only)......... -0.3V to (VDVREG + 0.3V)
LDO_OUT Output Current.................................Internally Limited
Switch DC Current (DRAIN and LX pins combined)
TJ = +125°C..........................................................................1.9A
TJ = +150°C........................................................................1.25A
RESET Sink Current.............................................................5mA
Continuous Power Dissipation (TA = +70°C)
36-Pin TQFN (derate 26.3mW/°C above +70°C)
Single-Layer Board.....................................................2105mW
36-Pin TQFN (derate 35.7mW/°C above +70°C)
Multilayer Board..........................................................2857mW
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature......................................+150°C
Storage Temperature Range............................. -60°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V,
CREG = 1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
System Supply Current (Not
Switching)
SYMBOL
ISYS
CONDITIONS
No load
Switching System Supply
Current
ISW
No load
LDO Quiescent Current
ILDO
VEN_SYS = 14V,
VEN_SW = 0V
System Shutdown Current
System Enable Voltage
ISHDN
TYP
MAX
VFB = 1.3V,
MAX15014/MAX15017
MIN
0.7
1.8
VFB = 1.3V,
MAX15015/MAX15016
0.85
1.8
VFB = 0V, MAX15014/
MAX15017
5.6
VFB = 0V, MAX15015/
MAX15016
8.6
ILDO_OUT = 100µA
47
63
ILDO_OUT = 50mA
130
200
6
10
mA
mA
VEN_SYS = 0V, VEN_SW = 0V
VEN_SYSH
EN_SYS = high, system on
VEN_SYSL
EN_SYS = low, system off
2.4
0.8
System Enable Hysteresis
System Enable Input Current
220
IEN_SYS
UNITS
µA
µA
V
mV
VEN_SYS = 2.4V
0.5
2
VEN_SYS = 14V
0.6
2
µA
BUCK CONVERTER
Input Voltage Range
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VIN_SW
MAX15014/MAX15017
7.5
40.0
MAX15015/MAX15016
4.5
40.0
V
Maxim Integrated │ 2
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Electrical Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V,
CREG = 1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Undervoltage Lockout
Threshold
UVLOTH
Undervoltage Lockout
Hysteresis
UVLOHYST
Output Voltage Range
VOUT
Output Current
IOUT
EN_SW Input Voltage
Threshold
CONDITIONS
VIN_SW and IN_LDO rising, MAX15014/
MAX15017
VIN_SW and IN_LDO rising, MAX15015/
MAX15016
MIN
TYP
MAX
6.7
7.0
7.4
3.90
4.08
4.25
V
MAX15014/MAX15017
0.54
MAX15015/MAX15016
0.3
Minimum output
1.26
Maximum output
32
EN_SW = high, switching power supply is on
V
VEN_SWL
EN_SW = low, switching power supply is off
A
2.4
0.8
EN_SW Hysteresis
Switching Enable Input Current
V
1
VEN_SWH
220
IEN_SW
UNITS
V
mV
VEN_SW = 2.4V
0.5
2
VEN_SW = 14V
0.6
2
µA
INTERNAL VOLTAGE REGULATOR
Output Voltage
VREG
Line Regulation
MAX15014/MAX15017, VIN_SW = 9V to 40V
7.6
8.4
MAX15015/MAX15016, VIN_SW = 5.5V to 40V
4.75
5.25
VIN_SW = 9.0V to 40V, MAX15014/MAX15017
1
VIN_SW = 5.5V to 40V, MAX15015/MAX15016
1
V
mV/V
Load Regulation
IREG = 0 to 20mA
0.25
V
Dropout Voltage
VIN_SW = 7.5V (MAX15014/MAX15017),
VIN_SW = 4.5V (MAX15015/MAX15016),
IREG = 20mA
0.5
V
OSCILLATOR
Frequency Range
Maximum Duty Cycle
Minimum LX Low Time
SYNC High-Level Voltage
SYNC Low-Level Voltage
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fCLK
DMAX
VSYNC = 0V, MAX15014/MAX15016
122
136
150
VSYNC = 0V, MAX15015/MAX15017
425
500
575
VSYNC = 0V, VIN_SW = 7.5V, MAX15014
(135kHz)
90
98
VSYNC = 0V, VIN_SW = 4.5V, MAX15016
(135kHz)
90
98
VSYNC = 0V, VIN_SW = 4.5V, MAX15015
(500kHz)
90
96
VSYNC = 0V, VIN_SW = 7.5V, MAX15017
(500kHz)
90
98
VSYNC = 0V
94
kHz
%
ns
2.2
0.8
V
Maxim Integrated │ 3
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Electrical Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V,
CREG = 1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYNC Frequency Range
SYMBOL
fSYNC
CONDITIONS
MIN
TYP
MAX
MAX15014/MAX15016
100
200
MAX15015/MAX15017
400
600
Ramp Level Shift (Valley)
0.3
UNITS
kHz
V
ERROR AMPLIFER
Soft-Start Reference Voltage
VSS
1.210
1.235
1.260
V
Soft-Start Current
ISS
7
12
17
µA
FB Regulation Voltage
VFB
1.210
1.235
1.260
V
FB Input Range
VFB
0
1.5
V
FB Input Current
IFB
VFB = 1.244V
-250
+250
nA
ICOMP = -500µA to +500µA
0.25
4.5
V
COMP Voltage Range
VSS = 0V
Open-Loop Gain
80
dB
Unity-Gain Bandwidth
1.8
MHz
PWM Modulator Gain
fSYNC = 500kHz, MAX15015/MAX15017
10
fSYNC = 135kHz, MAX15014/MAX15016
10
V/V
CURRENT-LIMIT COMPARATOR
Pulse Skip Threshold
IPFM
100
200
300
mA
Cycle-by-Cycle Current Limit
IILIM
1.3
2
2.6
A
Number of Consecutive ILIM
Events to Hiccup
Hiccup Timeout
7
—
512
Clock
periods
POWER SWITCH
Switch On-Resistance
VBST - VLX = 6V
Switch Gate Charge
VBST - VLX = 6V
Switch Leakage Current
BST Quiescent Current
BST Leakage Current
CHARGE PUMP (MAX15015/MAX15016)
0.15
0.4
0.80
4
VIN_SW = VIN_LDO = VLX = VDRAIN =
40V, VFB = 0V
VBST = 40V, VDRAIN = 40V, VFB = 0V,
DVREG = 5V
VBST = VDRAIN = VLX = VIN_SW = VIN_
LDO = 40V, EN_SW = 0V
400
Ω
nC
10
µA
600
µA
1
µA
C- Output Voltage Low
Sinking 10mA
0.1
V
C- Output Voltage High
Relative to DVREG, sourcing 10mA
0.1
V
DVREG to C+ On-Resistance
Sourcing 10mA
10
Ω
LX to PGND On-Resistance
Sinking 10mA
12
Ω
40
V
4.25
V
LDO
Input Voltage Range
Undervoltage Lockout Threshold
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VIN_LDO
UVLO_LDOTH
5
VIN_LDO rising
3.90
4.1
Maxim Integrated │ 4
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Electrical Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V,
CREG = 1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Undervoltage Lockout
Hysteresis
Output Current
SYMBOL
CONDITIONS
UVLO_
LDOHYST
IOUT
VIN = 6V (Note 2)
65
VLDO_OUT
4.90
5
5.06
4.85
5
5.15
1mA ≤ IOUT ≤ 50mA,
VIN_LDO = 14V
4.85
5
5.15
ILDO_OUT = 100µA
3.22
3.3
3.35
ILDO_OUT = 1mA
3.22
3.3
3.35
3.2
3.3
3.4
3.2
3.3
3.4
Dropout Voltage
ΔVDO
Power-Supply Rejection Ratio
Short-Circuit Current
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ISET_LDO
PSRR
ISC
11.0
IOUT = 10mA
0.6
IOUT = 50mA
0.82
IOUT = 10mA
0.1
IOUT = 50mA
0.4
VSET_LDO
Minimum SET_LDO Threshold
SET_LDO Input Leakage
Current
VIN_LDO = 4.0V,
MAX1501_B
1.5
From EN_SYS high to LDO_OUT rise,
RL = 500Ω, SET_LDO = SGND
Startup Response Time
SET_LDO Reference Voltage
VSET_LDO > 0.25V
VIN_LDO = 5V,
MAX1501_A
200
5.06
1mA ≤ ILDO_OUT ≤
50mA, VIN_LDO = 14V
400
1.220
1.241
(Note 3)
185
VSET_LDO = 11V
0.5
IOUT = 10mA, f = 100Hz, 500mVP-P, VLDO_
OUT = 5V
78
IOUT = 10mA, f = 1MHz, 500mVP-P, VLDO_
OUT = 5V
24
UNITS
V
5
SET_LDO = SGND, 6V ≤ V
IN_LDO ≤ 40V,
MAX1501_B
ILDO_OUT = 1mA
VADJ
MAX
4.90
ILDO_OUT = 1mA
SET_LDO = SGND, 6V ≤ V
IN_LDO ≤ 40V,
MAX1501_A
ILDO_OUT = 1mA
Adjustable Output Voltage
Range
TYP
0.3
ILDO_OUT = 100µA
Output Voltage
MIN
mA
V
V
V
µs
1.265
V
mV
100
nA
dB
125
185
300
mA
Maxim Integrated │ 5
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Electrical Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V,
CREG = 1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
RESET OUTPUT
RESET Threshold
SYMBOL
VRESET
CONDITIONS
RESET goes high after rising VLDO_OUT
crosses this threshold
RESET Output Low Voltage
VRL
(VLDO_OUT – VRESET) / IRESET = 4kΩ
RESET Output High Leakage
Current
IRH
VRESET = 3.3V (For MAX15_ _ _B),
VRESET = 5V (For MAX15_ _ _A)
MIN
TYP
MAX
UNITS
90
92.5
95
%VOUT
0.4
V
1
µA
RESET Output Minimum
Timeout Period
When LDO_OUT reaches RESET threshold,
CT = unconnected
50
µs
ENABLE to RESET Minimum
Timeout Period
When EN_SYS goes high, CLDO_OUT =
10µF, ILDO_OUT = 50mA,
VLDO_OUT = 3.3V, CT = unconnected
650
µs
Delay Comparator Threshold
(Rising)
VCT-TH
Delay Comparator Threshold
Hysteresis
VCTTH-HYST
CT Charge Current
ICT-CHQ
CT Discharge Current
ICT-DIS
1.220
1.241
1.265
100
VCT = 0V
1.5
2
V
mV
3
µA
18
mA
+160
°C
20
°C
THERMAL SHUTDOWN
Thermal Shutdown
Temperature
Thermal Shutdown Hysteresis
Temperature rising
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: Maximum output current is limited by package power dissipation.
Note 3: This is the minimum voltage needed at SET_LDO for the system to recognize that the user wants an adjustable LDO_OUT.
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Maxim Integrated │ 6
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Typical Operating Characteristics
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG =
1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.)
5
4
3
2
1
135
134
133
132
0
50
100
TEMPERATURE (°C)
130
150
MAXIMUM DUTY CYCLE
vs. INPUT VOLTAGE (MAX15016A)
MAX15014 toc04
98
97
96
95
94
93
92
100
98
96
94
92
90
88
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
86
84
80
TA = 0°C
10
15
20
1.5
TA = +85°C
35
460
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
ERROR AMPLIFIER OPEN-LOOP GAIN
AND PHASE vs. FREQUENCY
MAX15014 toc06
340
90
80
70
60
50
300
GAIN
260
220
40
30
20
10
0
-10
40
MAX15014 toc03
470
180
140
PHASE
100
0.1
1
10
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
MAX15014 toc09
ILOAD = 100mA
EN_SW
2V/div
EN_SW
2V/div
0V
TA = +135°C
VOUT
2V/div
10
20
30
INPUT VOLTAGE (V)
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40
50
VOUT
2V/div
0V
0V
0
60
TURN-ON/-OFF WAVEFORM
ILOAD = 1A
0.5
0
30
480
MAX15014 toc08
0V
1.0
25
490
TURN-ON/-OFF WAVEFORM
MAX15014 toc07
TA = +25°C
2.0
5
500
INPUT VOLTAGE (V)
OUTPUT CURRENT LIMIT
vs. INPUT VOLTAGE
2.5
0
510
110
100
82
91
OUTPUT CURRENT LIMIT (A)
MAXIMUM DUTY CYCLE
vs. INPUT VOLTAGE (MAX15015A)
MAX15015A
520
450
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
GAIN (dB)
-50
99
MAXIMUM DUTY CYCLE (%)
136
131
100
90
137
530
MAX15014 toc05
0
138
SWITCHING FREQUENCY
vs. TEMPERATURE
PHASE (DEGREES)
6
MAX15016A
139
SWITCHING FREQUENCY (kHz)
7
MAX15014 toc02
8
SWITCHING FREQUENCY
vs. TEMPERATURE
140
SWITCHING FREQUENCY (kHz)
MAX15016
9
MAXIMUM DUTY CYCLE (%)
SYSTEM SHUTDOWN CURRENT (A)
10
MAX15014 toc01
SYSTEM SHUTDOWN CURRENT
vs. TEMPERATURE
2ms/div
2ms/div
Maxim Integrated │ 7
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG =
1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.)
TURN-ON/-OFF WAVEFORM
INCREASING VIN
MAX15014 toc11
ILOAD = 100mA
3.38
VIN
5V/div
VIN
5V/div
0V
VOUT
2V/div
0V
EFFICIENCY vs. LOAD CURRENT
(MAX15015A)
VIN = 4.5V
80
70
60
VIN = 12V
50
VIN = 24V
40
VIN = 40V
30
20
1
VIN = 4.5V
80
10
100
LOAD CURRENT (mA)
VOUT = 5V
90
VIN = 7.5V
80
VIN = 7.5V
70
VIN = 12V
60
50
VIN = 24V
40
20
ILOAD = 1A
-40
-15
10
35
60
85
TEMPERATURE (°C)
110
135
EFFICIENCY vs. LOAD CURRENT
(MAX15014)
VOUT = 5V
VIN = 7.5V
80
70
VIN = 24V
60
50
VIN = 12V
40
VIN = 40V
30
20
10
0
1
100
10
1000
0
1
LOAD CURRENT (mA)
LOAD-TRANSIENT RESPONSE
VIN = 12V, IOUT = 0.25A TO 1A
MAX15015A
10
100
LOAD CURRENT (mA)
1000
LOAD-TRANSIENT RESPONSE
MAX15014 toc17
70
MAX15014 toc18
VIN = 4.5V, IOUT = 0.25A TO 1A
MAX15015A
VOUT
AC-COUPLED
100mV/div
VOUT
AC-COUPLED
100mV/div
VIN = 24V
60
50
VIN = 12V
40
30
ILOAD
500mA/div
VIN = 40V
20
ILOAD
500mA/div
0
10
0
3.26
90
10
1000
3.28
100
VIN = 40V
EFFICIENCY vs. LOAD CURRENT
(MAX15017A)
100
EFFICIENCY (%)
90
MAX15014 toc16
0
VOUT = 3.3V
30
MAX15016A
ILDO_OUT = 0A
10
100
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY vs. LOAD CURRENT
VIN = 7.5V
ILOAD = 0A
3.30
3.20
MAX15014 toc14
90
3.32
3.22
10ms/div
VOUT = 3.3V
3.34
3.24
0V
10ms/div
MAX15014 toc13
100
VOUT
2V/div
EFFICIENCY (%)
0V
3.36
OUTPUT VOLTAGE (V)
ILOAD = 1A
OUTPUT VOLTAGE vs. TEMPERATURE
3.40
MAX15014 toc12
MAX15014 toc10
MAX15014 toc15
TURN-ON/-OFF WAVEFORM
INCREASING VIN
1
10
100
LOAD CURRENT (mA)
www.maximintegrated.com
1000
200µs/div
0
200µs/div
Maxim Integrated │ 8
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG =
1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.)
LX VOLTAGE AND INDUCTOR CURRENT
LX VOLTAGE AND INDUCTOR CURRENT
MAX15014 toc19
MAX15014 toc20
MAX150_ _
VLX
5V/div
VLX
5V/div
0V
0V
INDUCTOR CURRENT
100mA/div
INDUCTOR CURRENT
200mA/div
0V
ILOAD = 40mA
ILOAD = 160mA
2µs/div
2µs/div
LX VOLTAGE AND INDUCTOR CURRENT
MINIMUM LX PULSE WIDTH
vs. LOAD CURRENT
MAX15014 toc21
MAX15014 toc22
400
350
LX PULSE WIDTH (ns)
VLX
5V/div
0V
INDUCTOR CURRENT
500mA/div
300
250
200
150
100
50
ILOAD = 1A
0
2µs/div
VOUT = 3.3V
300
400
500
600
700
800
900 1000
LOAD CURRENT (mA)
50
40
NO LOAD
30
20
10
0
-25
0
25
50
75
TEMPERATURE (°C)
www.maximintegrated.com
100
ILOAD = 1mA
5.00
ILOAD = 10mA
4.95
ILOAD = 50mA
4.90
125
4.85
-40
-15
10
35
60
85
TEMPERATURE (°C)
110
135
MAX15014 toc25
ILOAD = 1mA
3.30
3.29
3.28
ILOAD = 10mA
3.27
3.26
ILOAD = 50mA
3.25
3.24
MAX15015A
MAX15015B
-50
5.05
OUTPUT VOLTAGE
vs. TEMPERATURE
3.31
LDO OUTPUT VOLTAGE (V)
ILOAD = 100A
MAX15014 toc24
60
OUTPUT VOLTAGE
vs. TEMPERATURE
5.10
LDO OUTPUT VOLTAGE (V)
LDO QUIESCENT CURRENT (µA)
70
MAX15014 toc23
LDO QUIESCENT CURRENT
vs. TEMPERATURE
3.23
MAX15015B
-40
-15
10
35
60
85
TEMPERATURE (°C)
110
135
Maxim Integrated │ 9
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG =
1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.)
700
10
0
TA = +85°C
600
400
TA = -40°C
300
EN_SYS
2V/div
-40
-50
-60
100
-70
0
-80
10
ILOAD = 50mA
0V
-30
200
0
MAX15014 toc28
ILDO_OUT = 10mA
-20
TA = +25°C
500
ILDO_OUT = 50mA
-10
PSRR (dB)
DROPOUT VOLTAGE (mV)
800
TURN-ON/-OFF WAVEFORM
TOGGLING EN_SYS
POWER-SUPPLY REJECTION RATIO
MAX15014 toc27
VIN = 5V, ILOAD = 0 TO 50mA
MAX15015A
TA = +135°C
MAX15014 toc26
900
DROPOUT VOLTAGE vs. LOAD CURRENT
20
30
40
LOAD CURRENT (mA)
50
VOUT
2V/div
ILDO_OUT = 1mA
0.1k
1k
10k
100k
FREQUENCY (Hz)
0V
1M
TURN-ON/-OFF WAVEFORM
TOGGLING EN_SYS
10M
2ms/div
TURN-ON/-OFF WAVEFORM
TOGGLING EN_SYS
MAX15014 toc29
MAX15014 toc30
RLOAD = 1kΩ
MAX15015B
RLOAD = 66Ω
EN_SYS
2V/div
EN_SYS
2V/div
0V
0V
VOUT
2V/div
VLDO_OUT
1V/div
0V
0V
10ms/div
10ms/div
TURN-ON/-OFF WAVEFORM
TOGGLING EN_SYS
TURN-ON/-OFF WAVEFORM
INCREASING VIN
MAX15014 toc31
MAX15014 toc32
ILOAD = 50mA
MAX15015B
RLOAD = 660Ω
EN_SYS
2V/div
VIN
5V/div
0V
0V
VLDO_OUT
1V/div
0V
0V
10ms/div
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VLDO_OUT
2V/div
10ms/div
Maxim Integrated │ 10
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG =
1μF, CIN_SW = 0.1μF, CIN_LDO = 0.1μF, CLDO_OUT = 10μF, CDRAIN = 0.22μF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.)
LDO TURN-ON/-OFF WAVEFORM
WITH INCREASING VIN
TURN-ON/-OFF WAVEFORM
INCREASING VIN
MAX15014 toc33
MAX15014 toc34
ILOAD = 5mA
MAX15015B
RLOAD = 66Ω
VIN
2V/div
VIN
5V/div
0V
0V
VLDO_OUT
1V/div
VLDO_OUT
2V/div
0V
0V
10ms/div
10ms/div
TURN-ON/-OFF WAVEFORM
INCREASING VIN
LOAD-TRANSIENT RESPONSE
MAX15014 toc35
MAX15015B
RLOAD = 660Ω
MAX15014 toc36
VIN
5V/div
VLDO_OUT
AC-COUPLED
100mV/div
0V
VLDO_OUT
1V/div
0V
ILOAD
20mA/div
0
10ms/div
100µs/div
INPUT-VOLTAGE STEP RESPONSE
RESIDUAL SWITCHING NOISE
ON THE LDO OUTPUT
MAX15014 toc38
MAX15014 toc37
DC-DCLOAD = 1A
MAX15015B
ILOAD = 1mA
VIN
20V/div
VLDO_OUT
10mV/div
0V
VLDO_OUT
AC-COUPLED
100mV/div
1ms/div
www.maximintegrated.com
400ns/div
Maxim Integrated │ 11
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Pin Description
PIN
NAME
FUNCTION
MAX15014/
MAX15017
MAX15015/
MAX15016
1–3, 9, 12, 14,
16, 19, 24, 26,
27, 30, 35
1–3, 9, 12, 14,
16, 19, 24, 26,
27, 30, 35
N.C.
No Connection. Not internally connected. Leave unconnected or connect to SGND.
23, 28
—
I.C.
Internally Connected. Leave unconnected.
4
4
RESET
Active-Low Reset Output. When the rising VLDO_OUT voltage crosses the reset
threshold, RESET goes high after an adjustable delay. Pull up RESET to LDO_OUT
with at least 4kΩ. RESET is an active-low open-drain output.
5
5
SGND
Signal Ground Connection. Connect SGND and PGND together at one point near
the input bypass capacitor negative terminal.
Reset Timeout Delay Capacitor Connection. CT is pulled low during reset. When out
of reset, CT is pulled up to an internal 3.6V rail with a 2µA current source. When the
rising CT voltage reaches the trip threshold (typically 1.24V), RESET is deasserted.
When EN_SYS is low or in thermal shutdown, CT is low.
6
6
CT
7
7
EN_SW
Switching Regulator Enable Input (Active High). If EN_SW is high and EN_SYS is
high, the switching power supply is enabled. EN_SW is internally pulled down to
SGND through a 0.5µA current sink.
8
8
EN_SYS
Active-High System Enable Input. Connect EN_SYS high to turn on the system. The
LDO is active if EN_SYS is high; once EN_SYS is high, the switching regulator can
be turned on if EN_SW is high. EN_SYS is internally pulled down to SGND through
a 0.5µA current sink.
10
10
SET_LDO
LDO Feedback Input/Output Voltage Setting. Connect SET_LDO to SGND to select
the preset output voltage (5V or 3.3V). Connect SET_LDO to an external resistordivider network for adjustable output operation.
11
11
LDO_
OUT
Linear Regulator Output. Bypass with at least 10µF low-ESR capacitor from LDO_
OUT to SGND. In the 5V LDO versions (A), the LDO operates in dropout below 6V
down to the UVLO trip point.
13
13
IN_LDO
LDO Input Voltage. The input voltage range for the LDO extends from 5V to 40V.
Bypass with a 0.1µF ceramic capacitor to SGND.
15
15
BST
High-Side Gate Driver Supply. Connect BST to the cathode of the bootstrap diode
and to the positive terminal of the bootstrap capacitor.
17, 18
17, 18
LX
20, 21
20, 21
DRAIN
Drain Connection of the Internal High-Side Switch. Connect both DRAIN inputs
together.
PGND
Power Ground Connection. Connect the input bypass capacitor negative terminal,
the anode of the freewheeling diode, and the output filter capacitor negative terminal
to PGND. Connect PGND to SGND together at a single point near the input bypass
capacitor negative terminal.
22
22
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Source Connection of Internal High-Side Switch. Connect both LX pins to the
inductor and the cathode of the freewheeling diode.
Maxim Integrated │ 12
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Pin Description (continued)
PIN
MAX15014/
MAX15017
MAX15015/
MAX15016
NAME
—
23
C-
25
25
DVREG
—
28
C+
29
29
SYNC
Oscillator Synchronization Input. SYNC can be driven by an external clock to
synchronize the switching frequency. Connect SYNC to SGND when not used.
31
31
COMP
Error Amplifier Output. Connect COMP to the compensation feedback network.
32
32
FB
33
33
SS
34
34
REG
Internal Regulator Output. 5V output for the MAX15015/MAX15016 and 8V output for
the MAX15014/MAX15017. Bypass to SGND with at least a 1µF ceramic capacitor.
36
36
IN_SW
Supply Input Connection. Connect to IN_LDO and an external voltage source from
4.5V to 40V. EN_SW and EN_SYS must be high and IN_SW must be above its
UVLO threshold for operation of the switching regulator.
—
—
EP
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FUNCTION
Charge-Pump Flying Capacitor Negative Connection (MAX15015/MAX15016 only)
Gate Drive Supply for the High-Side MOSFET Driver. Connect to REG and to
the anode of the bootstrap diode for MAX15014/MAX15017. Connect to REG for
MAX15015/MAX15016.
Charge-Pump Flying Capacitor Positive Connection (MAX15015/MAX15016 only).
Connect to the positive terminal of the external pump capacitor and to the anode of
the bootstrap diode.
Feedback Regulation Point. Connect to the center tap of a resistive divider from
converter output to SGND to set the output voltage. The FB voltage regulates to the
voltage present at SS (1.235V).
Soft-Start and Reference Output. Connect a capacitor from SS to SGND to set the
soft-start time. See the Applications Information section to calculate the value of the
CSS capacitor.
Exposed Pad. The exposed pad must be electrically connected to SGND. For an
effective heatsinking, solder the exposed pad to a large copper plane.
Maxim Integrated │ 13
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Detailed Description
the supply current falls to 6μA. Additional features include
a programmable soft-start, cycle-by-cycle current limit,
hiccup-mode output short-circuit protection, and thermal
shutdown.
The MAX15014–MAX15017 combine a voltage-mode
buck converter with an internal 0.5Ω power-MOSFET
switch and a low-quiescent-current LDO regulator. The
buck converter of the MAX15015/MAX15016 has a wide
input voltage range of 4.5V to 40V. The MAX15014/
MAX15017’s input voltage range is 7.5V to 40V. Fixed
switching frequencies of 135kHz and 500kHz are available. The internal low RDS_ON switch allows for up to 1A
of output current, and the output voltage can be adjusted
from 1.26V to 32V. External compensation and voltage feed-forward simplify loop-compensation design and
allow for a wide variety of L and C filter components. All
devices offer an automatic switchover to pulse-skipping
(PFM) mode, providing low-quiescent current and high
efficiency at light loads. Under no load, PFM mode operation reduces the current consumption to 5.6mA for the
MAX15014/MAX15017 and 8.6mA for the MAX15015/
MAX15016. In shutdown (DC-DC and LDO regulator off),
IN_SW
EN_SYS
IN_LDO
7.0V OR 4.1V
REG
VREG_OK
EN_SW
VREFOK
VINTOK
THERMAL
SHDN
VREF
VREFOK
VINT
VREG_EN
PREREG
C-
TSD
DVREG
LEVEL
SHIFT
PCLK
VREF
VINT
VINT
SET_LOD
MUX
VINT
VINT
2A
OUT_LDO
185mV
-
-
VREF
+
RESET
+
DELAY COMPARATOR
EN
CT
DRAIN
+
+
E/A
-
FB
+
SSA
-
VREF
OVERLOAD
MANAGEMENT
COMP
DVREG
LDO_OUT
-
SHDN
0.925 x VREF
VREG_ OK
SS
C+
+
ENABLE LDO
UVLO_LDO
TSD
SHDN
VINT
REF
IN_LDO
MAX15015
MAX15016
VINTOK
UVLO_SW
TSD
SHDN
-
VINT
ISS
UVLO_LDO
+
VREF
The MAX15014–MAX15017 feature two logic inputs,
EN_SW (active-high) and EN_SYS (active-high) that
can be used to enable the switching power supply and
the LDO_OUT outputs. When VEN_SW is higher than
the threshold and EN_SYS is high, the switching power
supply is enabled. When EN_SYS is high, the LDO is
PASS ELEMENT
4.1V
VINT
Enable Inputs and UVLO
UVLO_SW
VREFOK
VINT V
INTOK
+
REG_LDO
The LDO linear regulator operates from 5V to 40V and
delivers a guaranteed 50mA load current. The devices
feature a preset output voltage of 5.0V (MAX1501_A) or
3.3V (MAX1501_B). Alternatively, the output voltage can
be adjusted from 1.5V to 11V using an external resistive
divider. The LDO section also features a RESET output
with adjustable timeout period.
REF_ILIM
PFM
+
-
REF_PFM
CLK
HIGH-SIDE
CURRENT
SENSE
BST
OVERL
IN S/W
SYNC
EN
OSC
RAMP
+
-
CPWM
+
0.3V
SGND
LX
-
CLK
DVREG
LOGIC
PFM
SCLK
PCLK
PGND
Figure 1. MAX15015/MAX15016 Simplified Block Diagram
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Maxim Integrated │ 14
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
IN_SW
EN_SYS
IN_LDO
7.0V OR 4.1V
+
REG_LDO
REG
VREG_OK
EN_SW
VINT
ISS
REF
VREFOK
VINT V
INTOK
PASS ELEMENT
4.1V
UVLO_LDO
VREFOK
VINT VINTOK
VREG_EN
THERMAL
SHDN
PREREG
TSD
ENABLE LDO
-
SHDN
VREF
VINT
VINT
0.925 x VREF
MUX
SET_LOD
VINT
VINT
2A
OUT_LDO
185mV
-
-
VREG_ OK
LDO_OUT
+
UVLO_LDO
TSD
SHDN
VINT
VREF
VREFOK
VINT
VINTOK
UVLO_SW
TSD
SHDN
-
MAX15014
MAX15017
UVLO_SW
+
VREF
IN_LDO
VREF
+
+
RESET
DELAY COMPARATOR
EN
CT
+
+
E/A
-
SS
FB
+
SSA
-
ILIM
VREF
OVERLOAD
MANAGEMENT
COMP
DRAIN
-
REF_ILIM
PFM
+
-
REF_PFM
HIGH-SIDE
CURRENT
SENSE
CLK
BST
OVERL
IN S/W
EN
OSC
SYNC
RAMP
+
-
CPWM
PFM
0.3V
SCLK
PCLK
CLK
SGND
LX
DVREG
LOGIC
+
PGND
Figure 2. MAX15014/MAX15017 Simplified Block Diagram
Table 1. Enable Inputs Configuration
EN_SW
LDO REGULATOR
DC-DC SWITCHING
CONVERTER
Low
Low
Off
Off
Low
High
Off
Off
High
Low
On
Off
High
High
On
On
EN_SYS
active. When EN_SYS is low, the entire chip is off (see
Table 1).
The MAX15014–MAX15017 provide undervoltage lockout
(UVLO). The UVLO monitors the input voltage (VIN_LDO)
and is fixed at 4.1V (MAX15015/MAX15016) or 7V
(MAX15014/MAX15017).
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Internal Linear Regulator (REG)
REG is the output terminal of a 5V (MAX15015/
MAX15016), or 8V (MAX15014/MAX15017) LDO that
is powered from IN_SW and provides power to the IC.
Connect REG externally to DVREG to provide power for
the high-side MOSFET gate driver. Bypass REG to SGND
with a ceramic capacitor (CREG) of at least 1μF. Place the
Maxim Integrated │ 15
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
capacitor physically close to the MAX15014–MAX15017
to provide good bypassing. During normal operation, REG
is intended for powering up only the internal circuitry and
should not be used to supply power to external loads.
Soft-Start and Reference (SS)
SS is the 1.235V reference bypass connection for the
MAX15014–MAX15017 and also controls the soft-start
period. At startup, after input voltage is applied at IN_SW,
IN_LDO and the UVLO thresholds are reached, the
device enters soft-start. During soft-start, 14μA is sourced
into the capacitor (CSS) connected from SS to SGND
causing the reference voltage to ramp up slowly. When
VSS reaches 1.244V, the output becomes fully active. Set
the soft-start time (tSS) using following equation:
t SS =
VSS × C SS
I SS
where VSS = soft-start reference voltage = 1.235V
(typ), ISS = soft-start current = 14 x 10-6A (typ), tSS is in
seconds and CSS is in Farads.
Internal Charge Pump (MAX15015/MAX15016)
The MAX15015/MAX15016 feature an internal charge
pump to enhance the turn-on of the internal MOSFET,
allowing for operation with input voltages down to 4.5V.
Connect a flying capacitor (CF) between C+ and C-,
a boost diode from C+ to BST, as well as a bootstrap
capacitor (CBST) between BST and LX to provide the
gate-drive voltage for the high-side n-channel DMOS
switch. During the on-time, the flying capacitor is charged
to VDVREG. During the off-time, the positive terminal of
the flying capacitor (C+) is pumped to two times VDVREG,
and charge is dumped onto CBST to provide twice the
regulator voltage across the high-side DMOS driver. Use
a ceramic capacitor of at least 0.1μF for CBST and CF,
located as close as possible to the device.
Gate-Drive Supply (DVREG)
DVREG is the supply input for the internal high-side
MOSFET driver. The power for DVREG is derived from
the output of the internal regulator (REG). Connect
DVREG to REG externally. To filter the switching noise,
the use of an RC filter (1Ω and 0.47μF) from REG to
DVREG is recommended. In the MAX15015/MAX15016,
the high-side drive supply is generated using the internal charge pump along with the bootstrap diode and
capacitor. In the MAX15014/MAX15017, the high-side
MOSFET driver supply is generated using only the bootstrap diode and capacitor.
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Error Amplifier
The output of the internal error amplifier (COMP) is available for frequency compensation (see the Compensation
Design section). The inverting input is FB, the noninverting input SS, and the output COMP. The error amplifier
has an 80dB open-loop gain and a 1.8MHz GBW product.
See the Typical Operating Characteristics for the Gain
and Phase vs. Frequency graph.
Oscillator/Synchronization Input (SYNC)
With SYNC connected to SGND, the MAX15014–
MAX15017 use their internal oscillator and switch at a
fixed frequency of 135kHz and 500kHz. The MAX15014/
MAX15016 are the 135kHz options and MAX15015/
MAX15017 are the 500kHz options. For external synchronization, drive SYNC with an external clock from 400kHz
to 600kHz (MAX15015/MAX15017), or 100kHz to 200kHz
(MAX15014/MAX15016). When driven with an external
clock, the device synchronizes to the rising edge of SYNC.
PWM Comparator/Voltage Feed-Forward
An internal ramp generator clocked by the internal
oscillator is compared against the output of the error
amplifier to generate the PWM signal. The maximum
amplitude of the ramp (VRAMP) automatically adjusts to
compensate for input voltage and oscillator frequency
changes. This causes the VIN_SW/VRAMP to be a constant 10V/V across the input voltage range of 4.5V to 40V
(MAX15015/MAX15016), or 7.5V to 40V (MAX15014/
MAX15017), and the SYNC frequency range of 400kHz
to 600kHz (MAX15015/MAX15017), or 100kHz to 200kHz
(MAX15014/MAX15016).
Output Short-Circuit Protection
(Hiccup Mode)
The MAX15014–MAX15017 protect against an output
short circuit by utilizing hiccup-mode protection. In hiccup
mode, a series of sequential cycle-by-cycle current-limit
events cause the part to shut down and restart with a softstart sequence. This allows the device to operate with a
continuous output short circuit.
During normal operation, the current is monitored at the
drain of the internal power MOSFET. When the current
limit is exceeded, the internal power MOSFET turns off until
the next on-cycle and a counter increments. If the counter
counts seven consecutive current-limit events, the device
discharges the soft-start capacitor and shuts down for 512
clock periods before restarting with a soft-start sequence.
Each time the power MOSFET turns on and the device
does not exceed the current limit, the counter is reset.
Maxim Integrated │ 16
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
LDO Regulator
where VFB = 1.235V.
The LDO regulator operates over an input voltage from
5V to 40V, and can be enabled independently of the
DC-DC converter section. Its quiescent current is as
low as 47μA with a load current of 100μA. All devices
feature a preset output voltage of 5V (MAX1501_A) or
3.3V (MAX1501_B). Alternatively, the output voltage can
be adjusted using an external resistive-divider network
connected between LDO_OUT, SET_LDO, and SGND.
See Figure 5.
RESET Output
The RESET output is typically connected to the reset
input of a microprocessor (μP). A μP’s reset input starts
or restarts the μP in a known state. The MAX15014–
MAX15017 supervisory circuits provide the reset logic to
prevent code-execution errors during power-up, powerdown, and brownout conditions. RESET changes from
high to low whenever the monitored voltage drops below
the RESET threshold voltage. Once the monitored voltage exceeds its respective RESET threshold voltage(s),
RESET remains low for the RESET timeout period, then
goes high. The RESET timeout period is adjustable with
an external capacitor (CCT) connected to CT.
Thermal-Shutdown Protection
The MAX15014–MAX15017 feature thermal-shutdown
protection that limits the total power dissipation in the
device and protects it in the event of an extended
thermal-fault condition. When the die temperature exceeds
+160°C, an internal thermal sensor shuts down the part,
turning off the DC-DC converter and the LDO regulator,
and allowing the IC to cool. After the die temperature falls
by 20°C, the part restarts with a soft-start sequence.
Applications Information
Setting the Output Voltage
Connect a resistive divider (R3 and R4, see Figures
6 and 7) from OUT to FB to SGND to set the output
voltage. Choose R3 and R4 so that DC errors due to the FB
input bias current do not affect the output-voltage setting
precision. For the most common output-voltage
settings (3.3V or 5V), R3 values in the 10kΩ range are
adequate. Select R3 first and calculate R4 using the
following equation:
R4 =
www.maximintegrated.com
R3
VOUT
− 1
VFB
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX15014–MAX15017:
inductance value (L), peak inductor current (IPEAK), and
inductor saturation current (ISAT). The minimum required
inductance is a function of operating frequency, inputto-output voltage differential, and the peak-to-peak
inductor current (ΔIP-P). Higher ΔIP-P allows for a lower
inductor value, while a lower ΔIP-P requires a higher
inductor value. A lower inductor value minimizes size and
cost and improves large-signal and transient response,
but reduces efficiency due to higher peak currents and
higher peak-to-peak output-voltage ripple for the same
output capacitor. On the other hand, higher inductance
increases efficiency by reducing the ΔIP-P. Resistive
losses due to extra wire turns can exceed the benefit gained from lower ΔIP-P levels, especially when the
inductance is increased without also allowing for larger
inductor dimensions. A good compromise is to choose
ΔIP-P equal to 40% of the full load current. Calculate the
inductor using the following equation:
L=
VOUT (VIN − VOUT )
VIN × f SW × ∆IP−P
VIN and VOUT are typical values so that efficiency is
optimum for typical conditions. The switching frequency
(fSW) is internally fixed at 135kHz (MAX15014/MAX15016)
or 500kHz (MAX15015/MAX15017) and can vary when
synchronized to an external clock (see the Oscillator/
Synchronization Input (SYNC) section). The ΔIP-P, which
reflects the peak-to-peak output ripple, is worst at the maximum input voltage. See the Output Capacitor Selection
section to verify that the worst-case output ripple is acceptable. The inductor current (ISAT) is also important to avoid
current runaway during continuous output short circuit.
Select an inductor with an ISAT specification higher than
the maximum peak current limit of 2.6A.
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the input
capacitor must be carefully chosen to keep the input
voltage ripple within design requirements. The input voltage ripple is comprised of ΔVQ (caused by the capacitor
discharge) and ΔVESR (caused by the ESR of the input
capacitor). The total voltage ripple is the sum of ΔVQ and
ΔVESR. Calculate the input capacitance and ESR required
for a specified ripple using the following equations:
Maxim Integrated │ 17
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
∆VESR
∆I
I OUT_MAX + P−P
2
I OUT_MAX × D
ESR =
C IN =
∆VQ × f SW
where CIN is the sum of CDRAIN and additional decoupling
capacitance at the buck converter input,
(VIN − VOUT ) × VOUT
∆IP−P =
and
VIN × f SW × L
D=
VOUT
VIN
IOUT_MAX is the maximum output current, D is the duty
cycle, and fSW is the switching frequency.
The output capacitor supplies the load current during
a load step until the controller responds with a greater
duty cycle. The response time (tRESPONSE) depends
on the closed-loop bandwidth of the converter (see
the Compensation Design section). The resistive drop
across the output capacitor’s ESR, the drop across the
capacitor’s ESL (ΔVESL), and the capacitor discharge
causes a voltage droop during the load step.
Use a combination of low-ESR tantalum/aluminum
electrolytic and ceramic capacitors for better
transient load and voltage-ripple performance. Non-leaded
capacitors and capacitors in parallel help reduce the ESL.
Keep the maximum output-voltage deviation below the
tolerable limits of the electronics being powered. Use the
following equations to calculate the required ESR, ESL,
and capacitance value during a load step:
∆VESR
I STEP
The MAX15014–MAX15017 include UVLO hysteresis
and soft-start to avoid chattering during turn-on. However,
use additional bulk capacitance if the input source
impedance is high. Use enough input capacitance
at lower input voltages to avoid possible undershoot
below the undervoltage-lockout threshold during transient
loading.
ESR =
Output Capacitor Selection
tRESPONSE ≅
The allowable output-voltage ripple and the maximum
deviation of the output voltage during load steps determine the output capacitance (COUT) and its equivalent
series resistance (ESR). The output ripple is mainly
composed of ΔVQ (caused by the capacitor discharge)
and ΔVESR (caused by the voltage drop across the ESR
of the output capacitor). The equations for calculating the
peak-to-peak output-voltage ripple are:
∆IP−P
∆VQ =
8 × C OUT × f SW
∆VESR
= ESR × ∆IP−P
Normally, a good approximation of the output-voltage
ripple is ΔVRIPPLE = ΔVESR + ΔVQ. If using ceramic
capacitors, assume the contribution to the output-voltage
ripple from ESR and the capacitor discharge to be equal
to 20% and 80%, respectively. ΔIP-P is the peak-topeak inductor current (see the Input Capacitor Selection
section) and fSW is the converter’s switching frequency.
The allowable deviation of the output voltage during fastload transients also determines the output capacitance,
its ESR, and its equivalent series inductance (ESL).
www.maximintegrated.com
I
×t
C OUT = STEP RESPONSE
∆VQ
ESL =
∆VESL × t STEP
I STEP
1
3ƒ C
where ISTEP is the load step, tSTEP is the rise time of
the load step, tRESPONSE is the response time of the
controller, and fC is the closed-loop crossover frequency.
Compensation Design
The MAX15014–MAX15017 use a voltage-mode-control
scheme that regulates the output voltage by comparing
the error-amplifier output (COMP) with an internal ramp
to produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequency,
which has a gain drop of -40dB/decade. The error amplifier must compensate for this gain drop and phase shift to
achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback-divider, and a voltage error amplifier.
The power modulator has a DC gain set by VIN/VRAMP,
with a double pole and a single zero set by the output
inductance (L), the output capacitance (COUT), and its
ESR. The power modulator incorporates a voltage feedforward feature, which automatically adjusts for variations
in the input voltage, resulting in a DC gain of 10.
Maxim Integrated │ 18
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
The following equations define the power modulator:
C8
VIN
= =
G MOD_DC
10
VRAMP
1
f LC =
2 × π × L × C OUT
f ZESR =
1
2 × π × C OUT × ESR
The switching frequency is internally set at 500kHz
for MAX15015/MAX15017 and can vary from 400kHz
to 600kHz when driven with an external SYNC signal.
The switching frequency is internally set at 135kHz for
MAX15014/MAX15016 and can vary from 100kHz to
200kHz when driven with an external SYNC signal. The
crossover frequency (fC), which is the frequency when the
closed-loop gain is equal to unity, should be set to around
1/10 of the switching frequency or below.
The crossover frequency occurs above the LC double-pole
frequency, and the error amplifier must provide a gain and
phase bump to compensate for the rapid gain and phase
loss from the LC double pole, which exhibits little damping.
This is accomplished by utilizing a Type 3 compensator
that introduces two zeroes and three poles into the control
loop. The error amplifier has a low-frequency pole (fP1)
near the origin so that tight voltage regulation at DC can
be achieved.
The two zeroes are at:
1
f ZI =
2π × R5 × C7
and
f Z2 =
1
2π × (R3 + R6) × C6
and the higher frequency poles are at:
f P2 =
1
2π × R6 × C6
and
f P3 =
1
2π × R5 ×
C7 × C8
C7 + C8
The compensation design primarily depends on the type
of output capacitor. Ceramic capacitors exhibit very low
ESR, and are well suited for high-switching-frequency
www.maximintegrated.com
VOUT
C7
R5
C6
R6
R3
EA
R4
COMP
REF
GAIN
(dB)
CLOSED-LOOP
GAIN
fZ1 fZ2
fC
EA
GAIN
fP2 fP3
FREQUENCY
Figure 3. Error Amplifier Compensation Circuit (Closed-Loop
and Error-Amplifier Gain Plot) for Ceramic Capacitors
applications, but are limited in capacitance value and
tend to be more expensive. Aluminum electrolytic capacitors have much larger ESR but can reach much larger
capacitance values.
Compensation when fC < fZESR
This is usually the case when a ceramic capacitor is
selected. In this case, fZESR occurs after fC. Figure 3
shows the error amplifier feedback as well as its gain
response.
fZ1 is set to 0.5 to 0.8 x fLC and fZ2 is set to fLC to
compensate for the gain and phase loss due to the double
pole. To achieve a 0dB crossover with -20dB/decade
slope, poles fP2 and fP3 are set above the crossover
frequency (fC).
The values for R3 and R4 are already determined in the
Setting the Output Voltage section. The value of R3 is
also used in the following calculations.
Since fZ2 < fC < fP2, then R3 >> R6, and R3 + R6 can be
approximated as R3.
Now we can calculate C6 for zero fZ2:
C6 =
1
2π × f LC × R3
Maxim Integrated │ 19
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
fC occurs between fZ2 and fP2. In this region, the
compensatorgain (GEA) at fC is due primarily to C6 and
R5. Therefore, GEA(fC) = 2π x fC x C6 x R5 and the
modulator gain at fC is:
G MOD (f C ) =
C8
G MOD_DC
(2π × f C ) 2 × L × C OUT
Since GEA(fC) x GMOD(fC) = 1, R5 is calculated by:
VOUT
The frequency of fZ1 is set to 0.5 x fLC and now we can
calculate C7 by:
C7 =
R3
EA
1
2π × C6 × (0.5 × f SW )
Note that if the crossover frequency has been chosen as
1/10 of the switching frequency, then fP2 = 5xfC.
The purpose of fP3 is to further attenuate the residual
switching ripple at the COMP pin.
If the ESR zero (fZESR) occurs in a region between fC and
fSW/2, then fP3 can be used to cancel it. This way, the
Bode plot of the loop-gain plot does not flatten out soon
after the 0dB crossover, and maintains its -20dB/decade
slope up to 1/2 of the switching frequency.
COMP
REF
GAIN
(dB)
CLOSED-LOOP
GAIN
1
0.5 × 2π × R5 × f LC
fP2 is set at 1/2 the switching frequency (fSW). R6 is then
calculated by:
R6 =
R6
R4
f × L × C OUT × 2π
R5 = C
C6 × G MOD_DC
C7
R5
C6
fZ1 fZ2
fP2
EA
GAIN
fC fP3
FREQUENCY
Figure 4. Error Amplifier Compensation Circuit (ClosedLoop and Error-Amplifier Gain Plot) for Higher ESR Output
Capacitors
frequency. The equations that define the error amplifier’s
poles and zeros (fZ1, fZ2, fP2, and fP3) are the same as
before; however, fP2 is now lower than the closed-loop
crossover frequency. Figure 4 shows the error-amplifier
feedback as well as its gain response for circuits that
use higher-ESR output capacitors (tantalum or aluminum
electrolytic).
If the ESR zero well exceeds fSW/2 (or even fSW), fP3
should in any case be set high enough not to erode the
phase margin at the crossover frequency. For example, it
can be set between 5 x fC and 10 x fC.
Again, starting from R3, calculate C6 for zero fZ2:
The value for C8 is calculated from:
and then place fP2 to cancel the ESR zero. R6 is
calculated as:
C8 =
C7
(2π × C7 × R5 × f P3 − 1)
Compensation when fC > fZESR
For larger ESR capacitors such as tantalum and
aluminum electrolytic, fZESR can occur before fC. If fZESR
< fC, then fC occurs between fP2 and fP3. fZ1 and fZ2
remain the same as before; however, fP2 is now set equal
to fZESR. The output capacitor’s ESR zero frequency is
higher than fLC but lower than the closed-loop crossover
www.maximintegrated.com
C6 =
R6 =
1
2π × f LC × R3
C OUT × ESR
C6
If the value obtained here for R6 is not considerably
smaller than R3, recalculate C6 using (R3 + R6) in place
of R3. Then use the new value of C6 to obtain a better
approximation for R6. The process can be further iterated,
and convergence is ensured as long as fLC < fZESR.
Maxim Integrated │ 20
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
The error-amplifier gain between fP2 and fP3 is approximately equal to R5/(R6 || R3).
The ESR zero frequency (fZESR) might not be very much
higher than the double-pole frequency fLC; therefore, the
value of R5 can be calculated as:
fC 2
R3 × R6
=
R5
×
R3 + R6 G MOD_DC × f LC 2
C7 can still be calculated as:
C7 =
IN_LDO
LDO_OUT
MAX15014–
MAX15017
1
0.5 × 2π × R5 × f LC
fP3 is set at 5xfC. Therefore, C8 is calculated as:
C8 =
VIN_LDO
C7
2π × C7 × R5 × f P3 − 1
Setting the LDO Linear Regulator
Output Voltage
The MAX15014–MAX15017 LDO regulator features Dual
Mode™ operation: it can operate in either a preset voltage mode or an adjustable mode. In preset-voltage mode,
internal trimmed feedback resistors set the internal linear
regulator to 3.3V or 5V (see the Selector Guide). Select
preset-voltage mode by connecting SET_LDO to ground.
In adjustable mode, select an output voltage between
1.5V and 11V using two external resistors connected as
a voltage-divider to SET_LDO (see Figure 5). Set the
output voltage using the following equation:
R1
VOUT VSET_LDO 1 +
=
R2
where VSET_LDO = 1.241V and the recommended value
for R2 is around 50kΩ.
Setting the RESET Timeout Delay
The RESET timeout period is adjustable to accommodate
a variety of μP applications. Adjust the RESET timeout
period by connecting a capacitor (CCT) between CT and
SGND.
C
× VCT-TH
t RP = CT
ICT -THQ
where VCT-TH = delay-comparator threshold (rising) =
1.241V (typ), ICT-THQ = CT charge current = 2 x 10-6A
(typ), tRP is in seconds and CCT is in Farads.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
www.maximintegrated.com
R1
SET_LDO
SGND
R2
Figure 5. Setting the Output Voltage Using a Resistive Divider
Connect CT to LDO_OUT to select the internally
fixed timeout period. CCT must be a low-leakage-type
capacitor. Ceramic capacitors are recommended; do not
use capacitors lower than 200pF to avoid the influence of
parasitic capacitances.
Capacitor Selection and Regulator Stability
For stable operation over the full temperature range and
with load currents up to 50mA, use a 10μF (min) output
capacitor (CLDO_OUT) with a maximum ESR of 0.4Ω.
To reduce noise and improve load-transient response,
stability, and power-supply rejection, use larger output
capacitor values. Some ceramic dielectrics such as
Z5U and Y5V exhibit very large capacitance and ESR
variation with temperature and are not recommended.
With X7R or X5R dielectrics, 15μF should be sufficient for
operation over their rated temperature range. For higher
ESR tantalum capacitors (up to 1Ω), use 22μF or more
to maintain stability. To improve power-supply rejection
and transient response, use a minimum 0.1μF capacitor
between IN_LDO and SGND.
Power Dissipation
The MAX15014–MAX15017 are available in a thermally
enhanced package and can dissipate up to 2.86W at TA
= +70°C. When the die temperature reaches +160°C,
the part shuts down and is allowed to cool. After the die
cools by 20°C, the device restarts with a soft-start. The
power dissipated in the device is the sum of the power
dissipated in the LDO, power dissipated from supply
current (PQ), transition losses due to switching the
internal power MOSFET (PSW), and the power
Maxim Integrated │ 21
MAX15014–MAX15017
R6
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
VIN
4.5V TO 40V
R3
CIN_LDO
CDRAIN
CIN_SW
D1
C8
C6
IN_LDO
C7
R5
IN_SW
DRAIN
BST
COMP
CBST
FB
R4
VIN
5V TO 40V
EN_SW
COUT
D2
C+
MAX15015
MAX15016
C-
RESET
SS
10kΩ
CT
SYNC
PGND SGND
VOUT1 AT 1A
LX
EN_SYS
CF
L
VOUT2 AT 50mA
LDO_OUT
REG
CSS
CCT
1Ω
CREG
DVREG
0.47µF
CLDO_OUT
SET_LDO
PGND
SGND
Figure 6. MAX15015/MAX15016 Typical Application Circuit (4.5V to 40V Input Operation)
dissipated due to the RMS current through the internal
power MOSFET (PMOSFET). The total power dissipated
in the package must be limited such that the junction
temperature does not exceed its absolute maximum rating
of +150°C at maximum ambient temperature. Calculate
the power lost in the MAX15014–MAX15017 using the
following equations:
The power loss through the switch:
=
PMOSFET (IRMS_MOSFET )2 × R ON
IRMS_MOSFET =
D 2
× I PK + (IPK × IDC ) + I 2 DC
3
∆IP−P
2
∆IP−P
IDC I OUT −
=
2
VOUT
D=
VIN
IPK I OUT +
=
www.maximintegrated.com
RON is the on-resistance of the internal power MOSFET
(see the Electrical Characteristics).
The power loss due to switching the internal MOSFET:
PSW =
VIN × I OUT × (t R + t F ) × f SW
4
tR and tF are the rise and fall times of the internal power
MOSFET measured at LX.
The power loss due to the switching supply current (ISW):
PQ = VIN_SW ×ISW
The power loss due to the LDO regulator:
PLDO = (VIN_LDO − VLDO_OUT) ×ILDO_OUT
The total power dissipated in the device will be:
PTOTAL = PMOSFET + PSW + PQ + PLDO
Maxim Integrated │ 22
MAX15014–MAX15017
R6
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
VIN
7.5V TO 40V
R3
CIN_SW
CIN_LDO
CDRAIN
D1
C8
C6
IN_LDO
C7
R5
IN_SW
DRAIN
BST
COMP
CBST
FB
R4
VIN
7.5V TO 40V
EN_SW
VOUT1 AT 1A
LX
EN_SYS
COUT
D2
MAX15014
MAX15017
RESET
SS
10kΩ
CT
SYNC
PGND SGND
L
VOUT2 AT 50mA
LDO_OUT
REG
CSS
CCT
1
CREG
DVREG
0.47µF
CLDO_OUT
SET_LDO
PGND
SGND
Figure 7. MAX15014/MAX15017 Typical Application Circuit (7.5V to 40V Input-Voltage Operation)
www.maximintegrated.com
Maxim Integrated │ 23
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
28 C+ (I.C.)
29 SYNC
30 N.C.
31 COMP
32 FB
PROCESS: BiCMOS/DMOS
33 SS
34 REG
Chip Information
27
N.C.
26
N.C.
3
25
DVREG
4
24
N.C.
23
C- (I.C.)
22
PGND
21
DRAIN
20
DRAIN
19
N.C.
1
2
+
5
MAX15014–
MAX15017
6
7
8
EP*
10
11
12
13
14
15
16
17
18
SET_LDO
N.C.
IN_LDO
N.C.
BST
N.C.
LX
LX
9
LDO_OUT
N.C.
N.C.
N.C.
RESET
SGND
CT
EN_SW
EN_SYS
N.C.
36 IN_SW
TOP VIEW
35 N.C.
Pin Configuration
( ) MAX15014/MAX15017
*EP = EXPOSED PAD.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
36 TQFN
T3666+3
21-0141
90-0050
TQFN
Selector Guide
LDO OUTPUT
SWITCHING
FREQUENCY (kHz)
DC-DC MINIMUM
INPUT VOLTAGE (V)
CHARGE
PUMP
5V
3.3V
ADJUSTABLE
OUTPUT
MAX15014A
135
7.5
—
X
—
X
MAX15014B
135
7.5
—
—
X
X
MAX15015A
500
4.5
X
X
—
X
MAX15015B
500
4.5
X
—
X
X
MAX15016A
135
4.5
X
X
—
X
MAX15016B
135
4.5
X
—
X
X
MAX15017A
500
7.5
—
X
—
X
MAX15017B
500
7.5
—
—
X
X
PART
www.maximintegrated.com
Maxim Integrated │ 24
MAX15014–MAX15017
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
1/07
Initial release
1
11/14
No /V OPNs in Ordering Information; deleted automotive reference in
Applications section; update Packaging Information
DESCRIPTION
—
1, 25
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2014 Maxim Integrated Products, Inc. │ 25
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