EVALUATION KIT AVAILABLE
MAX15046
40V, High-Performance, Synchronous
Buck Controller
General Description
Features
The MAX15046 synchronous step-down controller operates from a 4.5V to 40V input voltage range and generates an adjustable output voltage from 85% of the input
voltage down to 0.6V, supporting loads up to 25A. The
device allows monotonic startup into a prebiased bus
without discharging the output and features adaptive
internal digital soft-start.
The MAX15046 offers the ability to adjust the switching frequency from 100kHz to 1MHz with an external resistor. The
MAX15046’s adaptive synchronous rectification eliminates
the need for an external freewheeling Schottky diode.
The device also utilizes the external low-side MOSFET’s
on-resistance as a current-sense element, eliminating the
need for a current-sense resistor. This protects the DC-DC
components from damage during output overloaded conditions or output short-circuit faults without requiring a
current-sense resistor. Hiccup-mode current limit reduces power dissipation during short-circuit conditions. The
MAX15046 includes a power-good output and an enable
input with precise turn-on/turn-off threshold, which can be
used for input supply monitoring and power sequencing.
Additional protection features include sink-mode current
limit and thermal shutdown. Sink-mode current limit prevents reverse inductor current from reaching dangerous
levels when the device is sinking current from the output.
The MAX15046A/MAX15046B feature soft-stop operation. Soft-stop operation is disabled in the MAX15046C.
The MAX15046 is available in a 16-pin QSOP or 16-pin
QSOP-EP package and operates over the -40°C to
+125°C temperature range.
●● Input Voltage Ranges from 4.5V to 40V or 5V ±10%
●● Adjustable Outputs from 0.85 x VIN Down to 0.6V
●● Adjustable Switching Frequency (100kHz to 1MHz)
with ±10% (1MHz) Accuracy
●● Adaptive Internal Digital Soft-Start
●● Up to 25A Output Capability
●● Cycle-by-Cycle Valley-Mode Current Limit with
Adjustable, Temperature-Compensated Threshold
(30mV to 300mV)
●● Monotonic Startup into Prebiased Output
●● ±1% Accurate Voltage Reference
●● 90% Maximum Duty Cycle (MAX15046C)
●● 3A Peak Gate Drivers
●● Hiccup-Mode Short-Circuit Protection
●● Overtemperature Shutdown
●● Power-Good (PGOOD) Output and Enable Input
(EN) with ±5% Accurate Threshold
●● Thermally Enhanced 16-Pin QSOP Package
Applications
●● Industrial Power Supplies (PLC, Industrial Computers,
Fieldbus Components, Fieldbus Couplers)
●● Telecom Power Supplies
●● Base Stations
Ordering Information and Pin Configurations appear at end
of data sheet.
Typical Operating Circuit
4.5V TO 40V
VIN
C1
IN
VCC
MAX15046
PGOOD
ON
OFF
Q1
DH
LX
EN
BST
LIM
DL
L1
C2
Q2
D1
R4
COMP
C5
R3
DRV
C4
C6
C7
R1
FB
PGND
RT
GND
R3
R2
19-4719; Rev 3; 6/14
CSP
R5
0.6V TO 0.85V x VIN
VOUT
C3
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Absolute Maximum Ratings
IN to GND...............................................................-0.3V to +45V
VCC to GND..................... -0.3V to lower of (VIN + 0.6V) and 6V
EN, DRV to GND......................................................-0.3V to +6V
PGOOD to GND.....................................................-0.3V to +45V
PGND to GND.......................................................-0.3V to +0.3V
DL to PGND............................................ -0.3V to (VDRV + 0.3V)
BST to PGND ........................................................-0.3V to +50V
LX and CSP to PGND...............................................-1V to +45V
LX and CSP to PGND............................-2V (50ns max) to +45V
BST to LX.................................................................-0.3V to +6V
CSP to LX..............................................................-0.3V to +0.3V
DH to LX...................................................-0.3V to (VBST + 0.3V)
All Other Pins to GND............................... -0.3V to (VCC + 0.3V)
VCC Short Circuit to GND..........................................Continuous
PGOOD Maximum Sink Current.........................................20mA
Continuous Power Dissipation (TA = +70°C):
16-Pin QSOP (derate 9.6mW/°C above +70°C)........771.5mW
16-Pin QSOP-EP
(derate 22.7mW/°C above +70°C)..........................1818.2mW
Operating Temperature Range.......................... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
QSOP
Junction-to-Ambient Thermal Resistance (θJA)......+103.7°C/W
Junction-to-Case Thermal Resistance (θJC)................+37°C/W
QSOP-EP
Junction-to-Ambient Thermal Resistance (θJA)...........+44°C/W
Junction-to-Case Thermal Resistance (θJC)..................+6°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VIN = 24V, VEN = 5V, VGND = VPGND = 0V, CIN = 1µF, CVCC = 4.7µF, RRT = 49.9kΩ, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input-Voltage Range
VIN
Quiescent Supply Current
IIN_Q
Shutdown Supply Current
IIN_SBY
VIN = VCC = VDRV
4.5
40
4.5
5.5
VIN = 24V, VFB = 0.9V, no switching
VIN = 24V, VEN = 0V, IVCC = 0, PGOOD
= unconnected
V
2
3
mA
0.35
0.55
mA
5.25
5.5
V
VCC REGULATOR
Output Voltage
VCC
6V ≤ VIN ≤ 40V, ILOAD = 6mA
5
VCC Regulator Dropout
VIN = 4.5V, ILOAD = 25mA
0.18
0.45
V
VCC Short-Circuit Output Current
VIN = 5V
30
55
90
mA
VCC rising
3.8
4
4.2
V
VCC Undervoltage Lockout
VCCUVLO
VCC Undervoltage Lockout
Hysteresis
400
mV
ERROR AMPLIFIER (FB, COMP)
FB Input-Voltage Set Point
VFB
584
FB Input Bias Current
IFB
VFB = 0.6V
-250
FB to COMP Transconductance
gM
ICOMP = ±20µA
600
Open-Loop Gain
Unity-Gain Bandwidth
www.maximintegrated.com
Capacitor from COMP to GND = 47pF
590
1200
596
mV
+250
nA
1800
µS
80
dB
5
MHz
Maxim Integrated │ 2
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Electrical Characteristics (continued)
(VIN = 24V, VEN = 5V, VGND = VPGND = 0V, CIN = 1µF, CVCC = 4.7µF, RRT = 49.9kΩ, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
VCOMP-RAMP Minimum Voltage
COMP Source/Sink Current
TYP
MAX
200
ICOMP
VCOMP = 1.4V
EN Input High
VEN_H
VEN rising
EN Input Low
VEN_L
VEN falling
IEN
VEN = 5.5V
-1
Switching Frequency (100kHz)
fSW
RRT = 150kΩ
80
Switching Frequency (300kHz)
fSW
RRT = 49.9kΩ
Switching Frequency (1MHz)
fSW
UNITS
mV
50
80
110
µA
1.14
1.20
1.26
V
+1
µA
100
120
kHz
270
300
330
kHz
RRT = 14.3kΩ
0.9
1
1.1
MHz
(Note 3)
100
1000
kHz
RRT = 49.9kΩ
1.15
1.25
V
ENABLE (EN)
EN Input Leakage Current
1.05
V
OSCILLATOR
Switching Frequency Adjustment
Range
RT Voltage
VRT
1.2
PWM MODULATOR
PWM Ramp Peak-to-Peak
Amplitude
PWM Ramp Valley
VRAMP
VVALLEY
1.5
MAX15046A/B
1.5
MAX15046C
0.75
Minimum Controllable On-Time
Maximum Duty Cycle
70
DMAX
Minimum Low-Side On-Time
fSW = 300kHz
(RRT = 49.9kΩ)
MAX15046A/B
85
87.5
MAX15046C
90
93
fSW = 1MHz
(RRT = 14.3kΩ)
MAX15046A/B
110
MAX15046C
90
V
V
125
ns
%
ns
OUTPUT DRIVERS/DRIVERS SUPPLY (VDRV)
Undervoltage Lockout
VDRV_UVLO
VDRV rising
4.0
DRV Undervoltage Lockout
Hysteresis
DH On-Resistance
DH Peak Current
www.maximintegrated.com
4.4
400
Low, sinking 100mA, VBST - VLX = 5V
High, sourcing 100mA, VBST - VLX = 5V
DL On-Resistance
4.2
Low, sinking 100mA,
VDRV = VCC = 5.25V
High, sourcing 100mA,
VDRV = VCC = 5.25V
CLOAD = 10nF
V
mV
1
3
1.5
4
Ω
1
3
1.5
4
Sinking,
VBST - VLX = 5V
3
Sourcing,
VBST - VLX = 5V
2
A
Maxim Integrated │ 3
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Electrical Characteristics (continued)
(VIN = 24V, VEN = 5V, VGND = VPGND = 0V, CIN = 1µF, CVCC = 4.7µF, RRT = 49.9kΩ, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
DL Peak Current
CONDITIONS
CLOAD = 10nF
DH, DL Break-Before-Make Time
(Dead Time)
MIN
TYP
Sinking,
VDRV = VCC = 5.25V
3
Sourcing,
VDRV = VCC = 5.25V
2
MAX
UNITS
A
MAX15046A/B
10
MAX15046C
20
ns
SOFT-START
Soft-Start Duration
Reference Voltage Steps
2048
Switching
Cycles
64
Steps
CURRENT LIMIT/HICCUP
Cycle-by-Cycle Valley CurrentLimit Threshold Adjustment
Range
VCSP - VPGND,
valley limit =
VLIM/10
LIM Reference Current
ILIM
VLIM = 0.3V
30
VLIM = 3V
300
VLIM = 0.3V to 3V, TA = +25°C
45
LIM Reference Current
Temperature Coefficient
50
mV
55
2300
CSP Input Bias Current
VCSP = 40V
-1
Number of Consecutive CurrentLimit Events to Hiccup
Hiccup Timeout
VCSP - VPGND, sink limit = VLIM/20,
RILIM = 30kΩ, VLIM = 1.5V,
TA = +25°C
Peak Low-Side Sink CurrentLimit Threshold
µA
ppm/°C
+1
µA
7
Events
4096
Switching
Cycles
75
mV
POWER-GOOD (PGOOD)
PGOOD Threshold
VFB rising
PGOOD Threshold Hysteresis
90
VFB falling
PGOOD Output Low Voltage
VPGOOD_L
PGOOD Output Leakage Current
ILEAK_PGOOD
94
2.65
IPGOOD = 2mA, VEN = 0V
VPGOOD = 40V, VEN = 5V, VFB = 1V
97.5
-1
%VFB
%VFB
0.4
V
+1
µA
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Temperature rising
Thermal Shutdown Hysteresis
+150
°C
20
°C
Note 2: All devices are 100% tested at room temperature and guaranteed by design over the specified temperature range.
Note 3: Select RRT as:R RT
www.maximintegrated.com
=
15.14 × 10 9
f SW + (1 x 10 -7 ) (f SW 2 )
, where fSW is in Hertz.
Maxim Integrated │ 4
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Typical Operating Characteristics
(VIN = 24V, TA = +25°C, unless otherwise noted.)
30
40
30
20
20
10
10
3
0
9
12
0
15
12
VCC LINE REGULATION
5.248
10
15
20
25
30
35
40
4.6
4.0
45
SWITCHING FREQUENCY
vs. RRT
1200
MAX15046 toc07
900
800
600
500
400
300
200
100
40
80
RRT (kΩ)
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120
160
800
MAX15046 toc03
6
8
10
12
VCC vs. TEMPERATURE
ILOAD = 5mA
5.263
0
5
10
15
20
5.261
25
30
35
5.260
40
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SWITCHING FREQUENCY
vs. TEMPERATURE
RT = 25.5kΩ
2.8
2.5
RT = 49.9kΩ
2.4
200
RT = 150kΩ
2.3
TEMPERATURE (°C)
CDH = CDL = 0
2.6
400
-40 -25 -10 5 20 35 50 65 80 95 110 125
IIN vs.
SWITCHING FREQUENCY
2.7
RT = 14.3kΩ
600
0
4
5.262
IVCC = 40mA
1000
FREQUENCY (kHz)
700
0
2
0
VIN (V)
LOAD CURRENT (mA)
1000
0.10
5.265
IIN (mA)
5
0.15
5.264
4.8
4.2
0
0.20
5.266
4.4
5.244
0.25
LOAD CURRENT (A)
IVCC = 5mA, 10mA, 20mA, 30mA
5.0
VCC (V)
5.250
0.30
0
15
5.2
5.246
FREQUENCY (kHz)
9
VCC vs. LOAD CURRENT
5.252
0
6
LOAD CURRENT (A)
5.254
5.242
3
0
LOAD CURRENT (A)
MAX15046 toc04
5.256
6
0.35
0.05
MAX15046 toc08
0
VCC (V)
50
0.40
MAX15046 toc06
40
VOUT = 3.3V
VOUT = 1.2V
60
VOUT = 5V
MAX15046 toc09
50
VOUT = 1.8V
70
0.45
% OUTPUT FROM NORMAL
VOUT = 3.3V V
OUT = 1.8V
VOUT = 1.2V
VOUT = 5V
60
80
VCC (V)
70
90
VOUT vs. LOAD CURRENT
0.50
MAX15046 toc05
80
EFFICIENCY (%)
90
EFFICIENCY (%)
100
MAX15046 toc01
100
EFFICIENCY vs. LOAD CURRENT
(VIN = 12V)
MAX15046 toc02
EFFICIENCY vs. LOAD CURRENT
(VIN = 24V)
2.2
100
1000
FREQUENCY (kHz)
Maxim Integrated │ 5
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Typical Operating Characteristics (continued)
(VIN = 24V, TA = +25°C, unless otherwise noted.)
CURRENT (FA)
70
65
60
55
50
45
40
SINK AND SOURCE CURRENT LIMIT
THRESHOLDS vs. RESISTANCE (RILIM)
LOAD TRANSIENT ON OUT (1A TO 10A)
MAX15046 toc12a
MAX15046 toc11
75
0.20
CURRENT-LIMIT THRESHOLD (V)
MAX15046 toc10
80
LIM REFERENCE CURRENT
vs. TEMPERATURE
0.15
0.10
0.05
VOUT
200mV/div
SINK CURRENT LIMIT
0
-0.05
-0.10
SOURCE CURRENT LIMIT
-0.15
-0.20
IOUT
5A/div
-0.25
-0.30
-0.35
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
RESISTANCE (kΩ)
LOAD TRANSIENT ON OUT (1A TO 15A)
LOAD TRANSIENT ON OUT (1A TO 6A)
MAX15046 toc12b
200µs/div
STARTUP DISABLE FROM EN
(RLOAD = 3.3Ω) (MAX15046A/B)
MAX15046 toc12c
VOUT
200mV/div
MAX15046 toc13
IN
20V/div
VOUT
100mV/div
EN
5V/div
IOUT
5A/div
VOUT
2V/div
IOUT
5A/div
PGOOD
5V/div
200µs/div
200µs/div
4ms/div
STARTUP AND DISABLE FROM IN
(RLOAD = 3.3kΩ)
STARTUP WITH PREBIASED
OUTPUT (4.0V)
STARTUP WITH PREBIASED
OUTPUT (1.0V)
MAX15046 toc14
MAX15046 toc15a
IN
10V/div
VOUT
2V/div
PGOOD
5V/div
20ms/div
www.maximintegrated.com
4ms/div
MAX15046 toc15b
24V
24V
IN
10V/div
IN
10V/div
4V
1V
VOUT
2V/div
VOUT
2V/div
PGOOD
5V/div
PGOOD
5V/div
4ms/div
Maxim Integrated │ 6
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Typical Operating Characteristics (continued)
(VIN = 24V, TA = +25°C, unless otherwise noted.)
STARTUP WITH PREBIASED
OUTPUT (2V)
MAX15046 toc15c
VOUT = 3.3V
SINK CURRENT-LIMIT WAVEFORMS
(5V PREBIASED)
STARTUP WITH PREBIASED
OUTPUT (0.5V)
MAX15046 toc16
MAX15046 toc15d
24V
24V
IN
10V/div
VIN
10V/div
2V
0.5V
VOUT
2V/div
VOUT
2V/div
PGOOD
5V/div
PGOOD
5V/div
VOUT
500mV/div
VLX
50V/div
ILX
5A/div
VOUT = 3.3V
4ms/div
200µs/div
4ms/div
BREAK-BEFORE-MAKE TIME
(DH_ FALLING TO DL_ RISING)
BREAK-BEFORE-MAKE TIME
(DL_ FALLING TO DH_ RISING)
MAX15046 toc17a
MAX15046 toc17b
VDH
20V/div
VDH
20V/div
VDL
5V/div
VDL
5V/div
VLX
20V/div
VLX
20V/div
40ns/div
40ns/div
OUTPUT SHORT-CIRCUIT BEHAVIOR
LINE-TRANSIENT RESPONSE
MAX15046 toc18
MAX15046 toc19
24V
VIN
10V/div
VOUT
200mV/div
5V
IOUT
10A/div
VOUT
(AC-COUPLED)
200mV/div
10ms/div
www.maximintegrated.com
10ms/div
Maxim Integrated │ 7
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Pin Description
PIN
NAME
1
IN
Regulator Input. Connect to the input rail of the buck converter. Bypass IN to PGND with a 100nF
minimum ceramic capacitor. When operating in the 5V ±10% range, connect IN to VCC.
2
VCC
5.25V Linear Regulator Output. Bypass VCC to PGND with a ceramic capacitor of at least 4.7µF
when VCC supplies MOSFET gate-driver current at DRV or 2.2µF when VCC is not used to power
DRV.
3
PGOOD
4
EN
Active-High Enable Input. Pull EN to GND to disable the buck converter output. Connect to VCC for
always-on operation. EN can be used for power sequencing and as a UVLO adjustment input.
5
LIM
Current-Limit Input. Connect a resistor from LIM to GND to program the current-limit threshold from
30mV (RLIM = 6kΩ) to 300mV (RLIM = 60kΩ).
6
COMP
Error-Amplifier Output. Connect compensation network from COMP to FB or from COMP to GND.
7
FB
Feedback Input (Inverting Input of Error Amplifier). Connect FB to a resistive divider between the
buck converter output and GND to adjust the output voltage from 0.6V up to 0.85 x IN.
8
RT
Oscillator-Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency
from 100kHz to 1MHz.
9
GND
10
PGND
11
DRV
12
DL
13
BST
14
LX
Inductor Connection. Also serves as a return terminal for the high-side MOSFET driver current.
Connect LX to the switching side of the inductor.
15
DH
High-Side External MOSFET Gate-Driver Output. DH swings from BST to LX.
16
CSP
Current-Sense Positive Input. Connect to the drain of low-side MOSFET with Kelvin connection.
—
EP
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FUNCTION
Open-Drain Power-Good Output. Pull up PGOOD to an external power supply or output with an
external resistor.
Analog Ground. Connect PGND and AGND together at a single point.
Power Ground. Use PGND as a return path for the low-side MOSFET gate driver.
Gate-Driver Supply Voltage. DRV is internally connected to the low-side driver supply. Bypass DRV to
PGND with a 2.2µF minimum ceramic capacitor (see the Typical Application Circuits).
Low-Side External MOSFET Gate-Driver Output. DL swings from DRV to PGND.
Boost Flying Capacitor Connection. Internally connected to the high-side driver supply. Connect a
ceramic capacitor of at least 100nF between BST and LX and a diode between BST and DRV for
the high-side MOSFET gate-driver supply.
Exposed Pad. Connect EP to a large copper ground plane to maximize thermal performance.
Maxim Integrated │ 8
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Functional Diagram
VREF
OSCILLATOR
RT
FB
HICCUP
CK
SOFT-START/STOP
AND
HICCUP
LOGIC
VREF
EN
CK
OSC ENABLE
ENABLE
COMPARATOR
GM
COMP
DAC_VREF
HICCUP TIMEOUT
ENABLE
DH_DL_ENABLE
EN_INT
PWM
COMPARATOR
VREF
BGAP_OK
V_BGAP
VIN_OK
V_BGAP
VCC
BGAP_OK
BGAP_OK
V_DRV
VIN_OK
LIM
IN
BANDGAP
OK
GENERATOR
VREF
RAMP
BST
INTERNAL
VOLTAGE
REGULATOR
VCC
UVLO
PWM
RAMP GENERATOR
CK
BGAP_OK
CK
DC-DC
OSCILLATOR
AND
ENABLE
LOGIC
DH_DL_ENABLE
PWM
CONTROL
LOGIC
HIGHSIDE
DRIVER
HICCUP
DH
LX
HICCUP TIMEOUT
VL_OK
CSP
DRV
DRV
UVLO
THERMAL
SHUTDOWN
AND ILIM
CURRENT
GENERATOR
IN
UVLO
SINK
CURRENT-LIMIT
COMPARATOR
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LIM/20
DL
PGND
SHUTDOWN
FB
ENABLE
VALLEY
CURRENT-LIMIT
COMPARATOR
VIN_OK
VIN_OK
IBIAS
MAX15046
LOWSIDE
DRIVER
VDRV_OK
VREF = 0.6V
VBGAP = 1.24V
MAIN
BIAS
CURRENT
GENERATOR
PGOOD
LIM/10
VREF
PGOOD
COMPARATOR
GND
BANDGAP
REFERENCE
Maxim Integrated │ 9
MAX15046
Detailed Description
The MAX15046 synchronous step-down controller operates from a 4.5V to 40V input-voltage range and generates an adjustable output voltage from 85% of the inputvoltage down to 0.6V while supporting loads up to 25A. As
long as the device supply voltage is within 5.0V to 5.5V,
the input power bus (VIN) can be as low as 3.3V.
The MAX15046 offers adjustable switching frequency
from 100kHz to 1MHz with an external resistor. The
adjustable switching frequency provides design flexibility
in selecting passive components. The MAX15046 adopts
an adaptive synchronous rectification to eliminate external freewheeling Schottky diodes and improve efficiency.
The device utilizes the on-resistance of the external lowside MOSFET as a current-sense element. The currentlimit threshold voltage is resistor-adjustable from 30mV
to 300mV and is temperature-compensated, so that the
effects of the MOSFET RDS(ON) variation over temperature are reduced. This current-sensing scheme protects
the external components from damage during output
overloaded conditions or output short-circuit faults without
requiring a current-sense resistor. Hiccup-mode current
limit reduces power dissipation during short-circuit conditions. The MAX15046 includes a power-good output and
an enable input with precise turn-on/-off threshold to be
used for monitoring and for power sequencing.
The MAX15046 features internal digital soft-start that
allows prebias startup without discharging the output. The
digital soft-start function employs sink current limiting to
prevent the regulator from sinking excessive current when
the prebias voltage exceeds the programmed steady-state
regulation level. The digital soft-start feature prevents the
synchronous rectifier MOSFET and the body diode of the
high-side MOSFET from experiencing dangerous levels
of current while the regulator is sinking current from the
output. The MAX15046 shuts down at a +150°C junction
temperature to prevent damage to the device.
DC-DC PWM Controller
The MAX15046 step-down controller uses a PWM voltage-mode control scheme (see the Functional Diagram).
Control-loop compensation is external for providing maximum flexibility in choosing the operating frequency and
output LC filter components. An internal transconductance error amplifier produces an integrated error voltage
at COMP that helps to provide higher DC accuracy. The
voltage at COMP sets the duty cycle using a PWM comparator and a ramp generator. On the rising edge of an
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40V, High-Performance, Synchronous
Buck Controller
internal clock, the high-side n-channel MOSFET turns on,
and remains on, until either the appropriate duty cycle or
the maximum duty cycle is reached. During the on-time
of the high-side MOSFET, the inductor current ramps
up. During the second-half of the switching cycle, the
high-side MOSFET turns off and the low-side n-channel
MOSFET turns on. The inductor releases the stored
energy as the inductor current ramps down, providing current to the output. Under overload conditions, when the
inductor current exceeds the selected valley current-limit
threshold (see the Current-Limit Circuit (LIM) section), the
high-side MOSFET does not turn on at the subsequent
clock rising edge and the low-side MOSFET remains on
to let the inductor current ramp down.
Internal 5.25V Linear Regulator
An internal linear regulator (VCC) provides a 5.25V nominal supply to power the internal functions and to drive the
low-side MOSFET. Connect IN and VCC together when
using an external 5V ±10% power supply. The maximum
regulator input voltage (VIN) is 40V. Bypass IN to GND
with a 1µF ceramic capacitor. Bypass the output of the
linear regulator (VCC) with a 4.7µF ceramic capacitor
to GND. The VCC dropout voltage is typically 180mV.
When VIN is higher than 5.5V, VCC is typically 5.25V. The
MAX15046 also employs an undervoltage lockout circuit
that disables the internal linear regulator when VCC falls
below 3.6V (typical). The 400mV UVLO hysteresis prevents chattering on power-up/power-down.
MOSFET Gate Drivers (DH, DL)
DH and DL are optimized for driving large-size n-channel
power MOSFETs. Under normal operating conditions and
after startup, the DL low-side drive waveform is always
the complement of the DH high-side drive waveform,
with controlled dead time to prevent crossconduction or
“shoot-through.” An adaptive dead-time circuit monitors
the DH and DL outputs and prevents the opposite-side
MOSFET from turning on until the MOSFET is fully off.
Thus, the circuit allows the high-side driver to turn on only
when the DL gate driver has turned off and prevents the
low side (DL) from turning on until the DH gate driver has
turned off.
The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from DL and DH to
the MOSFET gates for the adaptive dead-time circuits
to function properly. The stray impedance in the gate
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MAX15046
40V, High-Performance, Synchronous
Buck Controller
discharge path can cause the sense circuitry to interpret
the MOSFET gate as “off” while the VGS of the MOSFET
is still high. To minimize stray impedance, use very short,
wide traces.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch. The
MAX15046 features a robust internal pulldown transistor
with a typical 1Ω RDS(ON) to drive DL low. This low onresistance prevents DL from being pulled up during the
fast rise time of the LX node, due to capacitive coupling
from the drain to the gate of the low-side synchronous
rectifier MOSFET.
High-Side Gate-Drive Supply (BST)
An external Schottky diode between BST and DH is
required to boost the gate voltage above LX providing the
necessary gate-to-source voltage to turn on the high-side
MOSFET. The boost capacitor connected between BST
and LX holds up the voltage across the gate driver during
the high-side MOSFET on-time.
UVLO
A
B
C
D
E
The charge lost in the boost capacitor for delivering the
gate charge is replenished when the high-side MOSFET
turns off and the LX node goes to ground. When LX is
low, the external diode between VDRV and BST recharges
the boost capacitor. See the Boost Capacitor and Diode
Selection sections in Applications Information to choose
the right boost capacitor and diode.
Enable Input (EN), Soft-Start, and Soft-Stop
Drive EN high to turn on the MAX15046. A soft-start
sequence starts to increase (step-wise) the reference
voltage of the error amplifier. The duration of the softstart ramp is 2048 switching cycles and the resolution
is 1/64th of the steady-state regulation voltage allowing
a smooth increase of the output voltage. A logic-low on
EN initiates a soft-stop sequence by stepping down the
reference voltage of the error amplifier. Once the soft-stop
sequence is completed, the MOSFET drivers are both
turned off. See Figure 1. Soft-stop operation is disabled
for the MAX15046C.
Connect EN to VCC for always-on operation. Owing to
the accurate turn-on/-off thresholds, EN can be used
as a UVLO adjustment input, and for power sequencing
together with the PGOOD outputs.
F
G
H
I
VCC
EN
VOUT
2048 CLOCK
CYCLES
2048 CLOCK
CYCLES
DAC_VREF
DH
DL
SYMBOL
UVLO
VCC
EN
VOUT
DAC_VREF
DH
DL
A
DEFINITION
SYMBOL
Undervoltage threshold value is provided in
the Electrical Characteristics table.
Internal 5.25V linear regulator output.
Active-high enable input.
Regulator output voltage.
Regulator internal soft-start and soft-stop signal.
Regulator high-side gate-driver output.
Regulator low-side gate-driver output.
B
VCC is higher than the UVLO threshold. EN is low.
C
EN is pulled high. DH and DL start switching.
Normal operation.
VCC drops below UVLO.
VCC goes above the UVLO threshold. DH and DL
start switching. Normal operation.
VCC rising while below the UVLO threshold.
EN is low.
D
E
F
DEFINITION
G
EN is pulled low. VOUT enters soft-stop.
H
EN is pulled high. DH and DL start switching.
Normal operation.
VCC drops below UVLO.
I
Figure 1. Power On-Off Sequencing
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Maxim Integrated │ 11
MAX15046
When the valley current limit is reached during soft-start,
the MAX15046 regulates to the output impedance times
the limited inductor current and turns off after 4096 clock
cycles. When starting up into a large capacitive load (for
example), the inrush current will not exceed the currentlimit value. If the soft-start is not completed before 4096
clock cycles, the device turns off. The device remains off
for 8192 clock cycles before trying to soft-start again. This
implementation allows the soft-start time to be automatically adapted to the time necessary to keep the inductor
current below the limit while charging the output capacitor.
Power-Good Output (PGOOD)
The MAX15046 includes a power-good comparator to
monitor the output voltage and detect the power-good
threshold, fixed at 93% of the nominal FB voltage. The
open-drain PGOOD output requires an external pullup
resistor. PGOOD sinks up to 2mA of current while low.
PGOOD goes high (high-Z) when the regulator output
increases above 93% of the designed nominal regulated
voltage. PGOOD goes low when the regulator output voltage drops to below 90% of the nominal regulated voltage.
PGOOD asserts low during the hiccup timeout period.
Startup into a Prebiased Output
When the MAX15046 starts into a prebiased output, DH
and DL are off so that the converter does not sink current
from the output. DH and DL do not start switching until
the PWM comparator commands the first PWM pulse.
The first PWM pulse occurs when the ramping reference
voltage increases above the FB voltage.
When the output voltage is biased above the output set
point, the controller tries to pull the output down to the
set point once the internal soft-start is complete. This
pulldown is controlled by the sink current limit, which is
slowly increased to its normal value to minimize output
undershoot.
Current-Limit Circuit (LIM)
The current-limit circuit employs a ‘valley’ and sink
current-sensing algorithm that uses the on-resistance
of the low-side MOSFET as a current-sensing element
to eliminate costly sense resistors. The current-limit
circuit is also temperature-compensated to track the onresistance variation of the MOSFET overtemperature.
The current limit is adjustable with an external resistor at
LIM and accommodates MOSFETs with a wide range of
on-resistance characteristics (see the Setting the Valley
Current Limit section). The adjustment range is from 0.3V
to 3V for the valley current limit, corresponding to resistor
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40V, High-Performance, Synchronous
Buck Controller
values of 6kΩ to 60kΩ. The valley current-limit threshold
across the low-side MOSFET is precisely 1/10th of the
voltage at LIM, while the sink current-limit threshold is
1/20th of the voltage at LIM.
Valley current limit acts when the inductor current flows
towards the load, and CSP is more negative than PGND
during the low-side MOSFET on-time. If the magnitude of
the current-sense signal exceeds the valley current-limit
threshold at the end of the low-side MOSFET on-time, the
MAX15046 does not initiate a new PWM cycle and lets
the inductor current decay in the next cycle. The controller also ‘rolls back’ the internal reference voltage so that
the controller finds a regulation point determined by the
current-limit value and the resistance of the short. In this
manner, the controller acts as a constant current source.
This method greatly reduces inductor ripple current during
the short event, which reduces inductor sizing restrictions
and reduces the possibility for audible noise. After 4096
clock cycles, the device goes into hiccup mode. Once the
short is removed, the internal reference voltage soft-starts
back up to the normal reference voltage and regulation
continues.
Sink current limit is implemented by monitoring the voltage drop across the low-side MOSFET when CSP is more
positive than PGND. When the voltage drop across the
low-side MOSFET exceeds 1/20th of the voltage at LIM
at any time during the low-side MOSFET on-time, the
low-side MOSFET turns off and the inductor current flows
from the output through the body diode of the high-side
MOSFET. When the sink current limit activates, the DH/
DL switching sequence is no longer complementary and
both MOSFETs are turned off.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals at CSP and PGND. Mount the MAX15046 close
to the low-side MOSFET with short, direct traces making
a Kelvin-sense connection so that trace resistance does
not add to RDS(ON) of the low-side MOSFET.
Hiccup Mode Overcurrent Protection
Hiccup mode overcurrent protection reduces power dissipation during prolonged short-circuit or severe overload
conditions. An internal 3-bit counter counts up on each
switching cycle when the valley current-limit threshold
is reached. The counter counts down on each switching
cycle when the threshold is not reached, and stops at zero
(000). When the current-limit condition persists and the
counter reaches 111 (= 7 events), the MAX15046 stops
both DL and DH drivers and waits for 4096 switching
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MAX15046
40V, High-Performance, Synchronous
Buck Controller
cycles (hiccup timeout delay) before attempting a new
soft-start sequence. The hiccup-mode protection remains
active during the soft-start time.
Undervoltage Lockout
The maximum voltage conversion ratio is limited by the
maximum duty cycle (Dmax):
VOUT
D
× VDROP2 + (1-D max ) × VDROP1
< D max - max
VIN
VIN
The MAX15046 provides an internal undervoltage lockout
(UVLO) circuit to monitor the voltage on VCC. The UVLO
circuit prevents the MAX15046 from operating when VCC
is lower than VUVLO. The UVLO threshold is 4V, with
400mV hysteresis to prevent chattering on the rising/
falling edge of the supply voltage. DL and DH stay low
to inhibit switching when the device is in undervoltage
lockout.
where VDROP1 is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous rectifier, inductor, and PCB resistance. VDROP2 is the sum of
the voltage drops by the resistance in the charging path,
including high-side switch, inductor, and PCB resistance.
In practice, provide adequate margin to the above conditions for good load-transient response.
Thermal-Overload Protection
Setting the Output Voltage
Thermal-overload protection limits total power dissipation
in the MAX15046. When the junction temperature of the
device exceeds +150°C, an on-chip thermal sensor shuts
down the device, forcing DL and DH low, which allows
the device to cool. The thermal sensor turns the device
on again after the junction temperature cools by 20°C.
The regulator shuts down and soft-start resets during
thermal shutdown. Power dissipation in the LDO regulator
and excessive driving losses at DH/DL trigger thermaloverload protection. Carefully evaluate the total power
dissipation (see the Power Dissipation section) to avoid
unwanted triggering of the thermal-overload protection in
normal operation.
Set the MAX15046 output voltage by connecting a resistive divider from the output to FB to GND (Figure 2). When
using Type II compensation, select R2 from between 4kΩ
and 16kΩ. Calculate R1 with the following equation:
V
R 1 = R 2 OUT -1
VFB
where VFB = 0.59V (see the Electrical Characteristics
table) and VOUT can range from 0.6V to (0.85 x VIN).
When using Type III compensation, calculate the values
of R1 and R2 as shown in the Type III Compensation
Network (Figure 4) section.
Applications Information
OUT
Effective Input-Voltage Range
The MAX15046 operates from 4.5V to 40V input supplies
and regulates output down to 0.6V. The minimum voltage
conversion ratio (VOUT/VIN) is limited by the minimum
controllable on-time. For proper fixed-frequency PWM
operation, the voltage conversion ratio must obey the following condition:
VOUT
> t ON(MIN) × f SW
VIN
where tON(MIN) is 125ns and fSW is the switching frequency in Hertz. Pulse skipping occurs to decrease the
effective duty cycle when the desired voltage conversion
does not meet the above condition. Decrease the switching frequency or lower the input voltage VIN to avoid pulse
skipping.
www.maximintegrated.com
R1
FB
MAX15046
R2
Figure 2. Adjustable Output Voltage
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40V, High-Performance, Synchronous
Buck Controller
Setting the Switching Frequency
An external resistor connecting RT to GND sets the
switching frequency (fSW). The relationship between fSW
and RRT is:
15.14 × 10 9
RRT =
f SW + (1 x 10 -7 ) (f SW 2 )
where fSW is in Hz and RRT is in Ω. For example, a
300kHz switching frequency is set with RRT = 49.9kΩ.
Higher frequencies allow designs with lower inductor
values and less output capacitance. Peak currents and
I2R losses are lower at higher switching frequencies, but
core losses, gate-charge currents, and switching losses
increase.
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX15046: inductance value (L), inductor
saturation current (ISAT), and DC resistance (RDC). To
determine the inductance, select the ratio of inductor
peak-to-peak AC current to DC average current (LIR) first.
For LIR values that are too high, the RMS currents are
high, and, therefore, I2R losses are high. Use high-valued
inductors to achieve low LIR values. Typically, inductor
resistance is proportional to inductance for a given package type, which again makes I2R losses high for very low
LIR values. A good compromise between size and loss
is a 30% peak-to-peak ripple current to average-current
ratio (LIR = 0.3). The switching frequency, input voltage,
output voltage, and selected LIR determine the inductor
value as follows:
L=
VOUT (VIN - VOUT )
VIN × f SW × I OUT × LIR
where VIN, VOUT, and IOUT are typical values. The
switching frequency is set by RT (see Setting the
Switching Frequency section). The exact inductor value is
not critical and can be adjusted to make trade-offs among
size, cost, and efficiency. Lower inductor values minimize
size and cost, but also improve transient response and
reduce efficiency due to higher peak currents. On the
other hand, higher inductance increases efficiency by
reducing the RMS current.
Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. The saturation
current rating (ISAT) must be high enough to ensure that
saturation cannot occur below the maximum current-limit
value (ICL(MAX)), given the tolerance of the on-resistance
of the low-side MOSFET and of the LIM reference current
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(ILIM). Combining these conditions, select an inductor
with a saturation current (ISAT) of:
ISAT ≥ 1.35 ×ICL(TYP)
where ICL(TYP) is the typical current-limit set point. The
factor 1.35 includes RDS(ON) variation of 25% and 10%
for the LIM reference current error. A variety of inductors
from different manufacturers are available to meet this
requirement (for example, Vishay IHLP-4040DZ-1-5 and
other inductors from the same series).
Setting the Valley Current Limit
The minimum current-limit threshold must be high enough
to support the maximum expected load current with the
worst-case low-side MOSFET on-resistance value as the
RDS(ON) of the low-side MOSFET is used as the currentsense element. The inductor’s valley current occurs at
ILOAD(MAX) minus one half of the ripple current. The minimum value of the current-limit threshold voltage (VITH)
must be higher than the voltage on the low-side MOSFET
during the ripple-current valley,
LIR
VITH > R DS(ON,MAX) × ILOAD(MAX) × 1 −
2
where RDS(ON,MAX) in Ω is the maximum on-resistance
of the low-side MOSFET at maximum load current
ILOAD(MAX) and is calculated from the following equation:
R DS(ON,MAX)
= R DS(ON) ×
[1 + TC MOSFET × (TMAX - T AMB )]
where RDS(ON) (in Ω is the on-resistance of the lowside MOSFET at ambient temperature TAMB (in degrees
Celsius), TCMOSFET is the temperature coefficient of
the low-side MOSFET in ppm/°C, and TMAX (in degrees
Celsius) is the temperature at maximum load current
ILOAD(MAX). Obtain the RDS(ON) and TCMOSFET from
the MOSFET data sheet.
Connect an external resistor (RLIM) from LIM to GND
to adjust the current-limit threshold, which is temperature-compensated with a temperature coefficient of
2300ppm/°C. The relationship between the current-limit
threshold (VITH) and RLIM is:
R LIM =
10 × VITH
ppm
50 × 10 -6 × 1 + 2300
× (TMAX - T AMB)
°C
where RLIM is in Ω, VITH is in V, TMAX and TAMB are in
°C.
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40V, High-Performance, Synchronous
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An RLIM resistance range of 6kΩ to 60kΩ corresponds to
a current-limit threshold of 30mV to 300mV. Use 1% tolerance resistors when adjusting the current limit to minimize
error in the current-limit threshold.
Input Capacitor
The input filter capacitor reduces peak current drawn from
the power source and reduces noise and voltage ripple
on the input caused by the switching circuitry. The input
capacitor must meet the ripple current requirement (IRMS)
imposed by the switching currents as defined by the following equation:
IRMS = ILOAD(MAX)
VOUT (VIN - VOUT )
VIN
IRMS attains a maximum value when the input voltage equals twice the output voltage (VIN = 2VOUT),
so IRMS(MAX) = ILOAD(MAX)/2. For most applications,
nontantalum capacitors (ceramic, aluminum, polymer, or
OS-CON) are preferred at the inputs due to the robustness of nontantalum capacitors to accommodate high
inrush currents of systems being powered from very low
impedance sources. Additionally, two (or more) smallervalue low-ESR capacitors should be connected in parallel
to reduce high-frequency noise.
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple voltage, and transient response. The output ripple has two
components: variations in the charge stored in the output
capacitor, and the voltage drop across the capacitor’s ESR
caused by the current flowing into and out of the capacitor:
ΔVRIPPLE = ΔVESR + ΔVQ
The output-voltage ripple as a consequence of the ESR
and the output capacitance is:
∆VESR =IP-P × ESR
I
∆VQ = P-P
8 × C OUT × f SW
V - VOUT VOUT
IP-P IN
=
×
f SW × L VIN
where IP-P is the peak-to-peak inductor current ripple
(see the Inductor Selection section). Use these equations
for initial capacitor selection. Decide on the final values by
testing a prototype or an evaluation circuit.
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Check the output capacitor against load-transient
response requirements. The allowable deviation of the
output voltage during fast load transients determines the
capacitor output capacitance, ESR, and equivalent series
inductance (ESL). The output capacitor supplies the load
current during a load step until the controller responds
with a higher duty cycle. The response time (tRESPONSE)
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the ESR of the output capacitor, the voltage
drop across the ESL (ΔVESL) of the capacitor, and the
capacitor discharge, cause a voltage droop during the
load step.
Use a combination of low-ESR tantalum/aluminum electrolytic and ceramic capacitors for improved transient load
and voltage ripple performance. Nonleaded capacitors
and capacitors in parallel help reduce the ESL. Keep the
maximum output-voltage deviation below the tolerable
limits of the load. Use the following equations to calculate
the required ESR, ESL, and capacitance value during a
load step:
ESR =
∆VESR
I STEP
I
×t
C OUT = STEP RESPONSE
∆VQ
ESL =
∆VESL × t STEP
I STEP
t RESPONSE ≅
1
3 × fO
where ISTEP is the load step, tSTEP is the rise time of the
load step, tRESPONSE is the response time of the controller, and fO is the closed-loop crossover frequency.
Compensation Design
The MAX15046 provides an internal transconductance
amplifier with the inverting input and the output available for external frequency compensation. The flexibility
of external compensation offers wide selection of output
filtering components, especially the output capacitor.
Use high-ESR aluminum electrolytic capacitors for costsensitive applications. Use low-ESR tantalum or ceramic
capacitors at the output for size-sensitive applications. The
high switching frequency of the MAX15046 allows the use
of ceramic capacitors at the output. Choose all passive
power components to meet the output ripple, component
size, and component cost requirements. Choose the compensation components for the error amplifier to achieve
the desired closed-loop bandwidth and phase margin.
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MAX15046
40V, High-Performance, Synchronous
Buck Controller
To choose the appropriate compensation network type,
the power-supply poles and zeros, the zero-crossover
frequency, and the type of the output capacitor must be
determined first.
In a buck converter, the LC filter in the output stage introduces a pair of complex poles at the following frequency:
f PO =
1
2π × L OUT × C OUT
The output capacitor introduces a zero at:
f ZO =
1
2π × ESR × C OUT
where ESR is the equivalent series resistance of the output capacitor.
The loop-gain crossover frequency (fO), where the loop
gain equals 1 (0dB) should be set below 1/10th of the
switching frequency:
f
f O ≤ SW
10
Type II Compensation Network
(Figure 3)
If fZO is lower than fO and close to fPO, the phase lead of
the capacitor ESR zero almost cancels the phase loss of
one of the complex poles of the LC filter around the crossover frequency. Use a Type II compensation network with
a midband zero and a high-frequency pole to stabilize the
loop. In Figure 3, RF and CF introduce a midband zero
(fZ1). RF and CCF in the Type II compensation network
provide a high-frequency pole (fP1), which mitigates the
effects of the output high-frequency ripple.
Use the following steps to calculate the component values
for Type II compensation network as shown in Figure 3:
1) Calculate the gain of the modulator (GAINMOD),
comprised of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry at
crossover frequency:
VIN
V
ESR
GAINMOD =
×
× FB
VRAMP (2π × f O × L OUT ) VOUT
Choosing a lower crossover frequency reduces the
effects of noise pickup into the feedback loop, such as
jittery duty cycle.
where VIN is the input voltage of the regulator, VRAMP
is the amplitude of the ramp in the pulse-width modulator, VFB is the FB input voltage set point (0.6V typically,
see the Electrical Characteristics table), and VOUT is the
desired output voltage.
To maintain a stable system, two stability criteria must be
met:
The gain of the error amplifier (GAINEA) in midband frequencies is:
1) The phase shift at the crossover frequency, fO, must
be less than 180°. In other words, the phase margin of
the loop must be greater than zero.
GAINEA = gM x RF
2) The gain at the frequency where the phase shift is
-180° (gain margin) must be less than 1.
Maintain a phase margin of around 60° to achieve a
robust loop stability and well-behaved transient response.
When using an electrolytic or large-ESR tantalum output
capacitor, the capacitor ESR zero fZO typically occurs
between the LC poles and the crossover frequency fO
(fPO < fZO < fO). Choose the Type II (PI-Proportional,
Integral) compensation network.
When using a ceramic or low-ESR tantalum output
capacitor, the capacitor ESR zero typically occurs above
the desired crossover frequency fO, that is fPO < fO <
fZO. Choose the Type III (PID- Proportional, Integral, and
Derivative) compensation network.
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where gM is the transconductance of the error amplifier.
The total loop gain, which is the product of the modulator
gain and the error-amplifier gain at fO, is:
1) GAINMOD × GAINEA =
1
So :
VIN
V
ESR
×
× FB × g M × R F =
1
VOSC (2π × f O × L OUT ) VOUT
Solving for R F :
RF =
VOSC × (2π × f O × L OUT ) × VOUT
VFB × VIN × g M × ESR
2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel one
of the LC poles):
=
f Z1
1
= 0.75 × f PO
2π × R F × C F
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MAX15046
40V, High-Performance, Synchronous
Buck Controller
VOUT
1
C × C CF
2π × R F × F
C F + C CF
f P3 =
R1
COMP
gM
R2
VREF
RF
CF
CCF
Figure 3. Type II Compensation Network
Solving for CF:
CF =
1
2π × R F × f PO × 0.75
fP3 attenuates the high-frequency output ripple.
Place the zeros and poles such that the phase margin
peaks around fO.
Ensure that RF >> 2/gM and the parallel resistance of
R1, R2, and RI is greater than 1/gM. Otherwise, a 180N
phase shift is introduced to the response making the loop
unstable.
Use the following compensation procedures:
1) With RF >> 10kΩ, place the first zero (fZ1) at 0.8 x fPO:
So:
3) Place a high-frequency pole at fP1 = 0.5 x fSW (to
attenuate the ripple at the switching frequency fSW) and
calculate CCF using the following equation:
C CF =
1
1
π × R F × f SW CF
Type III Compensation Network (Figure 4)
When using a low-ESR tantalum or ceramic type, the
ESR-induced zero frequency is usually above the targeted zero crossover frequency (fO). Use Type III compensation. Type III compensation provides two zeros and three
poles at the following frequencies:
1
f Z1 =
2π × R F × C F
f Z2 =
1
2π × C I × (R 1 + R I )
Two midband zeros (fZ1 and fZ2) cancel the pair of complex poles introduced by the LC filter:
fP1 = 0
fP1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors:
f P2 =
1
2π × R I × C I
Depending on the location of the ESR zero (fZO), use fP2
to cancel fZO, or to provide additional attenuation of the
high-frequency output ripple:
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1
= 0.8 × f PO
2π × R F × C F
f=
Z1
CF =
1
2π × R F × 0.8 × f PO
2) The gain of the modulator (GAINMOD), comprised of
the pulse-width modulator, LC filter, feedback divider,
and associated circuitry at crossover frequency is:
GAIN
=
MOD
VIN
1
×
VRAMP (2π × f O ) 2 × L OUT × C OUT
The gain of the error amplifier (GAINEA) in midband
frequencies is:
GAINEA = 2π × f O × C I × R F
The total loop gain as the product of the modulator
gain and the error amplifier gain at fO is 1.
GAINMOD × GAINEA =
1
So :
IN
RAMP
×
(2π × f O ) × C OUT × L OUT
× 2π × f O × C I × R F = 1
Solving for C :
VRAMP × (2π × f O × L OUT × C OUT )
VIN × R F
3) Use the second pole (fP2) to cancel fZO when fPO <
fO < fZO < fSW/2. The frequency response of the loop
gain does not flatten out soon after the 0dB crossover,
Maxim Integrated │ 17
MAX15046
40V, High-Performance, Synchronous
Buck Controller
and maintains -20dB/decade slope up to 1/2 of the
switching frequency. This is likely to occur if the output
capacitor is low-ESR tantalum. Set fP2 = fZO.
When using a ceramic capacitor, the capacitor ESR zero
(fZO) is likely to be located even above one half of the
switching frequency, fPO < fO < fSW/2 < fZO. In this case,
place the frequency of the second pole (fP2) high enough
in order not to significantly erode the phase margin at the
crossover frequency. For example, set fP2 at 5 x fO so
that the contribution to phase loss at the crossover frequency fO is only about 11°:
fP2 = 5 x fO
Once fP2 is known, calculate RI:
RI =
1
2π × f P2 × C I
4) Place the second zero (fZ2) at 0.2 x fO or at fPO,
whichever is lower and calculate R1 using the following
equation:
R1 =
1
- RI
2π × f Z2 × C I
5) Place the third pole (fP3) at one half the switching frequency and calculate CCF:
C CF =
CF
(2π × 0.5 × f SW × R F × C F ) - 1
VFB
× R1
VOUT − VFB
RF
RI
VREF
Figure 4. Type III Compensation Network
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●● Total Gate Charge (QG)
●● Reverse Transfer Capacitance (CRSS)
●● Power Dissipation
The two n-channel MOSFETs must be a logic-level
type with guaranteed on-resistance specifications at
VGS = 4.5V. For maximum efficiency, choose a highside MOSFET that has conduction losses equal to the
switching losses at the typical input voltage. Ensure that
the conduction losses at minimum input voltage do not
exceed the MOSFET package thermal limits, or violate
the overall thermal budget. Also ensure that the conduction losses plus switching losses at the maximum input
voltage do not exceed package ratings or violate the
overall thermal budget. Ensure that the DL gate driver can
drive the low-side MOSFET. In particular, check that the
dv/dt caused by the high-side MOSFET turning on does
not pull up the low-side MOSFET gate through the drainto-gate capacitance of the low-side MOSFET, which is the
most frequent cause of crossconduction problems.
The MAX15046 uses a bootstrap circuit to generate the
necessary gate-to-source voltage to turn on the high-side
MOSFET. The selected n-channel high-side MOSFET
determines the appropriate boost capacitance value
(CBST in the Typical Application Circuits) according to the
following equation:
CF
CI
gM
●● Minimum Threshold Voltage (VTH(MIN))
Boost Capacitor and Diode Selection
R1
R2
●● On-resistance (RDS(ON))
●● Maximum Drain-to-Source Voltage (VDS(MAX))
PDRIVE = VCC x QG_TOTAL x fSW
where QG_TOTAL is the sum of the gate charges of the
two external MOSFETs.
CCF
VOUT
The MAX15046 step-down controller drives two external logic-level n-channel MOSFETs. The key selection
parameters to choose these MOSFETs include:
Check power dissipation when using the internal linear
regulator to power the gate drivers. Select MOSFETs with
low gate charge so that VCC can power both drivers without overheating the device:
6) Calculate R2 as:
=
R2
MOSFET Selection
COMP
C BST =
QG
∆VBST
where QG is the total gate charge of the high-side
MOSFET and ΔVBST is the voltage variation allowed
on the high-side MOSFET driver after turn-on. Choose
Maxim Integrated │ 18
MAX15046
40V, High-Performance, Synchronous
Buck Controller
ΔVBST such that the available gate-drive voltage is not
significantly degraded (e.g. ΔVBST = 100mV to 300mV)
when determining CBST.
Use a low-ESR ceramic capacitor as the boost capacitor
with a minimum value of 100nF.
A small-signal diode can be used for the bootstrap circuit
and must have a minimum voltage rating of VIN + 3V
to withstand the maximum BST voltage. The average
forward current of the diode should meet the following
requirement:
IF > QGATE x fSW
where QGATE is the gate charges of the high-side
MOSFET.
Power Dissipation
The maximum power dissipation of the device depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB copper
area, other thermal mass, and airflow.
The power dissipated into the package (PT) depends
on the supply configuration (see the Typical Application
Circuits). Use the following equation to calculate power
dissipation:
PT = VIN x [QG_TOTAL x fSW + IQ]
where IQ is the quiescent supply current at the switching
frequency. See the IIN vs. Switching Frequency graph in
the Typical Operating Characteristics for the IQ.
Use the following equation to estimate the temperature
rise of the die:
TJ = TA + (PT x θJA)
where θJA is the junction-to-ambient thermal impedance
of the package, PT is power dissipated in the device, and
TA is the ambient temperature. The θJA is 103.7°C/W
for the 16-pin QSOP and 44°C/W for the 16-pin QSOPEP package on multilayer boards, with the conditions
specified by the respective JEDEC standards (JESD51-5,
JESD51-7). An accurate estimation of the junction temperature requires a direct measurement of the case
temperature (TC) when actual operating conditions significantly deviate from those described in the JEDEC
standards. The junction temperature is then:
package. The case-to-ambient thermal impedance (θCA)
is dependent on how well the heat is transferred from the
PCB to the ambient. Use large copper areas to keep the
PCB temperature low.
PCB Layout Guidelines
Careful PCB layout is critical to achieve clean and stable
operation. The switching power stage requires particular
attention. Follow these guidelines for good PCB layout:
1) Place decoupling capacitors as close as possible to
the IC. Connect the power ground plane (connected to
PGND) and signal ground plane (connected to GND)
at one point near the device.
2) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal
ground plane.
3) Keep the high-current paths as short and wide as possible. Keep the path of switching current (C2 to IN and
C2 to PGND) short. Avoid vias in the switching paths.
4) Connect CSP to the drain of the low-side FET using a
Kelvin connection for accurate current-limit sensing.
5) Ensure all feedback connections are short and direct.
Place the feedback resistors as close as possible to
the IC.
6) Route high-speed switching nodes (BST, LX, DH, and
DL) away from sensitive analog areas (RT, FB, COMP,
and LIM).
24V Supply, 3.3V Output Operation
Typical Application Circuit 1 in the Typical Application
Circuits section shows an application circuit that operates
out of 24V and outputs up to 10A at 3.3V. R5 sets the
switching frequency to 350kHz.
Single 4.5V to 5.5V Supply Operation
Typical Application Circuit 2 in the Typical Application
Circuits section shows an application circuit for a single
+4.5V to +5.5V power-supply operation.
Auxiliary 5V Supply Operation
Typical Application Circuit 3 in the Typical Application
Circuits section shows an application circuit for a +24V
supply to drive the external MOSFETs and an auxiliary
+5V supply to power the device
TJ = TC + (PT x θJC)
Use 37°C/W as θJC thermal impedance for the 16-pin
QSOP package and 6°C/W for the 16-pin QSOP-EP
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Maxim Integrated │ 19
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Typical Application Circuits
TYPICAL APPLICATION CIRCUIT 1
VIN
+24V
C1
100µF
C2
10µF
C3
10µF
C4
0.1µF
C16
1µF
CSP
IN
R7
51kΩ
VCC
MAX15046
PGOOD
ON
Q1
LX
OFF
EN
BST
LIM
DL
C5
0.47µF
Q2
COMP
C13
68pF
R8
22.6kΩ
C14
1500pF
C15
15pF
FB
PGND
RT
GND
R5
43.2kΩ
R6
23.2kΩ
DRV
C12
220pF
R3
3.65kΩ
R1
10Ω
C8
100µF
C9
100µF
C10
47µF
C7
1000pF
D1
R9
32.4kΩ
VOUT
+3.3V
L1
1.5µH
DH
C6
2.2µF
R2
2.2Ω
C11
4.7µF
R4
105kΩ
Q1: VISHAY SILICONIX Si7850DP
Q2: VISHAY SILICONIX Si7460DP
D1: DIODES INC. ZHCS506
L1: VISHAY IHLP-4040PZ ER1R5M
C1: PANASONIC EEVFK1H101P
C8, C9: MURATA GRM31CR60J476K
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Maxim Integrated │ 20
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Typical Application Circuits (continued)
TYPICAL APPLICATION CIRCUIT 2
VIN
+4.5V TO +5.5V
C1
C2
CSP
IN
VCC
MAX15046
Q1
DH
PGOOD
PGOOD
ENABLE
EN
BST
LIM
DL
L1
LX
C3
VOUT
C4
Q2
C5
D1
R4
COMP
C7
R3
DRV
C6
C8
C9
R1
FB
PGND
RT
GND
R3
R2
TYPICAL APPLICATION CIRCUIT 3
VIN
+24V
VAUX
+4.5V TO +5.5V
C1
C2
CSP
IN
VCC
MAX15046
Q1
DH
PGOOD
PGOOD
ENABLE
EN
BST
LIM
DL
L1
LX
C3
Q2
VOUT
C4
C5
D1
R4
COMP
C7
R3
DRV
C6
C8
C9
R1
FB
PGND
RT
GND
R3
R2
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Maxim Integrated │ 21
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Pin Configurations
TOP VIEW
IN 1
+
IN 1
16 CSP
+
16 CSP
VCC 2
15 DH
VCC 2
15 DH
PGOOD 3
14 LX
PGOOD 3
14 LX
EN 4
MAX15046A
EN 4
13 BST
LIM 5
12 DL
LIM 5
COMP 6
11 DRV
FB 7
RT 8
MAX15046B
MAX15046C
FB 7
9
RT 8
GND
12 DL
11 DRV
COMP 6
10 PGND
13 BST
EXPOSED
PAD
10 PGND
9 GND
QSOP-EP
QSOP
Ordering Information
Package Information
PART
TEMP RANGE
PIN-PACKAGE
MAX15046AAEE+
-40°C to +125°C
16 QSOP
MAX15046BAEE+
-40°C to +125°C
16 QSOP-EP*
MAX15046CAEE+
-40°C to +125°C
16 QSOP-EP*
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
The MAX15046C is recommended for new designs.
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
16 QSOP
E16+4
21-0055
16 QSOP-EP
E16E+9
21-0055
Chip Information
PROCESS: BiCMOS
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Maxim Integrated │ 22
MAX15046
40V, High-Performance, Synchronous
Buck Controller
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
7/09
Initial release
1
2/10
Corrected Minimum Low-Side On-Time conditions in Electrical
Characteristics; corrected TOCs 2, 18, and 19; corrected MOSFET Gate
Drivers (DH, DL), Setting the Switching Frequency, Setting the Valley
Current Limit, MOSFET Selection, and Power Dissipation sections;
corrected Typical Application Circuit 1
2
1/13
Added MAX15046C
3
6/14
Modify the constant in the Rt/Fsw equation
DESCRIPTION
—
3, 5, 7, 10, 14, 15,
18, 19, 21
1, 3, 4, 6–8, 11
13, 14
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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