19-1357; Rev 1; 7/98
KIT
ATION
EVALU
E
L
B
AVAILA
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
____________________________Features
♦ 96% Efficiency
The MAX1652–MAX1655 achieve up to 96% efficiency
and deliver up to 10A using a unique Idle Mode™ synchronous-rectified PWM control scheme. These devices
automatically switch between PWM operation at heavy
loads and pulse-frequency-modulated (PFM) operation
at light loads to optimize efficiency over the entire output current range. The MAX1653/MAX1655 also feature
logic-controlled, forced PWM operation for noise-sensitive applications.
All devices operate with a selectable 150kHz/300kHz
switching frequency, which can also be synchronized
to an external clock signal. Both external power switches are inexpensive N-channel MOSFETs, which provide
low resistance while saving space and reducing cost.
The MAX1652 and MAX1654 have an additional feedback pin that permits regulation of a low-cost second
output tapped from a transformer winding. The
MAX1652 provides an additional positive output. The
MAX1654 provides an additional negative output.
The MAX1652–MAX1655 have a 4.5V to 30V input voltage range. The MAX1652/MAX1653/MAX1654’s output
range is 2.5V to 5.5V while the MAX1655’s output range
extends down to 1V. An evaluation kit (MAX1653EVKIT)
is available to speed designs.
♦ 170µA Quiescent Supply Current
♦ Small, 16-Pin QSOP Package
(half the size of a 16-pin narrow SO)
♦ Pin-Compatible with MAX797 (MAX1653/MAX1655)
♦ Output Voltage Down to 1V (MAX1655)
♦ 4.5V to 30V Input Range
♦ 99% Duty Cycle for Lower Dropout
♦ 3µA Logic-Controlled Shutdown
♦ Dual, N-Channel, Synchronous-Rectified Control
♦ Fixed 150kHz/300kHz PWM Switching,
or Synchronized from 190kHz to 340kHz
♦ Programmable Soft Start
♦ Low-Cost Secondary Outputs (MAX1652/MAX1654)
Ordering Information
TEMP. RANGE
PIN-PACKAGE
MAX1652EEE
PART
-40°C to +85°C
16 QSOP
MAX1653ESE
-40°C to +85°C
16 Narrow SO
MAX1653EEE
-40°C to +85°C
16 QSOP
MAX1654EEE
-40°C to +85°C
16 QSOP
MAX1655ESE
-40°C to +85°C
16 Narrow SO
MAX1655EEE
-40°C to +85°C
16 QSOP
Selection Guide
Applications
Notebook Computers
PART
FEEDBACK
VOLTAGE (V)
MAX1652
2.5
Regulates positive Same pin order
secondary voltage as MAX796, but
(such as +12V)
smaller package
MAX1653
2.5
Logic-controlled, Pin-compatible
low-noise mode with MAX797
MAX1654
2.5
Regulates negative Same pin order
secondary voltage as MAX799, but
(such as -5V)
smaller package
PDAs
Cellular Phones
Hand-Held Computers
Handy-Terminals
Mobile Communicators
Distributed Power
Pin Configurations appear at end of data sheet.
Idle Mode is a trademark of Maxim Integrated Products.
MAX1655
1
SPECIAL
FEATURE
Low output voltages (1V to 5.5V);
logic-controlled,
low-noise mode
COMPATIBILITY
Pin compatible
with MAX797
(except for feedback voltage)
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX1652–MAX1655
General Description
The MAX1652–MAX1655 are high-efficiency, pulsewidth-modulated (PWM), step-down DC-DC controllers
in small QSOP packages. The MAX1653/MAX1655 also
come in 16-pin narrow SO packages that are pincompatible upgrades to the popular MAX797. Improvements include higher duty-cycle operation for better
dropout, lower quiescent supply currents for better
light-load efficiency, and an output voltage down to 1V
(MAX1655).
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +36V
GND to PGND .......................................................-0.3V to +0.3V
VL to GND ................................................................-0.3V to +6V
BST to GND ............................................................-0.3V to +36V
DH to LX .....................................................-0.3V to (BST + 0.3V)
LX to BST..................................................................-6V to +0.3V
SHDN to GND...............................................-0.3V to (V+ + 0.3V)
SYNC, SS, REF, SECFB, SKIP, FB to GND...-0.3V to (VL + 0.3V)
DL to PGND ..................................................-0.3V to (VL + 0.3V)
CSH, CSL to GND ....................................................-0.3V to +6V
VL Short Circuit to GND..............................................Momentary
REF Short Circuit to GND ...........................................Continuous
VL Output Current ...............................................+50mA to -1mA
REF Output Current...............................................+5mA to -1mA
Continuous Power Dissipation (TA = +70°C)
SO (derate 8.70mW/°C above +70°C) .......................696mW
QSOP (derate 8.3mW/°C above +70°C) ....................667mW
Operating Temperature Range
MAX165_E_E ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
30
V
3.3V AND 5V STEP-DOWN CONTROLLERS
Input Supply Range
4.5
5V Output Voltage (CSL)
0 < (CSH - CSL) < 80mV, FB = VL, 6V < V+ < 30V,
includes line and load regulation
4.85
5.06
5.25
V
3.3V Output Voltage (CSL)
0 < (CSH - CSL) < 80mV, FB = 0V, 4.5V < V+ < 30V,
includes line and load regulation
3.20
3.34
3.46
V
Nominal Adjustable Output
Voltage Range
External resistor divider
Feedback Voltage
CSH - CSL = 0V, CSL = FB,
SKIP = 0V, 4.5V < V+ < 30V
MAX1655
Load Regulation
Line Regulation
1
5.5
MAX1652/MAX1653/
MAX1654
2.5
5.5
MAX1655
0.97
1.00
1.03
MAX1652/MAX1653/
MAX1654
2.43
2.50
2.57
0 < (CSH - CSL) < 80mV
2
25mV < (CSH - CSL) < 80mV
0.03
0.06
CSH - CSL, positive
80
100
120
CSH - CSL, negative
-50
-100
-160
SS Source Current
VSS = 0V
2.5
4.0
6.5
SS Fault Sink Current
VSS = 4V
2.0
Falling edge, rising edge, hysteresis = 22mV (MAX1652)
2.45
2.50
2.55
Rising edge, falling edge, hysteresis = 22mV (MAX1654)
-0.05
0
0.05
Current-Limit Voltage
V
%
1.2
6V < V+ < 30V
V
%/V
mV
µA
mA
FLYBACK/PWM CONTROLLER
SECFB Regulation Setpoint
V
INTERNAL REGULATOR AND REFERENCE
VL Output Voltage
SHDN = 2V, 0 < IVL < 25mA, 5.5V < V+ < 30V
4.7
5.0
5.3
V
VL Fault Lockout Voltage
Rising edge, falling edge hysteresis = 50mV
3.8
3.9
4.0
V
VL/CSL Switchover Voltage
Rising edge, falling edge hysteresis = 60mV
4.2
4.5
4.7
V
2
_______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
(V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA = 0°C to +85°C, unless otherwise noted.)
MIN
TYP
MAX
UNITS
Reference Output Voltage
PARAMETER
No external load (Note 1)
CONDITIONS
2.46
2.50
2.54
V
Reference Fault Lockout Voltage
Falling edge
2.0
Reference Load Regulation
0 < IREF < 100µA
CSL, CSH Shutdown Leakage
Current
SHDN = 0V, CSL = 5.5V, CSH = 5.5V, V+ = 0 or 30V,
VL = 0V
V+ Shutdown Current
SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V
V+ Off-State Leakage Current
FB = CSH = CSL = 5.5V, VL switched over to CSL
Dropout Power Consumption
Quiescent Power Consumption
2.4
V
5
15
mV
0.1
1
µA
3
7
µA
5
15
µA
V+ = 4.5V, CSH = CSL = 4.0V (Note 2)
1
8
mW
CSH = CSL = 5.5V
1
2
mW
OSCILLATOR AND INPUTS/OUTPUTS
Oscillator Frequency
SYNC = REF
270
300
330
SYNC = 0 or 5V
125
150
175
kHz
SYNC High Pulse Width
200
ns
SYNC Low Pulse Width
200
ns
SYNC Rise/Fall Time
Guaranteed by design, not tested
Oscillator Sync Range
Dropout-Mode Maximum Duty
Cycle
190
SYNC = REF
97
98
SYNC = 0 or 5V
98
99
SYNC
Input High Voltage
SHDN, SKIP
Input Low Voltage
Input Current
200
ns
340
kHz
%
VL - 0.5
V
2.0
SYNC
0.8
SHDN, SKIP
0.5
SHDN, 0 or 30V
3.0
SECFB, 0 or 4V
0.1
SYNC, SKIP
1.0
CSH, CSL, CSH = CSL ≤ 4V
70
FB, FB = REF
V
µA
±0.1
DL Sink/Source Current
DL forced to 2V
1
DH Sink/Source Current
DH forced to 2V, BST - LX = 4.5V
1
A
DL On-Resistance
High or low
1.5
5
Ω
DH On-Resistance
High or low, BST - LX = 4.5V
1.5
5
Ω
A
Note 1: Since the reference uses VL as its supply, V+ line-regulation error is insignificant.
Note 2: At very low input voltages, quiescent supply current may increase due to excessive PNP base current in the VL linear
regulator. This occurs if V+ falls below the preset VL regulation point (5V nominal).
_______________________________________________________________________________________
3
MAX1652–MAX1655
ELECTRICAL CHARACTERISTICS (continued)
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
30
V
3.3V and 5V STEP-DOWN CONTROLLERS
Input Supply Range
5V Output Voltage (CSL)
0 < (CSH - CSL) < 70mV, FB = VL, 6V < V+ < 30V,
includes line and load regulation
4.80
5.30
V
3.3V Output Voltage (CSL)
0 < (CSH - CSL) < 70mV, FB = VL, 4.5V < V+ < 30V,
includes line and load regulation
3.16
3.50
V
MAX1655
0.96
1.04
Feedback Voltage
CSH - CSL = 0V, 5V < V+ < 30V,
CSL = FB, SKIP = 0V
MAX1652/MAX1653/
MAX1654
2.40
2.60
V
V
Line Regulation
6V < V+ < 30V
0.06
%/V
Current-Limit Voltage
CSH - CSL, positive
70
130
CSH - CSL, negative
-40
-160
Falling edge, hysteresis = 22mV (MAX1652)
2.40
2.60
Falling edge, hysteresis = 22mV (MAX1654)
-0.08
0.08
mV
FLYBACK/PWM CONTROLLER
SECFB Regulation Setpoint
V
INTERNAL REGULATOR AND REFERENCE
VL Output Voltage
SHDN = 2V, 0 < IVL < 25mA, 5.5V < V+ < 30V
4.7
5.3
V
VL Fault Lockout Voltage
Rising edge, hysteresis = 50mV
3.75
4.05
V
VL/CSL Switchover Voltage
Rising edge, hysteresis = 60mV
4.2
4.7
V
Reference Output Voltage
No external load (Note 1)
2.43
2.57
V
Reference Load Regulation
0 < IREF < 100µA
15
mV
V+ Shutdown Current
SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V
10
µA
V+ Off-State Leakage Current
FB = CSH = CSL = 5.5V, VL switched over to CSL
15
µA
2
mW
Quiescent Power Consumption
OSCILLATOR AND INPUTS/OUTPUTS
Oscillator Frequency
SYNC = REF
250
350
SYNC = 0 or 5V
120
180
SYNC High Pulse Width
250
SYNC Low Pulse Width
250
Oscillator Sync Range
210
Maximum Duty Cycle
SYNC = REF
97
SYNC = 0 or 5V
98
kHz
ns
ns
320
kHz
%
DL On-Resistance
High or low
5
Ω
DH On-Resistance
High or low, BST - LX = 4.5V
5
Ω
Note 3: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
4
_______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
INPUT
4.5V TO 30V
V+
VL
SHDN
MAX1653
MAX1655
DH
BST
SS
LX
REF
DL
+3.3V
OUTPUT
PGND
SYNC
CSH
GND
CSL
SKIP
FB
INPUT
6V TO 30V
V+
SHDN
SECFB
FB
+12V
OUTPUT
VL
MAX1652
DH
BST
+5V
OUTPUT
LX
DL
SS
PGND
REF
CSH
GND
SYNC
CSL
_______________________________________________________________________________________
5
MAX1652–MAX1655
Typical Operating Circuits
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
MAX1652–MAX1655
Typical Operating Circuits (continued)
INPUT
6V TO 30V
FROM
REF
V+
SECFB
SHDN
FB
VL
MAX1654
-5V
OUTPUT
DH
BST
+5V
OUTPUT
LX
DL
SS
PGND
REF
CSH
GND
CSL
SYNC
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, SKIP = GND, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs.
LOAD CURRENT (3.3V/2A CIRCUIT)
80
V+ = 28V
70
V+ = 12V
V+ = 6V
V+ = 6V
90
EFFICIENCY (%)
EFFICIENCY (%)
90
100
MAX1652 toc02
V+ = 6V
90
EFFICIENCY (%)
100
MAX1652 toc01
100
EFFICIENCY vs.
LOAD CURRENT (3.3V/3A CIRCUIT)
80
V+ = 28V
70
V+ = 12V
MAX1652 toc03
EFFICIENCY vs.
LOAD CURRENT (3.3V/1A CIRCUIT)
80
V+ = 28V
70
V+ = 12V
60
60
60
MAX1653
f = 300kHz
50
0.001
0.01
0.1
LOAD CURRENT (A)
6
1
10
MAX1653
f = 300kHz
50
0.001
0.01
0.1
LOAD CURRENT (A)
1
MAX1653
f = 300kHz
10
50
0.001
0.01
0.1
LOAD CURRENT (A)
_______________________________________________________________________________________
1
10
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
V+ = 28V
70
0.01
V+ = 28V
V+ = 12V
70
0.1
1
V+ = 24V
V+ = 12V
50
0.001
0.01
0.1
1
50
0.001
10
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
IDLE-MODE SUPPLY CURRENT vs.
INPUT VOLTAGE (3.3V/3A CIRCUIT)
PWM-MODE SUPPLY CURRENT vs.
INPUT VOLTAGE (3.3V/3A CIRCUIT)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
20
15
10
8
5
10
15
20
25
4
0
0
30
6
2
0
0.01
MAX1652 toc08
SHDN = 0V
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
0.1
MAX1653
SKIP = VL
f = 300kHz
NO LOAD
25
10
MAX1652 toc07
MAX1652 toc06
30
5
5
10
15
20
25
0
30
5
10
15
20
25
30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
REF LOAD-REGULATION ERROR
vs. REF LOAD CURRENT
VL LOAD-REGULATION ERROR
vs. VL LOAD CURRENT
MAX1652 MAXIMUM SECONDARY OUTPUT
CURRENT vs. SUPPLY VOLTAGE
15
10
40
35
30
25
20
15
10
5
5
50
100 150
200 250 300 350
LOAD CURRENT (µA)
400
1200
VSEC > 12.75V,
+5V OUTPUT > 4.75V,
CIRCUIT OF FIGURE 9
900
+5V LOAD = 0A
600
+5V LOAD = 3A
300
0
0
0
1500
MAX1652 toc12
45
MAXIMUM SECONDARY CURRENT (mA)
20
MAX1652 toc011
25
50
LOAD REGULATION ∆V (mV)
MAX1652 toc010
30
LOAD REGULATION ∆V (mV)
70
LOAD CURRENT (A)
1
0
80
MAX1653
f = 300kHz
10
MAX1653
SKIP = 0
NO LOAD
0
V+ = 6V
90
60
MAX1653
f = 300kHz
10
SUPPLY CURRENT (mA)
80
MAX1655
f = 300kHz
60
V+ = 12V
50
0.001
100
EFFICIENCY (%)
80
V+ = 6V
90
EFFICIENCY (%)
EFFICIENCY (%)
90
EFFICIENCY vs.
LOAD CURRENT (1.8V/2.5A CIRCUIT)
MAX1652 toc04a
V+ = 6V
60
100
MAX1652 toc04
100
EFFICIENCY vs.
LOAD CURRENT (5V/3A CIRCUIT)
MAX1652 toc05
EFFICIENCY vs.
LOAD CURRENT (3.3V/5A CIRCUIT)
0
10
20
30
40
50
LOAD CURRENT (mA)
60
70
80
0
5
10
15
20
25
30
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX1652–MAX1655
____________________________________Typical Operating Characteristics (continued)
(Circuit of Figure 1, SKIP = GND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, SKIP = GND, TA = +25°C, unless otherwise noted.)
DROPOUT VOLTAGE vs.
LOAD CURRENT (3.3V/3A CIRCUIT)
MAX1652 toc09
500
OUTPUT SET FOR 5V (FB = VL)
VOUT > 4.85V
DROPOUT VOLTAGE (mV)
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
400
300
f = 300kHz
200
100
f = 150kHz
0
0.01
0.1
1
10
LOAD CURRENT (A)
PULSE-WIDTH-MODULATION
MODE WAVEFORMS
IDLE-MODE WAVEFORMS
MAX1652-14
MAX1652-13
OUTPUT
VOLTAGE
10mV/div,
AC
LX
VOLTAGE
5V/div
OUTPUT
VOLTAGE
50mV/div,
AC
LX
VOLTAGE
5V/div
TIME (2.5µs)
TIME (1µs)
ILOAD = 300mA, VIN = 10V, 3.3V/3A CIRCUIT
VIN = 6V, 3.3V/3A CIRCUIT
DROPOUT WAVEFORMS
LOAD-TRANSIENT RESPONSE
MAX1652-15
10mV/div,
AC
OUTPUT
VOLTAGE
LX
VOLTAGE
OUTPUT
VOLTAGE
100mV/div,
AC
LOAD
CURRENT
2A/div
5V/div
TIME (5µs)
VIN = 5.1V, NO LOAD, 3.3V/3A CIRCUIT,
SET TO 5V OUTPUT (FB = VL)
8
MAX1652-16
TIME (10µs)
VIN = 15V, 3.3V/3A CIRCUIT
_______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
PIN
NAME
1
SS
FUNCTION
Soft-Start Timing Capacitor Connection. Ramp time to full current limit is approximately 1ms/nF.
SECFB
(MAX1652/
MAX1654)
Secondary Winding Feedback Input. Normally connected to a resistor divider from an auxiliary output.
Don’t leave SECFB unconnected.
• MAX1652: SECFB regulates at VSECFB = 2.50V. Tie to VL if not used.
• MAX1654: SECFB regulates at VSECFB = 0V. Tie to a negative voltage through a high-value currentlimiting resistor (IMAX = 100µA) if not used.
SKIP
(MAX1653/
MAX1655)
Disables pulse-skipping mode when high. Connect to GND for normal use. Don’t leave SKIP unconnected.
With SKIP grounded, the device will automatically change from pulse-skipping operation to full PWM operation when the load current exceeds approximately 30% of maximum (Table 3).
2
3
REF
Reference Voltage Output. Bypass to GND with 0.33µF minimum.
4
GND
Low-Noise Analog Ground and Feedback Reference Point
5
SYNC
Oscillator Synchronization and Frequency Select. Tie to GND or VL for 150kHz operation; tie to REF for
300kHz operation. A high-to-low transition begins a new cycle. Drive SYNC with 0 to 5V logic levels (see the
Electrical Characteristics table for VIH and VIL specifications). SYNC capture range is 190kHz to 340kHz.
6
SHDN
Shutdown Control Input, active low. Logic threshold is set at approximately 1V (VTH of an internal N-channel
MOSFET). Tie SHDN to V+ for automatic start-up.
7
FB
Feedback Input. Regulates at the feedback voltage in adjustable mode. FB is a Dual ModeTM input that also
selects the fixed output voltage settings as follows:
• Connect to GND for 3.3V operation.
• Connect to VL for 5V operation.
• Connect FB to a resistor divider for adjustable mode. FB can be driven with +5V CMOS logic in order to
change the output voltage under system control.
8
CSH
Current-Sense Input, high side. Current-limit level is 100mV referred to CSL.
9
CSL
Current-Sense Input, low side. Also serves as the feedback input in fixed-output modes.
10
V+
Battery Voltage Input (4.5V to 30V). Bypass V+ to PGND close to the IC with a 0.1µF capacitor. Connects to a
linear regulator that powers VL.
11
VL
5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. VL is switched to the output voltage via CSL (VCSL > 4.5V) for automatic bootstrapping. Bypass to GND with 4.7µF. VL can supply up
to 5mA for external loads.
12
PGND
13
DL
Low-Side Gate-Drive Output. Normally drives the synchronous-rectifier MOSFET. Swings from 0V to VL.
14
BST
Boost Capacitor Connection for High-Side Gate Drive (0.1µF)
15
LX
Switching Node (inductor) Connection. Can swing 2V below ground without hazard.
16
DH
High-Side Gate-Drive Output. Normally drives the main buck switch. DH is a floating driver output that swings
from LX to BST, riding on the LX switching-node voltage.
Power Ground
Dual Mode is a trademark of Maxim Integrated Products.
_______________________________________________________________________________________
9
MAX1652–MAX1655
Pin Description
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
Standard Application Circuits
Detailed Description
It’s easy to adapt the basic MAX1653 single-output 3.3V
buck converter (Figure 1) to meet a wide range of applications with inputs up to 30V (limited by choice of external MOSFET). Simply substitute the appropriate
components from Table 1 (candidate suppliers are provided in Table 2). These circuits represent a good set of
trade-offs among cost, size, and efficiency while staying
within the worst-case specification limits for stress-related parameters such as capacitor ripple current.
The MAX1652 family are BiCMOS, switch-mode powersupply controllers designed primarily for buck-topology
regulators in battery-powered applications where high
efficiency and low quiescent supply current are critical.
The parts also work well in other topologies such as
boost, inverting, and Cuk due to the flexibility of their
floating high-speed gate driver. Light-load efficiency is
enhanced by automatic idle-mode operation—a variable-frequency pulse-skipping mode that reduces
losses due to MOSFET gate charge. The step-down
power-switching circuit consists of two N-channel
MOSFETs, a rectifier, and an LC output filter. The output voltage is the average of the AC voltage at the
switching node, which is adjusted and regulated by
changing the duty cycle of the MOSFET switches. The
gate-drive signal to the N-channel high-side MOSFET
must exceed the battery voltage and is provided by a
flying capacitor boost circuit that uses a 100nF capacitor connected to BST.
Don’t change the frequency of these circuits without
first recalculating component values (particularly inductance value at maximum battery voltage).
For a discussion of dual-output circuits using the
MAX1652 and MAX1654, see Figure 9 and the
Secondary Feedback-Regulation Loop section.
INPUT
C1
C7
0.1µF
10
V+
ON/OFF
CONTROL
LOW-NOISE
CONTROL
6
+5V AT
5mA
11
D2
CMPSH-3
VL
DH
SHDN
BST
2
MAX1653
SKIP
LX
DL
PGND
1
CSH
SS
C6
0.01µF
(OPTIONAL)
CSL
GND
FB
7
NOTE: KEEP CURRENT-SENSE
LINES SHORT AND CLOSE
TOGETHER. SEE FIGURE 8.
SYNC
REF
16
C4
4.7µF
Q1
14
15
C3
0.1µF
L1
+3.3V
OUTPUT
R1
C2
13
Q2
D1
GND
OUT
12
8
9
4
3
5
C5
0.33µF
J1
150kHz/300kHz
JUMPER
Figure 1. Standard 3.3V Application Circuit (see Table 1 for Component Values)
10
______________________________________________________________________________________
REF OUTPUT
+2.5V AT 100µA
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
COMPONENT
3.3V at 1A
3.3V at 2A
5V/3.3V at 3A
3.3V at 5A
1.8V at 2.5A
Input Range
4.75V to 28V
4.75V to 28V
4.75V to 28V
4.75V to 28V
4.75V to 22V
Frequency
300kHz
300kHz
300kHz
300kHz
150kHz
Q1 High-Side International Rectifier
MOSFET
1/2 IRF7101
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
International Rectifier
IRF7403 or
Fairchild
Semiconductor
NDS 8410A
Fairchild
Semiconductor
FDS6680
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
Q2 Low-Side
MOSFET
International Rectifier
1/2 IRF7101
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
International Rectifier
IRF7403 or
Fairchild
Semiconductor
NDS 8410A
Fairchild
Semiconductor
FDS6680
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
C1 Input
Capacitor
10µF, 35V
AVX
TPSD106M035R0300
22µF, 35V
AVX
TPSE226M035R0300
(2) 22µF, 35V
AVX
TPSE226M035R0300
(3) 22µF, 35V
AVX
TPSE226M035R0300
10µF, 25V ceramic
Taiyo Yuden
TMK325F106Z
C2 Output
Capacitor
100µF, 6.3V
AVX TPSC107M006R
220µF, 10V
AVX
TPSE227M010R0100
or Sprague
594D227X001002T
470µF, 6V (for 3.3V)
Kemet
T510X477M006AS
or
(2) 220µF, 10V (for 5V)
AVX
TPSE227M010R011
(3) 330µF, 10V
Sprague
594D337X0010R2T
or
(2) 470µF, 6V
Kemet
T510X477M006AS
470µF, 4V
Sprague
594D477X0004R2T
or
470µF, 6V
Kemet
T510X477M006AS
D1 Rectifier
1N5819 or Motorola
MBR0520L
1N5819 or Motorola
MBRS130LT3
1N5819 or Motorola
MBRS130LT3
1N5821 or Motorola
MBRS340T3
1N5817 or Motorola
MBRS130LT3
R1 Sense
Resistor
70mΩ
33mΩ
25mΩ
12mΩ
Dale WSL-1206-R070F Dale WSL-2010-R033F Dale WSL-2010-R025F
Dale WSL-2512-R012F
or IRC LR2010-01-R070 or IRC LR2010-01-R033 or IRC LR2010-01-R025
L1 Inductor
33µH
Sumida CDR74B-330
15µH
10µH
Sumida CDR105B-150 Sumida CDRH125-100
30mΩ
Dale WSL-2010-R030F
or IRC LR2010-01-R030
4.7µH
15µH
Sumida CDRH127-4R7 Sumida CDRH125-150
Table 2. Component Suppliers
MANUFACTURER
AVX
Central Semiconductor
Coilcraft
Coiltronics
Dale
Fairchild
International Rectifier
IRC
Kemet
Matsuo
Motorola
USA PHONE
803-946-0690
516-435-1110
847-639-6400
561-241-7876
605-668-4131
408-822-2181
310-322-3331
512-992-7900
408-986-0424
714-969-2491
602-303-5454
FACTORY FAX
[Country Code]
[1] 803-626-3123
[1] 516-435-1824
[1] 847-639-1469
[1] 561-241-9339
[1] 605-665-1627
[1] 408-721-1635
[1] 310-322-3332
[1] 512-992-3377
[1] 408-986-1442
[1] 714-960-6492
[1] 602-994-6430
USA PHONE
FACTORY FAX
[Country Code]
Murata
814-237-1431
800-831-9172
[1] 814-238-0490
NIEC
Sanyo
805-867-2555*
619-661-6835
[81] 3-3494-7414
[81] 7-2070-1174
Siliconix
408-988-8000
800-554-5565
[1] 408-970-3950
Sprague
Sumida
Taiyo Yuden
TDK
Transpower Technologies
603-224-1961
847-956-0666
408-573-4150
847-390-4461
702-831-0140
[1] 603-224-1430
[81] 3-3607-5144
[1] 408-573-4159
[1] 847-390-4405
[1] 702-831-3521
MANUFACTURER
* Distributor
______________________________________________________________________________________
11
MAX1652–MAX1655
Table 1. Component Selection for Standard Applications
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
The MAX1652–MAX1655 contain nine major circuit
blocks, which are shown in Figure 2:
PWM Controller Blocks:
• Multi-Input PWM Comparator
• Current-Sense Circuit
• PWM Logic Block
• Dual-Mode Internal Feedback Mux
• Gate-Driver Outputs
• Secondary Feedback Comparator
Bias Generator Blocks:
• +5V Linear Regulator
• Automatic Bootstrap Switchover Circuit
• +2.50V Reference
These internal IC blocks aren’t powered directly from
the battery. Instead, a +5V linear regulator steps down
the battery voltage to supply both the IC internal rail (VL
pin) as well as the gate drivers. The synchronousswitch gate driver is directly powered from +5V VL,
while the high-side-switch gate driver is indirectly powered from VL via an external diode-capacitor boost circuit. An automatic bootstrap circuit turns off the +5V
linear regulator and powers the IC from its output voltage if the output is above 4.5V.
PWM Controller Block
The heart of the current-mode PWM controller is a
multi-input open-loop comparator that sums three signals: output voltage error signal with respect to the reference voltage, current-sense signal, and slope
compensation ramp (Figure 3). The PWM controller is a
direct summing type, lacking a traditional error amplifier and the phase shift associated with it. This directsumming configuration approaches the ideal of
cycle-by-cycle control over the output voltage.
Under heavy loads, the controller operates in full PWM
mode. Each pulse from the oscillator sets the main
PWM latch that turns on the high-side switch for a period determined by the duty factor (approximately
VOUT/VIN). As the high-side switch turns off, the synchronous rectifier latch is set. 60ns later the low-side
switch turns on, and stays on until the beginning of the
next clock cycle (in continuous mode) or until the
inductor current crosses zero (in discontinuous mode).
Under fault conditions where the inductor current
exceeds the 100mV current-limit threshold, the highside latch resets and the high-side switch turns off.
If the load is light in Idle Mode (SKIP = low), the inductor current does not exceed the 25mV threshold set by
the Idle Mode comparator. When this occurs, the controller skips most of the oscillator pulses in order to
reduce the switching frequency and cut back gate12
charge losses. The oscillator is effectively gated off at
light loads because the Idle Mode comparator immediately resets the high-side latch at the beginning of each
cycle, unless the feedback signal falls below the reference voltage level.
When in PWM mode, the controller operates as a fixedfrequency current-mode controller where the duty ratio
is set by the input/output voltage ratio. The currentmode feedback system regulates the peak inductor
current as a function of the output voltage error signal.
Since the average inductor current is nearly the same
as the peak current, the circuit acts as a switch-mode
transconductance amplifier and pushes the second output LC filter pole, normally found in a duty-factorcontrolled (voltage-mode) PWM, to a higher frequency.
To preserve inner-loop stability and eliminate regenerative inductor current “staircasing,” a slope-compensation ramp is summed into the main PWM comparator to
reduce the apparent duty factor to less than 50%.
The relative gains of the voltage- and current-sense
inputs are weighted by the values of current sources
that bias three differential input stages in the main PWM
comparator (Figure 4). The relative gain of the voltage
comparator to the current comparator is internally fixed
at K = 2:1. The resulting loop gain (which is relatively
low) determines the 2% typical load regulation error.
The low loop-gain value helps reduce output filter
capacitor size and cost by shifting the unity-gain
crossover to a lower frequency.
The output filter capacitor C2 sets a dominant pole in
the feedback loop. This pole must roll off the loop gain
to unity before the zero introduced by the output
capacitor’s parasitic resistance (ESR) is encountered
(see Design Procedure section). A 12kHz pole-zero
cancellation filter provides additional rolloff above the
unity-gain crossover. This internal 12kHz lowpass compensation filter cancels the zero due to the filter capacitor’s ESR. The 12kHz filter is included in the loop in
both fixed- and adjustable-output modes.
Synchronous-Rectifier Driver (DL Pin)
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky diode with
a low-resistance MOSFET switch. The synchronous rectifier also ensures proper start-up of the boost-gate driver circuit. If you must omit the synchronous power
MOSFET for cost or other reasons, replace it with a
small-signal MOSFET such as a 2N7002.
If the circuit is operating in continuous-conduction mode,
the DL drive waveform is simply the complement of the
DH high-side drive waveform (with controlled dead
time to prevent cross-conduction or “shoot-through”).
______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
MAX1652–MAX1655
BATTERY VOLTAGE
TO
CSL
V+
+5V LINEAR
REGULATOR
4.5V
OUT
VL
+5V AT 5mA
AUXILIARY
OUTPUT
SHDN
BST
SECFB
DH
PWM
LOGIC
LX
MAIN
OUTPUT
DL
+2.50V
REF
+2.50V
AT 100µA
PGND
PWM
COMPARATOR
CSH
REF
CSL
LPF
12kHz
GND
ON/OFF
3.3V FB
5V FB
SHDN
SS
ADJ FB
FB
MAX1652
MAX1653
MAX1654
MAX1655
4V
SYNC
1V
Figure 2. MAX1652–MAX1655 Functional Diagram
______________________________________________________________________________________
13
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
CSH
CSL
2.5V (1V, MAX1655)
FROM
FEEDBACK
DIVIDER
MAIN PWM
COMPARATOR
BST
R
LEVEL
SHIFT
Q
S
DH
LX
SLOPE COMP
OSC
IDLE MODE
COMPARATOR
SKIP
(MAX1653/
MAX1655
ONLY)
25mV
VL
4µA
CURRENT
LIMIT
SHOOTTHROUGH
CONTROL
24R
SS
2.5V
N
SHDN
1R
SYNCHRONOUSRECTIFIER CONTROL
R
-100mV
VL
Q
S
LEVEL
SHIFT
DL
PGND
REF (MAX1652)
GND (MAX1654)
SECFB
COMPARATOR
1µs
SINGLE-SHOT
(NOTE 1)
MAX1652, MAX1654 ONLY
NOTE 1: COMPARATOR INPUT POLARITIES
ARE REVERSED FOR THE MAX1654.
Figure 3. PWM Controller Detailed Block Diagram
14
______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
MAX1652–MAX1655
VL
R1
R2
TO PWM
LOGIC
UNCOMPENSATED
HIGH-SPEED
LEVEL TRANSLATOR
AND BUFFER
OUTPUT DRIVER
FB
I1
I2
I3
REF
CSH
CSL
SLOPE COMPENSATION
Figure 4. Main PWM Comparator Block Diagram
In discontinuous (light-load) mode, the synchronous
switch is turned off as the inductor current falls through
zero. The synchronous rectifier works under all operating conditions, including idle mode. The synchronousswitch timing is further controlled by the secondary
feedback (SECFB) signal in order to improve multipleoutput cross-regulation (see Secondary FeedbackRegulation Loop section).
Internal VL and REF Supplies
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, logic, reference, and other
blocks. This +5V low-dropout linear regulator can supply up to 5mA for external loads, with a reserve of
20mA for gate-drive power. Bypass VL to GND with
4.7µF. Important: VL must not be allowed to exceed
5.5V. Measure VL with the main output fully loaded. If
VL is being pumped up above 5.5V, the probable
cause is either excessive boost-diode capacitance or
excessive ripple at V+. Use only small-signal diodes for
D2 (10mA to 100mA Schottky or 1N4148 are preferred)
and bypass V+ to PGND with 0.1µF directly at the
package pins.
The 2.5V reference (REF) is accurate to ±1.6% over
temperature, making REF useful as a precision system
reference. Bypass REF to GND with 0.33µF minimum.
REF can supply up to 1mA for external loads. However,
if tight-accuracy specs for either V OUT or REF are
essential, avoid loading REF with more than 100µA.
Loading REF reduces the main output voltage slightly,
according to the reference-voltage load regulation
error. In MAX1654 applications, ensure that the SECFB
divider doesn’t load REF heavily.
When the main output voltage is above 4.5V, an internal
P-channel MOSFET switch connects CSL to VL while
simultaneously shutting down the VL linear regulator.
This action bootstraps the IC, powering the internal circuitry from the output voltage, rather than through a linear regulator from the battery. Bootstrapping reduces
power dissipation caused by gate-charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a less
efficient linear regulator.
It’s often possible to achieve a bootstrap-like effect,
even for circuits that are set to VOUT < 4.5V, by powering VL from an external-system +5V supply. To achieve
this pseudo-bootstrap, add a Schottky diode between
the external +5V source and VL, with the cathode to the
VL side. This circuit provides a 1% to 2% efficiency
boost and also extends the minimum battery input to
less than 4V. The external source must be in the range
of 4.8V to 5.5V.
Boost High-Side
Gate-Driver Supply (BST Pin)
Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit as shown
in Figure 5. The capacitor is alternately charged from
the VL supply and placed in parallel with the high-side
MOSFET’s gate-source terminals.
On start-up, the synchronous rectifier (low-side MOSFET) forces LX to 0V and charges the BST capacitor to
5V. On the second half-cycle, the PWM turns on the
high-side MOSFET by closing an internal switch
between BST and DH. This provides the necessary
enhancement voltage to turn on the high-side switch,
______________________________________________________________________________________
15
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
BATTERY
+5V
VL SUPPLY INPUT
VL
VL
MAX1652
MAX1653
MAX1654
MAX1655
BST
DH
LEVEL
TRANSLATOR
PWM
LX
Oscillator Frequency and
Synchronization (SYNC Pin)
The SYNC input controls the oscillator frequency.
Connecting SYNC to GND or to VL selects 150kHz
operation; connecting SYNC to REF selects 300kHz.
SYNC can also be used to synchronize with an external
5V CMOS clock generator. SYNC has a guaranteed
190kHz to 340kHz capture range.
300kHz operation optimizes the application circuit for
component size and cost. 150kHz operation provides
increased efficiency and improved low-duty factor
operation (see Dropout Operation section).
VL
Dropout Operation
DL
Figure 5. Boost Supply for Gate Drivers
an action that “boosts” the 5V gate-drive signal above
the battery voltage.
Ringing seen at the high-side MOSFET gate (DH) in
discontinuous-conduction mode (light loads) is a natural operating condition caused by the residual energy in
the tank circuit formed by the inductor and stray capacitance at the switching node LX. The gate-driver negative rail is referred to LX, so any ringing there is directly
coupled to the gate-drive output.
Current-Limiting and
Current-Sense Inputs (CSH and CSL)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor must be sized for
80mV/R1 to guarantee enough load capability, while
components must be designed to withstand continuous
current stresses of 120mV/R1.
For breadboarding purposes or very-high-current applications, it may be useful to wire the current-sense inputs
with a twisted pair rather than PC traces.
16
Dropout (low input-output differential operation) is enhanced by stretching the clock pulse width to increase
the maximum duty factor. The algorithm follows: if the output voltage (VOUT) drops out of regulation without the
current limit having been reached, the controller skips an
off-time period (extending the on-time). At the end of the
cycle, if the output is still out of regulation, another off-time
period is skipped. This action can continue until three offtime periods are skipped, effectively dividing the clock
frequency by as much as four.
The typical PWM minimum off-time is 300ns, regardless
of the operating frequency. Lowering the operating frequency raises the maximum duty factor above 98%.
Low-Noise Mode (SKIP Pin)
The low-noise mode (SKIP = high) is useful for minimizing RF and audio interference in noise-sensitive applications such as audio-equipped systems, cellular
phones, RF communicating computers, and electromagnetic pen-entry systems. See the summary of operating modes in Table 3. SKIP can be driven from an
external logic signal.
The MAX1653 and MAX1655 can reduce interference
due to switching noise by ensuring a constant switching frequency regardless of load and line conditions,
thus concentrating the emissions at a known frequency
outside the system audio or IF bands. Choose an oscillator frequency where harmonics of the switching frequency don’t overlap a sensitive frequency band. If
necessary, synchronize the oscillator to a tight-tolerance external clock generator.
The low-noise mode (SKIP = high) forces two changes
upon the PWM controller. First, it ensures fixed-frequency operation by disabling the minimum-current comparator and ensuring that the PWM latch is set at the
beginning of each cycle, even if the output is in regulation. Second, it ensures continuous inductor current
______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
SHDN
SKIP
LOAD
CURRENT
MODE
NAME
Low
X
X
Shutdown
DESCRIPTION
All circuit blocks
turned off; supply
current = 3µA typ
High
Low
Low,
––––––––––––––––———–––
VOUT x RSENSE x f
RSENSE x VOUT
RESR < ————————
VREF
(can be multiplied by 1.5, see note below)
These equations are “worst-case” with 45 degrees of
phase margin to ensure jitter-free fixed-frequency operation and provide a nicely damped output response for
zero to full-load step changes. Some cost-conscious
designers may wish to bend these rules by using less
expensive (lower quality) capacitors, particularly if the
load lacks large step changes. This practice is tolerable if
some bench testing over temperature is done to verify
acceptable noise and transient response.
There is no well-defined boundary between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope won’t quite sync up. Technically speaking, this
(usually) harmless jitter is unstable operation, since the
switching frequency is now nonconstant. As the capacitor quality is reduced, the jitter becomes more pronounced and the load-transient output voltage
waveform starts looking ragged at the edges.
Eventually, the load-transient waveform has enough
ringing on it that the peak noise levels exceed the
allowable output voltage tolerance. Note that even with
zero phase margin and gross instability present, the
output voltage noise never gets much worse than IPEAK
x RESR (under constant loads, at least).
Note: Designers of RF communicators or other noisesensitive analog equipment should be conservative
and stick to the ESR guidelines. Designers of notebook
computers and similar commercial-temperature-range
digital systems can multiply the RESR value by a factor
of 1.5 without hurting stability or transient response.
The output voltage ripple is usually dominated by the
ESR of the filter capacitor and can be approximated as
IRIPPLE x RESR. There is also a capacitive term, so the
full equation for ripple in the continuous mode is
VNOISE(p-p) = IRIPPLE x [RESR + 1 / (8 x f x COUT)]. In
Idle Mode, the inductor current becomes discontinuous
with high peaks and widely spaced pulses, so the noise
can actually be higher at light load compared to full load.
In Idle Mode, the output ripple can be calculated as:
0.025 x RESR
VNOISE(p-p) = —————— +
RSENSE
(0.025)2 x L x [1 / VOUT + 1 / (VIN - VOUT)]
———————————————————
(RSENSE)2 x COUT
Transformer Design
(MAX1652/MAX1654 Only)
Buck-plus-flyback applications, sometimes called “coupled-inductor” topologies, use a transformer to generate
multiple output voltages. The basic electrical design is a
simple task of calculating turns ratios and adding the
power delivered to the secondary in order to calculate the
current-sense resistor and primary inductance. However,
extremes of low input-output differentials, widely different
output loading levels, and high turns ratios can complicate the design due to parasitic transformer parameters
such as interwinding capacitance, secondary resistance,
and leakage inductance. For examples of what is possible with real-world transformers, see the graphs of
Maximum Secondary Current vs. Input Voltage in the
Typical Operating Characteristics.
______________________________________________________________________________________
21
MAX1652–MAX1655
Input Capacitor Value
Place a small ceramic capacitor (0.1µF) between V+ and
GND, close to the device. Also, connect a low-ESR bulk
capacitor directly to the drain of the high-side MOSFET.
Select the bulk input filter capacitor according to input
ripple-current requirements and voltage rating, rather
than capacitor value. Electrolytic capacitors that have
low enough effective series resistance (ESR) to meet the
ripple-current requirement invariably have more than
adequate capacitance values. Ceramic capacitors or
low-ESR aluminum-electrolytic capacitors such as Sanyo
OS-CON or Nichicon PL are preferred. Tantalum types
are also acceptable but may be less tolerant of high
input surge currents. RMS input ripple current is determined by the input voltage and load current, with the
worst possible case occurring at VIN = 2 x VOUT:
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
Power from the main and secondary outputs is lumped
together to obtain an equivalent current referred to the
main output voltage (see Inductor Value section for definitions of parameters). Set the value of the currentsense resistor at 80mV / ITOTAL.
PTOTAL = the sum of the output power from
all outputs
ITOTAL = PTOTAL / VOUT = the equivalent output
current referred to VOUT
VOUT (VIN(MAX) - VOUT)
L(primary) = —————————————
VIN(MAX) x f x ITOTAL x LIR
VSEC + VFWD
Turns Ratio N = ——————————————
VOUT(MIN) + VRECT + VSENSE
where: VSEC is the minimum required rectified
secondary-output voltage
VFWD is the forward drop across the
secondary rectifier
VOUT(MIN) is the minimum value of the main
output voltage (from the Electrical
Characteristics)
VRECT is the on-state voltage drop across the
synchronous-rectifier MOSFET
VSENSE is the voltage drop across the sense
resistor
In positive-output (MAX1652) applications, the transformer secondary return is often referred to the main
output voltage rather than to ground in order to reduce
the needed turns ratio. In this case, the main output
voltage must first be subtracted from the secondary
voltage to obtain VSEC.
______Selecting Other Components
MOSFET Switches
The two high-current N-channel MOSFETs must be
logic-level types with guaranteed on-resistance specifications at VGS = 4.5V. Lower gate threshold specs are
better (i.e., 2V max rather than 3V max). Drain-source
breakdown voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating
factor. The best MOSFETs will have the lowest on-resistance per nanocoulomb of gate charge. Multiplying
RDS(ON) x QG provides a meaningful figure by which to
compare various MOSFETs. Newer MOSFET process
technologies with dense cell structures generally give
the best performance. The internal gate drivers can tolerate more than 100nC total gate charge, but 70nC is a
more practical upper limit to maintain best switching
times.
22
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
I2R losses are distributed between Q1 and Q2 according to duty factor (see the equations below). Switching
losses affect the upper MOSFET only, since the
Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. Gate-charge losses are
dissipated by the driver and don’t heat the MOSFET.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. The worst-case dissipation for the high-side MOSFET occurs at the minimum
battery voltage, and the worst-case for the low-side
MOSFET occurs at the maximum battery voltage.
PD (upper FET) = ILOAD2 x RDS(ON) x DUTY
(
)
VIN x CRSS
+ VIN x ILOAD x f x ––––––––––– +20ns
IGATE
PD (lower FET) = ILOAD2 x RDS(ON) x (1 - DUTY)
DUTY = (VOUT + VQ2) / (VIN - VQ1 + VQ2)
where the on-state voltage drop VQ_ = ILOAD x RDS(ON)
CRSS = MOSFET reverse transfer capacitance
IGATE = DH driver peak output current capability
(1A typically)
20ns = DH driver inherent rise/fall time
Under output short circuit, the synchronous-rectifier
MOSFET suffers extra stress and may need to be oversized if a continuous DC short circuit must be tolerated.
During short circuit, Q2’s duty factor can increase to
greater than 0.9 according to:
Q2 DUTY (short circuit) = 1 - [VQ2 / (VIN(MAX) - VQ1 + VQ2)]
where the on-state voltage drop VQ = (120mV / RSENSE)
x RDS(ON).
Rectifier Diode D1
Rectifier D1 is a clamp that catches the negative inductor swing during the 60ns dead time between turning
off the high-side MOSFET and turning on the low-side.
D1 must be a Schottky type in order to prevent the
lossy parasitic MOSFET body diode from conducting. It
is acceptable to omit D1 and let the body diode clamp
the negative inductor swing, but efficiency will drop one
or two percent as a result. Use an MBR0530 (500mA
rated) type for loads up to 1.5A, a 1N5819 type for
loads up to 3A, or a 1N5822 type for loads up to 10A.
D1’s rated reverse breakdown voltage must be at least
equal to the maximum input voltage, preferably with a
20% derating factor.
______________________________________________________________________________________
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
Rectifier Diode D3
(Transformer Secondary Diode)
The secondary diode in coupled-inductor applications
must withstand high flyback voltages greater than 60V,
which usually rules out most Schottky rectifiers.
Common silicon rectifiers such as the 1N4001 are also
prohibited, as they are far too slow. This often makes
fast silicon rectifiers such as the MURS120 the only
choice. The flyback voltage across the rectifier is related to the VIN-VOUT difference according to the transformer turns ratio:
VFLYBACK = VSEC + (VIN - VOUT) x N
where: N is the transformer turns ratio SEC/PRI
VSEC is the maximum secondary DC output voltage
VOUT is the primary (main) output voltage
Subtract the main output voltage (VOUT) from VFLYBACK
in this equation if the secondary winding is returned to
VOUT and not to ground. The diode reverse breakdown
rating must also accommodate any ringing due to leakage inductance. D3’s current rating should be at least
twice the DC load current on the secondary output.
_____________Low-Voltage Operation
Low input voltages and low input-output differential voltages each require some extra care in the design. Low
absolute input voltages can cause the VL linear regulator to enter dropout, and eventually shut itself off. Low
input voltages relative to the output (low VIN-VOUT differential) can cause bad load regulation in multi-output flyback applications. See Transformer Design section.
Finally, low VIN-VOUT differentials can also cause the
output voltage to sag when the load current changes
abruptly. The amplitude of the sag is a function of inductor value and maximum duty factor (DMAX an Electrical
Characteristics parameter, 98% guaranteed over temperature at f = 150kHz) as follows:
(ISTEP)2 x L
VSAG = ———————————————
2 x COUT x (VIN(MIN) x DMAX - VOUT)
The cure for low-voltage sag is to increase the value of
the output capacitor. For example, at VIN = 5.5V, VOUT
= 5V, L = 10µH, f = 150kHz, a total capacitance of
660µF will prevent excessive sag. Note that only the
capacitance requirement is increased and the ESR
requirements don’t change. Therefore, the added
capacitance can be supplied by a low-cost bulk
capacitor in parallel with the normal low-ESR capacitor.
Table 4 summarizes low-voltage operational issues.
Table 4. Low-Voltage Troubleshooting
SYMPTOM
CONDITION
ROOT CAUSE
SOLUTION
Sag or droop in VOUT
under step load change
Low VIN-VOUT differential, Limited inductor-current slew
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