EVALUATION KIT AVAILABLE
MAX17048/MAX17049
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
General Description
The MAX17048/MAX17049 ICs are tiny, micropower current fuel gauges for lithium-ion (Li+) batteries in handheld
and portable equipment. The MAX17048 operates with
a single lithium cell and the MAX17049 with two lithium
cells in series.
The ICs use the sophisticated Li+ battery-modeling algorithm ModelGauge™ to track the battery relative state-ofcharge (SOC) continuously over widely varying charge
and discharge conditions. The ModelGauge algorithm
eliminates current-sense resistor and battery-learn cycles
required in traditional fuel gauges. Temperature compensation is implemented using the system microcontroller.
The ICs automatically detect when the battery enters a
low-current state and enters low-power 3µA hibernate
mode, while still providing accurate fuel gauging. The
ICs automatically exit hibernate mode when the system
returns to active state.
Features and Benefits
●● MAX17048: 1 Cell, MAX17049: 2 Cells
●● Precision ±7.5mV/Cell Voltage Measurement
●● ModelGauge Algorithm
• Provides Accurate State-of-Charge
• Compensates for Temperature/Load Variation
• Does Not Accumulate Errors, Unlike Coulomb
Counters
• Eliminates Learning
• Eliminates Current-Sense Resistor
●● Ultra-Low Quiescent Current
• 3μA Hibernate, 23μA Active
• Fuel Gauges in Hibernate Mode
• Automatically Enters and Exits Hibernate Mode
●● Reports Charge and Discharge Rate
●● Battery-Insertion Debounce
• Best of 16 Samples to Estimate Initial SOC
On battery insertion, the ICs debounce initial voltage
measurements to improve the initial SOC estimate,
thus allowing them to be located on system side. SOC,
voltage, and rate information is accessed using the I2C
interface. The ICs are available in a tiny 0.9mm x 1.7mm,
8-bump wafer-level package (WLP), or a 2mm x 2mm,
8-pin TDFN package.
●● Programmable Reset for Battery Swap
• 2.28V to 3.48V Range
Applications
●● I2C Interface
●●
●●
●●
●●
●●
●●
●●
●●
●●
Smartphones, Tablets
Smartwatches, Wearables
Bluetooth Headsets
Health and Fitness Monitors
Digital Still, Video, and Action Cameras
Medical Devices
Handheld Computers and Terminals
Wireless Speakers
Home and Building Automation, Sensors
●● Configurable Alert Indicator
• Low SOC
• 1% Change in SOC
• Battery Undervoltage/Overvoltage
• VRESET Alert
●● 8-Bit OTP ID Register (Contact Factory)
Simple Fuel-Gauge Circuit Diagram
MAX17048
ONLY ONE
EXTERNAL
COMPONENT
Ordering Information appears at end of data sheet.
ModelGauge is a trademark of Maxim Integrated Products, Inc.
19-6171; Rev 7; 11/16
VDD
ALRT
CELL
SDA
CTG
SCL
GND
QSTRT
SYSTEM
µP
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Absolute Maximum Ratings
Storage Temperature Range............................. -55°C to +125°C
Lead Temperature (TDFN only) (soldering, 10s) ............+300°C
Soldering Temperature (reflow).......................................+260°C
CELL to GND.........................................................-0.3V to +12V
All Other Pins to GND..............................................-0.3V to +6V
Continuous Sink Current, SDA, ALRT................................20mA
Operating Temperature Range............................ -40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = 2.5V to 4.5V, TA= -20°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Supply Voltage
VDD
Fuel-Gauge SOC Reset
(VRESET Register)
VRST
Data I/O Pins
SCL, SDA,
ALRT
CONDITIONS
MIN
(Note 2)
2.5
Configuration range, in 40mV steps
2.28
Trimmed at 3V
2.85
(Note 2)
-0.3
Sleep mode, TA ≤ +50°C
Supply Current
Time Base Accuracy
V
3.48
V
3.15
V
+5.5
V
Hibernate mode, reset comparator
disabled (VRESET.Dis = 1)
3
5
Hibernate mode, reset comparator
enabled (VRESET.Dis = 0)
4
IDD1
Active mode
23
40
tERR
Active, hibernate modes (Note 3)
±1
+3.5
IDD0
µA
-3.5
Active mode
250
Hibernate mode
VERR
VCELL = 3.6V, TA = +25°C (Note 4)
45
s
-7.5
+7.5
-20
+20
2.5
5
MAX17049: CELL pin
5
10
VIH
SDA, SCL, QSTRT Input
Logic-Low
VIL
SDA, ALRT Output
Logic-Low
VOL
IOL = 4mA
SDA, SCL Bus
Low-Detection Current
IPD
VSDA = VSCL = 0.4V (Note 5)
tSLEEP
1.4
(Note 6)
V
V
0.2
1.75
mV/cell
mV/cell
MAX17048: VDD pin
SDA, SCL, QSTRT Input
Logic-High
%
ms
1.25
Voltage-Measurement Range
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UNITS
4.5
2
Voltage-Measurement Resolution
Bus Low-Detection Timeout
3.0
MAX
0.5
ADC Sample Period
Voltage Error
TYP
0.5
V
0.4
V
0.4
µA
2.5
s
Maxim Integrated │ 2
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Electrical Characteristics (I2C INTERFACE)
(2.5V < VDD < 4.5V, TA = -20°C to +70°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
SCL Clock Frequency
fSCL
Bus Free Time Between a
STOP and START Condition
tBUF
START Condition (Repeated)
Hold Time
tHD:STA
CONDITIONS
(Note 7)
(Note 8)
MIN
TYP
0
MAX
UNITS
400
kHz
1.3
µs
0.6
µs
Low Period of SCL Clock
tLOW
1.3
µs
High Period of SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated
START Condition
tSU:STA
0.6
µs
Data Hold Time
tHD:DAT
(Notes 9, 10)
Data Setup Time
tSU:DAT
(Note 9)
0
0.9
100
µs
ns
Rise Time of Both SDA and
SCL Signals
tR
20 + 0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals
tF
20 + 0.1CB
300
ns
Setup Time for STOP Condition
tSU:STO
Spike Pulse Widths Suppressed
by Input Filter
tSP
(Note 11)
Capacitive Load for Each Bus
Line
CB
(Note 12)
SCL, SDA Input Capacitance
CB,IN
0.6
0
µs
50
ns
400
pF
60
pF
Note 1: Specifications are 100% tested at TA = +25°C. Limits over the operating range are guaranteed by design and
characterization.
Note 2: All voltages are referenced to GND.
Note 3: Test is performed on unmounted/unsoldered parts.
Note 4: The voltage is trimmed and verified with 16x averaging.
Note 5: This current is always present.
Note 6: The IC enters shutdown mode after SCL < VIL and SDA < VIL for longer than 2.5s.
Note 7: Timing must be fast enough to prevent the IC from entering sleep mode due to bus low for period > tSLEEP.
Note 8: fSCL must meet the minimum clock low time plus the rise/fall times.
Note 9: The maximum tHD:DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIH,MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 11: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instance.
Note 12: CB is total capacitance of one bus line in pF.
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Maxim Integrated │ 3
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
SDA
tF
tLOW
tSP
tF
tSU:DAT
tR
tR
tBUF
tHD:STA
SCL
tHD:STA
S
tSU:STA
tHD:DAT
tSU:STO
Sr
P
S
Figure 1. I2C Bus Timing Diagram
Typical Operating Characteristics
(TA = +25°C, battery is Sanyo UF504553F, unless otherwise noted.)
1
20
15
TA = +25°C
TA = -20°C
10
5
2.5
3.0
3.5
4.0
0
4.5
2.5
VCELL (V)
4.0
MAX17048 toc04
0.25
0
-0.25
-0.50
MEASURED CRATE
-4
-2
0
2
TIME (Hr)
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VCELL = 4.5V
5
0
-5
VCELL = 2.5V
-10
4
VCELL = 3.6V
-15
-20
4.5
MAX17048 toc03
10
-20
-5
10
25
40
55
70
TEMPERATURE (°C)
ENTER HIBERNATE MODE
AUTOMATICALLY
0.50
-0.75
15
VCELL (V)
MAX17048 CRATE
0.75
CRATE (%/Hr)
3.5
CRATE ACCURACY
1.00
-1.00
3.0
6
8
MAX17048 toc05
600
CURRENT (I_BATT mA, I_DD uA)
0
25
VOLTAGE ADC ERROR vs. TEMPERATURE
500
3.95
400
3.90
VBATT
300
3.85
200
3.80
IBATT
100
3.75
0
-100
4.00
VBATT (V)
TA = -20°C
TA = +25°C
2
TA = +70°C
VOLTAGE ADC ERROR (mV/CELL)
3
35
30
20
MAX17048 toc02
TA = +70°C
4
QUIESCENT CURRENT vs. SUPPLY
VOLTAGE (ACTIVE MODE)
40
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
5
MAX17048 toc01
QUIESCENT CURRENT vs. SUPPLY
VOLTAGE (HIBERNATE MODE)
3.70
IDD0
IDD1
0
5
10
15
20
3.65
TIME (min)
Maxim Integrated │ 4
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Typical Operating Characteristics (continued)
(TA = +25°C, battery is Sanyo UF504553F, unless otherwise noted.)
EXIT HIBERNATE MODE
AUTOMATICALLY
3.95
400
3.90
300
3.85
200
3.80
IBATT
100
3.75
0
75
5
50
0
25
-5
3.70
IDD1
0
2
IDD0
4
6
8
10
0
3.65
-4
-2
0
ZIGZAG PATTERN SOC ACCURACY (1/3)
REFERENCE SOC
MODELGAUGE
6
8
10
-10
MODELGAUGE
ERROR
MAX17048 toc09
100
75
5
75
5
50
0
50
0
25
-5
25
-5
-10
0
0
0
20
40
60
80
100
SOC (%)
10
ERROR (%)
SOC (%)
4
ZIGZAG PATTERN SOC ACCURACY (2/3)
REFERENCE SOC
ERROR
MAX17048 toc08
100
2
TIME (Hr)
TIME (min)
0
2
4
TIME (Hr)
5
50
0
25
-5
VCELL
97
99
101
103
105
-10
OCV
0V
0V
0V
0A
95
-10
MAX17048 toc11
10
75
0
10
8
BATTERY-INSERTION DEBOUNCE/
OCV ACQUISITION
ERROR
MAX17048 toc10
ERROR (%)
MODELGAUGE
100
6
10
TIME (Hr)
ZIGZAG PATTERN SOC ACCURACY (3/3)
REFERENCE SOC
SOC (%)
10
ERROR (%)
-100
ERROR
MAX17048 toc07
ERROR (%)
500
SOC (%)
VBATT
MODELGAUGE
100
4.00
VBATT (V)
MAX17048 toc06
600
CURRENT (I_BATT mA, I_DD uA)
SOC ACCURACY TA = 20°C, HIBERNATE MODE
REFERENCE SOC
DEBOUNCE
BEGINS
DEBOUNCE
COMPLETED
4ms/div
TIME (Hr)
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Maxim Integrated │ 5
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Pin/Bump Configurations
TOP VIEW
(PAD SIDE DOWN)
TOP VIEW
(BUMP SIDE DOWN)
SCL
QSTRT
ALRT
8
7
6
5
MAX17048
MAX17049
+
SDA
MAX17048
MAX17049
+
1
2
3
4
CTG
CELL
VDD
GND
CTG
CELL
VDD
GND
A1
A2
A3
A4
SDA
SCL
QSTRT
ALRT
B1
B2
B3
B4
WLP
TDFN
Pin/Bump Descriptions
PIN/BUMP
NAME
FUNCTION
TDFN
WLP
1
A1
CTG
Connect to Ground
2
A2
CELL
Connect to the Positive Battery Terminal.
MAX17048: Not internally connected.
MAX17049: Voltage sense input.
3
A3
VDD
Power-Supply Input. Bypass with 0.1µF to GND.
MAX17048: Voltage sense input. Connect to positive battery terminal.
MAX17049: Connect to regulated power-supply voltage.
4
A4
GND
Ground. Connect to negative battery terminal.
B4
ALRT
Open-Drain, Active-Low Alert Output. Optionally connect to interrupt input of the system
microcontroller.
5
6
B3
QSTRT
7
B2
SCL
8
B1
SDA
—
—
EP
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Quick-Start Input. Allows reset of the device through hardware. Connect to GND if not used.
I2C Clock Input. SCL has an internal pulldown (IPD) for sensing disconnection.
Open-Drain I2C Data Input/Output. SDA has an internal pulldown (IPD) for sensing
disconnection.
Exposed Pad (TDFN Only). Connect to GND.
Maxim Integrated │ 6
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
Detailed Description
ModelGauge Theory of Operation
The MAX17048/MAX17049 ICs simulate the internal,
nonlinear dynamics of a Li+ battery to determine its SOC.
The sophisticated battery model considers impedance
and the slow rate of chemical reactions in the battery
(Figure 2).
ModelGauge performs best with a custom model, obtained
by characterizing the battery at multiple discharge currents and temperatures to precisely model it. At power-on
reset (POR), the ICs have a preloaded ROM model that
performs well for some batteries. Contact Maxim if you
need a custom model.
Fuel-Gauge Performance
In coulomb counter-based fuel gauges, SOC drifts
because offset error in the current-sense ADC measurement accumulates over time. Instantaneous error can be
very small, but never precisely zero. Error accumulates
over time in such systems (typically 0.5%–2% per day)
and requires periodic corrections. Some algorithms correct drift using occasional events, and until such an event
occurs the algorithm’s error is boundless:
• Reaching predefined SOC levels near full or empty
• Measuring the relaxed battery voltage after a long
period of inactivity
• Completing a full charge/discharge cycle
To correctly measure performance of a fuel gauge as
experienced by end-users, exercise the battery dynamically. Accuracy cannot be fully determined from only
simple cycles.
Battery Voltage and State-Of-Charge
Open-circuit voltage (OCV) of a Li+ battery uniquely
determines its SOC; one SOC can have only one value of
OCV. In contrast, a given VCELL can occur at many different values of OCV because VCELL is a function of time,
OCV, load, temperature, age, and impedance, etc.; one
value of OCV can have many values of VCELL. Therefore,
one SOC can have many values of VCELL, so VCELL cannot uniquely determine SOC.
Figure 3 shows that VCELL = 3.81V occurs at 2%, 50%,
and 72% SOC.
Even the use of sophisticated tables to consider both
voltage and load results in significant error due to the
load transients typically experienced in a system. During
charging or discharging, and for approximately 30min
after, VCELL and OCV differ substantially, and VCELL has
been affected by the preceding hours of battery activity.
ModelGauge uses voltage comprehensively.
MAX17048
MAX17049
BIAS
VOLTAGE
REFERENCE
ADC (VCELL)
IC
GROUND
4.2V
VCELL
4.0V
3.8V
3.81V
TIME BASE
(32kHz)
STATE
MACHINE
(SOC, RATE)
CTG
80%
QSTRT
60%
2-WIRE
INTERFACE
SDA
ALRT
SCL
3.6V
3.81V = 72%
3.81V = 2%
100%
SOC
VDD
CELL
GND
ModelGauge requires no correction events because it
uses only voltage, which is stable over time. As TOCs 8,
9, and 10 show, ModelGauge remains accurate despite
the absence of any of the above events; it neither drifts
nor accumulates error over time.
VCELL
MAX17048/MAX17049
3.4V
3.81V = 50%
3.2V
SOC
40%
20%
0%
0
1
2
3
4
5
6
7
8
TIME (HOURS)
Figure 2. Block Diagram
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Figure 3. Instantaneous Voltage Does Not Translate Directly to
SOC
Maxim Integrated │ 7
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Temperature Compensation
Impact of Empty-Voltage Selection
For best performance, the host microcontroller must measure battery temperature periodically, and compensate
the RCOMP ModelGauge parameter accordingly, at least
once per minute. Each custom model defines constants
RCOMP0 (default is 0x97), TempCoUp (default is -0.5),
and TempCoDown (default is -5.0). To calculate the new
value of CONFIG.RCOMP:
Most applications have a minimum operating voltage
below which the system immediately powers off (empty
voltage). When characterizing the battery to create a custom model, choose empty voltage carefully. As shown in
Figure 4, capacity unavailable to the system increases at
an accelerating rate as empty voltage increases.
To ensure a controlled shutdown, consider including
operating margin into the fuel gauge based on some low
threshold of SOC, for example shutting down at 3% or
5%. This utilizes the battery more effectively than adding
error margin to empty voltage.
// T is battery temperature (degrees Celsius)
if (T > 20) {
RCOMP = RCOMP0 + (T - 20) x TempCoUp;
}
Battery Insertion
else {
When the battery is first inserted into the system, the
fuel-gauge IC has no previous knowledge about the battery’s SOC. Assuming that the battery is relaxed, the IC
translates its first VCELL measurement into the best initial
estimate of SOC. Initial error caused by the battery not
being in a relaxed state diminishes over time, regardless
of loading following this initial conversion. While SOC estimated by a coulomb counter diverges, ModelGauge SOC
converges, correcting error automatically as illustrated in
Figure 5; initial error has no long-lasting impact.
RCOMP = RCOMP0 + (T - 20) x TempCoDown;
}
60
C/3 LOAD
CAPACITY LOST (%)
50
40
30
Battery Insertion Debounce
Any time the IC powers on or resets (see the VRESET/
ID Register (0x18) section), it estimates that OCV is the
maximum of 16 VCELL samples (1ms each, full 12-bit
resolution). OCV is ready 17ms after battery insertion,
and SOC is ready 175ms after that.
20
10
0
C/10 LOAD
3.0
3.1
3.2
3.3
3.4
3.5
TARGET EMPTY VOLTAGE (V)
Figure 4. Increasing Empty Voltage Reduces Battery Capacity
MODELGAUGE HEALS ERROR
AUTOMATICALLY OVER TIME
45
RELAXED ERROR
UNRELAXED ERROR
-10
-20
0
-5
VOLTAGE ERROR
0.1
1
10
100
-10
1000
RELAXATION TIME BEFORE INSERTION (MINUTES)
0
30
REFERENCE SOC
RELAXED SOC
-5
-10
SOC (%)
SOC ERROR
0
SOC ERROR (%)
INITIAL VOLTAGE ERROR (mV)
LONGER BATTERY RELAXATION
IMPROVES INITIAL ACCURACY
15
UNRELAXED SOC
0
20
40
60
80
0
TIME AFTER INSERTION (MINUTES)
Figure 5. ModelGauge Heals Error Automatically
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Maxim Integrated │ 8
MAX17048/MAX17049
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
Battery Swap Detection
If VCELL falls below VRST, the IC quick-starts when
VCELL returns above VRST. This handles battery swap;
the SOC of the previous battery does not affect that of the
new one. See the Quick-Start and VRESET/ID Register
(0x18) sections.
Quick-Start
If the IC generates an erroneous initial SOC, the battery
insertion and system powerup voltage waveforms must
be examined to determine if a quick-start is necessary,
as well as the best time to execute the command. The IC
samples the maximum VCELL during the first 17ms. See
the Battery Insertion Debounce section. Unless VCELL is
fully relaxed, even the best sampled voltage can appear
greater or less than OCV. Therefore, quick-start must be
used cautiously.
Most systems should not use quick-start because the
ICs handle most startup problems transparently, such as
intermittent battery-terminal connection during insertion. If
battery voltage stabilizes faster than 17ms, as illustrated
in Figure 6, then do not use quick-start.
The quick-start command restarts fuel-gauge calculations in the same manner as initial power-up of the IC. If
the system power-up sequence is so noisy that the initial
estimate of SOC has unacceptable error, the system
microcontroller might be able to reduce the error by using
quick-start. A quick-start is initiated by a rising edge on
the QSTRT pin, or by writing 1 to the quick-start bit in the
MODE register.
Power-On Reset (POR)
POR includes a quick-start, so only use it when the battery is fully relaxed. See the Quick-Start section. This
command restores all registers to their default values.
After this command, reload the custom model. See the
CMD Register (0xFE) section.
Hibernate Mode
The ICs have a low-power hibernate mode that can accurately fuel gauge the battery when the charge/discharge
rate is low. By default, the device automatically enters
and exits the hibernate mode according to the charge/
discharge rate, which minimizes quiescent current (below
5µA) without compromising fuel-gauge accuracy. The ICs
can be forced into hibernate or active modes. Force the
IC into hibernate mode to reduce power consumption in
applications with less than C/4-rate maximum loading.
For applications with higher loading, Maxim recommends
the default configuration of automatic control of hibernate
mode.
In hibernate mode, the device reduces its ADC conversion period and SOC update to once per 45s. See the
HIBRT Register (0x0A) section for details on how the IC
automatically enters and exits hibernate mode.
VCELL
STEADY SYSTEM
LOAD BEGINS
STEADY
SYSTEM
LOAD BEGINS
VCELL
BEST TIME TO
QUICK-START
VCELL HAS
FULLY RELAXED
TIME
VCELL HAS
FULLY RELAXED
TIME
INITIAL SAMPLE
DEBOUNCE WINDOW
QUICK-START DURING
THIS TIME SPAN
INITIAL SAMPLE
DEBOUNCE WINDOW
Figure 6. Insertion Waveform Not Requiring Quick-Start
Command
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Figure 7. Insertion Waveform Requiring Quick-Start Command
Maxim Integrated │ 9
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Alert Interrupt
The ICs can interrupt a system microcontroller with
five configurable alerts (see Table 1). All alerts can be
disabled or enabled with software. When the interrupt
occurs, the system microcontroller can determine the
cause from the STATUS register.
When an alert is triggered, the IC drives the ALRT
pin logic-low and sets CONFIG.ALRT = 1. The ALRT
pin remains logic-low until the system software writes
CONFIG.ALRT = 0 to clear the alert. The alert function
is enabled by default, so any alert can occur immediately
upon power-up. Entering sleep mode clears no alerts.
Sleep Mode
In sleep mode, the IC halts all operations, reducing current consumption to below 1µA. After exiting sleep mode,
the IC continues normal operation. In sleep mode, the
IC does not detect self-discharge. If the battery changes
state while the IC sleeps, the IC cannot detect it, causing
SOC error. Wake up the IC before charging or discharging. To enter sleep mode, write MODE.EnSleep = 1 and
either:
• Hold SDA and SCL logic-low for a period for tSLEEP.
A rising edge on SDA or SCL wakes up the IC.
• Write CONFIG.SLEEP = 1. To wake up the IC, write
CONFIG.SLEEP = 0. Other communication does not
wake up the IC. POR does wake up the IC.
Register Summary
All registers must be written and read as 16-bit words;
8-bit writes cause no effect. Any bits marked X (don’t
care) or read only must be written with the rest of the
register, but the value written is ignored by the IC. The
values read from don’t care bits are undefined. Calculate
the register’s value by multiplying the 16-bit word by the
register’s LSb value, as shown in Table 2.
VCELL Register (0x02)
The MAX17048 measures VCELL between the VDD and
GND pins. The MAX17049 measures VCELL between the
CELL and GND pins. VCELL is the average of four ADC
conversions. The value updates every 250ms in active
mode and every 45s in hibernate mode.
SOC Register (0x04)
The ICs calculate SOC using the ModelGauge algorithm.
This register automatically adapts to variation in battery
size since ModelGauge naturally recognizes relative SOC.
The upper byte least-significant bit has units of 1%. The
lower byte provides additional resolution.
The first update is available approximately 1s after POR
of the IC. Subsequent updates occur at variable intervals
depending on application conditions.
Applications which can tolerate 4µA should use hibernate
rather than sleep mode.
Table 1. Alert Interrupt Summary
ALERT FUNCTION
WHERE CONFIGURED
INDICATOR BIT
Low SOC
CONFIG.ATHD
STATUS.HD
SOC 1% change
CONFIG.ALSC
STATUS.SC
Reset
VRESET, STATUS.RI
STATUS.VR
Overvoltage
VALRT.MAX
STATUS.VH
Undervoltage
VALRT.MIN
STATUS.VL
Table 2. Register Summary
ADDRESS
REGISTER
NAME
16-BIT LSb
0x02
VCELL
78.125µV/cell
0x04
SOC
1%/256
0x06
MODE
0x08
0x0A
DESCRIPTION
READ/WRITE
DEFAULT
ADC measurement of VCELL.
R
—
Battery state of charge.
R
—
—
Initiates quick-start, reports hibernate mode,
and enables sleep mode.
W
0x0000
VERSION
—
IC production version.
R
0x001_
HIBRT
—
Controls thresholds for entering and exiting
hibernate mode.
R/W
0x8030
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Maxim Integrated │ 10
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Table 2. Register Summary (continued)
ADDRESS
REGISTER
NAME
16-BIT LSb
0x0C
CONFIG
—
0x14
VALRT
—
0x16
CRATE
0.208%/hr
0x18
VRESET/ID
0x1A
STATUS
0x40 to 0x7F
TABLE
—
Configures battery parameters.
0xFE
CMD
—
Sends POR command.
DESCRIPTION
READ/WRITE
DEFAULT
Compensation to optimize performance, sleep
mode, alert indicators, and configuration.
R/W
0x971C
Configures the VCELL range outside of which
alerts are generated.
R/W
0x00FF
Approximate charge or discharge rate of the
battery.
R
—
—
Configures VCELL threshold below which
the IC resets itself, ID is a one-time factoryprogrammable identifier.
R/W
0x96__
—
Indicates overvoltage, undervoltage, SOC
change, SOC low, and reset alerts.
R/W
0x01__
MSB—ADDRESS 0x06
X
QuickStart
EnSleep
HibStat
X
W
—
R/W
0xFFFF
LSB—ADDRESS 0x07
X
X
MSb
X
X
LSb
MSb
X
X
X
X
X
X
X
LSb
Figure 8. MODE Register Format
MODE Register (0x06)
The MODE register allows the system processor to send
special commands to the IC (see Figure 8).
• Quick-Start generates a first estimate of OCV and
SOC based on the immediate cell voltage. Use with
caution; see the Quick-Start section.
www.maximintegrated.com
• EnSleep enables sleep mode. See the Sleep Mode
section.
• HibStat indicates when the IC is in hibernate mode
(read only).
VERSION Register (0x08)
The value of this read-only register indicates the production version of the IC.
Maxim Integrated │ 11
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
HIBRT Register (0x0A)
To disable hibernate mode, set HIBRT = 0x0000. To
always use hibernate mode, set HIBRT = 0xFFFF (see
Figure 9).
• ActThr (active threshold): If at any ADC sample |OCVCELL| is greater than ActThr, the IC exits hibernate
mode. 1 LSb = 1.25mV.
• HibThr (hibernate threshold). If the absolute value of
CRATE is less than HibThr for longer than 6min, the IC
enters hibernate mode. 1 LSb = 0.208%/hr.
CONFIG Register (0x0C)
• RCOMP is an 8-bit value that can be adjusted to optimize IC performance for different lithium chemistries
or different operating temperatures. Contact Maxim
for instructions for optimization. The POR value of
RCOMP is 0x97.
• SLEEP forces the IC in or out of sleep mode if Mode.
EnSleep is set. Writing 1 forces the IC to enter sleep
mode, and 0 forces the IC to exit. The POR value of
SLEEP is 0.
• ALSC (SOC change alert) enables alerting when
SOC changes by at least 1%. Each alert remains until
STATUS.SC is cleared, after which the alert automatically clears until SOC again changes by 1%. Do not
use this alert to accumulate changes in SOC.
• ALRT (alert status bit) is set by the IC when an alert
occurs. When this bit is set, the ALRT pin asserts
low. Clear this bit to service and deassert the ALRT
pin. The power-up default value for ALRT is 0. The
STATUS register specifies why the ALRT pin was
asserted.
• ATHD (empty alert threshold) sets the SOC threshold,
where an interrupt is generated on the ALRT pin and
can be programmed from 1% up to 32%. The value is
(32 - ATHD)% (e.g., 00000b → 32%, 00001b → 31%,
00010b → 30%, 11111b → 1%). The POR value of
ATHD is 0x1C, or 4%. The alert only occurs on a falling
edge past this threshold.
MSB (HibThr)—ADDRESS 0x0A
27
26
25
24
23
22
21
MSb
LSB (ActThr)—ADDRESS 0x0B
20
27
LSb
MSb
26
25
24
23
22
21
20
LSb
HibThr 20 UNIT: 0.208%/hr
ActThr 20 UNIT: 1.25mV
Figure 9. HIBRT Register Format
MSB (RCOMP)—ADDRESS 0x0C
LSB—ADDRESS 0x0D
RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP
7
6
5
4
3
2
1
0
SLEEP ALSC ALRT
MSb
MSb
LSb
ATHD ATHD ATHD ATHD ATHD
4
3
2
1
0
LSb
Figure 10. CONFIG Register Format
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Maxim Integrated │ 12
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
VALRT Register (0x14)
This register is divided into two thresholds: Voltage alert
maximum (VALRT.MAX) and minimum (VALRT. MIN).
Both registers have 1 LSb = 20mV. The IC alerts while
VCELL > VALRT.MAX or VCELL < VALRT.MIN (see
Figure 11).
CRATE Register (0x16)
The IC calculates an approximate value for the average
SOC rate of change. 1 LSb = 0.208% per hour (not for
conversion to ampere).
VRESET/ID Register (0x18)
to distinguish multiple cell types in production. Writes
to these bits are ignored.
• VRESET[7:1] adjusts a fast analog comparator and a
slower digital ADC threshold to detect battery removal
and reinsertion. For captive batteries, set to 2.5V. For
removable batteries, set to at least 300mV below the
application’s empty voltage, according to the desired
reset threshold for your application. If the comparator
is enabled, the IC resets 1ms after VCELL rises above
the threshold. Otherwise, the IC resets 250ms after the
VCELL register rises above the threshold.
• Dis. Set Dis = 1 to disable the analog comparator in
hibernate mode to save approximately 0.5µA.
See Figure 12.
• ID is an 8-bit read-only value that is one-time programmable at the factory, which can be used as an identifier
MSB (VALRT.MIN)—ADDRESS 0x14
LSB (VALRT.MAX)—ADDRESS 0x15
MIN7 MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0
MAX7 MAX6 MAX5 MAX4 MAX3 MAX2 MAX1 MAX0
MSb
MSb
LSb
LSb
UNIT: 20mV
Figure 11. VALRT Register Format
MSB (VRESET)—ADDRESS 0x18
27
26
25
24
23
MSb
22
21
LSB (ID)—ADDRESS 0x19
Dis
ID6
LSb
MSb
ID5
ID4
ID3
ID2
ID1
ID0
ID
LSb
VRESET 20 UNITS: 40mV
Figure 12. VRESET/ID Register Format
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Maxim Integrated │ 13
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
STATUS Register (0x1A)
An alert can indicate many different conditions. The
STATUS register identifies which alert condition was met.
Clear the corresponding bit after servicing the alert (see
Figure 13).
To unlock the TABLE registers, write 0x57 to address
0x3F, and 0x4A to address 0x3E. While TABLE is
unlocked, no ModelGauge registers are updated, so
relock as soon as possible by writing 0x00 to address
0x3F, and 0x00 to address 0x3E.
Reset Indicator:
CMD Register (0xFE)
• RI (reset indicator) is set when the device powers up.
Any time this bit is set, the IC is not configured, so the
model should be loaded and the bit should be cleared.
Alert Descriptors:
These bits are set only when they cause an alert (e.g., if
CONFIG.ALSC = 0, then SC is never set).
• VH (voltage high) is set when VCELL has been above
ALRT.VALRTMAX.
• VL (voltage low) is set when VCELL has been below
ALRT.VALRTMIN.
• VR (voltage reset) is set after the device has been
reset if EnVr is set.
• HD (SOC low) is set when SOC crosses the value in
CONFIG.ATHD.
• SC (1% SOC change) is set when SOC changes by at
least 1% if CONFIG.ALSC is set.
Enable or Disable VRESET Alert:
• EnVr (enable voltage reset alert) when set to 1 asserts
the ALRT pin when a voltage-reset event occurs under
the conditions described by the VRESET/ ID register.
Writing a value of 0x5400 to this register causes
the device to completely reset as if power had been
removed (see the Power-On Reset (POR) section). The
reset occurs when the last bit has been clocked in. The
IC does not respond with an I2C ACK after this command sequence.
Application Examples
The ICs have a variety of configurations, depending on
the application. Table 3 shows the most common system
configurations and the proper pin connections for each.
In all cases, the system must provide pullup circuits for
ALRT (if used), SDA, and SDL.
Figure 14 shows an example application for a 1S cell
pack. In this example, the ALRT pin is connected to the
microcontroller’s interrupt input to allow the MAX17048 to
signal when the battery is low. The QSTRT pin is unused
in this application and is connected to GND.
Figure 15 shows a MAX17049 example application using
a 2S cell pack. The MAX17049 is mounted on the system
side and powered from a 3.3V supply generated by the
system. The CELL pin is still connected directly to PACK+.
TABLE Registers (0x40 to 0x7F)
Contact Maxim for details on how to configure these
registers. The default value is appropriate for some Li+
batteries.
MSB—ADDRESS 0x1A
X
EnVR
SC
HD
MSb
VR
VL
LSB—ADDRESS 0x1B
VH
RI
LSb
X
MSb
X
X
X
X
X
X
X
LSb
Figure 13. STATUS Register Format
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Maxim Integrated │ 14
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
SYSTEM
2.5V TO 4.5V OUTPUT
BATTERY PACK
MAX17048
0.1µF
PROTECTION
SYSTEM µP
I2C MASTER
BATTERY PACK
ALRT
CELL
SDA
SDA
CTG
SCL
SCL
GND
QSTRT
0.1µF
PROTECTION
Figure 14. MAX17048 Application Circuit (1S Cell Pack)
SYSTEM µP
I2C MASTER
MAX17049
INTERRUPT
VDD
INTERRUPT
VDD
ALRT
CELL
SDA
SDA
CTG
SCL
SCL
GND
QSTRT
Figure 15. MAX17049 Application Circuit (2S Cell Pack)
Table 3. Possible Application Configurations
SYSTEM CONFIGURATION
IC
VDD
ALRT
QSTRT
1S pack-side location
MAX17048
Power directly from battery
Leave unconnected
Connect to GND
1S host-side location
MAX17048
Power directly from battery
Leave unconnected
Connect to GND
1S host-side location,
low-cell interrupt
MAX17048
Power directly from battery
Connect to system
interrupt
Connect to GND
1S host-side location,
hardware quick-start
MAX17048
Power directly from battery
Leave unconnected
Connect to rising-edge
reset signal
2S pack-side location
MAX17049
Power from +2.5V to +4.5V
LDO in pack
Leave unconnected
Connect to GND
2S host-side location
MAX17049
Power from +2.5V to +4.5V
LDO or PMIC
Leave unconnected
Connect to GND
2S host-side location,
low-cell interrupt
MAX17049
Power from +2.5V to +4.5V
LDO or PMIC
Connect to system
interrupt
Connect to GND
2S host-side location,
hardware quick-start
MAX17049
Power from +2.5V to +4.5V
LDO or PMIC
Leave unconnected
Connect to rising-edge
reset signal
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Maxim Integrated │ 15
MAX17048/MAX17049
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
I2C Bus System
The I2C bus system supports operation as a slave-only
device in a single or multislave, and single or multimaster
system. Slave devices can share the bus by uniquely setting the 7-bit slave address. The I2C interface consists of
a serial-data line (SDA) and serial-clock line (SCL). SDA
and SCL provide bidirectional communication between
the IC’s slave device and a master device at speeds up to
400kHz. The IC’s SDA pin operates bidirectionally; that is,
when the IC receives data, SDA operates as an input, and
when the IC returns data, SDA operates as an open-drain
output, with the host system providing a resistive pullup.
The IC always operates as a slave device, receiving and
transmitting data under the control of a master device.
The master initiates all transactions on the bus and generates the SCL signal, as well as the START and STOP bits,
which begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle,
with the cycle defined by SCL transitioning low-to-high
and then high-to-low. The SDA logic level must remain
stable during the high period of the SCL clock pulse.
Any change in SDA when SCL is high is interpreted as a
START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no master
device has control. Both SDA and SCL remain high when
the bus is idle. The STOP condition is the proper method
to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition
(S) by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP
condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used in
place of a STOP then START sequence to terminate one
transaction and begin another without returning the bus to
the idle state. In multimaster systems, a Repeated START
allows the master to retain control of the bus. The START
and STOP conditions are the only bus activities in which
the SDA transitions when SCL is high.
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Acknowledge Bits
Each byte of a data transfer is acknowledged with an
acknowledge bit (A) or a no-acknowledge bit (N). Both
the master and the MAX17048 slave generate acknowledge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep it
low until SCL returns low. To generate a no- acknowledge
(also called NAK), the receiver releases SDA before the
rising edge of the acknowledge-related clock pulse and
leaves SDA high until SCL returns low. Monitoring the
acknowledge bits allows for detection of unsuccessful
data transfers. An unsuccessful data transfer can occur
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master should reattempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant
bit (MSb) first. The least significant bit (LSb) of each
byte is followed by the acknowledge bit. The IC registers
composed of multibyte values are ordered MSB first.
The MSB of multibyte registers is stored on even datamemory addresses.
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave address
(SAddr) and the read/write (R/W) bit. When the bus is
idle, the ICs continuously monitor for a START condition
followed by its slave address. When the ICs receive a
slave address that matches the value in the slave address
register, they respond with an acknowledge bit during the
clock period following the R/W bit. The 7-bit slave address
is fixed to 0x6C (write)/0x6D (read):
MAX17048 /MAX17049
SLAVE ADDRESS
0110110
Read/Write Bit
The R/W bit following the slave address determines the
data direction of subsequent bytes in the transfer. R/W =
0 selects a write transaction with the following bytes being
written by the master to the slave. R/W = 1 selects a read
transaction with the following bytes being read from the
slave by the master (Table 4).
Maxim Integrated │ 16
MAX17048/MAX17049
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
Table 4. I2C Protocol Key
KEY
S
DESCRIPTION
KEY
DESCRIPTION
START bit
Sr
SAddr
Slave address (7 bit)
W
R/W bit = 0
MAddr
Memory address byte
P
STOP bit
Data
Data byte written by master
Data
Repeated START
Data byte returned by slave
A
Acknowledge bit—master
A
Acknowledge bit—slave
N
No acknowledge—master
N
No acknowledge bit—slave
R
R/W bit = 1
Bus Timing
The ICs are compatible with any bus timing up to 400kHz.
No special configuration is required to operate at any
speed.
I2C Command Protocols
The command protocols involve several transaction
formats. The simplest format consists of the master
writing the START bit, slave address, R/W bit, and then
monitoring the acknowledge bit for presence of the ICs.
More complex formats, such as the Write Data and Read
Data, read data and execute device-specific operations.
All bytes in each command format require the slave or
host to return an acknowledge bit before continuing with
the next byte. Table 4 shows the key that applies to the
transaction formats.
Basic Transaction Formats
A write transaction transfers 2 or more data bytes to the
ICs. The data transfer begins at the memory address
supplied in the MAddr byte. Control of the SDA signal is
retained by the master throughout the transaction, except
for the acknowledge cycles:
A read transaction transfers 2 or more bytes from the
ICs. Read transactions are composed of two parts, a
write portion followed by a read portion, and are therefore
inherently longer than a write transaction. The write portion communicates the starting point for the read operation. The read portion follows immediately, beginning with
a Repeated START, slave address with R/W set to a 1.
Control of SDA is assumed by the ICs, beginning with the
slave address acknowledge cycle. Control of the SDA
signal is retained by the ICs throughout the transaction,
except for the acknowledge cycles. The master indicates
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the end of a read transaction by responding to the last
byte it requires with a no acknowledge. This signals the
ICs that control of SDA is to remain with the master following the acknowledge clock.
Write: S. SAddr W. A. MAddr. A. Data0. A. Data1. A. P
Read: S. SAddr W. A. MAddr. A. Sr. SAddr R. A. Data0. A. Data1. N. P
Write Portion
Read Portion
Write Data Protocol
The write data protocol is used to write to register to the
ICs starting at memory address MAddr. Data0 represents
the data written to MAddr, Data1 represents the data
written to MAddr + 1, and DataN represents the last data
byte, written to MAddr + N. The master indicates the end
of a write transaction by sending a STOP or Repeated
START after receiving the last acknowledge bit:
S. SAddr W. A. MAddr. A. Data0. A. Data1. A... DataN. A. P
The MSb of the data to be stored at address MAddr can
be written immediately after the MAddr byte is acknowledged. Because the address is automatically incremented
after the LSb of each byte is received by the ICs, the MSb
of the data at address MAddr + 1 can be written immediately after the acknowledgment of the data at address
MAddr. If the bus master continues an autoincremented
write transaction beyond address 4Fh, the ICs ignore
the data. A valid write must include both register bytes.
Data is also ignored on writes to read-only addresses.
Incomplete bytes and bytes that are not acknowledged by
the ICs are not written to memory.
Maxim Integrated │ 17
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
MAX17048/MAX17049
Read Data Protocol
The read data protocol is used to read to register from the
ICs starting at the memory address specified by MAddr.
Both register bytes must be read in the same transaction
for the register data to be valid. Data0 represents the data
byte in memory location MAddr, Data1 represents the
data from MAddr + 1, and DataN represents the last byte
read by the master:
S. SAddr W. A. MAddr. A. Sr. SAddr R. A.
Data0. A. Data1. A... DataN. N. P
Data is returned beginning with the MSb of the data in
MAddr. Because the address is automatically incremented
after the LSb of each byte is returned, the MSb of the data
at address MAddr + 1 is available to the host immediately
after the acknowledgment of the data at address MAddr.
If the bus master continues to read beyond address FFh,
the ICs output data values of FFh. Addresses labeled
Reserved in the memory map return undefined data. The
bus master terminates the read transaction at any byte
boundary by issuing a no acknowledge followed by a
STOP or Repeated START.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DESCRIPTION
MAX17048G+
-40°C to +85°C
8 TDFN-EP*
1-Cell ModelGauge IC
MAX17048G+T10
-40°C to +85°C
8 TDFN-EP*
1-Cell ModelGauge IC
MAX17048X+
-40°C to +85°C
8 WLP
1-Cell ModelGauge IC
MAX17048X+T10
-40°C to +85°C
8 WLP
1-Cell ModelGauge IC
MAX17049G+
-40°C to +85°C
8 TDFN-EP*
2-Cell ModelGauge IC
MAX17049G+T10
-40°C to +85°C
8 TDFN-EP*
2-Cell ModelGauge IC
MAX17049X+
-40°C to +85°C
8 WLP
2-Cell ModelGauge IC
MAX17049X+T10
-40°C to +85°C
8 WLP
2-Cell ModelGauge IC
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 WLP
W80B1+1
21-0555
Refer to
Application Note 1891
8 TDFN-EP
T822+3
21-0168
90-0065
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Maxim Integrated │ 18
MAX17048/MAX17049
3μA 1-Cell/2-Cell Fuel Gauge with ModelGauge
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
2/12
Initial release
1
4/12
Corrected byte-order errors
10, 11, 13
—
2
8/12
Updated soldering temperature in Absolute Maximum Ratings; corrected Hibernate
register names that were switched
2, 12, 14
3
10/12
Corrected VDD pin names in Absolute Maximum Ratings and Electrical
Characteristics
2, 3
4
8/13
Corrected version number
10
5
10/13
Corrected conditions for Supply Current in Electrical Charateristics
2
6
10/14
Updated VRESET recommendation from 40mV–80mV below 300mW empty voltage
and corrected VR bit of Status register
7
11/16
Updated front page title, description, applications, and features
13, 14
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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