TION KIT
EVALUA BLE
AVAILA
19-4756; Rev 1; 4/10
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
Features
The MAX17115 includes a high-performance step-up
regulator, a high-accuracy, high-voltage, low-dropout
linear regulator (LDO), a high-performance buffer ampifier, and a logic-controlled high-voltage switch block.
S 2.5V to 5.5V Input Supply Range
S Pin-Programmable 640kHz/1.2MHz Switching
Frequency
S Current-Mode Step-Up Converter
Fast-Transient Response to Pulsed Load_
High-Accuracy Output Voltage (0.8%)_
Built-In 20V, 4.6A, 0.1I n-Channel Power MOSFET
Cycle-by-Cycle Current Limit_
High Efficiency (88%)
S Programmable Soft-Start
S High-Performance Operational Amplifier
200mA Output Short-Circuit Current_
45V/µs Slew Rate_
20MHz -3dB Bandwidth_
Rail-to-Rail Input and Output
S High-Voltage LDO
High ±0.5% Accuracy_
40mA Guaranteed Output Current
S Logic-Controlled High-Voltage Switch with
Adjustable Delay
S High-Voltage Stress Mode
S Built-In Sequencing
S Thermal-Overload Protection
S Gate Driver for Input-Side True Shutdown™
Switch
S Logic-Level Shutdown Input
S Timer-Delayed Fault Shutdown for BoostRegulator Output
PIN-PACKAGE
32 TQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
N.C.
PGND
PGND
LX
LX
GATE
21
20
19
18
17
COMP 25
16
IN
AGND 26
15
IN
SS 27
14
AGND
N.C. 28
13
EN
MAX17115
12
FREQ
VGH 30
11
HVS_EN
VGHM 31
10
VDET
DRN 32
9
XAO
VDPM 29
1
2
3
4
5
6
7
8
VFLK
TEMP RANGE
-40NC to +85NC
22
OPGND
PART
MAX17115ETJ+
23
OPI
Ordering Information
24
OPO
LCD TVs
TOP VIEW
VOP
LCD Monitors
Pin Configuration
RHVS
Applications
True Shutdown is a trademark of Maxim Integrated Products, Inc.
VREF_I
The MAX17115 is available in a lead-free, 32-pin, thin
QFN package. The package is a 5mm x 5mm square
with a maximum thickness of 0.8mm for thin LCD panel
design.
FB
The high-voltage stress (HVS) function is used to temporarily increase the source-driver supply voltage of the
LCD panel for aging tests. The HVS digital input controls
an open-drain internal switch, which is typically used to
change the feedback divider of the step-up regulator.
VREF_O
The operational amplifier, typically used to drive the LCD
backplane (VCOM), features high-output short-circuit
current (200mA), fast slew rate (45V/Fs), and wide bandwidth (20MHz). Its rail-to-rail input and output maximize
application flexibility. The high-voltage LDO is adjustable
and has a high accuracy of Q0.5%. It is typically used to
drive a gamma reference divider string. The high-voltage
switch control block modulates the shape of the gate-on
supply and provides an adjustable delay for power-up
sequencing.
VREF_FB
The DC-DC converter is a high-frequency (1.2MHz/
640kHz) current-mode step-up regulator with a built-in
power MOSFET. It provides fast-transient response to
pulsed loads while producing efficiencies over 88%. The
built-in power MOSFET allows output voltages as high as
18V from inputs from 2.5V to 5.5V. A programmable softstart function controls startup inrush currents.
THIN QFN
5mm x 5mm
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX17115
General Description
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
ABSOLUTE MAXIMUM RATINGS
IN, VFLK, EN to AGND..........................................-0.3V to +7.5V
VDET, XAO, HVS_EN, RHVS, VREF_FB,
FREQ to AGND..................................................-0.3V to +7.5V
VDPM, FB, COMP, GATE,
SS to AGND............................................. -0.3V to (VIN + 0.3V)
PGND, OPGND to AGND......................................-0.3V to +0.3V
VREF_O to AGND.................................-0.3V to (VVREF_I + 0.3V)
LX to PGND............................................................-0.3V to +22V
VOP, VREF_I to AGND..........................................-0.3V to +22V
VGH to AGND........................................................-0.3V to +40V
VGHM, DRN to AGND............................. -0.3V to (VVGH + 0.3V)
VGHM to DRN........................................................-0.3V to +40V
OPI, OPO to OPGND............................... -0.3V to (VVOP + 0.3V)
OPO Maximum Continuous Output Current..................... Q75mA
LX, PGND RMS Current Rating (per pin)..............................1.6A
Continuous Power Dissipation (TA = +70NC)
32-Pin TQFN (derate 34.5mW/NC above +70NC).......2758mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +160NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VEN = +5V, Circuit of Figure 1, VVOP = +16V, VVGH = 30V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
6.0
V
2.25
2.49
V
VFB = 1.3V, LX not switching
0.5
1
VFB = 1.2V, switching
2.5
5
SUPPLY
IN Input-Supply Range
(Note 1)
2.5
IN Undervoltage Lockout
VIN rising, hysteresis = 200mV
2.0
IN Quiescent Current
Thermal Shutdown
Temperature rising
+160
Hysteresis
mA
°C
15
HIGH-VOLTAGE LDO
VREF_I Input Voltage Range
10
18
V
VREF_I Undervoltage Lockout
VVREF_I rising
5.4
5.8
V
VREF_I Input-Bias Current
No load
100
250
µA
VREF_O Dropout Voltage
VREF_I - VREF_O; IVREF_O = 30mA
0.25
0.5
V
VREF_FB
Regulation Voltage
1mA ≤ IVREF_O ≤ 30mA
1.240
1.246
V
+0.9
mV/V
10V < VVREF_I < 18V, IVREF_O = 20mA, VVREF_O = 9V
VREF_O Maximum
Output Current
1.234
-0.9
40
mA
STEP-UP REGULATOR
Output-Voltage Range
VIN
FB Regulation Voltage
No load
FB Fault Trip Level
Falling edge
1.228
1.24
18
V
1.252
V
1.00
V
55
ms
FB Fault Delay
VFB = 0.95V
FB Load Regulation
1mA < ILOAD < 0.5A
-0.1
FB Line Regulation
VIN = 2.5V to 6V
0.05
0.15
%/V
FB Input-Bias Current
VFB = 1.24V; TA = +25°C
120
250
nA
FB Transconductance
ICOMP = +2.5µA
100
250
500
µS
LX Current Limit
VFB = 1.2V, duty cycle = 75%
3.9
4.6
5.4
A
2 _______________________________________________________________________________________
%
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
(VIN = VEN = +5V, Circuit of Figure 1, VVOP = +16V, VVGH = 30V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
LX On-Resistance
TYP
MAX
VIN = 5V
CONDITIONS
MIN
0.10
0.2
VIN = 3V
0.13
0.26
UNITS
W
LX Bias Current
VLX = 20V, TA = +25°C
10
25
µA
Current-Sense Transresistance
VIN = 5V
0.08
0.15
0.25
V/A
VFREQ = 0V
500
640
780
VFREQ = 5V
1000
1200
1400
OSCILLATOR
Frequency
FREQ Pulldown Current
VFREQ = 5V
3
6
9
Maximum Duty Cycle
VFREQ = 0V or 5V
89
93
96
Minimum On-Time
100
kHz
µA
%
ns
SOFT-START
SS Reset Resistance
VEN = 0V, ISS = 10mA
SS Charge Current
VSS = 1.2V
SS Done Threshold
SS voltage rising
1.4
V
SS Time
33nF on SS pin
6.6
ms
2
10
20
I
4
6
µA
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
VDPM Capacitor Charge Current
MLG startup, VVDPM = 0V
VDPM Turn-On Threshold
VDPM rising
VDPM Pulldown Resistance
IVDPM = 10mA
VFLK Input Low Voltage
4
5
6
µA
1.21
1.24
1.27
10
20
V
I
0.7
V
VIN = 2.5V to 6V
2.5V < VIN < 4.5V
1.9
4.5V < VIN < 6V
2.3
VFLK Input Leakage Current
VVFLK = 0V or 5V, TA = +25°C
-1
VFLK-to-VGH Propagation Delay
VFLK rising and falling
VFLK Input High Voltage
V
+1
200
VGH Input-Voltage Range
VGH Input Current
µA
ns
35
V
VVDPM = 1.5V, VVFLK = 5V
300
450
µA
VVDPM = 1.5V, VVFLK = 0V
200
350
VGH-to-VGHM Resistance
VVDPM = 1.5V, VVFLK = 5V, I = 10mA
8
15
µA
I
VGHM-to-DRN Resistance
VVDPM = 1.5V, VVFLK = 0V, I = 10mA
30
60
I
10
12
µA
INPUT SERIES SWITCH GATE DRIVER
GATE Output Sink Current
VGATE = 5V
8
VGATE = 0.2V
10
20
mA
GATE Done Voltage Threshold
GATE falling
0.3
0.5
V
GATE Output Voltage Low
IGATE = 1mA
0.01
0.05
V
GATE Output Voltage High
IGATE = -1mA, VEN = 0V
VIN 0.05
VIN 0.02
V
OPERATIONAL AMPLIFIER
VOP Supply Range
6
VOP Overvoltage Threshold
VOP rising
VOP Supply Current
No load
19
18
V
20
21
V
3
5
mA
_______________________________________________________________________________________ 3
MAX17115
ELECTRICAL CHARACTERISTICS (continued)
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = +5V, Circuit of Figure 1, VVOP = +16V, VVGH = 30V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.)
MAX
UNITS
VOP Input Offset Voltage
PARAMETER
VOPI = VVOP/2
CONDITIONS
-14
+14
mV
OPI Input-Bias Current
VOPO, VOPI = VVOP /2, TA = +25°C
-50
+50
nA
0
VVOP
V
Input Common-Mode
Voltage Range
MIN
VVOP
- 100
TYP
VVOP
- 40
OPO Output Voltage High
IOPO = +5mA, VOPI = VVOP
OPO Output Voltage Low
IOPO = -5mA, VOPI = 0V
40
Slew Rate
20% to 80% of VVOP, CLOAD = 10pF, RLOAD = 10kW
45
V/µs
-3dB Bandwidth
CLOAD = 10pF, RLOAD = 10kW
20
MHz
Short-Circuit Current
Power-Supply Rejection Ratio
Sourcing, VOPI = VVOP - 3V, VOPO = VVOP - 4V
100
200
Sinking, VOPI = 3V, VOPO = 4V
100
200
DC,10V P VVOP P 18V
60
VDET falling, VIN = 5V
1.22
mV
100
mV
mA
dB
XAO FUNCTION
VDET Threshold
VDET Hysteresis
1.24
1.26
50
VDET Input-Bias Current
VVDET = 0V or 5V, TA = +25°C
XAO Output Voltage
VVDET = 0V, IXAO = 10mA
-1
0.1
V
mV
+1
µA
0.4
V
HIGH-VOLTAGE STRESS MODE
HVS_EN Input Low Voltage
0.8
HVS_EN Input High Voltage
2.1
HVS_EN Pulldown Resistance
300
RHVS Output Voltage
(Note 1)
RHVS Leakage Current
VRHVS = 6V, VHVS_EN = 0V, TA = +25°C
RHVS On-Resistance
VHVS_EN = 5V, IRHVS = 10mA
V
V
6
kI
6
V
20
µA
W
0.6
V
CONTROL INPUTS
Input Low Voltage [EN, FREQ]
Input High Voltage [EN, FREQ]
VIN = 2.5V to 6V
VIN = 4.5V to 6V
2.4
VIN = 2.5V to 4.5V
1.9
TA = +25°C
-1
Hysteresis [EN, FREQ]
Input-Bias Current [EN]
V
0.15
V
+1
µA
ELECTRICAL CHARACTERISTICS
(VIN = VEN = +5V, Circuit of Figure 1, VVOP = +16V, VVGH = 30V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
IN Input Supply Range
(Note 1)
2.5
6.0
V
IN Undervoltage Lockout
VIN rising, hysteresis = 200mV
2.0
2.5
V
IN Quiescent Current
VFB = 1.3V, LX not switching
1
VFB = 1.2V, switching
5
4 _______________________________________________________________________________________
mA
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
(VIN = VEN = +5V, Circuit of Figure 1, VVOP = +16V, VVGH = 30V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-VOLTAGE LDO
VREF_I Input-Voltage Range
VREF_I Undervoltage Lockout
18
V
VREF_I rising
10
5.8
V
µA
VREF_I Input-Bias Current
No load
250
VREF_O Dropout Voltage
IVREF_O = 30mA, VREFI - VREFO
0.5
V
VREF_FB
Regulation Voltage
1mA ≤ IVREF_O ≤ 30mA
1.23
1.25
V
10V < VVREF_I < 18V, IVREF_O = 20mA, VVREF_O = 9V
-0.9
+0.9
mV/V
VREF_O Maximum Output
Current
40
mA
STEP-UP REGULATOR
Output-Voltage Range
VIN
18
1.228
1.252
V
0.15
%/V
V
FB Regulation Voltage
No load
FB Line Regulation
VIN = 2.5V to 6V
FB Transconductance
ICOMP = ±2.5µA
80
550
µS
VFB = 1.2V, duty cycle = 75%
3.9
5.4
A
LX SWITCH
LX Current Limit
LX On-Resistance
VIN = 5V
0.2
VIN = 3V
0.26
Current-Sense Transresistance
0.08
0.25
W
V/A
OSCILLATOR
Frequency
VFREQ = 0V
500
780
VFREQ = 5V
1000
1400
kHz
FREQ Pulldown Current
VFREQ = 5V
3
9
µA
Maximum Duty Cycle
VFREQ = 0V or 5V
89
96
%
SOFT-START
SS Reset Resistance
VEN = 0V, ISS = 10mA
SS Charge Current
VSS = 1.2V
20
W
6
µA
4
6
µA
1.21
1.27
20
V
W
0.7
V
2
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
VDPM Capacitor Charge Current
MLG startup, VVDPM = 0V
VDPM Turn-On Threshold
VDPM rising
VDPM Pulldown Resistance
IVDPM = 10mA
VFLK Input Low Voltage
VIN = 2.5V to 6V
VFLK Input High Voltage
2.5V < VIN < 4.5V
4.5V < VIN < 6V
VGH Input-Voltage Range
1.9
V
2.3
35
V
VVDPM = 1.5V, VFLK = IN
450
VVDPM = 1.5V, VFLK = AGND
350
VGH-to-VGHM Resistance
VVDPM = 1.5V, VVFLK = 5V, I = 10mA
15
W
VGHM-to-DRN Resistance
VVDPM = 1.5V, VVFLK = 0V, I = 10mA
60
W
VGH Input Current
µA
_______________________________________________________________________________________ 5
MAX17115
ELECTRICAL CHARACTERISTICS (continued)
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = +5V, Circuit of Figure 1, VVOP = +16V, VVGH = 30V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SERIES SWITCH GATE DRIVER
GATE Output Sink Current
VGATE = 5V
8
VGATE = 0V
10
GATE Done Voltage Threshold
GATE falling
GATE Output Voltage Low
IGATE = 1mA
GATE Output Voltage High
IGATE = -1mA, VEN = 0V
12
µA
mA
0.5
V
0.05
V
VIN 0.05
V
OPERATIONAL AMPLIFIER
VOP Supply Range
VOP Overvoltage Threshold
VOP rising
VOP Supply Current
No load
VOP Input Offset Voltage
VOPI = VVOP/2
Input Common-Mode
Voltage Range
6
18
V
19
21
V
5
mA
-14
+14
mV
0
VVOP
V
VVOP
- 100
OPO Output Voltage High
IOPO = +5mA, VOPI = VVOP
OPO Output Voltage Low
IOPO = -5mA, VOPI = 0V
Sourcing, VOPI = VVOP - 3V, VOPO = VVOP - 4V
100
Sinking, VOPI = 3V, VOPO = 4V
100
DC, 10V P VVOP P 18V
60
VDET Threshold
VDET falling, VIN = 5V
1.22
XAO Output Voltage
VVDET = 0V, IXAO = 10mA
Short-Circuit Current
Power-Supply Rejection Ratio
mV
100
mV
mA
dB
XAO FUNCTION
1.26
V
0.4
V
0.8
V
HIGH-VOLTAGE STRESS MODE
HVS_EN Input Low Voltage
HVS_EN Input High Voltage
2.1
HVS_EN Pulldown Resistance
RHVS Output Voltage
RHVS On-Resistance
V
300
kI
(Note 1)
6
VHVS_EN = 5V, IRHVS = 10mA
20
W
0.6
V
V
CONTROL INPUTS
Input Low Voltage [EN, FREQ]
Input High Voltage [EN, FREQ]
VIN = 2.5V to 6V
VIN = 4.5V to 6V
2.4
VIN = 2.5V to 4.5V
1.9
Note 1: For 5.5V < VIN < 6.0V, use IC for no longer than 1% of IC lifetime. For continuous operation, input voltage should not
exceed 5.5V.
Note 2: Specifications to TA = -40NC are guaranteed by design, not production tested.
6 _______________________________________________________________________________________
V
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
POWER-UP SEQUENCE
VSUP = 5.0V
85
EFFICIENCY (%)
80
75
MAX17115 toc02
MAX17115 toc01
90
A
0V
B
RLOAD = 47I
VSUP = 3.3V
70
0V
65
C
60
0V
D
0V
0V E
F
0V
55
50
45
100
LOAD CURRENT (mA)
10
1000
A: VSUP, 5V/div
B: VLX, 10V/div
C: VMAIN, 10V/div
IN SUPPLY QUIESCENT CURRENT
vs. IN VOLTAGE
STEP-UP REGULATOR OUTPUT
LOAD REGULATION vs. LOAD CURRENT
CURRENT (mA)
SWITCHING
2
NONSWITCHING
0.4
LOAD REGULATION ERROR (%)
MAXX17115 toc03
3
1
10ms/div
D: VVREF_O, 10V/div
E: VVDPM, 2V/div
F: VVGHM, 20V/div
MAXX17115 toc04
40
VSUP = 5V
0.2
0
-0.2
-0.4
-0.6
-0.8
0
2.5
3.0
3.5
4.0
4.5
IN VOLTAGE (V)
5.0
-1.0
5.5
10
REFERENCE VOLTAGE OUTPUT
LOAD REGULATION vs. LOAD CURRENT
0
-0.20
-0.40
MAXX17115 toc06
0.10
LINE REGULATION ERROR (%)
0.20
1000
REFERENCE VOLTAGE OUTPUT
LINE REGULATION (%)
MAXX17115 toc05
LOAD REGULATION ERROR (%)
0.40
100
LOAD CURRENT (mA)
0.05
0
-0.05
-0.60
-0.80
0
20
40
60
LOAD CURRENT (mA)
80
-0.10
15
16
17
18
VVREF_I VOLTAGE (V)
19
20
_______________________________________________________________________________________ 7
MAX17115
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 5V, VMAIN = 16V, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 5V, VMAIN = 16V, TA = +25NC, unless otherwise noted.)
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE
STEP-UP REGULATOR SOFT-START
(HEAVY LOAD)
MAX17115 toc08
MAX17115 toc07
LOAD CURRENT
1A/div
50mA
VSUP
2V/div
0V
VGATE
2V/div
0V
VMAIN
10V/div
0V
INDUCTOR
CURRENT
1A/div
0A
RLOAD = 47I
2ms/div
STEP-UP REGULATOR
LOAD-TRANSIENT RESPONSE
0V
VMAIN
(AC-COUPLED)
200mV/div
INDUCTOR
CURRENT
1A/div
0A
10µs/div
POWER-UP SEQUENCE
MAX17115 toc09
MAX17115 toc10
RLOAD = 47I
LOAD CURRENT
500mA/div
50mA
A
0V
B
0V
C
0V
D
0V
0V
VMAIN
(AC-COUPLED)
200mV/div
INDUCTOR
CURRENT
2A/div
0A
0V E
F
0V
100µs/div
10ms/div
A: VSUP, 5V/div
D: VVREF_O, 10V/div
E: VVDPM, 2V/div
B: VLX, 10V/div
C: VMAIN, 10V/div F: VVGHM, 20V/div
OPERATIONAL AMPLIFIER
FREQUENCY RESPONSE
OPERATIONAL AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
MAX17115 toc12
MAXX17115 toc11
4
2
VVOP = 10V
VOPI
2V/div
0
GAIN (dB)
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
NO LOAD
-2
2V
-4
VOPO
2V/div
100pF LOAD
-6
-8
2V
-10
100
1000
10,000
FREQUENCY (Hz)
100,000
100ns/div
8 _______________________________________________________________________________________
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
OPERATIONAL AMPLIFIER
RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
MAX17115 toc14
MAX17115 toc13
VVOP = 10V
VOPI
100mV/div
(AC-COUPLED)
0V
VOPI
5V/div
0V
VOPO
5V/div
0V
VOPO
100mV/div
(AC-COUPLED)
0V
4µs/div
40ns/div
OPERATIONAL AMPLIFIER
LOAD-TRANSIENT RESPONSE
MAX17115 toc15
VOPO
(AC-COUPLED)
1V/div
0V
0mA
IOPO
100mA/div
400ns/div
_______________________________________________________________________________________ 9
MAX17115
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 5V, VMAIN = 16V, TA = +25NC, unless otherwise noted.)
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
Pin Description
PIN
NAME
FUNCTION
1
VREF_FB
High-Voltage LDO Regulator Feedback Input. Connect VREF_FB to the center of a resistive voltagedivider between VREF_O and AGND to set the LDO output voltage. Place the resistive voltage-divider within 5mm of VREF_FB.
2
VREF_O
High-Voltage LDO Regulator Output. Bypass VREF_O to AGND with a minimum 2.2FF capacitor
within 5mm of the pin.
3
VREF_I
High-Voltage LDO Regulator Supply Input. Bypass VREF_I to AGND with a minimum 1FF capacitor
within 5mm of the pin.
4
VOP
Operational Amplifier Supply Input. Typically connected to the output of the step-up regulator.
Bypass VOP to OPGND with a minimum 1FF capacitor within 5mm of the pin.
5
OPO
Operational Amplifier Output. OPO is high impedance in shutdown.
6
OPI
Operational Amplifier Noninverting Input
7
OPGND
Operational Amplifier Ground
8
VFLK
High-Voltage Switch Control Input. When VFLK is high, the high-voltage switch between VGH and
VGHM is on and the high-voltage switch between VGHM and DRN is off. When VFLK is low, the
switch between VGH and VGHM is off and the switch between VGHM and DRN is on. VFLK is inhibited by the IN UVLO and when the voltage on VDPM is less than 1.24V.
9
XAO
Reset and XAO Function Output
10
VDET
Voltage-Detection Input. Connect VDET to the center of a resistive voltage-divider between IN and
AGND to set the threshold voltage for the XAO function.
11
HVS_EN
12
FREQ
13
EN
14, 26
AGND
High-Voltage Stress Control Input. When HVS_EN is high, the internal switch between RHVS and
AGND is on. When HVS_EN is low, RHVS is high impedance.
Frequency-Select Input. Connect FREQ to AGND to select the step-up regulator’s 640kHz operating
frequency. Connect FREQ to IN to select the step-up regulator’s 1.2MHz operating frequency. This
input has 6FA pulldown current.
Shutdown Control Input. Connect EN to AGND to disable the boost operation. Connect EN to IN to
enable the boost operation.
Analog Ground
15, 16
IN
Power-Supply Input. IN supplies the internal reference and other internal circuitry. Connect IN to the
input supply voltage and bypass IN to AGND with a minimum 1FF ceramic capacitor. (Pin 15 supplies current to internal analog circuits. Using an RC filter on pin 15 improves noise performance of
the IC. Minimum resistor should be used on pin 16 due to high current through pin 16.)
17
GATE
External p-Channel MOSFET Gate-Drive Output. If used, connect GATE to the gate of an external
p-channel MOSFET between the input supply and the step-up converter’s inductor (see Figure 1). If
not used, leave GATE unconnected.
18, 19
LX
Step-Up Regulator Switching Node. Drain of the internal n-channel MOSFET between LX and PGND.
Connect the inductor and catch diode here and minimize trace area for lowest EMI.
20, 21
PGND
22, 28
N.C.
23
RHVS
24
FB
Power Ground. Source of the internal n-channel MOSFET between LX and PGND.
No Connection. Not internally connected.
Open-Drain Output of the Internal n-Channel MOSFET to AGND. Connect RHVS to FB through a
resistor to adjust the step-up converter’s output to a higher voltage. If unused, leave RHVS unconnected. When HVS_EN is low, RHVS is high impedance. When HVS_EN is logic-high, RHVS connects to AGND.
Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between
the step-up regulator output and AGND to set the regulator’s output voltage. Place the resistive
voltage-divider within 5mm of FB.
10
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Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
PIN
NAME
FUNCTION
25
COMP
Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND. Typical values are
47.5kI and 560pF.
27
SS
Soft-Start Control Pin. Connect a capacitor (CSS) to this pin. Leave SS unconnected if a slow soft-start is
not desired. The soft-start capacitor is charged by a 4FA current source. The full current limit is reached
after around t = CSS x 200Fs/nF. The soft-start capacitor is discharged to AGND when EN is low. On EN’s
rise, the soft-start capacitor is quickly charged to 0.4V, after which, soft-start begins.
29
VDPM
High-Voltage Switch Delay Input. Connect a capacitor from VDPM to AGND to set the high-voltage
switch startup delay.
30
VGH
High-Voltage Switch Supply Input. Source of the internal high-voltage p-channel MOSFET between
VGH and VGHM. Bypass VGH to PGND with a minimum of 0.1FF capacitor within 5mm of VGH.
31
VGHM
High-Voltage Switch Output. VGHM is the common junction of the internal high-voltage MOSFETs.
VGHM is typically used to power the gate-driver IC’s positive supply input.
32
DRN
—
EP
High-Voltage Switch Input. Drain of the internal high-voltage MOSFET switch between DRN and
VGHM.
Exposed Pad. Connect EP to AGND.
______________________________________________________________________________________ 11
MAX17115
Pin Description (continued)
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
390ω
VGOFF
-6.8V/20mA
VSUP
4.5V TO 5.5V
6.8V
0.1µF
0.1µF
0.1µF
0.1µF
D2
C1
10µF
6.3V
D3
L1
3µH
Q1
C2
10µF
6.3V
GATE
D1
R1
137kω
LX
VMAIN
16V/500mA
C4
10µF
25V
C3
10µF
25V
FB
R4
5.6ω
VIN
R2
11.5kω
IN
C5
1µF
PGND
R4
47.5kω
COMP
560pF
VGON
30V/20mA
0.1µF
AGND
OPEN
EN
SS
33nF
R3
150kω
FREQ
VIN
RHVS
HVS_EN
VGON
VGH
0.1µF
VGHM
VMAIN
VOP
1µF
MAX17115
OPGND
DRN
1kω
OPO
TO VCOM
BACKPLANE
150kω
FROM
TCON
VFLK
OPI
VREF_I
VDPM
33nF
VREF_O
VIN
2.2µF
20kω
TO GATE
DRIVER
100kω
VMAIN
1µF
R5
10kω
VREF_FB
XAO
R6
10kω
VGAMMA
15V/20mA
VSUP
110kω
VDET
EP
Figure 1. Typical Operating Circuit
12
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100kω
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
REFERENCE
DESIGNATION
REFERENCE
DESIGNATION
DESCRIPTION
C1, C2
10FF, 6.3V X5R ceramic capacitors
(0805)
TDK C2012X5R0J106K
C3, C4
10FF, 25V X5R ceramic capacitors
(1206)
TDK C3216X5R1E106M
D1
D2, D3
3A, 30V Schottky diode (M-flat)
Toshiba CMS02
DESCRIPTION
200mA, 100V dual diodes (SOT23)
Fairchild MMBD4148SE
L1
3.0FH, 3A inductor
Sumida CDRH6D28-3R0
Q1
SC-70 SiA443DJ, p-channel MOSFET,
-20V/63mI
Vishay PowerPak
Table 2. Component Suppliers
PHONE
FAX
Fairchild Semiconductor
SUPPLIER
847-803-6100
847-390-4405
www.fairchildsemi.com
Sumida Corp.
408-822-2000
408-822-2102
www.sumida.com
TDK Corp.
847-545-6700
847-545-6720
www.component.tdk.com
Toshiba America Electronic Components, Inc.
949-455-2000
949-859-3963
www.toshiba.com/taec
Vishay
402-563-6866
402-563-6296
www.vishay.com
Typical Operating Circuit
The MAX17115 typical operating circuit (Figure 1) is a
complete power-supply system for TFT LCD displays.
The circuit generates a +16V/500mA source-driver supply and +30V/20mA and -6.8V/20mA gate-driver supplies. The input-voltage range for the IC is from +2.5V to
+6.0V. The listed load currents in Figure 1 are available
from a +4.5V to +5.5V supply. Table 1 lists some recommended components, and Table 2 lists the contact
information of component suppliers.
Detailed Description
The MAX17115 contains a high-voltage step-up regulator, a high-accuracy linear regulator, a high-performance
amplifier, a high-voltage switch control block for gatedriver supply modulation, and a logic-controlled opendrain MOSFET switch to AGND for high-voltage stress
aging tests. Figure 2 shows the MAX17115 functional
diagram.
WEBSITE
Step-Up Regulator
The main step-up regulator employs a current-mode,
fixed-frequency (1.2MHz/640kHz-selectable) PWM architecture to maximize loop bandwidth and provides fasttransient response to pulsed loads typical of TFT-LCD
panel source drivers. High switching frequency operation allows the use of low-profile inductors and ceramic
capacitors to minimize the thickness of LCD panel
designs. A current-control external capacitor-controlled
programmable soft-start minimizes inrush currents. The
output voltage can be set from VIN to 18V with an external resistive voltage-divider.
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
V
-V
D ≈ MAIN IN
VMAIN
______________________________________________________________________________________ 13
MAX17115
Table 1. Component List
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
VGON
VGOFF
VIN
VMAIN
LX
GATE
FB
STEP-UP
CONTROLLER
IN
PGND
EN
AGND
COMP
FREQ
IN
OSCILLATOR
SS
SOFT-START
RHVS
HVS_EN
VGH
VOP
SWITCH
CONTROL
VGHM
OPO
DRN
OPGND
VFLK
OPI
VREF_I
VDPM
VREF_O
LINEAR
REGULATOR
MAX17115
VREF_FB
XAO
REF
VDET
EP
Figure 2. MAX17115 Functional Diagram
14
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Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
the MOSFET. Since the inductor current is continuous,
a transverse potential develops across the inductor that
turns on the boost diode (D1). The voltage across the
inductor then becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp back
down, transferring the energy stored in the magnetic
field to the output capacitor and the load. The MOSFET
remains off for the rest of the clock cycle.
On the rising edge of the internal clock, the controller sets
a flip-flop, turning on the n-channel MOSFET and applying the input voltage across the inductor. The current
through the inductor ramps up linearly, storing energy in
its magnetic field. Once the sum of the current-feedback
signal and the slope compensation exceeds the COMP
voltage, the controller resets the flip-flop and turns off
The MAX17115 has one operational amplifier. The buffer
amplifier is typically used to drive the LCD backplane
voltage (VCOM) in TFT LCDs. It features high output current, 45V/Fs slew rate, and 20MHz/3dB bandwidth. The
rail-to-rail input and output capability maximizes system
flexibility.
Operational Amplifier
LX
CLOCK
LOGIC
AND
DRIVER
PGND
ILIM
COMPARATOR
IN
SS
SOFT-START
SLOPE COMP
PWM
COMPARATOR
C
FREQ
CURRENT
SENSE
OSCILLATOR
TO FAULT
LOGIC
ERROR AMP
1.00V
FB
FAULT
COMPARATOR
1.24V
COMP
Figure 3. Step-Up Regulator Functional Diagram
______________________________________________________________________________________ 15
MAX17115
Figure 3 shows the functional diagram of the step-up
regulator. An error amplifier compares the signal at FB
to 1.24V and changes the COMP output. The voltage at
COMP sets the peak inductor current. As the load varies, the error amplifier sources or sinks current to the
COMP output accordingly to produce the inductor peak
current necessary to service the load. To maintain stability at high duty cycles, a slope-compensation signal is
summed with the current-sense signal.
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
Short-Circuit Current Limit
The operational amplifier limits short-circuit current to
approximately Q200mA if the output is directly shorted to
VOP or to OPGND. If the short-circuit condition persists,
the junction temperature of the IC rises until it reaches
the thermal-shutdown threshold (+160NC typ) and activates the thermal-fault protection, shutting off all the IC’s
outputs. The IC restarts automatically when the device
cools down by approximately 15NC.
Driving a Pure Capacitive Load
In general, the LCD backplane (VCOM) consists of a distributed series capacitance and resistance, a load that
can be easily driven by the buffer. However, if the buffer
is used in an application with a pure capacitive load,
steps must be taken to ensure stable operation.
As the buffer amplifier’s capacitive load increases, the
amplifier’s bandwidth decreases and gain peaking
increases. A 5I to 50I small resistor placed between
OPO and the capacitive load reduces peaking, but also
reduces the gain. An alternative method of reducing
peaking is to place a series RC network (snubber) in parallel with the capacitive load. The RC network does not
continuously load the output or reduce the gain. Typical
values of the resistor are between 100I and 200I, and
the typical value of the capacitor is 10nF.
Undervoltage Lockout (UVLO)
The UVLO circuit compares the input voltage at IN with
the UVLO threshold (2.25V typ) to ensure the input
voltage is high enough for reliable operation. The wide
200mV (typ) hysteresis prevents supply transients from
causing a restart. The startup procedure begins when
the input voltage exceeds the UVLO rising threshold and
EN goes above threshold. During normal operation, if
the input voltage falls below the UVLO falling threshold,
the controller turns off the main step-up regulator, turns
off the linear regulator, pulls GATE high to turn off the
external p-channel MOSFET, disables the buffer, placing its output into a high-impedance state, and disables
the switch control block, placing VGHM into a highimpedance state.
High-Accuracy High-Voltage
LDO Regulator
The LDO features high output accuracy (Q0.5%) and
low-dropout (LDO) voltage (0.25V typ) and can supply at
least 40mA. The LDO is typically used to drive a gamma
buffer reference resistor string and its output voltage is
adjustable through a resistor-divider.
Power-Up Sequence and Soft-Start
Once IN exceeds its UVLO (2.25V typ) and EN is above
its logic-high threshold, the startup procedure begins.
GATE is initially high and pulled low to turn on the external p-channel MOSFET if no output fault is detected.
After GATE reaches its GATE-done threshold, the main
step-up regulator’s soft-start begins. With the main stepup regulator’s soft-start, the voltage on VOP and VREF_I
rises. Once VOP or VREF_I exceeds the UVLO, the
relative buffer amplifier and LDO are enabled. Figure 4
shows the power-up sequence.
The IC employs a current-based, external-capacitor
adjustable soft-start for the step-up regulator to control
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. The voltage level on the
SS pin directly controls an internal current limit. The current limit reaches its full current limit at approximately:
t = CSS x 200Fs/nF
The step-up regulator output voltage usually reaches
regulation before CSS reaches its fully charged state.
A capacitor (CVDPM) from VDPM to AGND determines
the switch-control-block startup delay. After the soft-start
routine is complete, a 5FA current source starts charging
CVDPM. Once the capacitor voltage exceeds 1.24V (typ),
the switch-control block is enabled as shown in Figure
4. After the switch-control block is enabled, VGHM can
be connected to VGH or DRN through the internal highvoltage p-channel switches, depending upon the state of
VFLK. Before startup (EN is low) or when IN is less than its
UVLO, both VGHM switches are turned off and VDPM is
internally connected to AGND to discharge CVDPM. Select
CVDPM to set the delay time using the following equation:
C VDPM =DELAY_TIME ×
5FA
1.24V
Switch-Control Block
The switch-control block is not activated until all four of
the following conditions are satisfied:
U The input voltage exceeds its UVLO.
U The soft-start routine of the boost regulator is
complete.
U No fault condition is detected.
U VVDPM exceeds its turn-on threshold. VDPM begins
charging when SS reaches the internal threshold.
Once activated, if VFLK is high, the 5I (typ) internal
p-channel switch between VGH and VGHM turns on
and the 30I (typ) p-channel switch between VGHM
16
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Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
IN UVLO
TIME
VEN
VTH > 2.1V
TIME
VGATE
TIME
VSS
SS DONE
0.4V
TIME
VMAIN
VGON
TIME
VGOFF
VVREF_O
5.4V
TIME
VGHM DEPENDS ON VFLK
VVGHM
VGHM IS FLOATING
VVDPM
1.24V
STARTUP SOFT-START
PROCEDURE BEGINS
BEGINS
SOFT-START
ENDS
TIME
Figure 4. Power-Up Sequence
______________________________________________________________________________________ 17
MAX17115
VIN
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
and DRN turns off. If VFLK is low, the 5I (typ) internal
p-channel switch between VGH and VGHM turns off
and the 30I (typ) p-channel switch between VGHM
and DRN turns on. Before activation, neither switch is
turned on and VGHM is in a high-impedance state.
Fault Protection
During steady-state operation, if the output of the main
regulator does not exceed its respective fault-detection
threshold, the MAX17115 activates an internal fault timer.
If the continuous fault exceeds the fault-timer duration
(55ms typ), the MAX17115 sets the fault latch to shut
down all the outputs and turn off the external p-channel
MOSFET (GATE is pulled high). Once the fault condition
is removed, cycle the input voltage to clear the fault latch
and reactivate the device.
The MAX17115 also provides OVP for the output of the
step-up regulator by monitoring the voltage on the VOP
pin. During normal operation, if VOP is higher than the
VOP overvoltage threshold (20V typ), the step-up converter stops switching to prevent excessive voltage from
damaging the MAX17115. Once VOP drops below the
threshold voltage, the step-up regulator resumes switching and regulates the needed output voltage.
Thermal-Overload Protection
Thermal-overload protection prevents excessive power
dissipation from overheating the MAX17115. When the
junction temperature exceeds TJ = +160NC (typ), a thermal sensor immediately activates the fault protection to
shut down all outputs and turns off the external p-channel MOSFET (GATE is pulled high), allowing the device
to cool down. Once the device cools down by approximately 15NC, the MAX17115 starts up automatically. The
thermal-overload protection protects the controller in the
event of fault conditions. For continuous operation, do
not exceed the absolute maximum junction temperature
rating of TJ = +150NC.
High-Voltage Stress (HVS) Mode
The HVS mode is used to increase the supply voltage
of TFT LCD for aging tests. The MAX17115 provides an
internal open-drain switch to AGND that is typically used
to change the feedback divider impedance of the stepup regulator (FB). Connect an appropriate resistor from
RHVS to FB to implement this feature.
A control input (HVS_EN) determines when the switch
is turned on. When HVS_EN is high, the internal switch
is turned on and the output voltage is adjusted according to the resistor connected to the feedback input.
Conversely, when HVS_EN is low, the switch is turned
off and the output remains in its original voltage setting.
XAO Function
XAO is an open-drain output that connects to AGND whenever VIN is below its UVLO threshold (2.25V typ) or VVDET is
below its detection threshold (1.24V typ). In the meantime,
VGHM is tied to VGH. XAO is guaranteed to remain low
until VIN falls below the XAO UVLO level (1.7V max).
Design Procedure
Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating, and
series resistance are factors to consider when selecting the inductor. These factors influence the converter’s
efficiency, maximum output load capability, transientresponse time, and output-voltage ripple. Size and cost
are also important factors to consider.
The maximum output current, input voltage, output voltage, and switching frequency determine the inductor
value. Very high inductance values minimize the current
ripple and therefore reduce the peak current, which
decreases core losses in the inductor and conduction
losses in the entire power path. However, large inductor values also require more energy storage and more
turns of wire, which increase size and can increase conduction losses in the inductor. Low-inductance values
decrease the size, but increase the current ripple and
peak current. Finding the best inductor involves choosing the best compromise between circuit efficiency,
inductor size, and cost.
The equations used here include a constant, LIR, which
is the ratio of the inductor peak-to-peak ripple current
to the average DC inductor current at the full-load current. The best trade-off between inductor size and circuit
efficiency for step-up regulators generally has an LIR
between 0.3 and 0.6. However, depending on the AC
characteristics of the inductor core material and ratio
of inductor resistance to other power-path resistances,
the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extremely
thin high-resistance inductors are used, as is common
for LCD panel applications, the best LIR can increase to
between 0.5 and 1.0.
18
�������������������������������������������������������������������������������������
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
In Figure 1, the LCD’s gate-on and gate-off supply
voltages are generated from two unregulated charge
pumps driven by the step-up regulator’s LX node. The
additional load on LX must therefore be considered in
the inductance and current calculations. The effective
maximum output current, IMAIN(EFF) becomes the sum
of the maximum load current of the step-up regulator’s
output plus the contributions from the positive and negative charge pumps:
IMAIN(EFF) = IMAIN(MAX)+ ENEG x INEG +
(EPOS + 1) x IPOS
where IMAIN(MAX) is the maximum step-up output current, ENEG is the number of negative charge-pump stages, EPOS is the number of positive charge-pump stages,
INEG is the negative charge-pump output current, and
IPOS is the positive charge-pump output current, assuming the initial pump source for IPOS is VMAIN.
Using the typical operating circuit of Figure 1, calculate
the approximate inductor value using the typical input
voltage (VSUP), the maximum output current (IMAIN(EFF)),
the expected efficiency (ETYP) taken from an appropriate
curve in the Typical Operating Characteristics section,
and an estimate of LIR based on the above discussion:
The inductor’s saturation current rating and the
MAX17115’s LX current limit (ILIM) should exceed IPEAK,
and the inductor’s DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor
with less than 0.1I series resistance.
Considering Figure 1, the maximum load current
(IMAIN(MAX)) is 500mA, with a 16V output and a typical
input voltage of 5V. The effective full-load step-up current is:
IMAIN(EFF) = 500mA + 1O 20mA +
(1+1) O 20mA = 560mA
Considering the typical operating circuit, the switching
frequency is set to 1.2MHz, the maximum load current
(IMAIN(MAX)) is 500mA with a 16V output and a typical
input voltage of 5V. Choosing an LIR of 0.5 and estimating efficiency 88% at this operating point:
5V 2
16V - 5V
0.88
L=(
) (
)(
) ≈ 3.0FH
16V 0.56A × 1.2MHz 0.5
Using the circuit’s minimum input voltage (4.5V) and estimating efficiency of 83% at that operating point:
IIN(DC,MAX) =
The ripple current and the peak current are:
V
VMAIN -VSUP
η
L=( SUP )(
)( TYP )
VMAIN IMAIN(EFF) × fOSC LIR
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current
at the minimum input voltage (VSUP(MIN)) using conservation of energy and the expected efficiency at that
operating point (EMIN) taken from the appropriate curve
in the Typical Operating Characteristics:
IMAIN(EFF) × VMAIN
IIN(DC,MAX) =
VSUP(MIN) × ηMIN
IRIPPLE =
VSUP (MIN) × (VMAIN - VIN(MIN) )
L × VMAIN × fOSC
I
IPEAK =IIN(DC,MAX) + RIPPLE
2
4.5V × (16V-4.5V)
≈ 0.90A
3.0FH × 16V × 1.2MHz
IPEAK =2.40A +
0.90A
= 2.85A
2
Output-Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due
to the capacitor’s ESR:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR)
Calculate the ripple current at that operating point and
the peak current required for the inductor:
IRIPPLE =
0.56A × 16V
= 2.40A
4.5V × 0.83
V
I
−V
VRIPPLE(C) ≈ MAIN MAIN IN
C OUT VMAIN × fOSC
and:
VRIPPLE(ESR) ≈ IPEAK × R ESR(COUT)
where IPEAK is the peak inductor current (see the
Inductor Selection section). For ceramic capacitors,
______________________________________________________________________________________ 19
MAX17115
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
the output-voltage ripple is typically dominated by
VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injection
into the IC. Two 10FF ceramic capacitors are used in the
typical operating circuit (Figure 1) because of the high
source impedance seen in typical lab setups. Actual
applications usually have much lower source impedance since the step-up regulator often runs directly
from the output of another regulated supply. Typically,
CIN can be reduced below the values used in the typical operating circuit. Ensure a low-noise supply at IN by
using adequate CIN. Alternatively, greater voltage variation can be tolerated on CIN if IN is decoupled from CIN
using an RC lowpass filter (see R4 and C5 in Figure 1).
Loop Compensation
Choose RCOMP to set the high-frequency integrator gain
for fast-transient response. Choose CCOMP to set the
integrator zero to maintain loop stability. For low-ESR
output capacitors, use the following equations to obtain
stable performance and good transient response:
R COMP ≈
253 × VSUP × VOUT × C OUT
L × IMAIN(MAX)
C COMP ≈
VOUT × C OUT
10 × IMAIN(MAX) × R COMP
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient-response waveforms.
High-Voltage LDO Linear Regulator
Rectifier Diode
The MAX17115’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 3A Schottky diode
complements the internal MOSFET well.
Output-Voltage Selection
The output voltage of the high-accuracy LDO is set by
connecting a resistive voltage-divider from the output
(VREF_O) to AGND with the center tap connected to
VREF_FB (see Figure 1). Select R6 in the 10kI to 50kI
range. Calculate R5 with the following equation:
Step-Up Regulator Output-Voltage Selection
The output voltage of the main step-up regulator is set
by connecting a resistive voltage-divider from the output
(VMAIN) to AGND with the center tap connected to FB
(see Figure 1). Select R2 in the 10kI to 50kI range.
Calculate R1 with the following equation:
V
R5=R6 × ( VREF_O -1)
VVREF_FB
R1=R2 × (
VMAIN
-1)
VFB
where VFB, the step-up regulator’s feedback set point, is
1.24V. Place R1 and R2 close to the IC.
High-Voltage Stress (HVS)
Mode Output-Voltage Setting
See Figure 1 for the typical operating circuit. R3 is connected to FB to change the output voltage whenever
HVS_EN is high. The required value for R3 can be calculated with the following equation:
R1
R3=
VMAIN_HVS
R1
− (1 +
)
VFB
R2
where VVREF_FB, the LDO’s feedback set point, is 1.24V.
Place R5 and R6 close to the IC.
Input and Output Capacitor Selection
To ensure stability of the LDO, use a minimum of 1FF on
the regulator’s input (VREF_I) and a minimum of 2.2FF
on the regulator’s output (VREF_O). Place the capacitors near the pins and connect their ground connections
directly together.
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the IC package, PCB copper area,
other thermal mass, and airflow. More PCB copper, cooler ambient air, and more airflow increase the possible
dissipation, while less copper or warmer air decreases
the IC’s dissipation capability. The major components
of power dissipation include the power dissipated in the
step-up regulator and the power dissipated by the buffer
amplifier and high-voltage LDO.
20
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Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
PLX_ON = I 2 IN(DC,MAX) × R DSON × D
where RDSON is the on-resistance for the internal power
MOSFET.
Operational Amplifiers
The power dissipated in the buffer amplifier depends on
the output current, the output voltage, and the supply
voltage:
PD SOURCE = IOPO_SOURCE × (VVOP - VOPO )
PD SINK = IOPO_SINK × VOPO
where IOPO_SOURCE is the output current sourced by
the amplifier, and IOPO_SINK is the output current that
the amplifier sinks.
High-Voltage LDO Regulator
The power dissipation of the high-voltage LDO depends
on load current and the voltage drop between VREF_I and
VREF_O. It can be estimated by the following formula:
PLR=ILOAD × VDROP
where ILOAD is the output current from the LDO and
VDROP is the voltage drop between VREF_I and VREF_O.
PCB Layout and Grounding
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
U Minimize the area of high-current loops by placing
the inductor, the output diode, and the output capacitors near the input capacitors and near the LX and
PGND pins. The high-current input loop goes from the
positive terminal of the input capacitor to the inductor, to the IC’s LX pin, out of PGND, and to the input
capacitor’s negative terminal. The high-current output
loop is from the positive terminal of the input capacitor to the inductor, to the output diode (D1), and to the
positive terminal of the output capacitors, reconnecting between the output capacitor and input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in the
high-current paths. If vias are unavoidable, use many
vias in parallel to reduce resistance and inductance.
Create a power-ground island (PGND) consisting
of the input and output capacitor grounds, PGND
pin, and any charge-pump components. Connect
all these together with short, wide traces or a small
ground plane. Maximizing the width of the power
ground traces improves efficiency and reduces output voltage ripple and noise spikes. Create an analog
ground plane (AGND) consisting of the AGND pin, all
the feedback-divider ground connections, the operational amplifier divider ground connection, the COMP,
VDPM and SS capacitor ground connections, and the
device’s exposed backside pad. Connect the AGND
and PGND islands by connecting the PGND pin
directly to the exposed backside pad. Make no other
connections between these separate ground planes.
U Place all feedback voltage-divider resistors within
5mm of their respective feedback pins. The divider’s
center trace should be kept short. Placing the resistors far away causes their FB traces to become
antennas that can pick up switching noise. Take care
to avoid running any feedback trace near LX or the
switching nodes in the charge pumps, or provide a
ground shield.
U Place the IN pin bypass capacitors as close as possible to the device. The ground connection of the IN
bypass capacitor should be connected directly to the
AGND pin with a wide trace.
U Minimize the length and maximize the width of the
traces between the output capacitors and the load for
best transient response.
U Minimize the size of the LX node while keeping it wide
and short. Keep the LX node away from feedback
nodes (FB) and analog ground. Use DC traces to
shield necessary.
Refer to the MAX17115 evaluation kit for an example of
proper PCB layout.
______________________________________________________________________________________ 21
MAX17115
Step-Up Regulator
The largest portions of power dissipation in the stepup regulator are the internal MOSFET, the inductor,
and the output diode. If the step-up regulator has 90%
efficiency, approximately 3% to 5% of the power is lost
in the internal MOSFET, approximately 3% to 4% in the
inductor, and approximately 1% in the output diode.
The remaining 1% to 3% is distributed among the input
and output capacitors and the PCB traces. If the input
power is approximately 5W, the power loss in the internal
MOSFET is approximately 150mW to 250mW. The following formula can be used to estimate the power loss in
the internal power MOSFET (excluding switching losses):
MAX17115
Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
Document No.
32 TQFN
T-3255+4
21-0140
22
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Internal-Switch Boost Regulator and High-Voltage,
Low-Dropout Linear Regulator for TFT LCDs
REVISION
NUMBER
REVISION
DATE
0
7/09
Initial release
1
4/10
Added reflow temperature and removed a line in the fault-protection description
DESCRIPTION
PAGES
CHANGED
0
2, 4, 6, 18, 22
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010
Maxim Integrated Products
23
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX17115
Revision History
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