EVALUATION KIT AVAILABLE
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
General Description
The MAX17244 high-efficiency, synchronous step-down
DC-DC converter with integrated MOSFETs operates
over a 3.5V to 36V input voltage range with 42V input
transient protection. The device can operate in dropout
condition by running at 98% duty cycle. This converter
delivers up to 2.5A and generates fixed output voltages of
3.3V/5V, along with the ability to program the output
voltage between 1V to 10V.
The MAX17244 uses a current-mode control architecture.
The device can operate in the pulse-width modulation
(PWM) or pulse-frequency modulation (PFM) control
schemes. PWM operation provides constant frequency
operation at all loads, and is useful in applications sensitive
to switching frequency. PFM operation disables negative
inductor current and additionally skips pulses at light
loads for high efficiency. Under light-load applications,
the external sync pin FSYNC logic input allows the
device to operate either in PFM mode for reduced current
consumption or fixed-frequency FPWM (forced-PWM)
mode to eliminate frequency variation to minimize EMI.
Fixed-frequency FPWM mode is extremely useful for
power supplies designed for RF transceivers where tight
emission control is necessary.
This device is available in a compact 16-pin (5mm x 5mm)
TQFN package with exposed pad and 16-pin TSSOP.
-40°C to +85°C operation.
Applications
●● Distributed Supply Regulation
●● Wall Transformer Regulation
●● General-Purpose Point-of-Load
Benefits and Features
●● Eliminates External Components and Reduces
Total Cost
• Integrated High-Side and Low-Side Switch Enables
Synchronous Operation for High Efficiency and
Reduced Cost
• All-Ceramic Capacitor Solution Allows UltraCompact Solution Size
• 220kHz to 2.2MHz Adjustable Frequency with
External Synchronization
• Power Good Output and High-Voltage EN Input
Simplify Power Sequencing
●● Increases Design Flexibility
• 180° Out-of-Phase Clock Output at SYNCOUT
Enables Cascaded Power Supplies for Increased
Power Output
• Fixed Output Voltage with ±2% Accuracy (5V/3.3V)
or Externally Resistor Adjustable (1V to 10V)
●● Reduces Power Dissipation
• >90% Peak Efficiency
• PWM and PFM Operation Optimizes Conversion
Efficiency From Heavy to Light Loads
• Automatic LX Slew-Rate Adjustment for Optimum
Efficiency Across Operating Frequency Range
• Low 5μA (typ.) Shutdown Current
• Low 28μA (typ.) Quiescent Current
●● Operates Reliably
• 42V Input Voltage Transient Protection
• Fixed 8ms Internal Software Start Reduces Input
Inrush Current
• Cycle-by-Cycle Current Limit, Thermal Shutdown
with Automatic Recovery
• Reduced EMI Emission with Spread-Spectrum
Control
Ordering Information and Typical Application Circuit
appears at end of data sheet.
19-8526; Rev 1; 3/17
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Typical Application Circuit
VBAT
CIN1
CIN2
4.7µF
CIN3
4.7µF
RIN3
0Ω
SUP
BST
EN
OSC SYNC PULSE
CCOMP1
1000pF
RCOMP
20kΩ
CCOMP2
12pF
L1
2.2µH
LX
FSYNC
COMP
CBST
0.1µF
SUPSW
MAX17244
VOUT
OUT
RSYNCOUT
100Ω
PGOOD
SYNCOUT
PGND
RSNUB*
COUT
22µF
VBIAS
VOUT
FOSC
BIAS
D1
CSNUB*
FB
RFOSC
12kΩ
CBIAS
1µF
VBIAS
VOUT
5V AT 2.5A
RPGOOD
10kΩ
POWER-GOOD OUTPUT
180° OUT-OF-PHASE OUTPUT
AGND
*RSNUB = 1Ω and CSNUB = 220pF REQUIRED FOR THE FOLLOWING OPERATING CONDITIONS:
VBAT ≥ 25V, VOUT ≤ 5V, fSW ≥ 1.8MHz, PWM MODE ENABLED
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Maxim Integrated │ 2
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Absolute Maximum Ratings
SUP, SUPSW, EN to PGND...................................-0.3V to +42V
LX (Note 1).............................................................-0.3V to +42V
SUP to SUPSW.....................................................-0.3V to +0.3V
BIAS to AGND..........................................................-0.3V to +6V
SYNCOUT, FOSC, COMP, FSYNC,
PGOOD, FB to AGND.........................-0.3V to (VBIAS + 0.3V)
OUT to PGND........................................................-0.3V to +12V
BST to LX (Note 1)...................................................-0.3V to +6V
AGND to PGND....................................................-0.3V to + 0.3V
LX Continuous RMS Current....................................................3A
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (TA = +70°C)*
TSSOP (derate 26.1mw/NC above +70°C).............2088.8mW
TQFN (derate 28.6mw/°C above +70°C)................2285.7mW
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................ +260°C
*As per JEDEC51 standard (multilayer board).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 2)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA)........38.3°C/W
Junction-to-Ambient Thermal Resistance (θJC).............3°C/W
TQFN
Junction-to-Ambient Thermal Resistance (θJA)...........35°C/W
Junction-to-Ambient Thermal Resistance (θJC)..........2.7°C/W
Note 1: Self-protected against transient voltages exceeding these limits for ≤ 50ns under normal operation and loads up to the
maximum rated output current.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VSUP = VSUPSW = 14V, VEN = 14V, L1 = 2.2µH, CIN = 4.7µF, COUT = 22µF, CBIAS = 1µF, CBST = 0.1µF, RFOSC = 12kΩ,
TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
Supply Voltage
Line Transient Event Supply
Voltage
Supply Current
SYMBOL
CONDITIONS
VSUP, VSUPSW
VSUP_t_LT
ISUP_STANDBY
MIN
TYP
3.5
tt_LT < 1s
MAX
UNITS
36
V
42
V
Standby mode, no load, VOUT = 5V,
VFSYNC = 0V
28
40
µA
5
8
µA
Shutdown Supply Current
ISHDN
VEN = 0V
BIAS Regulator Voltage
VBIAS
VSUP = VSUPSW = 6V to 42V,
IBIAS = 0 to 10mA
4.7
5
5.4
V
VBIAS rising
2.95
3.15
3.40
V
BIAS Undervoltage-Lockout
Hysteresis
450
650
mV
Thermal Shutdown Threshold
+175
°C
Thermal Shutdown Threshold
Hysteresis
15
°C
BIAS Undervoltage Lockout
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VUVBIAS
Maxim Integrated │ 3
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Electrical Characteristics (continued)
(VSUP = VSUPSW = 14V, VEN = 14V, L1 = 2.2µH, CIN = 4.7µF, COUT = 22µF, CBIAS = 1µF, CBST = 0.1µF, RFOSC = 12kΩ,
TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VOUT_5V
VFB = VBIAS, 6V < VSUPSW < 36V,
MAX17244____A, fixed-frequency mode
4.9
5
5.1
VOUT_3.3V
VFB = VBIAS, 6V < VSUPSW < 36V,
MAX17244____B, fixed-frequency mode
3.234
3.3
3.366
4.9
5
5.15
3.234
3.3
3.34
UNITS
OUTPUT VOLTAGE (OUT)
FPWM Mode Output Voltage
(Note 3)
PFM-Mode Output Voltage
(Note 4)
VOUT_5V
VOUT_3.3V
No load, VFB = VBIAS,
MAX17244____A, PFM mode
VFB = VBIAS, 6V < VSUPSW < 36V,
MAX17244____B, PFM mode
V
V
Load Regulation
VFB = VBIAS, 300mA < ILOAD < 2.5A
0.5
%
Line Regulation
VFB = VBIAS, 6V < VSUPSW < 36V
0.02
%/V
IBST_ON
High-side MOSFET on,
VBST - VLX = 5V
IBST_OFF
High-side MOSFET off,
VBST - VLX = 5V, TA = +25°C
BST Input Current
LX Current Limit
ILX
ISKIP_TH
Spread Spectrum
High-Side Switch
On-Resistance
TA = +25°C
RON_H
200
Low-Side Switch
Leakage Current
3.75
2
mA
5
µA
4.5
A
ns
400
500
mA
100
220
mΩ
1
3
µA
1.5
3
Ω
fOSC ±6%
ILX = 1A, VBIAS = 5V
High-side MOSFET off, VSUP = 36V,
VLX = 0V, TA = +25°C
RON_L
1.5
4
Spread spectrum enabled
High-Side Switch Leakage
Current
Low-Side Switch
On-Resistance
3
RFOSC = 12kΩ
LX Rise Time
PFM-Mode Current Threshold
Peak inductor current
1
ILX = 0.2A, VBIAS = 5V
VLX = 36V, TA = +25°C
1
µA
TRANSCONDUCTANCE AMPLIFIER (COMP)
FB Input Current
IFB
FB Regulation Voltage
VFB
FB connected to an external resistordivider, 6V < VSUPSW < 36V (Note 5)
0.99
20
100
nA
1.0
1.015
V
FB Line Regulation
∆VLINE
6V < VSUPSW < 36V
0.02
%/V
Transconductance
(from FB to COMP)
gm
VFB = 1V, VBIAS = 5V
700
µS
Minimum On-Time
tON_MIN
(Note 4)
80
ns
Maximum Duty Cycle
DCMAX
98
%
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Maxim Integrated │ 4
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Electrical Characteristics (continued)
(VSUP = VSUPSW = 14V, VEN = 14V, L1 = 2.2µH, CIN = 4.7µF, COUT = 22µF, CBIAS = 1µF, CBST = 0.1µF, RFOSC = 12kΩ,
TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RFOSC = 73.2kΩ
340
400
460
kHz
RFOSC = 12kΩ
2.0
2.2
2.4
MHz
OSCILLATOR FREQUENCY
Oscillator Frequency
EXTERNAL CLOCK INPUT (FSYNC)
External Input Clock
Acquisition Time
1
tFSYNC
External Input Clock Frequency
RFOSC = 12kΩ (Note 6)
1.8
1.4
External Input Clock High
Threshold
VFSYNC_HI
VFSYNC rising
External Input Clock Low
Threshold
VFSYNC_LO
VFSYNC falling
tSS
5.6
Enable Input High Threshold
VEN_HI
2.4
Enable Input Low Threshold
VEN_LO
Soft-Start Time
Cycles
2.6
MHz
V
8
0.4
V
12
ms
ENABLE INPUT (EN)
Enable Threshold-Voltage
Hysteresis
Enable Input Current
0.6
0.2
VEN_HYS
IEN
V
TA = +25°C
V
0.1
1
µA
POWER GOOD (PGOOD)
PGOOD Switching Level
VTH_RISING
VFB rising, VPGOOD = high
93
95
97
VTH_FALLING
VFB falling, VPGOOD = low
90
92
94
10
25
50
µs
0.4
V
1
µA
PGOOD Debounce Time
%VFB
PGOOD Output Low Voltage
ISINK = 5mA
PGOOD Leakage Current
VOUT in regulation, TA = +25°C
SYNCOUT Low Voltage
ISINK = 5mA
0.4
V
SYNCOUT Leakage Current
TA = +25°C
1
µA
FSYNC Leakage Current
TA = +25°C
1
µA
OVERVOLTAGE PROTECTION
Overvoltage Protection
Threshold
Note
Note
Note
Note
Note
3:
4:
5:
6:
7:
VOUT rising (monitored at FB pin)
105
VOUT falling (monitored at FB pin)
102
%
Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
Device not in dropout condition.
Guaranteed by design; not production tested.
FB regulation voltage is 1%, 1.01V (max), for -40°C < TA < +105°C.
Contact the factory for SYNC frequency outside the specified range.
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Maxim Integrated │ 5
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Typical Operating Characteristics
(VSUP = VSUPSW = 14V, VEN = 14V, VOUT = 5V, VFYSNC = 0V, RFOSC = 12kΩ, TA = +25°C, unless otherwise noted.)
3.3V
50
5V
40
PWM MODE
5V
60
40
4.98
4.96
4.94
10
10
4.92
0.1
0
10
0.001
0
5.06
2.26
FSW (MHz)
5.00
4.98
4.96
433
2.22
2.20
2.18
429
426
4.90
2.10
2.0
2.5
0
0.5
ILOAD (A)
2.12
2.08
2.00
VOUT = 3.3V
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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0
0.5
1.0
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
50
12
42
72
RFOSC (kΩ)
2.0
2.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
45
40
35
30
25
20
5V/2.2MHz
PFM MODE
15
0.25
0
1.5
ILOAD (A)
SUPPLY CURRENT (µA)
2.16
2.04
425
2.5
MAX17244 toc08
VOUT = 5V
2.0
SWITCHING FREQUENCY vs. RFOSC
2.50
SWITCHING FREQUENCY (MHz)
2.20
MAX17244 toc07
2.24
VIN = 14V,
PWM MODE
1.5
ILOAD (A)
fSW vs. TEMPERATURE
2.28
1.0
VOUT = 3.3V
428
VOUT = 3.3V
427
1.5
2.5
430
2.12
1.0
2.0
431
2.14
0.5
1.5
VOUT = 5V
432
4.92
0
1.0
VIN = 14V,
PWM MODE
434
VOUT = 5V
2.16
2.2MHz
4.94
VIN = 14V,
PWM MODE
2.28
2.24
400kHz
5.02
0.5
fSW vs. LOAD CURRENT
435
FSW (MHz)
5.04
0
ILOAD (A)
fSW vs. LOAD CURRENT
2.30
MAX17244 toc04
VOUT = 5V, VIN = 14V
PWM MODE
5.08
4.90
10
2.2MHz
LOAD CURRENT (A)
VOUT LOAD REGULATION
5.10
0.1
MAX17244 toc05
0.001
MAX17244 toc03
5.00
20
0
400kHz
5.02
20
LOAD CURRENT (A)
VOUT (V)
PWM MODE
30
30
0
FSW (MHz)
5.04
3.3V
3.3V
50
5.06
MAX17244 toc06
3.3V
5V
70
VOUT = 5V, VIN = 14V
PFM MODE
5.08
MAX17244 toc09
60
PFM MODE
80
EFFICIENCY (%)
70
fSW = 400kHz, VIN = 14V
90
VOUT LOAD REGULATION
5.10
VOUT (V)
PFM MODE
5V
80
EFFICIENCY (%)
MAX17244 toc01
fSW = 2.2MHz, VIN = 14V
90
EFFICIENCY vs. LOAD CURRENT
100
MAX17244 toc02
EFFICIENCY vs. LOAD CURRENT
100
102
132
10
6
16
26
36
SUPPLY VOLTAGE (V)
Maxim Integrated │ 6
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Typical Operating Characteristics (continued)
(VSUP = VSUPSW = 14V, VEN = 14V, VOUT = 5V, VFYSNC = 0V, RFOSC = 12kΩ, TA = +25°C, unless otherwise noted.)
4.99
7
VBIAS (V)
6
5
4
3
2
0
6
12
4.96
4.95
4.94
18
24
30
4.91
4.90
36
SUPPLY VOLTAGE (V)
VOUT (V)
4.96
4.94
VIN = 14V,
PWM MODE
4.92
4.90
-40 -25 -10 5 20 35 50 65 80 95 110 125
4.97
30
36
42
10V/div
VIN
0V
VOUT
0V
5V/div
5V/div
0A
VPGOOD
5V/div
ILOAD
VPGOOD
30
24
MAX17244 toc15
1A/div
24
18
SLOW VIN RAMP BEHAVIOR
0V
5V/div
0V
4.99
18
12
10V/div
VOUT
12
6
VIN (V)
VIN
6
4.98
MAX17244 toc14
5.01
4.95
5.00
FULL-LOAD STARTUP BEHAVIOR
MAX17244 toc13
5V/400kHz
PWM MODE
ILOAD = 0A
5.03
5.04
TEMPERATURE (°C)
VOUT vs. VIN
5.05
5V/2.2MHz
PWM MODE
ILOAD = 0A
5.06
5.02
4.98
4.97
4.93
4.92
5V/2.2MHz
PFM MODE
1
ILOAD = 0A
5.01
5.00
VOUT vs. VIN
5.08
MAX17244 toc12
8
VBIAS vs. TEMPERATURE
VOUT (V)
9
SUPPLY CURRENT (µA)
5.02
MAX17244 toc11
SHDN CURRENT vs. SUPPLY VOLTAGE
MAX17244 toc10
10
0V
2A/div
0V
ILOAD
36
VIN (V)
2ms
SLOW VIN RAMP BEHAVIOR
SYNC FUNCTION
MAX17244 toc16
0A
4s
DIPS AND DROPS TEST
MAX17244 toc17
MAX17244 toc18
10V/div
10V/div
VIN
0V
VIN
5V/div
VLX
5V/div
0V
VPGOOD
VFSYNC
2V/div
0V
10V/div
VLX
0V
2A/div
ILOAD
4s
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0A
5V/div
VPGOOD
200ns
0V
5V/div
VOUT
0V
VOUT
5V/2.2MHz
5V/div
0V
10ms
Maxim Integrated │ 7
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Typical Operating Characteristics (continued)
(VSUP = VSUPSW = 14V, VEN = 14V, VOUT = 5V, VFYSNC = 0V, RFOSC = 12kΩ, TA = +25°C, unless otherwise noted.)
LINE TRANSIENT
LINE TRANSIENT
MAX17244 toc19
MAX17244 toc20
VIN
2V/div
VOUT
2V/div
VPGOOD
2V/div
0V
VOUT
5V/div
0V
0V
400ms
10V/div
VIN
100ms
LOAD TRANSIENT (PWM MODE)
SHORT CIRCUIT IN PWM MODE
MAX17244 toc21
MAX17244 toc22
fSW = 2.2MHz
VOUT = 5V
VOUT
(AC-COUPLED)
2V/div
200mV/div
2A/div
LOAD
CURRENT
VOUT
0V
INDUCTOR
CURRENT
0A
2A/div
0A
5V/div
PGOOD
100µs
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10ms
0V
Maxim Integrated │ 8
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
LX
SUPSW
SUP
EN
16 15 14 13 12 11 10
BST
EN
SUPSW
SUP
LX
LX
PGND
TOP VIEW
PGOOD
Pin Configuration
12
11
10
9
9
LX 13
PGND 14
MAX17244
MAX17244
PGOOD 15
EP
7
8
1
2
3
4
FSYNC
FOSC
OUT
FB
6
EP
+
BIAS
FOSC
5
SYNCOUT 16
AGND
FSYNC
4
FB
3
COMP
2
OUT
1
SYNCOUT
+
TSSOP
8
BST
7
AGND
6
BIAS
5
COMP
TQFN
Pin Descriptions
PIN
NAME
FUNCTION
TSSOP
TQFN
1
16
SYNCOUT
2
1
FSYNC
3
2
FOSC
Resistor-Programmable Switching Frequency Setting Control Input. Connect a resistor
from FOSC to AGND to set the switching frequency.
4
3
OUT
Switching Regulator Output. OUT also provides power to the internal circuitry when the
output voltage of the converter is set between 3V to 5V during standby mode.
5
4
FB
Feedback Input. Connect an external resistive divider from OUT to FB and AGND to set
the output voltage. Connect to BIAS to set the output voltage to 5V.
6
5
COMP
7
6
BIAS
8
7
AGND
9
8
BST
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Open-Drain Clock Output. SYNCOUT outputs 180N out-of-phase signal relative to the
internal oscillator. Connect to OUT with a resistor between 100Ω and 1kΩ for 2MHz
operation. For low frequency operation, use a resistor between 1kΩ and 10kΩ.
Synchronization Input. The device synchronizes to an external signal applied to FSYNC.
Connect FSYNC to AGND to enable PFM mode operation. Connect to BIAS or to an
external clock to enable fixed-frequency forced PWM mode operation.
Error Amplifier Output. Connect an RC network from COMP to AGND for stable operation.
See the Compensation Network section for more information.
Linear Regulator Output. BIAS powers up the internal circuitry. Bypass with a 1µF
capacitor to AGND.
Analog Ground
High-Side Driver Supply. Connect a 0.1µF capacitor between LX and BST for
proper operation.
Maxim Integrated │ 9
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Pin Descriptions (continued)
PIN
NAME
FUNCTION
9
EN
SUP Voltage Compatible Enable Input. Drive EN low to PGND to disable the device. Drive
EN high to enable the device.
11
10
SUP
Voltage Supply Input. SUP powers up the internal linear regulator. Bypass SUP to PGND
with a 4.7µF ceramic capacitor. It is recommended to add a placeholder for an RC filter to
reduce noise on the internal logic supply (see the Typical Application Circuit)
12
11
SUPSW
13, 14
12, 13
LX
15
14
PGND
16
15
PGOOD
Open-Drain, Active-Low Power-Good Output. PGOOD asserts when VOUT is above 95%
regulation point. PGOOD goes low when VOUT is below 92% regulation point.
—
—
EP
Exposed Pad. Connect EP to a large-area contiguous copper ground plane for effective
power dissipation. Do not use as the only IC ground connection. EP must be connected to
PGND.
TSSOP
TQFN
10
Internal High-Side Switch Supply Input. SUPSW provides power to the internal switch.
Bypass SUPSW to PGND with 0.1µF and 4.7µF ceramic capacitors.
Inductor Switching Node. Connect a Schottky diode between LX and PGND.
Power Ground
Detailed Description
The MAX17244 is a 2.5A current-mode, step-down
converter with integrated high-side and low-side
MOSFETs designed to operate with an external Schottky
diode for better efficiency. The low-side MOSFET enables
fixed-frequency forced-PWM (FPWM) operation under
light-load applications. The device operates with input
voltages from 3.5V to 36V, while using only 28FA
quiescent current at no load. The switching frequency is
resistor programmable from 220kHz to 2.2MHz and can
be synchronized to an external clock. The output voltage
is available as 5V/3.3V fixed or adjustable from 1V to 10V.
The wide input voltage range, along with the ability to
operate at 98% duty cycle during undervoltage transients,
makes this device ideal for many applications.
Under light-load applications, the FSYNC logic input
allows the device to either operate in PFM mode for
reduced current consumption or fixed-frequency PWM
mode to eliminate frequency variation to minimize EMI.
Fixed-frequency PWM mode is extremely useful for
power supplies designed for RF transceivers where tight
emission control is necessary. Protection features include
cycle-by-cycle current limit, overvoltage protection, and
thermal shutdown with automatic recovery. Additional
features include a power-good monitor to ease powersupply sequencing and a 180° out-of-phase clock output
relative to the internal oscillator at SYNCOUT to create
cascaded power supplies with multiple devices.
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Wide Input Voltage Range
This device includes two separate supply inputs (SUP and
SUPSW) specified for a wide 3.5V to 36V input voltage
range. VSUP provides power to the device and VSUPSW
provides power to the internal switch. When the device
is operating with a 3.5V input supply, conditions such as
cold crank can cause the voltage at SUP and SUPSW to
drop below the programmed output voltage. Under such
conditions, the device operates in a high duty-cycle mode
to facilitate minimum dropout from input to output.
In applications where the input voltage exceeds 25V,
output is ≤ 5V, operating frequency is ≥ 1.8MHz, and the
IC is selected to be in PWM mode by either forcing the
FSYNC pin high, or by using an external clock, pulse
skipping is observed on the LX pin. This happens due to
insufficient minimum on time.
Add optional RSNUB = 1Ω and CSNUB = 220pF to reduce
ringing on the LX pin. (see the Typical Application Circuit).
Maximum Duty-Cycle Operation)
The devices have a maximum duty cycle of 98% (typ).
The IC monitors the off-time (time for which the lowside FET is on) in both PWM and PFM modes every
switching cycle. Once the off-time of 25ns (typ) is detected
continuously for 12μs, the low-side FET is forced on for
150ns (typ) every 12μs. The input voltage at which the
device enters dropout changes depending on the input
voltage, output voltage, switching frequency, load current,
and the efficiency of the design.
Maxim Integrated │ 10
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
OUT
FB
COMP
FBSW
PGOOD
FBOK
EN
SUP
AON
BIAS
HVLDO
SWITCH
OVER
BST
SUPSW
EAMP
LOGIC
PWM
HSD
REF
LX
CS
SOFT
START
BIAS
LSD
MAX17244
PGND
SLOPE
COMP
SYNCOUT
OSC
FSYNC
FOSC
AGND
Figure 1. Internal Block Diagram
The input voltage at which the device enters dropout can
be approximated as:
VSUP =
VOUT + (I OUT × R ON_H )
100mA. In addition, the linear regulator turns on anytime
the output voltage is outside the 3V to 5.5V range.
Power-Good Output (PGOOD)
Note: The equation above does not take into account the
efficiency and switching frequency, but is a good first-order
approximation. Use the RON_H number from the max column
in the Electrical Characteristics table.
The devices feature an open-drain power-good output,
PGOOD. PGOOD asserts when VOUT rises above 95%
of its regulation voltage. PGOOD deasserts when VOUT
drops below 92% of its regulation voltage. Connect
PGOOD to BIAS with a 10kΩ resistor.
Linear Regulator Output (BIAS)
Overvoltage Protection (OVP)
0.98
The devices include a 5V linear regulator (BIAS) that
provides power to the internal circuit blocks. Connect a
1µF ceramic capacitor from BIAS to AGND. When the
output voltage is set between 3V and 5.5V, the internal
linear regulator only provides power until the output is in
regulation. The internal linear regulator turns off once the
output is in regulation and allows OUT to provide power
to the device. The internal regulator turns back on once
the external load on the output of the device is higher than
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If the output voltage reaches the OVP threshold, the highside switch is forced off and the low-side switch is forced
on until negative-current limit is reached. After negativecurrent limit is reached, both the high-side and low-side
switches are turned off. The MAX17244 offers a lower
voltage threshold for applications requiring tighter limits
of protection.
Maxim Integrated │ 11
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Synchronization Input (FSYNC)
FSYNC is a logic-level input useful for operating mode
selection and frequency control. Connecting FSYNC to
BIAS or to an external clock enables fixed-frequency
PWM operation. Connecting FSYNC to AGND enables
PFM mode operation.
The external clock frequency at FSYNC can be higher
or lower than the internal clock by 20%. Ensure the duty
cycle of the external clock used has a minimum pulse
width of 100ns. The MAX17244 synchronizes to the external
clock within one cycle. When the external clock signal
at FSYNC is absent for more than two clock cycles, the
device reverts back to the internal clock.
System Enable (EN)
An enable control input (EN) activates the device from its
low-power shutdown mode. EN is compatible with inputs
from automotive battery level down to 3.5V. The high
voltage compatibility allows EN to be connected to SUP,
KEY/KL30, or the inhibit pin (INH) of a CAN transceiver.
EN turns on the internal regulator. Once VBIAS is above
the internal lockout threshold, VUVL = 3.15V (typ), the
controller activates and the output voltage ramps up
within 8ms.
A logic-low at EN shuts down the device. During shutdown,
the internal linear regulator and gate drivers turn off.
Shutdown is the lowest power state and reduces the
quiescent current to 5µA (typ). Drive EN high to bring the
device out of shutdown.
Spread-Spectrum Option
The devices have an internal spread-spectrum option
to optimize EMI performance. This is factory set and
the S-version of the device should be ordered. For
spread-spectrum-enabled ICs, the operating frequency is
varied ±6% centered on FOSC. The modulation signal is
a triangular wave with a period of 110µs at 2.2MHz.
Therefore, FOSC will ramp down 6% and back to 2.2MHz
in 110µs and also ramp up 6% and back to 2.2MHz in
110µs. The cycle repeats.
For operations at FOSC values other than 2.2MHz, the
modulation signal scales proportionally (e.g., at 400kHz,
the 110µs modulation period increases to 110µs x
2.2MHz/400kHz = 605µs).
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The internal spread spectrum is disabled if the device is
synced to an external clock. However, the device does not
filter the input clock and passes any modulation (including
spread-spectrum) present on the driving external clock to
the SYNCOUT pin.
Automatic Slew-Rate Control on LX
The MAX17244 has automatic slew-rate adjustment
that optimizes the rise times on the internal HSFET gate
drive to minimize EMI. The IC detects the internal clock
frequency and adjusts the slew rate accordingly. When
the user selects the external frequency setting resistor
RFOSC such that the frequency is > 1.1MHz, the HSFET
is turned on in 4ns (typ). When the frequency is < 1.1MHz
the HSFET is turned on in 8ns (typ). This slew-rate control
optimizes the rise time on LX node externally to minimize
EMI while maintaining good efficiency.
Internal Oscillator (FOSC)
The switching frequency (fSW) is set by a resistor
(RFOSC) connected from FOSC to AGND. See Figure 3
to select the correct RFOSC value for the desired switching frequency. The RFOSC value is approximated by the
equation below:
19.05E15
R FOSC =
(710.8E3 × fsw − 26.8E9
For example, a 400kHz switching frequency is set with
RFOSC = 73.2kΩ. Higher frequencies allow designs
with lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gate
charge currents, and switching losses increase.
Synchronizing Output (SYNCOUT)
SYNCOUT is an open-drain output that outputs a 180°
out-of-phase signal relative to the internal oscillator.
Overtemperature Protection
Thermal-overload protection limits the total power
dissipation in the devices. When the junction temperature
exceeds 175°C (typ), an internal thermal sensor shuts
down the internal bias regulator and the step-down
controller, allowing the device to cool. The thermal
sensor turns on the device again after the junction
temperature cools by 15°C.
Maxim Integrated │ 12
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Applications Information
Setting the Output Voltage
Connect FB to BIAS for a fixed +5V/+3.3 output voltage.
To set the output to other voltages between 1V and 10V,
connect a resistive divider from output (OUT) to FB to
AGND (Figure 2). Use the following formula to determine
the RFB2 of the resistive divider network:
RFB2 = RTOTAL x VFB/VOUT
where VFB = 1V, RTOTAL = selected total resistance of
RFB1, RFB2 in Ω, and VOUT is the desired output in volts.
Calculate RFB1 (OUT to FB resistor) with the following
equation:
=
R FB1 R FB2 OUT − 1
FB
where VFB = 1V (see the Electrical Characteristics table).
PWM/PFM Modes
The MAX17244 offers a pin-selectable PFM mode or
fixed-frequency PWM mode option. The IC has an internal LS
MOSFET that turns on when the FSYNC pin is connected
to VBIAS or if there is a clock present on the FSYNC
pin. This enables the fixed-frequency-forced PWM mode
operation over the entire load range. This option allows
the user to maintain fixed frequency over the entire load
range in applications that require tight control on EMI.
Even though the devices have an internal LS MOSFET
for fixed-frequency operation, an external Schottky diode
is still required to support the entire load range. If the
FSYNC pin is connected to AGND, the PFM mode is
enabled on the device.
In PFM mode of operation, the converter’s switching
frequency is load dependent. At higher load current, the
switching frequency does not change and the operating
mode is similar to the PWM mode. PFM mode helps
improve efficiency in light-load applications by allowing
the converters to turn on the high-side switch only when
the output voltage falls below a set threshold. As such,
the converters do not switch MOSFETs on and off as
often as is the case in the PWM mode. Consequently,
the gate charge and switching losses are much lower in
PFM mode. Refer to the Rectifier Selection section for
PFM mode.
Inductor Selection
Three key inductor parameters must be specified
for operation with the devices: inductance value (L),
inductor saturation current (ISAT), and DC resistance
(RDCR). To select inductance value, the ratio of inductor
peak-to-peak AC current to DC average current (LIR)
must be selected first. A good compromise between size
and loss is a 30% peak-to-peak ripple current to average
current ratio (LIR = 0.3). The switching frequency, input
voltage, output voltage, and selected LIR then determine
the inductor value as follows:
L=
where VSUP, VOUT, and IOUT are typical values (so that
efficiency is optimum for typical conditions). The switching
frequency is set by RFOSC (see Figure 3).
SWITCHING FREQUENCY vs. RFOSC
RFB1
MAX17244
FB
RFB2
SWITCHING FREQUENCY (MHz)
2.50
VOUT
VOUT ( VSUP − VOUT )
VSUP f SW I OUT LIR
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
12
42
72
102
132
RFOSC (kΩ)
Figure 2. Adjustable Output-Voltage Setting
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Figure 3. Switching Frequency vs. RFOSC
Maxim Integrated │ 13
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor RMS current requirement (IRMS) is
defined by the following equation:
IRMS = ILOAD ( MAX )
VOUT ( VSUP − VOUT )
VSUP
IRMS has a maximum value when the input voltage equals
twice the output voltage (VSUP = 2VOUT), so IRMS(MAX)
= ILOAD(MAX)/2.
Choose an input capacitor that exhibits less than +10°C
self-heating temperature rise at the RMS input current for
optimal long-term reliability.
The input voltage ripple is composed of ΔVQ (caused
by the capacitor discharge) and ΔVESR (caused by the
ESR of the capacitor). Use low-ESR ceramic capacitors
with high ripple current capability at the input. Assume
the contribution from the ESR and capacitor discharge
equal to 50%. Calculate the input capacitance and ESR
required for a specified input voltage ripple using the
following equations:
ESR IN =
∆VESR
∆I
I OUT + L
2
where:
− VOUT ) × VOUT
(V
∆IL = SUP
VSUP × f SW × L
and:
=
C IN
I OUT × D(1 − D )
VOUT
=
and D
∆VQ × f SW
VSUPSW
where IOUT is the maximum output current and D is the
duty cycle.
Output Capacitor
The output filter capacitor must have low enough ESR
to meet output ripple and load transient requirements.
The output capacitance must be high enough to absorb
the inductor energy while transitioning from full-load to
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no-load conditions without tripping the overvoltage fault
protection. When using high-capacitance, low-ESR
capacitors, the filter capacitor’s ESR dominates the output
voltage ripple. So the size of the output capacitor depends
on the maximum ESR required to meet the output voltage
ripple (VRIPPLE(P-P)) specifications:
VRIPPLE(P−P) =
ESR × ILOAD(MAX) × LIR
The actual capacitance value required relates to the physical
size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is
usually selected by ESR and voltage rating rather than by
capacitance value.
When using low-capacity filter capacitors, such as ceramic
capacitors, size is usually determined by the capacity
needed to prevent voltage droop and voltage rise from
causing problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem. However, low capacity filter capacitors
typically have high ESR zeros that can affect the overall
stability.
Rectifier Selection
The devices require an external Schottky diode rectifier
as a freewheeling diode when they are is configured for
PFM-mode operation. Connect this rectifier close to the
device using short leads and short PCB traces. In PWM
mode, the Schottky diode helps minimize efficiency losses by diverting the inductor current that would otherwise
flow through the low-side MOSFET. Choose a rectifier
with a voltage rating greater than the maximum expected
input voltage, VSUPSW. Use a low forward-voltage-drop
Schottky rectifier to limit the negative voltage at LX. Avoid
higher than necessary reverse-voltage Schottky rectifiers
that have higher forward-voltage drops.
Compensation Network
The devices use an internal transconductance error
amplifier with its inverting input and its output available to
the user for external frequency compensation. The output
capacitor and compensation network determine the loop
stability. The inductor and the output capacitor are chosen
based on performance, size, and cost. Additionally, the
compensation network optimizes the control-loop stability.
Maxim Integrated │ 14
MAX17244
3.5V–36V, 2.5A, Synchronous Buck Converter
With 28µA Quiescent Current and Reduced EMI
The controller uses a current-mode control scheme
that regulates the output voltage by forcing the required
current through the external inductor. The devices use
the voltage drop across the high-side MOSFET to sense
inductor current. Current-mode control eliminates the
double pole in the feedback loop caused by the inductor
and output capacitor, resulting in a smaller phase shift
and requiring less elaborate error-amplifier compensation
than voltage-mode control. Only a simple single-series
resistor (RC) and capacitor (CC) are required to have a
stable, high-bandwidth loop in applications where ceramic
capacitors are used for output filtering (Figure 4). For
other types of capacitors, due to the higher capacitance
and ESR, the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output capacitor
loop, add another compensation capacitor (CF) from
COMP to AGND to cancel this ESR zero.
The basic regulator loop is modeled as a power
modulator, output feedback divider, and an error
amplifier. The power modulator has a DC gain set by
gm x RLOAD, with a pole and zero pair set by RLOAD,
the output capacitor (COUT), and its ESR. The following
equations allow to approximate the value for the gain
of the power modulator (GAINMOD(dc)), neglecting the
effect of the ramp stabilization. Ramp stabilization is
necessary when the duty cycle is above 50% and is
internally done for the device.
GAINMOD(dc)
= g m × R LOAD
where RLOAD = VOUT/ILOUT(MAX) in Ω and gm = 3S.
In a current-mode step-down converter, the output capacitor,
its ESR, and the load resistance introduce a pole at the
following frequency:
f pMOD
= 1 (2π × C OUT × R LOAD)
The output capacitor and its ESR also introduce a zero at:
f zMOD =
1
2π × ESR × C OUT
When COUT is composed of “n” identical capacitors in
parallel, the resulting COUT = n x COUT(EACH), and
ESR = ESR(EACH)/n. Note that the capacitor zero for a
parallel combination of alike capacitors is the same as for
an individual capacitor.
The feedback voltage-divider has a gain of GAINFB = VFB/
VOUT, where VFB is 1V (typ). The transconductance error
amplifier has a DC gain of GAINEA(dc) = gm,EA x ROUT,EA,
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VOUT
R1
R2
COMP
gm
VREF
RC
CF
CC
Figure 4. Compensation Network
where gm,EA is the error amplifier transconductance,
which is 700µS (typ), and ROUT,EA is the output resistance
of the error amplifier 50MΩ.
A dominant pole (fdpEA) is set by the compensation
capacitor (CC) and the amplifier output resistance
(ROUT,EA). A zero (fzEA) is set by the compensation
resistor (RC) and the compensation capacitor (CC).
There is an optional pole (fpEA) set by CF and RC to
cancel the output capacitor ESR zero if it occurs near
the cross over frequency (fC, where the loop gain equals
1 (0dB)). Thus:
f dpEA =
1
2 π × C C × ( R OUT ,EA + R C )
1
2 π × CC × RC
1
f pEA =
2 π × CF × R C
f zEA =
The loop-gain crossover frequency (fC) should be set
below 1/5th of the switching frequency and much higher
than the power-modulator pole (fpMOD):
f
f pMOD
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