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MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
General Description
Benefits and Features
The Rainier series of isolated DC-DC products enable
small, efficient solutions with a lower BOM. The MAX17687
is a high-voltage, high-efficiency, iso-buck DC-DC converter designed to provide isolated power up to 10W. The
device operates over a wide 4.5V to 60V input voltage
range and uses primary-side feedback to regulate the
output voltage. It delivers primary peak current up to 3.2A
and regulates primary output voltage to within ±1.2%.
The device features peak-current-mode control with
pulse-width modulation (PWM) scheme. The low-resistance, on-chip MOSFETs ensure high efficiency at full
load and simplify the layout.
A programmable soft-start feature allows users to reduce
input inrush current. The device also incorporates an
output enable/undervoltage lockout pin (EN/UVLO) that
allows the user to turn on the part at the desired input-voltage level. An open-drain RESET pin provides a delayed
power-good signal to the system upon achieving successful regulation of the primary output voltage.
The device operates from -40°C to +125°C and is available in a compact 20-pin (4mm x 4mm) TQFN package.
Simulation models are available.
●● Eliminates External Components and Reduces Total
Cost
• Synchronous Primary Operation for High Efficiency
and Reduced Cost
• All-Ceramic Capacitors, Ultra-Compact Layout
●● Supports Numerous Isolated DC-DC Applications
• Wide 4.5V to 60V Input Voltage Range
• Delivers up to 3.2A Peak Current
• 100kHz to 500kHz Adjustable Frequency with
External Synchronization
• Available in a 20-Pin, 4mm x 4mm TQFN Package
●● Reduces Power Dissipation
• Peak Efficiency > 90%
• Shutdown Current = 2.8μA (typ)
●● Operates Reliably in Adverse Industrial Environments
• Hiccup-Mode Current Limit, Sink Current Limit, and
Auto-Retry Startup
• Programmable EN/UVLO Threshold
• Adjustable Soft-Start
• -40°C to +125°C Ambient Operating Temperature
Range
• -40°C to +150°C Junction Temperature Range
Applications
●●
●●
●●
●●
Industrial Process Control
Communication Hub in Smart Meters
Isolated Power Supplies in Medical Equipment
Floating Power Supply Generation
Ordering Information appears at end of data sheet.
Typical Application Circuit
VIN
16V TO 60V
C1
2.2μF
3
4
R4
105kΩ
EN/UVLO
VIN
2
VIN
1
VIN
BST
10
6
11
12
20
C5
0.1μF
RT
LX
SYNC
LX
MAX17687
LX
NC
VCC
RESET
17
NPRI
SGND
FB
COMP
SS
7
8
C7
2.2nF
R3
6.34kΩ
C8
33nF
C9
15nF
PGND
PGND
PGND
14
15
16
C4
10μF
x2
NSEC
5
R1
78.7kΩ
13
VOUT
12V, 750mA
D1
18
C6
2.2μF
19-100446; Rev 0; 12/18
T1
1:1.67
19
9
R2
10kΩ
C10
2700pF
C2
22μF
C3
22μF
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Absolute Maximum Ratings
VIN to PGND..........................................................-0.3V to +65V
EN/UVLO to PGND................................................-0.3V to +65V
LX to PGND................................................-0.3V to (VIN + 0.3V)
BST to PGND..................................................-0.3V to (LX + 5V)
BST to LX..............................................................-0.3V to +6.5V
BST to VCC............................................................-0.3V to +65V
VCC, SYNC, RESET, COMP, SS, RT to SGND
...........................................................................-0.3V to +6.5V
FB to SGND..........................................................-0.3V to +1.5V
SGND to PGND.....................................................-0.3V to +0.3V
LX Total RMS Current............................................................±4A
Output Short-Circuit Duration.....................................Continuous
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +160°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Junction temperature greater than +125°C degrades operating lifetimes.
Package Information
PACKAGE TYPE: 20 TQFN
Package Code
T2044+4
Outline Number
21-0139
Land Pattern Number
90-0409
THERMAL RESISTANCE, FOUR-LAYER BOARD
Juntion to Ambient (θJA)
33°C/W
Juntion to Case (θJC)
2°C/W
Continuous Power Dissipation (TA = +70°C)
(derate 30.3mW/°C above +70°C) (multilayer board)
2424.2mW
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
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Maxim Integrated │ 2
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Electrical Characteristics
(VIN = VEN = 24V, RRT = 82.5kΩ (250kHz), VSGND = VPGND = VSYNC = 0V, CVCC = 2.2μF, VFB = 1V, VBST to LX = 5V, LX = RESET
= SS = COMP = unconnected. TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are
referenced to SGND, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
60
V
2.8
4.5
µA
1.16
1.8
mA
INPUT SUPPLY (VIN)
Input Voltage Range
Input Quiescent Current
VIN
IIN-SH
4.5
VEN = 0V, shutdown mode
Input Quiescent Current
IQ
Input Switching Current
ISW
VFB = 0.8V
VENR
VEN rising
1.19
1.215
1.26
VENF
VEN falling
1.068
1.09
1.131
V
6
mA
ENABLE/UVLO (EN/UVLO)
EN Threshold
VEN-TRUESD
EN Input Leakage Current
IEN
VEN falling, true shutdown
VEN = VIN = 60V, TA = +25˚C
0.8
-50
0
+50
nA
4.75
5
5.25
V
55
100
mA
LDO
VCC Output Voltage Range
VCC Current Limit
VCC
1mA < IVCC < 25mA
VCC = 4.3V, VIN = 6V
26.5
VCC-DO
VIN = 4.5V, IVCC = 20mA
4.2
VCC-UVR
VCC rising
4.05
4.2
4.3
VCC-UVF
VCC falling
3.65
3.8
3.9
High-Side NMOS On-Resistance
RDS-ONH
ILX = 0.3A (sourcing)
165
325
mΩ
Low-Side NMOS On-Resistance
RDS-ONL
ILX = 0.3A (sinking)
80
150
mΩ
LX Leakage Current
ILX_LKG
TA = +25˚C, VLX = (VPGND +
1V) to (VIN – 1V)
-2
+2
μA
VSS = 0.5V
4.7
5
5.3
μA
0.89
0.9
0.91
V
+50
nA
VCC Dropout
VCC UVLO
IVCC-MAX
6V < VIN < 60V, IVCC = 1mA
V
V
POWER MOSFETs
SOFT-START (SS)
Charging Current
ISS
FEEDBACK (FB)
FB Regulation Voltage
VFB_REG
FB Input Bias Current
IFB
VFB = 1V, TA = +25˚C
-50
CURRENT LIMIT
Peak Current Limit Threshold
IPEAK-LIMIT
3.2
3.7
4.3
A
Runaway Current Limit Threshold
IRUNAWAY-
3.7
4.3
5
A
Valley Current Limit Threshold
ISINK-LIMIT
5
6.5
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LIMIT
A
Maxim Integrated │ 3
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Electrical Characteristics (continued)
(VIN = VEN = 24V, RRT = 82.5kΩ (250kHz), VSGND = VPGND = VSYNC = 0V, CVCC = 2.2μF, VFB = 1V, VBST to LX = 5V, LX = RESET
= SS = COMP = unconnected. TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are
referenced to SGND, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RT AND SYNC
Switching Frequency
fSW
SYNC Frequency Capture Range
RRT = OPEN
250
RRT = 210kΩ
100
RRT = 102kΩ
200
RRT = 82.5kΩ
250
RRT = 40.2kΩ
500
fSW set by RRT
SYNC Pulse Width
SYNC Threshold
Feedback Undervoltage Trip Level
to Cause Hiccup
1.1 x
fSW
kHz
1.4 x
fSW
50
VIH
ns
2.1
VIL
VFB-HICF
HICCUP Timeout
0.8
VSS > 0.95V
(soft-start is done)
0.56
(Note 2)
Minimum On-Time
tON_MIN
Minimum Off-Time
tOFF_MIN
LX Dead Time
0.58
0.65
32768
330
140
(Note 3)
Number of ZX Events to Trigger
HICCUP
kHz
V
V
Cycles
425
ns
160
ns
5
ns
16
Cycles
RESET
RESET Output Level Low
IRESET = 10mA
0.4
V
RESET Output Leakage
Current High
TA = TJ = 25°C
0.1
μA
94.6
%VFB-
97.8
%VFB-
FB Threshold for RESET
Assertion
FB Threshold for RESET
Deassertion
RESET Delay After FB Reaches
95% Regulation
VFB-OKF
VFB-OKR
VFB falling
VFB rising
90.5
93.8
92
95
REG
REG
VFB rising
1024
Cycles
Temperature rising
165
°C
10
°C
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Note 1: All limits are 100% tested at +25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
Note 2: See the Overcurrent Protection/Hiccup Mode section for more details.
Note 3: Guaranteed by design, not production tested.
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Maxim Integrated │ 4
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Typical Operating Characteristics
(VIN = 24V, VSGND = VPGND = 0V, CVIN = 2.2µF, CVCC = 2.2μF, VEN = 1.5V, CSS = 15000pF, RESET = unconnected, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
100
LOAD TRANSIENT RESPONSE,
(LOAD CURRENT STEPPED
FROM 75mA to 375mA)
toc01
toc02
90
EFFICIENCY (%)
80
VIN = 16V
70
60
500mV/div
IOUT
200mA/div
VIN = 24V
50
40
VIN = 36V
30
20
10
0
VOUT (AC)
0
100
200
300
400
500
600
700
400µs/div
800
LOAD CURRENT (mA)
LOAD TRANSIENT RESPONSE
(LOAD CURRENT STEPPED
FROM 375mA to 700mA)
FULL-LOAD SWITCHING WAVEFORMS
toc03
toc04
500mV/div
VOUT (AC)
20V/div
LX
200mV/div
VOUT
IOUT
500mA/div
400µs/div
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IPRI
2A/div
ISEC
2A/div
2µs/div
Maxim Integrated │ 5
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Typical Operating Characteristics (continued)
(VIN = 24V, VSGND = VPGND = 0V, CVIN = 2.2µF, CVCC = 2.2μF, VEN = 1.5V, CSS = 15000pF, RESET = unconnected, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
SOFT-START
SHUTDOWN WITH ENABLE
toc05
VEN/UVLO
5V/div
VEN/UVLO
5V/div
VSEC
toc06
5V/div
5V/div
VPRI
500mA/div
VSEC
5V/div
IOUT
IOUT
500mA/div
1ms/div
1ms/div
OVERLOAD PROTECTION
toc07
BODE PLOT
VOUT
toc08
5A/div
IPRI
GAIN
PHASE (°)
5V/div
GAIN (dB)
PHASE
fCR = 8.6kHz,
PHASE MARGIN = 66.4°
FREQUENCY (Hz)
20µs/div
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Maxim Integrated │ 6
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
PGND
SGND
VCC
N.C.
TOP VIEW
PGND
Pin Configuration
15
14
13
12
11
PGND
16
10
RT
LX
17
9
FB
LX
18
8
COMP
LX
19
7
SS
BST
20
6
SYNC
MAX17687
1
2
3
4
5
VIN
VIN
VIN
EN/UVLO
RESET
+
20-PIN TQFN 4mm × 4mm
*EXPOSED PAD (CONNECT TO GROUND).
Pin Description
PIN
NAME
FUNCTION
Power-Supply Input. 4.5V to 60V input supply range. Connect the VIN pins together. Decouple to PGND
with a 2.2µF capacitor; place the capacitor close to the VIN and PGND pins. Refer to the MAX17687EV kit
data sheet for a layout example.
1-3
VIN
4
EN/UVLO
Enable/Undervoltage Lockout Input. Drive EN/UVLO high to enable the output voltage. Connect to the
center of resistive divider between VIN and GND to set the input voltage (undervoltage threshold) at which
the device turns on. Pull up to VIN for always on.
5
RESET
Open-Drain RESET Output. RESET output is driven low if FB drops below 92.5% of its set value. RESET
goes high 1024 clock cycles after FB rises above 95.5% of its set value.
6
SYNC
The device can be synchronized to an external clock using this pin. See the External Frequency
Synchronization section for more details.
7
SS
8
COMP
Soft-Start Input. Connect a capacitor from SS to GND to set the soft-start time.
9
FB
Feedback Input. Connect FB to the center of resistive divider between VOUT and GND. See the Adjusting
Output Voltage section for more details.
10
RT
Connect a resistor from RT to SGND to set the regulator’s switching frequency. Leave RT open for the
default 250kHz frequency. See the Setting the Switching Frequency (RT) section for more details.
Compensation Input. Connect an RC network from COMP to GND
11
NC
No Connection. Do not connect any voltage to this pin.
12
VCC
5V LDO Output. Bypass VCC with 2.2μF ceramic capacitance to GND.
13
SGND
Analog Ground.
14-16
PGND
Power Ground. Connect PGND externally to the power ground plane. Connect GND and PGND pins
together at the ground return path of the VCC bypass capacitor.
17-19
LX
Switching Node. Connect LX to the switching side of the transformer. LX is high impedance when the
device is in shutdown mode.
20
BST
EP
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Boost Flying Capacitor. Connect a 0.1µF ceramic capacitor between BST and LX.
Exposed pad. Connect to the SGND pin. Connect to a large copper plane below the IC to improve heat
dissipation capability. Add thermal vias below the exposed pad.
Maxim Integrated │ 7
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Functional (or Block) Diagram
MAX17687
VCC
5V
BST
LDO
VIN
SGND
CURRENT-SENSE
LOGIC
EN/UVLO
PWM / HICCUP
LOGIC
LX
1.215V
HICCUP
RT
OSCILLATOR
SYNC
PGND
COMP
FB
ERROR
AMPLIFIER
SLOPE
COMPENSATION
VCC
SWITCHOVER
LOGIC
SS
HICCUP
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RESET
5ΜA
FB
RESET
LOGIC
Maxim Integrated │ 8
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Detailed Description
The MAX17687 a high-voltage, high-efficiency, Iso-Buck
DC-DC converter designed to operate over a wide 4.5V to
60V input voltage range. It delivers primary peak current
up to 3.2A and regulates primary output voltage to within
±1.2% over -40°C to +125°C.
The device features peak-current-mode control with
pulse-width modulation (PWM) scheme. The low-resistance,
on-chip MOSFETs ensure high efficiency at full load and
simplify the layout.
A programmable soft-start feature allows users to reduce
input inrush current. The device also incorporates an
output enable/undervoltage lockout pin (EN/UVLO) that
allows the user to turn on the part at the desired input-voltage level. An open-drain RESET pin provides a delayed
power-good signal to the system upon achieving successful regulation of the primary output voltage.
Table 1. Switching Frequency vs. RT
Resistor
SWITCHING FREQUENCY
(kHz)
RT RESISTOR
(kΩ)
100
210
200
102
250
82.5
500
40.2
External Frequency Synchronization (SYNC)
The device operates from -40°C to +125°C and is available in a compact 20-pin (4mm x 4mm) TQFN package.
The internal oscillator of the device can be synchronized
to an external clock signal on the SYNC pin. The external
synchronization clock frequency must be between
1.1 x fSW and 1.4 x fSW, where fSW is the frequency
programmed by the RRT resistor. The minimum external
clock pulse-width high should be greater than 50ns. See
the RT AND SYNC section in the Electrical Characteristics
table for details.
Linear Regulator (VCC)
Enable Input (EN/UVLO) and Soft-Start (SS)
An internal linear regulator (VCC) provides a 5V nominal
supply to power the internal blocks and the low-side
MOSFET driver. The output of the VCC linear regulator
should be bypassed with a 2.2μF ceramic capacitor to
GND. The device employs an undervoltage-lockout circuit
that disables the internal linear regulator when VCC falls
below 3.8V (typ). The internal VCC linear regulator can
source up to 20mA to supply the device and to power the
low-side gate driver.
When EN/UVLO voltage increases above 1.215V (typ),
the device initiates a soft-start sequence and duration of
the soft-start depends on the value of the capacitor
connected from SS to GND. A 5μA current source charges
the capacitor and ramps up the SS pin voltage. The SS
pin voltage is used as reference for the internal error
amplifier. Such a reference ramp up allows the output
voltage to increase monotonically from zero to the final
set value independent of the load current.
Setting the Switching Frequency (RT)
EN/UVLO can be used as an input voltage UVLO-adjustment
input. An external voltage divider between IN and EN/UVLO
to GND adjusts the input voltage at which the device turns
on or turns off. See the Setting the Input Undervoltage
Lockout Level section for details. If input UVLO programming is not desired, connect EN/UVLO to VIN (see the
Electrical Characteristics table for EN/UVLO rising and
falling-threshold voltages). Driving EN/UVLO low disables
the high-side FET and part enters into primary output
discharge mode (explained in the Overcurrent Protection/
Hiccup Mode section). Once hiccup timeout period expires,
other internal circuitry is disabled and SS capacitor is
discharged with an internal pull-down resistor. If the EN/
UVLO pin is driven from an external signal source, a
series resistance of minimum 1kΩ is recommended to
be placed between the signal source output and the EN/
UVLO pin, to reduce voltage ringing on the line.
The switching frequency of the device can be
programmed from 100kHz to 500kHz by using a resistor
connected from the RT pin to SGND. The switching
frequency (fSW) is related to the resistor connected at the
RT pin (RRT) by the following equation:
R RT ≅
21× 10 3
− 1.7
f SW
where RRT is in kΩ and fSW is in kHz. Leaving the RRT
pin open causes the device to operate at the default
switching frequency of 250 kHz. See Table 1 for RRT
resistor values for a few common switching frequencies.
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Maxim Integrated │ 9
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Overcurrent Protection/Hiccup Mode
2mA of current while low. RESET goes high (high impedance) 1024 switching cycles after the primary output
increases above 95.5% of the nominal regulated voltage.
RESET goes low when the primary output voltage drops to
below 92.5% of the nominal regulated voltage. RESET
also goes low during thermal shutdown. RESET is valid
when the device is enabled and VIN is above 4.5V.
The MAX17687 enters hiccup mode, either on one occurrence
of the runaway current limit, or when the feedback voltage
drops to 0.58V (typ) after the soft-start is completed, or
when EN/UVLO < 1.09V with VCC > 3.8V or when 16
consecutive negative current limit events occur. When
the hiccup mode is triggered, the converter enters a hiccup
timeout period of 32,768 clock cycles. During this period,
the high side switch is kept off and the low side switch is
turned on each cycle with a maximum possible duty cycle
of 98% till the negative current limit reaches 0.6A. This
mode of operation effectively produces a negative current in
the primary capacitor and discharges the primary voltage
towards zero. Once the hiccup timeout period expires,
soft-start is attempted again. For cases where the amount
of output capacitance is such that it is discharged to
zero within one hiccup timeout period, the MAX17687
executes a normal soft-start operation upon exit from the
Hiccup timeout period. For cases, where the capacitor
is sized such that it does not discharge to zero in one
hiccup timeout period, during the next soft-start attempt
the converter may re-enter the hiccup time period due to
one of the event which triggers hiccup mode. Eventually
the primary capacitor is completely discharged and the
smooth output voltage recovery is ensured.
Thermal-Shutdown Protection
Thermal-shutdown protection limits total power dissipation in
the device. When the junction temperature of the device
exceeds +165°C, an on-chip thermal sensor shuts down
the device, allowing the device to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 10°C. Soft-start resets during thermal shutdown.
Carefully evaluate the total power dissipation (see the
Power Dissipation section) to avoid unwanted triggering of
the thermal shutdown in normal operation.
Applications Information
Operation of the Iso-Buck Converter
Iso-buck is a synchronous buck converter based topology, useful for generating isolated outputs at low power
level without using an optocoupler. Figure 1 shows basic
circuit of an Iso-buck converter, consists of a Half bridge
transformer driver and secondary side filter.
RESET Output
The device includes a RESET comparator to monitor the
primary output voltage. The open-drain RESET output
requires an external pull-up resistor. RESET can sink
QHS
D1
T1
VIN
QLS
VOUT
+
NPRI
VPRI
NSEC
+
-
- COUT
RLOAD
CPRI
Figure 1. Iso-Buck Topology
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Maxim Integrated │ 10
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Figure 2 shows the equivalent circuit when high side
switch (QHS) is on. During this time, primary current
ramps up and stores energy in transformer magnetizing
inductance LPRI and primary capacitor CPRI. Secondary
side diode is reverse-biased by (VIN - VPRI) voltage and
load current is supplied by secondary filter capacitor
COUT.
Figure 3 shows the equivalent circuit when low side
switch (QLS) is on. During this time, secondary diode gets
forward biased by primary output voltage VPRI. Primary
current ramps down and releases stored energy in
transformer magnetizing inductance and primary capacitor
to the load. Operating waveforms of the converter are
shown in Figure 4. Neglecting diode drop VD and
transformer resistances, output voltage VOUT is
proportional to the primary output voltage VPRI and is
regulated by MAX17687 current mode control loop.
QHS
D1
T1
QLS
VOUT
+
NSEC
NPRI
VPRI
+
-
COUT
RLOAD
CPRI
-
Figure 2. On Period Equivalent Circuit
QHS
D1
T1
VOUT
NPRI
VIN
+
QLS
NSEC
VPRI
+
-
-
COUT
RLOAD
CPRI
Figure 3. Off Period Equivalent Circuit
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Maxim Integrated │ 11
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
QHS
QLS
ΔI
IPK_PRI
IPRI
IPK_VELLEY
IPK_SEC
ISEC
D*TS
(1-D)*TS
IOUT
Figure 4. Iso-Buck Operating Waveforms
Primary Output Voltage Selection
Primary output voltage is regulated by the MAX17687
control loop. The primary output voltage can be calculated
by using the equation:
=
VPRI
D MAX × VIN_MIN
where DMAX is the maximum duty cycle of the converter
and VIN_MIN is the minimum input voltage. Maximum duty
cycle should be in the range of 0.4 to 0.6 for ideal iso-buck
operation.
Adjusting Primary Output Voltage
Set the primary output voltage by connecting a resistordivider from primary output to FB to GND (see Figure 5).
Choose R2 in the range of 10kΩ to 100kΩ and calculate
R1 with the following equation:
Turns Ratio Selection
Neglecting parasitic resistances, Iso-buck output voltage
VOUT is proportional to the primary output voltage VPRI.
Select the turns ratio (K) using the equation:
N SEC VOUT + VD
=
NPRI
VPRI
K=
N SEC
NPRI
where, VD is the diode forward voltage drop.
Turns ratio can be adjusted to match with the readily
available off-the-shelf transformer turns ratio by adjusting
the primary output voltage.
V
R1 =×
R2 PRI − 1
0.9
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Maxim Integrated │ 12
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
D1
LX
+
NPRI
MAX17687
NSEC
-
COUT
+
R1
-
CPRI
FB
R2
Figure 5. Adjusting Primary Output Voltage
Primary Inductance Selection
Primary inductance value determines ripple current in the
transformer. Calculate required primary inductance using
the equation:
L PRI =
VPRI
f SW
where VPRI and fSW are nominal values.
Calculate the primary ripple current using the equation:
V
VPRI × 1 − PRI
VIN
∆I =
f SW × L PRI
where:
LPRI = Primary inductance in H
fSW = Switching frequency in Hz
Winding Peak and RMS Currents
Windings peak and RMS current ratings should be specified for selecting the Iso-buck transformer.
Primary and secondary winding peak currents are given
by the equations:
∆I
= (I OUT × K) +
IPK _PRI
2
2 × I OUT
IPK _SEC =
(1 − D)
VPRI
D=
VIN
where IOUT is load current, K is turns ratio and D is duty
cycle.
Primary RMS current is sum of the high-side and low-side
switch RMS currents.
VPRI = Primary output voltage
VIN = Input voltage.
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Maxim Integrated │ 13
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
High-side switch RMS current:
2
2 ∆I
IHS_RMS = D × (I OUT × K ) +
12
Low-side switch RMS current:
ILS_RMS =
(1 − D) ×
2
2 4 × (I
∆I
2 ∆I
OUT × K) × (3D − 1) +
+
(I OUT × K) +
12 3 × (1 − D) 2 × (1 − D) 4 × (I OUT × K)
Primary winding RMS current:
=
IPRI_RMS
Table 2. Switching Frequency vs. RT
Resistor
PARAMETER
SYMBOL
Primary Inductance
LPRI
Leakage Inductance
LLEAK
Primary Ripple Current
∆I
Primary Peak Current
IPK_PRI
Primary RMS Current
IPRI_RMS
Secondary Peak Current
IPK_SEC
Secondary RMS Current
ISEC_RMS
Working Voltage
VAC, VDC
Insulation Level
VAC, VDC
IHS_RMS 2 + ILS_RMS 2
Secondary winding RMS current is given by the equation:
I SEC_RMS =
2 × I OUT ×
1
3 × (1 − D)
Leakage Inductance
Transformer leakage inductance (L_LEAK) plays a key
role in determining the output voltage regulation. For better
output voltage regulation, leakage inductance should be
reduced to less than 1% of the primary inductance value.
Higher leakage inductance also limits the amount of
power delivered to the output.
Primary Negative Peak Current
The primary current can go negative when the low-side
switch is turned on. The primary negative peak current
can be calculated using the equation:
I_NEGPK_PRI = (-IOUT x K x (1 + D)/(1 - D)) - ΔI/2
Specifying the Iso-Buck Transformer
Off-the-shelf transformer or coupled inductor can be used
as Iso-buck transformer. If readily not available, use the
table below to specify the Iso-buck transformer parameters
to transformer vendor.
Primary Output Capacitor Selection
X7R ceramic output capacitors are preferred due to
their stability over temperature in industrial applications.
Calculate the minimum required output capacitance from
the equation:
VPRI
D MAX =
VIN_MIN
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C PRI =
where:
K × I OUT × D MAX
f SW × 0.01× VPRI
IOUT = Load current
K = Turns ratio
fSW = Switching frequency
VPRI = Primary output voltage
VIN_MIN = Minimum input voltage.
Secondary Output Capacitor Selection
Secondary side capacitor supplies load current when
high-side switch is on. Calculate the required output
capacitance to support 1% steady state ripple using the
equation:
C OUT =
I OUT × D MAX
f SW × 0.01× VOUT
It should be noted that dielectric materials used in
ceramic capacitors exhibit capacitance loss due to DC bias
levels and should be appropriately derated to ensure the
required output capacitance is obtained in the application.
Input Capacitor Selection
Ceramic input capacitors are recommended for the IC.
The input capacitor reduces peak current drawn from the
power source and reduces noise and voltage ripple on
the input caused by the switching circuitry. In applications
where the source is located distant from the device input,
an electrolytic capacitor should be added in parallel to the
input ceramic capacitor to provide necessary damping for
potential oscillations caused by the longer input power
path and input ceramic capacitor. Calculate required input
capacitance using the equation:
Maxim Integrated │ 14
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Soft-Start Capacitor Selection
C IN =
The device implements adjustable soft-start operation to
reduce inrush current. A capacitor connected from the SS
pin to SGND programs the soft-start time. The selected
output capacitance (CSEL) and the output voltage (VOUT)
determine the minimum required soft-start capacitor as
follows:
K × I OUT × D MAX × (1 − D MAX )
f SW × ∆VIN
D MAX =
VPRI
VIN_MIN
∆VIN is input voltage ripple, normally 2% of the minimum
input voltage, DMAX is maximum duty cycle, fSW switching
frequency of operation.
Secondary Diode Selection
Secondary rectifier diode should be rated to carry peak
secondary current and to withstand reverse voltage when
high side switch is on. Schottky diode with less forward
voltage drop should be selected for better output regulation.
Calculate peak current rating of the diode using the equation:
IPK _DIODE =
2 × I OUT
(1 − D)
Calculate peak reverse voltage rating of the diode using
the equation:
((
)
VDIODE = 2 × VIN_MAX − VPRI × K + VOUT
)
Power dissipated in the diode can be calculated using the
equation:
PDIODE
= VD × I OUT
Minimum Load Requirements
Under light-load conditions, the iso-buck converter output
voltage increases excessively due to the transformer
leakage inductance and parasitic capacitance. Normally,
a minimum load of 10% to 20% of the full load is sufficient
to keep the converter output voltage regulation within
±5%. The output voltage regulation should be verified
after testing prototype.
A resistor connected in series with a Zener diode can
be used as an overvoltage protection circuit to limit the
overvoltage under absolute no load conditions. The Zener
diode threshold can be selected as 15% higher than the
nominal regulated output voltage VOUT. The series resistor
(R1) value can be in the range of 30Ω to 60Ω.
CSS ≥ 28 x 10-6 x CSEL x VPRI
The soft-start time (tSS) is related to the capacitor
connected at SS (CSS) by the following equation:
C SS
t SS =
5.55 × 10 −6
For example, to program a 1ms soft-start time, a 5.6nF
capacitor should be connected from the SS pin to SGND.
Setting the Input Undervoltage
Lockout Level
The device offers an adjustable input undervoltage-lockout
level. Set the voltage at which the device turns on with
a resistive voltage divider connected from VIN to SGND
(see Figure 6). Connect the center node of the divider to
EN/UVLO.
Choose R1 to be 3.3MΩ max and then calculate R2 as
follows:
R2 =
R1× 1.215
(VINU − 1.215)
where VINU is the voltage at which the device is required
to turn on.
VIN
R1
MAX17687
EN/UVLO
R2
Figure 6. Setting the Input Undervoltage Lockout
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Maxim Integrated │ 15
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
RSEC = Secondary resistance of the transformer
VD = Diode drop.
The junction temperature of the device can be estimated
at any given maximum ambient temperature (TA_MAX)
from the equation below:
MAX17687
COMP
TJ_MAX = TA_MAX + (θJA × PLOSS)
RZ
if the application has a thermal management system that
ensures that the exposed pad of the device is maintained
at a given temperature (TEP_MAX) by using proper heat
sinks, then the junction temperature of the device can be
estimated at any given maximum ambient temperature
from the equation below:
CP
CZ
Figure 7. External Compensation Network
TJ_MAX = TEP_MAX + (θJC × PLOSS)
External Loop Compensation
The MAX17687 uses peak current-mode control scheme
and needs only a simple RC network to have a stable,
control loop. The compensation network is shown in
Figure 7. Use the following equations for calculating the
compensation components:
R Z= 1100 × f C × C OUT × (1-D) × K 2 + C PRI × VPRI
where RZ is in Ω and fC is bandwidth of the converter in
Hz. Choose fC to be 1/20th of the switching frequency.
5
CZ =
π × fC × R Z
CP =
1
π × f SW × R Z
Power Dissipation
At a particular operating condition, the power losses that
lead to temperature rise of the device can be estimated
as follows:
(
)
1
PLOSS = POUT × -1 − IPRI_RMS 2 × R PRI −
η
(ISEC_RMS 2 × R SEC) − (VD × IOUT )
P=
OUT VOUT × I OUT
where:
POUT = Output power
η = Efficiency of power conversion
RPRI = Primary resistance of the transformer
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Junction temperature greater than +125°C degrades
operating lifetimes.
PCB Layout Guidelines
All connections carrying pulsed currents must be very
short and as wide as possible. The inductance of these
connections must be kept to an absolute minimum due
to the high di/dt of the currents. Since inductance of a
current carrying loop is proportional to the area enclosed
by the loop, if the loop area is made very small, inductance
is reduced. Additionally, small-current loop areas reduce
radiated EMI.
A ceramic input filter capacitor should be placed close
to the VIN pins of the IC. This eliminates as much trace
inductance effects as possible and gives the IC a cleaner
voltage supply. A bypass capacitor for the VCC pin also
should be placed close to the pin to reduce effects of trace
impedance.
When routing the circuitry around the IC, the analog
small-signal ground and the power ground for switching currents must be kept separate. They should be
connected together at a point where switching activity
is at a minimum, typically the return terminal of the VCC
bypass capacitor. This helps keep the analog ground
quiet. The ground plane should be kept continuous/unbroken
as far as possible. No trace carrying high switching
current should be placed directly over any ground plane
discontinuity.
PCB layout also affects the thermal performance of
the design. A number of thermal vias that connect to
a large ground plane should be provided under the
exposed pad of the part, for efficient heat dissipation.
For a sample layout that ensures first pass success,
refer to the MAX17687 evaluation kit layout available at
www.maximintegrated.com.
Maxim Integrated │ 16
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Typical Application Circuit
R2
287kΩ
R1
3.3MΩ
VIN
16V TO 42V
C6
4.7μF
3
4
EN/UVLO
R3
105kΩ
VIN
2
VIN
1
VIN
20
BST
10
SYNC
11
12
MAX17687
17
LX
NPRI
C9
22μF
x3
NSEC
VCC
VCC
5
RESET
FB
COMP
8
SS
7
C8
22μF
x4
PGND
PGND
14
15
16
9
R7
10kΩ
C4
15nF
R4
6.34kΩ
C2
2.2nF
PGND
R9
40.2kΩ
R10
10kΩ
R6
78.7kΩ
SGND
R8
12Ω
U2
R5
10kΩ
C1
2.2μF
13
VOUT
12V, 750mA
D1
18
LX
NC
T1
1:1.67
19
LX
6
VCC
C5
0.1μF
RT
C6 : MURATA 4.7µF/X7R/100V/1206 (GRM31CZ72A475ME11)
C8 : MURATA 22µF/X7R/25V/1210 (GRM32ER71E226ME15)
C9: MURATA 22µF/X7R/25V/1210 (GRM32ER71E226ME15)
D1 : DIODES INC, SBR2U150SA
U2 : ST MICROELECTRONICS, TL431AIYDT
T1 : WURTH, 750343160
C7
2700pF
C3
33nF
Figure 8: 12V, 750mA Isolated Output Application Circuit -1
R1
3.3MΩ
R2
287kΩ
VIN
16V TO 60V
C6
4.7μF
3
4
R3
105kΩ
EN/UVLO
2
VIN
1
VIN
BST
10
6
11
VCC
VIN
12
20
C5
0.1μF
RT
LX
SYNC
LX
MAX17687
LX
NC
T1
1:1.67
19
17
NPRI
VCC
RESET
5
SGND
FB
COMP
8
C2
2.2nF
R4
6.34kΩ
SS
7
PGND
PGND
PGND
14
15
16
C4
15nF
C3
33nF
R8
200Ω
C8
120pF
R5
10kΩ
R6
78.7kΩ
C1
2.2μF
13
NSEC
VCC
9
VOUT
12V, 750mA
D1
18
C9
22µF
x3
R9
22Ω
D2
12V
C8
22μF
x4
R7
10kΩ
C7
2700pF
C6 : MURATA 4.7µF/X7R/100V/1206 (GRM31CZ72A475ME11)
C8 : MURATA 22µF/X7R/25V/1210 (GRM32ER71E226ME15)
C9 : MURATA 22µF/X7R/25V/1210 (GRM32ER71E226ME15)
D1 : TAIWAN SEMICONDUCTOR SK320A R3G
D2 : ON SEMICONDUCTOR 1SMA5927BT3G
T1 : WURTH, 750343160
Figure 9: 12V, 750mA Isolated Output Application Circuit -2
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Maxim Integrated │ 17
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Ordering Information
PART
MAX17687ATP+
Chip Information
PIN-PACKAGE
PROCESS: BiCMOS
20 TQFN-EP*
Note: All devices operate over the -40ºC to +125ºC temperature
range, unless otherwise noted.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
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Maxim Integrated │ 18
MAX17687
4.5V to 60V Input, Ultra-Small, High-Efficiency,
Iso-Buck DC-DC Converter
Revision History
REVISION
NUMBER
REVISION
DATE
0
12/18
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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