EVALUATION KIT AVAILABLE
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
General Description
Features
The MAX187/MAX189 serial 12-bit analog-to-digital converters (ADCs) operate from a single +5V supply and
accept a 0 to 5V analog input. Both parts feature an 8.5Fs
successive-approximation ADC, a fast track/hold (1.5Fs),
an on-chip clock, and a high-speed 3-wire serial interface.
S 12-Bit Resolution
The MAX187/MAX189 digitize signals at a 75ksps
throughput rate. An external clock accesses data from
the interface, which communicates without external
hardware to most digital signal processors and microcontrollers. The interface is compatible with SPI, QSPIK,
and MICROWIREM.
S Low Power: 2µA Shutdown Current
1.5mA Operating Current
The MAX187 has an on-chip buffered reference, and
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin PDIP and
16-pin SO packages. Power consumption is 7.5mW and
reduces to only 10FW in shutdown.
Excellent AC characteristics and very low power consumption combined with ease of use and small package
size make these converters ideal for remote DSP and
sensor applications, or for circuits where power consumption and space are crucial.
S ±½ LSB Integral Nonlinearity (MAX187A/MAX189A)
S Internal Track/Hold, 75kHz Sampling Rate
S Single +5V Operation
S Internal 4.096V Buffered Reference (MAX187)
S 3-Wire Serial Interface, Compatible with SPI, QSPI,
and MICROWIRE
S Small-Footprint 8-Pin PDIP and 16-Pin SO
Applications
Portable Data Logging
Remote Digital Signal Processing
Isolated Data Acquisition
High-Accuracy Process Control
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX187.related.
Functional Diagram
GND 5
REF10kI
+2.5V
DAC
AV = 1.638
(4.096V)
6 DOUT
8 SCLK
REF+
BANDGAP
REFERENCE
12-BIT
SAR
(MAX187 ONLY)
REF 4
AIN 2
OUTPUT
SHIFT
REGISTER
T/H
MAX187
MAX189
COMPARATOR
BUFFER ENABLE/DISABLE
VDD 1
CONTROL
AND
TIMING
7 CS
3 SHDN
NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY
QSPI is a trademark of Motorola.
MICROWIRE is a registered trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-0196; Rev 1; 3/12
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND.................................-0.3V to (VDD + 0.3V)
Digital Outputs to GND..............................-0.3V to (VDD + 0.3V)
SHDN to GND.............................................-0.3V to (VDD + 0.3V)
REF Load Current (MAX187) .........................4.0mA Continuous
REF Short-Circuit Duration (MAX187)............................. .......20s
DOUT Current..................................................................Q20mA
Continuous Power Dissipation (TA = +70NC)
8-Pin PDIP (derate 9.1mW/NC above +70NC)..............727mW
16-Pin Wide SO (derate 14.5mW/NC above 70NC).....1157mW
Operating Temperature Ranges
MAX187_C_ _/MAX189_C_ _..............................0NC to +70NC
MAX187_E_ _/MAX189_E_ _...........................-40NC to +85NC
Storage Temperature Range.............................-60NC to +150NC
Lead Temperature (soldering, 10s) .................................+300NC
Soldering Temperature (reflow) .......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
DC ACCURACY (Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
DNL
MAX18_A
Q½
MAX18_B
Q1
MAX18_C
Q2
No missing codes over temperature
Q1
MAX18_A
Offset Error
Gain Error (Note 3)
Q1½
MAX18_B/C
Q3
MAX187
Q3
MAX189A
Q1
MAX189B/C
Gain Temperature Coefficient
LSB
LSB
LSB
LSB
Q3
External reference, 4.096V
ppm/NC
Q0.8
DYNAMIC SPECIFICATIONS (10kHz Sine Wave Input, 0 to 4.096VP-P, 75ksps)
Signal-to-Noise Plus
Distortion Ratio
70
SINAD
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
Small-Signal Bandwidth
dB
-80
80
Rolloff -3dB
Full-Power Bandwidth
dB
dB
4.5
MHz
0.8
MHz
CONVERSION RATE
Conversion Time
tCONV
Track/Hold Acquisition Time
tACQ
Throughput Rate
Maxim Integrated
5.5
8.5
Fs
75
ksps
1.5
External clock, 4MHz, 13 clocks
Fs
2
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
Aperture Delay
CONDITIONS
MIN
tAPR
Aperture Jitter
TYP
MAX
UNITS
10
ns
< 50
ps
ANALOG INPUT
Input Voltage Range
0 to VREF
Input Capacitance (Note 4)
16
V
pF
INTERNAL REFERENCE (MAX187 Only, Reference Buffer Enabled)
4.076
TA = +25NC
REF Output Voltage
VREF
TA = TMIN to
TMAX
4.096
4.116
MAX187_C
4.060
4.132
MAX187_E
4.050
4.140
REF Short-Circuit Current
Q30
REF Tempco
Load Regulation (Note 5)
MAX187AC/BC
Q30
Q50
MAX187AE/BE
Q30
Q60
MAX187C
Q30
0 to 6mA output load
1
V
mA
ppm/NC
mV
EXTERNAL REFERENCE AT REF (Buffer Disabled, VREF = 4.096V)
Input Voltage Range
2.50
Input Current
VDD + 50mV
200
Input Resistance
12
Shutdown REF Input Current
350
20
1.5
V
µA
kI
10
µA
DIGITAL INPUTS (SCLK, CS, SHDN)
SCLK, CS Input High Voltage
SCKL, CS Input Low Voltage
SCLK, CS Input Hysteresis
VINH
2.4
V
VINL
0.8
VHYST
0.15
V
V
SCLK, CS Input Leakage
IIN
VIN = 0V or VDD
±1
µA
SCLK, CS Input Capacitance
CIN
(Note 4)
15
pF
SHDN Input High Voltage
VINSH
SHDN Input Low Voltage
VINSL
SHDN Input Current
IINS
SHDN Input Mid voltage
VIM
SHDN Voltage, Floating
VFLT
SHDN Maximum Allowed
Leakage, Mid-Input
Maxim Integrated
VDD - 50mV
VSHDN = VDD or 0V
1.5
0.5
V
±4.0
µA
VDD - 1.5
2.75
SHDN = Open
SHDN = Open
V
-100
V
V
100
nA
3
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT (DOUT)
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Output Capacitance
IL
COUT
ISINK = 5mA
0.4
ISINK = 16mA
0.3
ISOURCE = 1mA
4
V
V
VCS = 5V
VCS = 5V (Note 4)
Q10
FA
15
pF
5.25
V
POWER REQUIREMENTS
Supply Voltage
Supply Current
VDD
IDD
4.75
Operating mode
MAX187
1.5
2.5
MAX189
1.0
2.0
2
10
FA
Q0.06
Q0.5
mV
Power-down mode
Power-Supply Rejection
PSR
VDD = +5V Q5%; external reference,
4.096V; full-scale input (Note 6)
mA
TIMING CHARACTERISTICS
(VDD = +5V ±5%, TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
tACQ
CS = high (Note7)
SCLK Fall to Output Data Valid
tDQ
CLOAD = 100pF
CS Fall to Output Enable
tDV
CLOAD = 100pF
100
tTR
CLOAD = 100pF
100
ns
5
MHz
CS Rise to Output Disable
1.5
UNITS
Track/Hold Acquisition Time
µs
MAX18_ _C/E
20
150
MAX18_ _M
20
200
ns
ns
SCLK Clock Frequency
tSCLK
SCLK Pulse Width High
tCH
100
ns
SCLK Pulse Width Low
SCLK Low to CS Fall Setup Time
CS Pulse Width
tCL
100
ns
tCSO
50
ns
tCS
500
ns
Note 1: Tested at VDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimumtime needed for the signal to be acquired.
Maxim Integrated
4
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Typical Operating Characteristics
POWER-SUPPLY REJECTION
vs. TEMPERATURE
VREF vs. TEMPERATURE
0.12
0.10
0.08
0.06
0.04
0.02
4.089
4.088
4.087
4.086
4.085
4.084
4.083
4.082
4.081
0
4.080
-20
20
60
100
140
-60
-20
20
60
100
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
1.8
MAX187
1.4
MAX189
1.0
0.6
140
MAX187 toc04
2.2
7
SHUTDOWN SUPPLY CURRENT (µA)
MAX187 toc03
-60
SUPPLY CURRENT (mA)
MAX187 toc02
0.14
4.090
INTERNAL REFERENCE VOLTAGE (V)
MAX187 toc01
POWER-SUPPLY REJECTION (mV)
0.16
6
5
4
3
2
1
0.2
0
-60
-20
20
60
TEMPERATURE (°C)
Maxim Integrated
100
140
-60
-20
20
60
100
140
TEMPERATURE (°C)
5
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Pin Configurations
TOP VIEW
1
+
VDD
2
AIN
3
SHDN
4
REF
MAX187
MAX189
SCLK
8
CS
7
DOUT
6
GND
5
PDIP
+
VDD 1
16 SCLK
N.C. 2
15 CS
AIN 3
MAX187
MAX189
N.C. 4
14 N.C.
13 N.C.
N.C. 5
12 DOUT
SHDN 6
11 DGND
N.C. 7
10 AGND
REF 8
9 N.C.
Wide SO
Pin Description
PIN
NAME
FUNCTION
PDIP
WIDE SO
1
1
VDD
Supply Voltage. +5V, Q5%
2
3
AIN
Sampling Analog Input. 0V to VREF range
3
6
4
8
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX187/MAX189 down to 10FA
(max) supply current. Both MAX187 and MAX189 are fully operational with either SHDN
high or unconnected. For the MAX187, pulling SHDN high enables the internal reference,
and letting SHDN unconnected disables the internal reference and allows for the use of an
external reference.
REF
Reference Voltage—sets analog voltage range and functions as a 4.096V output for the
MAX187 with enabled internal reference. REF also serves as a +2.5V to VDD input for a
precision reference for both MAX187 (disabled internal reference) and MAX189. Bypass
with 4.7FF if internal reference is used, and with 0.1FF if an external reference is applied.
Analog and Digital Ground
5
—
GND
—
10
AGND
Analog Ground
—
11
DGND
Digital Ground
6
12
DOUT
Serial Data Output. Data changes state at SCLK’s falling edge.
7
15
CS
8
16
SCLK
Serial Clock Input. Clocks data out with rates up to 5MHz.
—
2, 4, 5, 7,
9, 13. 14
N.C.
No Connection. Not internally connected. Connect to AGND for best noise performance.
Maxim Integrated
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is
high impedance.
6
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Detailed Description
Converter Operation
The MAX187/MAX189 use input track/hold (T/H) and successive approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. No external hold capacitor is needed for the T/H. Figures 3a and
3b show the MAX187/MAX189 in their simplest configuration. The MAX187/MAX189 convert input signals in the
0V to VREF range in 10µs, including T/H acquisition time.
The MAX187’s internal reference is trimmed to 4.096V,
while the MAX189 requires an external reference. Both
devices accept external reference voltages from +2.5V to
VDD. The serial interface requires only three digital lines,
SCLK, CS, and DOUT, and provides easy interface to
microprocessors (µPs).
Both converters have two modes: normal and shutdown.
Pulling SHDN low shuts the device down and reduces
supply current to below 10µA, while pulling SHDN high or
leaving it floating puts the device into the operational mode.
A conversion is initiated by CS falling. The conversion result
is available at DOUT in unipolar serial format. A high bit,
signaling the end of conversion (EOC), followed by the data
bits (MSB first), make up the serial data stream.
The MAX187 operates in one of two states: (1) internal
reference and (2) external reference. Select internal
reference operation by forcing SHDN high, and external
reference operation by floating SHDN.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s analog comparator. The full-scale input voltage
depends on the voltage at REF.
ZERO SCALE
FULL SCALE
Internal Reference
(MAX187 only)
REFERENCE
0V
+4.096V
External Reference
0V
VREF
For specified accuracy, the external reference voltage
range spans from +2.5V to VDD.
+5V
3kI
DOUT
DOUT
CLOAD = 100pF
3kI
CLOAD = 100pF
DGND
DGND
A. HIGH-Z TO VOH AND VOL TO VOH
B. HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time
+5V
3kI
DOUT
DOUT
CLOAD = 100pF
3kI
DGND
A. VOH TO HIGH-Z
CLOAD = 100pF
DGND
B. VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
Maxim Integrated
7
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
4.7µF
4.7µF
0.1µF
0.1µF
1
+5V
ANALOG INPUT
0 TO +5V
2
SHUTDOWN
INPUT
3
ON
AIN
MAX187
SHDN
4
OFF
SCLK
VDD
CS
DOUT
GND
REF
8
+5V
7
SERIAL
INTERFACE
OFF
REFERENCE
INPUT
5
4.7µF
Figure 3a. MAX187 Operational Diagram
12-BIT CAPACITIVE DAC
TRACK INPUT
CHOLD
16pF
-
CPACKAGE
CSWITCH
COMPARATOR
ZERO
+
RIN
5kI
HOLD
TRACK
GND
3
SCLK
VDD
AIN
MAX189
SHDN
CS
DOUT
8
7
SERIAL
INTERFACE
6
ON
4
REF
GND
5
0.1µF
Figure 3b. MAX189 Operational Diagram
REF
AIN
2
ANALOG INPUT
0 TO +5V
SHUTDOWN
INPUT
6
1
HOLD
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
to 0V within the limits of a 12-bit resolution. This action
is equivalent to transferring a charge from CHOLD to the
binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal. At the
conversion’s end, the input side of CHOLD switches back
to AIN, and CHOLD charges to the input signal again.
The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is calculated by:
tACQ = 9 (RS + RIN) 16pF
Figure 4. Equivalent Input Circuit
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges capacitor CHOLD. Bringing CS low ends the acquisition interval.
At this instant, the T/H switches the input side of CHOLD
to GND. The retained charge on CHOLD represents a
sample of the input, unbalancing the node ZERO at the
comparator’s input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
Maxim Integrated
where RIN = 5kI, RS = the source impedance of the
input signal, and tACQ is never less than 1.5Fs. Source
impedances below 5kI do not significantly affect the AC
performance of the ADC.
Input Bandwidth
The ADCs’ input tracking circuitry has a 4.5MHz smallsignal bandwidth, and an 8V/Fs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is recommended. See the MAX274/MAX275 continuous-time
filters data sheet.
8
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Input Protection
Internal protection diodes that clamp the analog input
allow the input to swing from GND - 0.3V to VDD + 0.3V
without damage. However, for accurate conversions near
full scale, the input must not exceed VDD by more than
50mV, or be lower than GND by 50mV.
If the analog input exceeds the supplies by more than
50mV beyond the supplies, limit the input current
to 2mA, since larger currents degrade conversion
accuracy.
Driving the Analog Input
The input lines to AIN and GND should be kept as short
as possible to minimize noise pickup. Shield longer
leads. Also see the Input Protection section.
Because the MAX187/MAX189 incorporate a T/H, the
drive requirements of the op amp driving AIN are less
stringent than those for a successive-approximation ADC
without a T/H. The typical input capacitance is 16pF. The
amplifier bandwidth should be sufficient to handle the
frequency of the input signal. The MAX400 and OP07
work well at lower frequencies. For higher-frequency
operation, the MAX427 and OP27 are practical choices.
The allowed input frequency range is limited by the
75ksps sample rate of the MAX187/MAX189. Therefore,
the maximum sinusoidal input frequency allowed is
37.5kHz. Higher-frequency signals cause aliasing problems unless undersampling techniques are used.
Reference
The MAX187 can be used with an internal or external reference, while the MAX189 requires an external reference.
Internal Reference
The MAX187 has an on-chip reference with a buffered temperature-compensated bandgap diode, lasertrimmed to +4.096V Q0.5%. Its output is connected to
REF and also drives the internal DAC. The output can be
used as a reference voltage source for other components
and can source up to 0.6mA. Decouple REF with a 4.7FF
capacitor. The internal reference is enabled by pulling
the SHDN pin high. Letting SHDN float disables the internal reference, which allows the use of an external reference, as described in the External Reference section.
External Reference
The MAX189 operates with an external reference at the
REF pin. To use the MAX187 with an external reference,
disable the internal reference by letting SHDN float. Stay
within the voltage range +2.5V to VDD to achieve specified accuracy. The minimum input impedance is 12kI for
DC currents. During conversion, the external reference
must be able to deliver up to 350FA DC load current and
have an output impedance of 10I or less. The recommended minimum value for the bypass capacitor is 0.1FF.
If the reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7FF capacitor.
COMPLETE CONVERSION SEQUENCE
CS
tWAKE
SHDN
DOUT
CONVERSION 1
POWERED UP
CONVERSION 1
POWERED DOWN
POWERED UP
Figure 5. MAX187/MAX189 Shutdown Sequence
Maxim Integrated
9
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, it takes the fully discharged
4.7FF reference bypass capacitor up to 20ms to provide
adequate charge for specified accuracy. With SHDN
not pulled low, the MAX187/MAX189 are now ready to
convert.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated.
After an internally timed 8.5Fs conversion period, the end
of conversion is signaled by DOUT pulling high. Data can
then be shifted out serially with the external clock.
Using SHDN to Reduce
Supply Current
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conversions. This is shown in Figure 6, a plot of average supply
current vs. conversion rate. Because the MAX189 uses
an external reference voltage (assumed to be present
continuously), it “wakes up” from shutdown more quickly,
and therefore provides lower average supply currents.
The wakeup-time, tWAKE, is the time from SHDN deasserted to the time when a conversion may be initiated.
For the MAX187, this time is 2Fs. For the MAX189, this
time depends on the time in shutdown (see Figure 7)
because the external 4.7FF reference bypass capacitor
loses charge slowly during shutdown (see the specifications for shutdown, REF Input Current = 10FA max).
External Clock
The actual conversion does not require the external
clock. This frees the FP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the FP’s convenience at any clock rate
from 0 to 5MHz. The clock duty cycle is unrestricted if
each clock phase is at least 100ns. Do not run the clock
while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline the operation of the serial
interface.
A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to convert,
and DOUT changes from high impedance to logic low.
SCLK must be kept inactive during the conversion. An
internal register stores the data when the conversion is
in progress.
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing signal. SCLK shifts the data out of this register any time after
the conversion is complete. DOUT transitions on SCLK’s
falling edge. The next falling clock edge produces the
MSB of the conversion at DOUT, followed by the remaining bits. Since there are 12 data bits and one leading
high bit, at least 13 falling clock edges are needed to
shift out these bits. Extra clock pulses occurring after the
conversion result has been clocked out, and prior to a
rising edge of CS, produce trailing 0s at DOUT and have
no effect on converter operation.
3.0
10,000
2.0
tWAKE (ms)
SUPPLY CURRENT (µA)
2.5
1000
MAX187
100
1.0
MAX189*
10
1.5
0.5
*REF CONNECTED TO VDD
1
0.1
1
10
100
1k
10k
100k
CONVERSIONS PER SECOND
Figure 6. Average Supply Current vs. Conversion Rate
Maxim Integrated
0
0.0001
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 7. tWAKE vs. Time in Shutdown (MAX187 Only)
10
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
CS
1
SCLK
4
B11 B10 B9
DOUT
8
B8
B7
B6
B5
12
B4
B3
B2
B1
B0
EOC
INTERFACE IDLE
A/D
STATE
TRACK
CONVERSION
IN PROGRESS
EOC
CONVERSION
0
8.5µs
(tCONV)
TRAILING
ZEROS
CLOCK OUTPUT DATA
IDLE
TRACK
0µs
MINIMUM
CYCLE TIME
CONV. 1
0µs
12 x 0.250µs = 3.25µs
0.5µs
(tCS)
TOTAL = 12.25µs
Figure 8. MAX187/MAX189 Interface Timing Sequence
tCS
CS
tCS0
tCH
SCLK
tDO
tDV
tCL
tCONV
DOUT
B2
tTR
B1
B0
tAPR
INTERNAL
T/H
(TRACK)
(HOLD)
(TRACK)
Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing
Maxim Integrated
11
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
13 clock cycles at full speed. Raise CS after the conversion’s LSB has been read. After the specified minimum
time, tACQ, CS can be pulled low again to initiate the next
conversion.
Output Coding and Transfer Function
The data output from the MAX187/MAX189 is binary, and
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive integer
LSB values. If VREF = +4.096V, then 1 LSB = 1.00mV or
4.096V/4096.
Dynamic Performance
High-speed sampling capability and a 75ksps throughput
make the MAX187/MAX189 ideal for wideband signal processing. To support these and other related applications,
Fast Fourier Transform (FFT) test techniques are used
to guarantee the ADC’s dynamic frequency response,
distortion, and noise at the rated throughput. Specifically,
this involves applying a low-distortion sine wave to the
ADC input and recording the digital conversion results for
a specified time. The data is then analyzed using an FFT
algorithm that determines its spectral content. Conversion
errors are then seen as spectral elements outside of the
fundamental input frequency. ADCs have traditionally
been evaluated by specifications such as Zero and FullScale Error, Integral Nonlinearity (INL), and Differential
Nonlinearity (DNL). Such parameters are widely accepted
for specifying performance with DC and slowly varying
signals, but are less useful in signal-processing applications, where the ADC’s impact on the system transfer
function is the main concern. The significance of various
DC errors does not translate well to the dynamic case, so
different tests are required.
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS amplitude of all other ADC output signals. The input
bandwidth is limited to frequencies above DC and below
one-half the ADC sample (conversion) rate.
The theoretical minimum ADC noise is caused by quantization error and is a direct result of the ADC’s resolution:
SINAD = (6.02N + 1.76)dB, where N is the number of bits
of resolution. An ideal 12-bit ADC can, therefore, do no
better than 74dB. An FFT plot of the output shows the output level in various spectral bands. Figure 11 shows the
result of sampling a pure 10kHz sine wave at a 75ksps
rate with the MAX187/MAX189.
20
OUTPUT CODE
FULL-SCALE
TRANSITION
11...111
fS = 75ksps
fT = 10kHz
TA = +25°C
0
11...110
-20
FS = +4.096V
1 LSB = FS
4096
AMPLITUDE (dB)
11...101
-40
-60
-80
00...011
-100
00...010
00...01
-120
00...000
0
1
2
FS
3
INPUT VOLTAGE (LSBs)
FS - 3/2 LSB
-140
0
18.75
37.5
FREQUENCY (kHz)
Figure 10. MAX187/MAX189 UnipolarTransfer Function, 4.096V
= Full Scale
Maxim Integrated
Figure 11. MAX187/MAX189 FFT plot
12
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
above equation and substituting in the measured SINAD:
N = (SINAD - 1.76)/6.02. Figure 12 shows the effective
number of bits as a function of the input frequency for the
MAX187/MAX189.
Total Harmonic Distortion
If a pure sine wave is sampled by an ADC at greater than
the Nyquist frequency, the nonlinearities in the ADC’s
transfer function create harmonics of the input frequency
present in the sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not including
the DC component) to the RMS amplitude of the fundamental frequency. This is expressed as follows:
THD = 20log
V2 2 + V3 2 + V4 2 + … VN 2
V1
where V1 is the fundamental RMS amplitude, and V2
through VN are the amplitudes of the 2nd through
Nth harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th harmonics.
Connection to Standard Interfaces
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, set the CPU’s serial interface in master mode so the CPU generates the serial
clock. Choose a clock frequency up to 2.5MHz.
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a DOUT
rising edge to determine the end of conversion.
3) Activate SCLK for a minimum of 13 clock cycles.
The first falling clock edge will produce the MSB of
the DOUT conversion. DOUT output data transitions
on SCLK’s falling edge and is available in MSB-first
format. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the FP on SCLK’s
rising edge.
4) Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
5) With CS = high, wait the minimum specified time, tCS,
before launching a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversions end, wait for the minimum acquisition
time, tACQ, before starting a new conversion.
12.2
12.0
11.8
11.6
EFFECTIVE BITS
Applications Information
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of the
conversion padded with one leading 1, and trailing 0s if
SCLK is still active with CS kept low.
11.4
11.2
11.0
10.8
SPI and MICROWIRE
10.6
10.4
(UNDERSAMPLED)
10.2
1
10
100
INPUT FREQUENCY (kHz)
Figure 12. Effective Bits vs. Input Frequency
1000
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until DOUT
goes high or the maximum specified 8.5Fs conversion
time. Two consecutive 1-byte reads are required to get
the full 12 bits from the ADC. DOUT output data transitions on SCLK’s falling edge and is clocked into the FP
on SCLK’s rising edge.
The first byte contains a leading 1 and 7 bits of conversion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections and
Figure 14 for timing.
Maxim Integrated
13
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
QSPI
I/O
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX187/MAX189 require
13 clock cycles from the FP to clock out the 12 bits of
data with no trailing 0s (Figure 15). The maximum clock
frequency to ensure compatibility with QSPI is 2.77MHz.
CS
SCK
SCLK
MISO
DOUT
+5V
MAX187
MAX189
Opto-Isolated Interface,
Serial-to-Parallel Conversion
SS
Many industrial applications require electrical isolation to
separate the control electronics from hazardous electrical conditions, provide noise immunity, or prevent excessive current flow where ground disparities exist between
the ADC and the rest of the system. Isolation amplifiers
typically used to accomplish these tasks are expensive.
In cases where the signal is eventually converted to a
digital form, it is cost effective to isolate the input using
opto-couplers in a serial link.
The MAX187 is ideal in this application because it includes
both T/H amplifier and voltage reference, operates from a
single supply, and consumes very little power (Figure 16).
The ADC results are transmitted across a 1500V isolation
barrier provided by three 6N136 opto-isolators. Isolated
power must be supplied to the converter and the isolated
side of the opto-couplers. 74HC595 three-state shift registers are used to construct a 12-bit parallel data output.
The timing sequence is identical to the timing shown
in Figure 8. Conversion speed is limited by the delay
through the opto-isolators. With a 140kHz clock, conversion time is 100Fs.
The universal 12-bit parallel data output can also be used
without the isolation stage when a parallel interface is
required. Clock frequencies up to 2.9MHz are possible
without violating the 20ns shift-register setup time. Delay or
invert the clock signal to the shift registers beyond 2.9MHz.
A. SPI
CS
CS
SCK
SCLK
MISO
DOUT
+5V
MAX187
MAX189
SS
B. QSPI
I/O
CS
SK
SCLK
SI
DOUT
MAX187
MAX189
C. MICROWIRE
Figure 13. Common Serial-Interface Connections to the
MAX187/MAX189
1ST BYTE READ
2ND BYTE READ
SCLK
CS
HI-Z
DOUT
tCONV
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
HI-Z
EOC
Figure 14. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Maxim Integrated
14
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
SCLK
CS
tCONV
HI-Z
HI-Z
DOUT
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
EOC
Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)
+5V ON THIS SIDE OF
BARRIER MUST BE ISOLATED POWER
+5V
3kI
6N136
+5V
1
8
2
7
CS/START
SCLK/INPUT CLOCK
200I
3
6
4
74HC04
5
10µF
6N136
MAX187
0.1µF
1
2
4
ANALOG
INPUT
5
4.7µF
1
8
VDD
SHDN
AIN
CS
REF
GND
SCLK
DOUT
3
7
3kI
8
7
2
6
3
13
4
6N136
1
8
2
7
3
6
6
5
4
3
2
1
15
16
8
9
QH’
QH
QG
14
SER
74HC595 QF
11
QE
SCK
QD
12
QC
RCK
QB
10
SCLR
+5V
QA
6
5
SIGNAL
GROUND
7
D11 (MSB)
D10
D9
D8
+5V
0.1µF
200I
74HC04
470I
QH
14
QG
SER
74HC595 QF
11
QE
SCK
QD
12
QC
RCK
QB
10
QA
SCLR
8.2kI
13
8
7
6
5
4
3
2
1
15
16
D7
D6
D5
D4
D3
D10
D1
D0 (LSB)
+5V
0.1µF
4
5
Figure 16. 12-Bit Isolated ADC
Maxim Integrated
15
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Layout, Grounding, Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines underneath the ADC package.
Figure 17 shows the recommended system ground connections. A single-point analog ground (“star” ground
point) should be established at GND, separate from the
logic ground. All other analog grounds should be connected to this ground. The 16-pin versions also have a
dedicated DGND pin available. Connect DGND to this
star ground point for further noise reduction. No other
digital system ground should be connected to this singlepoint analog ground. The ground return to the power
supply for this ground should be low impedance and as
short as possible for noise-free operation.
High-frequency noise in the VDD power supply may
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01FF
and 4.7FF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection. If the +5V power
supply is very noisy, a 10I resistor can be connected
as a lowpass filter to attenuate supply noise (Figure 17).
Maxim Integrated
SUPPLIES
+5V
GND
R* = 10I
4.7µF
0.01µF
VDD
AGND
DGND
MAX187
MAX189
+5V
DGND
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 17. Power-Supply Grounding Condition
16
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Ordering Information
PINPACKAGE
ERROR
(LSB)
PART
TEMP RANGE
MAX187ACPA+
0NC to +70NC
8 PDIP
±1/2
MAX187BCPA+
0NC to +70NC
8 PDIP
±1
MAX187CCPA+
0NC to +70NC
8 PDIP
±2
MAX187ACWE+
0NC to +70NC
16 Wide SO
±1/2
MAX187BCWE+
0NC to +70NC
16 Wide SO
±1
MAX187CCWE+
0NC to +70NC
16 Wide SO
MAX187AEPA+
-40NC to +85NC
8 PDIP
±1/2
MAX187BEPA+
-40NC to +85NC
8 PDIP
±1
MAX187CEPA+
-40NC to +85NC
8 PDIP
±2
MAX187AEWE+
-40NC to +85NC
16 Wide SO
±1/2
MAX187BEWE+
-40NC to +85NC
16 Wide SO
±1
MAX187CEWE+
-40NC to +85NC
16 Wide SO
MAX189ACPA+
0NC to +70NC
8 PDIP
±1/2
MAX189BCPA+
0NC to +70NC
8 PDIP
±1
MAX189CCPA+
0NC to +70NC
8 PDIP
MAX189ACWE+
0NC to +70NC
16 Wide SO
±1/2
MAX189BCWE+
0NC to +70NC
16 Wide SO
±1
MAX189CCWE+
0NC to +70NC
16 Wide SO
MAX189AEPA+
-40NC to +85NC
8 PDIP
±1/2
MAX189BEPA+
-40NC to +85NC
8 PDIP
±1
MAX189CEPA+
-40NC to +85NC
8 PDIP
MAX189AEWE+
-40NC to +85NC
16 Wide SO
±1/2
MAX189BEWE+
-40NC to +85NC
16 Wide SO
±1
MAX189CEWE+
-40NC to +85NC
16 Wide SO
±2
±2
±2
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 PDIP
P8+3
21-0043
—
16 SO
W16+3
21-0042
90-0107
±2
±2
±2
*Denotes a lead(Pb)–free/RoHS–compliant package.
Maxim Integrated
17
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/93
Initial release
1
3/12
Updated the Electrical Characteristics and Ordering Information.
DESCRIPTION
PAGES
CHANGED
—
1, 3, 18
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012
Maxim Integrated Products, Inc.
18
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
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