19-4506; Rev 4; 2/97
ANUAL
N KIT M EET
IO
T
A
U
EVAL
TA SH
WS DA
FOLLO
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
The MAX191 operates from a single +5V supply or from
dual ±5V supplies, allowing ground-referenced bipolar
input signals. The device features a logic power-down
input, which reduces the 3mA VDD supply current to
50µA max, including the internal-reference current.
Decoupling capacitors are the only external components needed for the power supply and reference. This
ADC operates with either an external reference, or an
internal reference that features an adjustment input for
trimming system gain errors.
The MAX191 provides three interface modes: two 8-bit
parallel modes, and a serial interface mode that is compatible with SPITM, QSPITM, and MICROWIRETM serialinterface standards.
________________________Applications
Battery-Powered Data Logging
PC Pen Digitizers
High-Accuracy Process Control
Electromechanical Systems
Data-Acquisition Boards for PCs
Automatic Testing Systems
Telecommunications
Digital Signal Processing (DSP)
OSC
3-STATE
OUTPUT
2.46V
REF
12
AIN +
AIN -
8-BIT
BUS
AND
SERIAL
I/O
18
17
16
15
14
13
11
10
3
4
IN REF OUT
12-BIT
SAR ADC
MAX191
7
12
AGND
DGND
2
VSS
CONTROL
LOGIC
1 22 8
BIP
PD
PAR
Ordering Information
PART
TEMP. RANGE
MAX191ACNG
MAX191BCNG
MAX191ACWG
MAX191BCWG
MAX191BC/D
MAX191AENG
MAX191BENG
MAX191AEWG
MAX191BEWG
MAX191AMRG
MAX191BMRG
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
PIN-PACKAGE
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
24 Wide SO
Dice*
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
24 Wide SO
24 Narrow CERDIP**
24 Narrow CERDIP**
ERROR
(LSB)
±1/2
±1
±1/2
±1
±1
±1/2
±1
±1/2
±1
±1/2
±1
Pin Configuration
CLK/SCLK
23
5
VREF
6
REFADJ
12-Bit Resolution, 1/2LSB Linearity
+5V or ±5V Operation
Built-In Track/Hold
Internal Reference with Adjustment Capability
Low Power: 3mA Operating Mode
20µA Power-Down Mode
♦ 100ksps Tested Sampling Rate
♦ Serial and 8-Bit Parallel µP Interface
♦ 24-Pin Narrow DIP and Wide SO Packages
* Dice are specified at TA = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Functional Diagram
VDD
24
____________________________Features
♦
♦
♦
♦
♦
20
19
9
21
TOP VIEW
PD 1
24 VDD
VSS 2
23 CLK/SCLK
D7/DOUT
AIN+ 3
22 PAR
D6/SCLKOUT
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
AIN- 4
21 HBEN
CS
RD
BUSY
HBEN
VREF 5
MAX191
REFADJ 6
20 CS
19 RD
AGND 7
18 D7/DOUT
BIP 8
17 D6/SCLKOUT
BUSY 9
16 D5/SSTRB
D0/D8 10
15 D4
D1/D9 11
14 D3/D11
DGND 12
13 D2/D10
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX191
General Description
The MAX191 is a monolithic, CMOS, 12-bit analog-todigital converter (ADC) featuring differential inputs,
track/hold (T/H), internal voltage reference, internal or
external clock, and parallel or serial µP interface. The
MAX191 has a 7.5µs conversion time, a 2µs acquisition
time, and a guaranteed 100ksps sample rate.
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
ABSOLUTE MAXIMUM RATINGS
VDD to DGND............................................................-0.3V to +7V
VSS to AGND ............................................................-7V to +0.3V
VDD to VSS ..............................................................................12V
AGND, VREF, REFADJ to DGND................-0.3V to (VDD + 0.3V)
AIN+, AIN-, PD to VSS .................................-0.3V to (VDD + 0.3V)
CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (VDD + 0.3V)
BUSY, D0–D7 to DGND..............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW
Wide SO (derate 11.76mW/°C above +70°C) ......................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C) ........1000mW
Operating Temperature Ranges
MAX191_C_ _ ................................................................0°C to +70°C
MAX191_E_ _ .............................................................-40°C to +85°C
MAX191_M_ _ ..........................................................-55°C to +125°C
Storage Temperature Range.....................................-65°C to +160°C
Lead Temperature (soldering, 10sec).....................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
Integral Nonlinearity
Differential Nonlinearity
12
INL
DNL
Offset Error
Gain Error (Note 3)
Gain-Error Tempco (Note 4)
Bits
MAX191A
±1/2
MAX191B
±1
No missing codes over temperature
±1
MAX191A
±1
MAX191B
±2
MAX191A
±2
MAX191B
±3
Excludes internal-reference drift
±0.2
LSB
LSB
LSB
LSB
ppm/°C
DYNAMIC ACCURACY (sample rate = 100kHz, VIN = 4Vp-p)
Signal-to-Noise plus Distortion
Ratio
SINAD
1kHz input signal, TA = +25°C
Total Harmonic Distortion
(up to the 5th Harmonic)
THD
1kHz input signal, TA = +25°C
Spurious-Free Dynamic Range
SFDR
1kHz input signal, TA = +25°C
70
dB
-80
80
dB
dB
CONVERSION RATE
Conversion Time (Note 5)
tCONV
Synchronous CLK (12 to 13 CLKs)
Internal CLK, CL = 120pF
7.50
6
8.125
12
Track/Hold Acquisition Time
2
µs
µs
Aperture Delay
25
ns
Aperture Jitter
50
ps
External Clock Frequency
Range (Note 6)
2
18
fCLK
0.1
_______________________________________________________________________________________
1.6
MHz
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
V
±10
µA
ANALOG INPUT
VSS
Input Voltage Range (Note 7)
VIN = VSS to VDD
Input Leakage Current
Input Capacitance (Note 6)
45
Small-Signal Bandwidth
2
80
pF
MHz
INTERNAL REFERENCE
TA = +25°C
VREF Output Voltage
4.076
4.096
4.116
V
MAX191_C
50
VREF Output Tempco (Note 8)
MAX191_E
60
MAX191_M
TA = +25°C
80
Output Current Capability (Note 9)
2
mA
Load Regulation
TA = +25°C, IOUT = 0mA to 2mA
4
mV
Output Short-Circuit Current
18
Capacitive Load Required
Reference compensation mode—external
VDD = ±5%, VSS = ±5%
Power-Supply Rejection
mA
4.7
µF
±300
REFADJ Input Adjustment Range
(Note 10)
-60
REFADJ Disable Threshold
4.5
REFADJ Output Voltage
µV
30
mV
V
2.4
REFADJ Input Current
mA
ppm/°C
REFADJ = 5V
V
60
µA
5.0
V
1
mA
REFERENCE INPUT
Input Voltage Range
External-reference mode
Input Current
External-reference = 5V
Input Resistance
External-reference mode
2.5
5
10
kΩ
LOGIC INPUTS
Input Low Voltage
VIL
CS, RD, CLK, HBEN, PAR, BIP
Input High Voltage
VIH
CS, RD, CLK, HBEN, PAR, BIP
Input Current
IIN
VIN = 0V to VDD
±10
PD = high/float
±200
0.8
2.4
V
V
µA
Input Current CLK
IIN
Input Capacitance (Note 6)
CIN
10
pF
PD Input Low Voltage
VIL
0.5
V
PD Input High Voltage
VIH
PD Input Current
IIN
PD = 0V to VDD (Note 11)
±20
µA
Maximum current allowed for “floating state”
±100
nA
PD External Leakage for Float
State (Note 12)
PD Floating-State Voltage
VFLT
PD = low
±0.1
4.5
Reference compensation mode—external
µA
V
2.8
V
_______________________________________________________________________________________
3
MAX191
ELECTRICAL CHARACTERISTICS (continued)
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.4
V
LOGIC OUTPUTS
Output Low Voltage
VOL
IOUT = 1.6mA
Output High Voltage
VOH
IOUT = -200µA
Three-State Leakage Current
IL
Three-State Output
Capacitance (Note 6)
4.0
V
D0/D8-D7/DOUT
COUT
±10
µA
15
pF
5.25
V
POWER REQUIREMENTS
Positive Supply Voltage
VDD
Negative Supply Voltage
VSS
Positive Supply Current
IDD
Negative Supply Current
ISS
4.75
-5.25
CS = RD = VDD,
AIN = 5V, D0/D8–D7/
DOUT = 0V or VDD,
HBEN = PAR = BIP
= 0V or VDD
0
V
PD = high/float
3
5
mA
PD = low
20
50
µA
PD = high/float
20
100
PD = low
1
20
µA
Positive Supply Rejection (Note 13)
FS change, VDD = 5V ±5%
±1/2
LSB
Negative Supply Rejection (Note 13)
FS change, VSS = -5V ±5%
±1/2
LSB
TIMING CHARACTERISTICS (Figures 6–10)
(VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14)
PARAMETER
SYMBOL
CONDITIONS
TA = +25°C
MIN TYP MAX
MAX191C/E
MIN TYP MAX
MAX191M
MIN TYP MAX
UNITS
CS to RD Setup Time
t1
RD to BUSY Delay
t2
CL = 50pF
120
140
160
ns
Data Access Time (Note 15)
t3
CL = 100pF
120
140
160
ns
RD Pulse Width
t4
150
150
150
ns
CS to RD Hold Time
t5
0
0
0
ns
Data Setup Time After
BUSY (Note 15)
t6
Bus-Relinquish Time (Note 16)
t7
HBEN to RD Setup Time
t8
80
100
120
ns
HBEN to RD Hold Time
t9
0
0
0
ns
Delay Between Read
Operations (Note 6)
t10
200
200
200
ns
2
2
µs
0
0
80
100
100
110
ns
120
ns
120
ns
Delay Between Conversions
t11
Aperture Delay
t12
CLK to BUSY Delay (Note 6)
t13
200
230
260
ns
SCLKOUT to SSTRB
Rise Delay
t14
100
130
150
ns
SCLKOUT to SSTRB
Fall Delay
t15
100
130
150
ns
4
2
0
Jitter < 50ps
25
ns
_______________________________________________________________________________________
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
(VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14)
PARAMETER
SYMBOL
CONDITIONS
TA = +25°C
MIN TYP MAX
MAX191C/E
MIN TYP MAX
MAX191M
MIN TYP MAX
UNITS
CS or RD Hold Time
t16
10
10
10
CS or RD Setup Time
t17
150
150
150
CS to DOUT Three-State
t19
100
110
120
ns
SCLK to SCLKOUT Delay
t20
160
180
200
ns
SCLKOUT to DOUT Delay
t21
100
130
150
ns
SCLK to DOUT Delay
t22
240
260
280
ns
SCLK to SSTRB Delay
t23
260
310
350
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
ns
ns
Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
VDD = 5V, VSS = 0V, FS = VREF.
FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB.
Gain-Error Tempco = ∆GE is the gain-error change from TA = +25°C to TMIN or TMAX.
Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Guaranteed by design, not production tested.
AIN+, AIN- must not exceed supplies for specified accuracy.
VREF TC = ∆T, where ∆VREF is reference-voltage change from TA = +25°C to TMIN or TMAX.
Output current should not change during conversion. This current is in addition to the current required by the internal DAC.
REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V.
This will typically result in a 1.7 times larger change in the REF output (Figure 19a).
This current is included in the PD supply current specification.
Floating the PD pin guarantees external compensation mode.
VREF = 4.096V, external reference.
All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V.
t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
_______________________________________________________________________________________
5
MAX191
TIMING CHARACTERISTICS (Figures 6–10) (continued)
__________________________________________Typical Operating Characteristics
CLOCK FREQUENCY
vs. TIMING CAPACITOR
IDD
15
ISS (µA)
SUPPLY CURRENT (µA)
0.1
GR191-C
20
20
1
25
GR191-B
25
GR191-A
SEE FIGURE 5
TA = +25˚C
CLOCK FREQUENCY (MHz)
NEGATIVE SUPPLY CURRENT
vs. TEMPERATURE
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
10
VDD = +5V
VSS = -5V
PD = 0V
10
15
10
5
5
ISS
0
0
10
1
-60
-30
TIMING CAPACITOR (nF)
60
30
90
120
1.5
1.0
0
-60
-80
-94.3dB -96.1dB-98.0dB -93.8dB
-100
60
90
TEMPERATURE (°C)
120
150
150
-40
-60
-86.0dB
-80
-90.8dB
-100
-120
-140
30
120
fIN = 10kHz
fS = 100kHz
SNR = 71.2dB
TA = +25˚C
-20
-120
0.5
90
0
SIGNAL AMPLITUDE (dB)
2.0
-40
60
30
10kHz FFT PLOT
fIN = 1kHz
fS = 100kHz
SNR = 72dB
TA = +25˚C
-20
SIGNAL AMPLITUDE (dB)
2.5
0
0
1kHz FFT PLOT
3.0
-30
-30
TEMPERATURE (°C)
0
GR191-D
3.5
-60
-60
150
TEMPERATURE (°C)
POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
6
0
GR191-E
0.1
GR191-F
0.01
IDD (mA)
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
-140
0
1
2
3
4
FREQUENCY (kHz)
5
6
0
5
10
15
20
25
FREQUENCY (kHz)
_______________________________________________________________________________________
30
35
40
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
PIN
NAME
FUNCTION
1
PD
Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic
high selects normal operation, internal-reference compensation mode. An open-circuit condition selects
normal operation, external-reference compensation mode.
2
VSS
Negative Supply, 0V to -5.25V
3
AIN+
Sampled Analog Input
4
AIN-
Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section).
5
VREF
Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to
VDD.
6
REFADJ
7
AGND
8
BIP
9
BUSY
BUSY Output is low during a conversion.
10
D0/D8
Three-State Data Outputs: LSB = D0
11
D1/D9
Three-State Data Outputs
12
DGND
Digital Ground
13
D2/D10
Three-State Data Outputs
14
D3/D11
Three-State Data Outputs: MSB = D11
15
D4
16
D5/SSTRB
Three-State Data Output/Serial Strobe Output in serial mode
17
D6/SCLKOUT
Three-State Data Output/Serial Clock Output in serial mode
18
D7/DOUT
19
RD
Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory
mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKOUT and
SSTRB when CS is low. RD = high forces SCLKOUT and SSTRB into a high-impedance state.
20
CS
Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling
edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKOUT, SSTRB, and
DOUT into a high-impedance state.
21
HBEN
22
PAR
23
CLK/SCLK
24
VDD
Reference Adjust. Connect to VDD to use an extended reference at VREF.
Analog Ground
BIP = low selects unipolar mode
BIP = high selects bipolar mode (see Gain and Offset Adjustment section)
Three-State Data Output
Three-State Data Output/Data Output in serial mode
High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result
into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs
onto the data bus. In serial mode, HBEN = low enables SCLKOUT to operate during the conversion only,
HBEN = high enables SCLKOUT to operate continuously, provided CS is low.
Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.
Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to
this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal
oscillator.
Positive Supply, +5V ±5%
_______________________________________________________________________________________
7
MAX191
Pin Description
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
+5V
3k
OPEN
DN
DN
CL
CL
3k
DGND
DGND
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Access Time
+5V
3k
DN
DN
4.7µF
1
PD
VDD
CLK/SCLK
3 AIN+
PAR
4
AINHBEN
5
CS
VREF MAX191
0.1µF
6
RD
REFADJ
7
D7/DOUT
AGND
0.1µF 8
BIP
D6/SCLKOUT
OUTPUT 9
BUSY
D5/SSTRB
STATUS
10
DO/DB
D4
11
D1/D9
D3/D11
12
D2/D10
DGND
VSS
24 +5V
23 C1
22
21
SERIAL/PARALLEL
INTERFACE MODE
20
µP CONTROL
INPUTS
19
18
17
16
15
14
13
2
0V TO -5V
10pF
3k
10pF
DGND
DGND
a. VOH to High-Z
µP DATA BUS
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.
b. VOL to High-Z
Figure 2. Load Circuits for Bus-Relinquish Time
Figure 3. Operational Diagram
_______________Detailed Description
disconnects from the input during the conversion. In
unbuffered applications, an input filter capacitor
reduces conversion noise, but also may limit input
bandwidth.
The MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input signal to a 12-bit digital output. Flexible control logic provides easy interface to microprocessors (µPs), so most
applications require only the addition of passive components. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest operational configuration.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog comparator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s analog input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for lowbandwidth input signals (
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