Click here for production status of specific part numbers.
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
General Description
The
MAX19505–MAX19507/MAX19515–MAX19517
evaluation kits (EV kits) are fully assembled and tested
circuit boards that contain all the components necessary
to evaluate the performance of this family of 8-bit and
10-bit analog-to-digital converters (ADCs). The EV kits
also include Windows® 7/10-compatible software that
provides a simple graphical user interface (GUI) for
exercising the programmable features of the MAX19505/
MAX19507/MAX19515–MAX19517.
The MAX19505–MAX19507/MAX19515–MAX19517 EV
kits accept a single-ended analog input from an analog
signal source. The EV kits provide an on-board circuit that
transforms this analog single-ended signal into a differential
signal. The ADC digital output can be captured easily with
a basic logic analyzer. The EV kits can operate from a
single 3.6V nominal power supply and provide on-board
regulation for the analog, clock, digital, and logic circuitry.
Part Selection Table
PART
RESOLUTION (Bits)
SPEED (Msps)
MAX19505ETM+
8
65
MAX19506ETM+
8
100
MAX19507ETM+
8
130
MAX19515ETM+
10
65
MAX19516ETM+
10
100
MAX19517ETM+
10
130
Features
●● Single Power-Supply Operation
●● Low-Voltage and Low-Power Operation
●● On-Board Single-Ended to Differential
Transformer Circuitry
●● Differential or Single-Ended Clock Configuration
●● On-Board Clock-Shaping Circuit with Adjustable Duty
Cycle
●● On-Board SPI™ Interface Circuit
●● User-Selectable Supply Voltages
●● Lead(Pb)-Free and RoHS Compliant
●● Fully Assembled and Tested
Ordering Information
PART
TYPE
MAX19505EVKIT+
EV Kit
MAX19506EVKIT+
EV Kit
MAX19507EVKIT+
EV Kit
MAX19515EVKIT+
EV Kit
MAX19516EVKIT+
EV Kit
MAX19517EVKIT+
EV Kit
+Denotes lead(Pb)-free and RoHS compliant.
Component List
REF DES
QTY
DESCRIPTION
REF DES
QTY
C1, C40
2
4.7µF Tantalum Capacitor SMT
(3528), 16V, 20%
C2, C27,
C28, C76,
C77
5
10µF Ceramic Capacitor;
SMT (0805), 6.3V, 20%, X5R
C3
1
C4, C5
2
C6, C7, C29,
C48-C53,
C66-C73
17
0.1µF Ceramic Capacitor
SMT (0402), 10V; 10%; X5R
C25, C26
2
0.1µF Ceramic Capacitor
SMT (0603), 50V, 10%, X7R
1µF Ceramic Capacitor SMT
(0402), 6.3V; TOL = 10%, X5R
C30, C31
2
100pF Ceramic Capacitor
SMT (0402), 50V, 5%, C0G
8pF Ceramic Capacitor SMT (0402),
TOL = ±0.25pF
C43, C79,
C81-C89
11
0.1µF Ceramic Capacitor
SMT (0402), 10V, 10%, X7R
Windows 7, and Windows 10 are registered trademarks of Microsoft Corp.
SPI is a trademark of Motorola, Inc.
19-4301; Rev 2; 7/19
DESCRIPTION
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
Component List (continued)
REF DES
QTY
DESCRIPTION
C54, C55,
C75, C78
4
0.01µF Ceramic Capacitor
SMT (0603), 25V, 10%
C80
1
3.3µF Ceramic Capacitor
SMT (0402), 6.3V, 20%, X5R
CLK, SYNC,
VINA, VINB
4
D2
REF DES
QTY
DESCRIPTION
R81
1
1kΩ Resistor (0603), 5%, 0.10W
R82
1
12kΩ Resistor (0603), 1%, 0.10W
S1
1
Surface Mount Tactile Switch, SMT
T1-T4
4
0.4-800MHz Transformer, SMT
SMA Connector, 5 Pins
T5
1
1
Schottky Diode,
PIV = 70V, PD = 0.25W
0.20MHz TO 400MHz,
Transformer, SMT
TP1, TP2
2
Orange Test Point
DS1-DS4
4
Green LED SMT (0603)
TP3
1
Black Test Point
GND,
VSUPPLY
2
Banana Connector
U1
1
ADC, Dual-Channel, 10-BIT,
130Msps, TQFN 48-EP
J1, J8-J10,
JU6, JU7,
JU9, JU10
8
2 Pin Header
U2
1
Ultra-Low-Noise, High PSRR,
Low-Dropout, Linear Regulator
J5
1
48 Pin Header
U3
1
J6
1
USB MINI B-TYPE SMT Connector,
Right Angle, 9 PINS
Usb, Quad High Speed USB to
Multipurpose UART/MPSSE IC,
LQFP 64 12X12
U4
1
4-Bit Dual-Supply Bus Transceiver
With Configurable Voltage
Translation And 3-State Output,
TSSOP 16
U9
1
EEPROM, 2K, 16-BIT MICROWIRE
Compatible Serial EEPROM,
NSOIC8 150MIL
U10
1
TINYLOGIC, ULP-AS Dual Inverter,
SC70-6
U11, U12
2
16-BIT Buffer/Driver with
3-State Outputs, TSSOP 48
U14, U15
2
LOW-NOISE LDO regulator
PIN-Selectable Output Voltage.
TDFN8 2X2
USB3V3
1
Red Test Point
Y1
1
Crystal, SMT, 18pF, 12MHz
J7
1
10 Pin Header
JU1-JU3
3
4 Pin Header
L1, L2
2
28 Ferrite-Bead Inductor SMT
(0603), 25%; 4A
4
5/8IN Round-Thru Hole Spacer;
No Thread; M3.5; Nylon
R1, R3-R12,
R45, R58-R63,
R70-R75
24
47 Resistor SMT (0402),
5%, 0.1W
R2, R43, R44
3
100kΩ Resistor (0603), 5%; 0.1W
R19-R22
4
75Ω Resistor (0603), 0.1%, 0.10W
R23-R26
4
121Ω Resistor (0603), 0.1%, 0.10W
R27-R41,
R47-R49
18
0Ω Resistor; 0402, 0%, 0.10W
R42, R54, R55
3
49.9Ω Resistor (0603), 1%, 0.10W
R46
1
10kΩ Resistor, 10%, 0.5W
PCB
1
PCB: MAX19517
R56, R57, R65
3
100Ω Resistor (0603), 1%, 0.10W
J2-J4
0
Not Installed, 2 Pin Header
R64
1
0Ω Resistor (0603), 5%, 0.10W
R66-R68,
R83-R85
0
Not Installed, (0603) Resistor
6
10kΩ Resistor (0603), 5%, 0.10W
R13-R18, R50,
R52, R53
C32-C35
0
R69
1
2.2kΩ Resistor (0603),
2.2kΩ, 5%, 0.10W
Not Installed, (0402)
Non-Polar Capacitor
R76-R78
3
R51
0
Not Installed, (0402) Resistor
75Ω Resistor (0603), 1%, 0.10W
MH1-MH4
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Maxim Integrated │ 2
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
EV Kit-Specific Component List
PART
DESIGNATION
DESCRIPTION
MAX19505EVKIT+
8-bit 65Msps dual ADC (48 TQFN)
Maxim MAX19505ETM+
MAX19506EVKIT+
8-bit 100Msps dual ADC (48 TQFN)
Maxim MAX19506ETM+
MAX19507EVKIT+
8-bit 130Msps dual ADC (48 TQFN)
Maxim MAX19507ETM+
U1
MAX19515EVKIT+
10-bit 65Msps dual ADC (48 TQFN)
Maxim MAX19515ETM+
MAX19516EVKIT+
10-bit 100Msps dual ADC (48 TQFN)
Maxim MAX19516ETM+
MAX19517EVKIT+
10-bit 130Msps dual ADC (48 TQFN)
Maxim MAX19517ETM+
Component Suppliers
SUPPLIER
PHONE
WEBSITE
Central Semiconductor Corp.
631-435-1110
www.centralsemi.com
Coilcraft, Inc.
847-639-6400
www.coilcraft.com
Diodes, Inc.
805-446-4800
www.diodes.com
Fairchild Semiconductor
888-522-5372
www.fairchildsemi.com
Future Technology Devices International Ltd.
—
www.ftdichip.com
IRC, Inc.
361-992-7900
www.irctt.com
Mini-Circuits
718-934-4500
www.minicircuits.com
Murata Electronics North America, Inc.
770-436-1300
www.murata-northamerica.com
Panasonic Corp.
800-344-2112
www.panasonic.com
Link Instruments
973-808-8990
www.linkinstruments.com
Susumu International USA
208-328-0307
www.susumu-usa.com
Taiyo Yuden
800-348-2496
www.t-yuden.com
TDK Corp.
847-803-6100
www.component.tdk.com
Texas Instruments Inc.
972-644-5580
www.ti.com
Note: Indicate that you are using the MAX19505, MAX19506, MAX19507, MAX19515, MAX19516, or MAX19517 when contacting
these component suppliers.
www.maximintegrated.com
Maxim Integrated │ 3
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/
MAX19515–MAX19517 EV Kit Files
FILE
DESCRIPTION
MAX195xxDualADCEVKit
SoftwareInstaller.exe
Installs the EV kit files on
your computer
MAX195xxGUI.exe
Application program
ftd2xx.dll
Supporting Library
MaximStyle.dll
Supporting Library
libMPSSE.dll
Supporting Library
FTD2XX_NET.dll
Supporting Library
unins000.exe
Uninstalls the EV kit software
Quick Start
Recommended Equipment
●● Single nominal 3.6V, 1A DC power supply
●● Signal generator with low phase noise and low jitter
for clock input (e.g., HP 8644B)
●● Signal generator for analog signal input
(e.g., HP 8644B)
●● Logic analyzer (recommended, IO3232A)
●● Analog bandpass filters (e.g., K&L Microwave) for
input and clock signal
●● User-supplied Windows 7/10 PC with two spare USB
ports
Note: In the following sections, software-related items are
identified by bolding. Text in bold refers to items from the
EV kit software. Text in bold and underlined refers to
items from the Windows operating system.
Procedure
The MAX19505–MAX19507/MAX19515–MAX19517
EV kits are fully assembled and tested surface-mount
boards. Follow the steps below to verify board operation.
Caution: Do not turn on power supplies or enable
signal generators until all connections are completed.
1) Verify that shunts are installed across pins 1-3 of
jumpers JU1, JU2, and JU3 (SPI connected).
2) Verify that no shunts are installed across jumpers JU6
(device enabled) and JU7 (SPI enabled).
3) Verify that shunts are installed across jumpers JU9
(AVDD connected) and JU10 (OVDD connected).
4) Verify that shunt is installed across jumper J1, and no
jumper is installed across J8 (AVDD = 1.8V).
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5) Verify that shunt is installed across jumper J8, and no
jumper is installed across J10 (OVDD = 1.8V).
6) Connect the clock generator output to the clock bandpass filter input.
7) Connect the output of the clock bandpass filter to the
CLK SMA connector.
8) Connect the output of the analog signal generator to
the input of the signal bandpass filter. Keep the cable
connection between the signal generators, filters, and
EV kit board as short as possible for optimum dynamic performance.
9) Connect the output of the signal bandpass filter to the
VINA SMA connector. Note: It is recommended that a
3dB or 6dB attenuation pad be used to reduce reflections and distortion from the bandpass filter.
10) If using IO3200, apply power to the IO3232A by
connecting the USB cable from the computer’s typeA USB port to the IO3232A module’s mini-USB port.
11) Connect the MAX195xx J5 header pins to the logic
analyzer (See Connecting the IO3232A to the EV Kit
below, if applicable).
12) Connect the power supply to VSUPPLY. Connect the
ground terminal of this supply to the corresponding
GND pad.
13) Connect the USB cable from the computer’s type-A
USB port to the EV kit board’s Mini USB port.
14) Visit www.maximintegrated.com and search for
the device EV Kit to download the latest version of
the MAX195xx EV kit software and install it on your
computer by running the INSTALL.EXE program. The
program files are copied and icons are created in the
Windows Start menu.
15) Start the MAX195xx program by opening its icon in
the Start menu.
16) Turn on the 5V power supply.
17) Enable the signal generators.
18) Set the clock signal generator for an output amplitude
of 2VP-P or higher (recommended +16dBm to +19dBm
for optimum AC performance for input frequencies >
100MHz) and the frequency (fCLK) as appropriate.
19) Set the analog input signal generators for an output
amplitude of less than or equal to 2VP-P and to the
desired frequency.
20) Verify that the two signal generators are phase locked
to each other. Adjust the output power level of the
signal generators to overcome cable, bandpass filter,
and attenuation pad losses at the input.
21) Collect data using the logic analyzer.
Maxim Integrated │ 4
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Detailed Description of Software
Updating Registers
To send the new register values to the device through the
SPI interface, click the Update Registers button after the
settings are changed.
Application Menu
This menu contains 3 options, File, Device and Help.
These options allow the user to Exit the program, choose
their MAX195xx device, and view the splash screen,
respectively. The user should select a device upon startup,
as this will adjust the Output Timing Controls to the
device’s default settings.
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
User-Interface Panel
The program’s main window contains two tabs, Input/
Output/Clock (Figure 1) and Power Management (Figure
2), that provide controls for the MAX195xx softwareconfigurable features. The Input/Output/Clock tab
provides controls for Output Format, Input Common
Mode, Output CMOS Termination, Output Timing
Control, and Clock Controls. The Power Management
tab provides controls for Power Management and Output
Driver Power Mgmt. Controls. Changes to the controls
result in a write operation that updates the appropriate
registers of the ADC. A status bar is also provided at the
bottom of the program’s main window and is used to verify
command module and device connectivity. For reference,
a list of registers and their content is provided in a column
on the right side of the program’s main window.
Figure 1. MAX195xx EV Kit Software (Input/Output/Clock Tab)
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Maxim Integrated │ 5
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
Figure 2. MAX195xx EV Kit Software (Power Management Tab)
Input/Output/Clock Tab
Output Format
The Output Format group box contains several functions
that format the output data. The option to select between
single or dual data channels or set the multiplexer
between channels A or B is available through proper
selection of the radio buttons in the Data Channel Mode
and Mux Ch. Select group boxes. The CHA Reverse
and CHB Reverse checkboxes in the Reverse Bit Order
group box allow the user to reverse the bit order of
channels A and B, respectively.
The Format drop-down list in the Data group box configures the output data to two’s complement, offset binary,
or gray code. The Test Data drop-down list in the Data
Test Pattern group box gives the user the option to
choose between normal and test data modes. When Test
Data mode is selected, the Test Pattern drop-down list
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becomes active. The Test Pattern drop-down list allows
the user to choose between ramping or alternating test
pattern data.
Input Common Mode
The CHA Adjust and CHB Adjust drop-down lists
set the input common-mode voltage according to the
value selected. The CHA Self-Bias and CHB Self-Bias
checkboxes apply common-mode voltages to input pins
when checked, and disable common-mode inputs when
unchecked.
Output CMOS Termination
The Output CMOS Termination group box contains
independent controls to set the CMOS back termination
of CHA Data and CHB Data and CHA DCLK and CHB
DCLK. The CHA Data and CHB Data drop-down lists
set the data termination, while the CHA DCLK and CHB
DCLK drop-down lists sets the DCLK termination.
Maxim Integrated │ 6
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Output Timing Control
The Output Timing Control group box contains controls
to make adjustments to data and DCLK timing. The Data
Timing Adjust drop-down list adjusts DATA timing by the
selected value. The DCLK Timing Adjust drop-down list
adjusts DCLK timing by the selected value. By checking the Delay DATA/DCLK by T/2 checkbox, DATA and
DCLK outputs are delayed by a factor of T/2. The Data
Aligner Bypass checkbox bypasses the data aligner
delay line when checked. For more details on output
timing control, refer to the respective IC data sheet.
Clock Controls
The Clock Controls group box contains controls for
manipulating the clock. The Divider drop-down list sets
the clock divider. The Sync Mode drop-down list sets
clock synchronization to either slip or edge mode. In slip
mode, the divided output is forced to skip a state transition
on the third rising edge of the input clock (CLK) after the
rising edge of SYNC. In edge mode, the divided output
is forced to state 0 on the third rising edge of CLK. The
100 Ohm Input Term. checkbox switches 100Ω across
differential clock inputs when checked. For more details
on clock synchronization and control, refer to the respective
IC data sheet.
Power Management Tab
Power Management Controls
The Power Management group box contains two sets of
controls. The first set is used only when the SHDN pin on
the EV kit is set low; the second set is used only when
the SHDN pin on the EV kit is set high. When checked,
the CHA Active and CHB Active checkboxes activate
channel A and channel B, respectively, and power down/
standby channel A and channel B when unchecked. The
Standby checkbox toggles between standby mode when
checked and full power-down mode when unchecked,
as long as CHA Active or CHB Active checkboxes are
unchecked. The A+B Adder mode checkbox toggles
between A+B adder mode when checked and normal
dual mode when unchecked. For more details on power
management, refer to the respective IC data sheet.
Output Driver Power Management Controls
The Output Driver Power Mgmt. Controls group box
contains controls to disable the digital clock (DCLK) and
out-of-range indicator (DOR). The Disable DCLK checkbox disables the DCLK when checked and the Disable
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Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
DOR checkbox disables DOR. Note: Disable DCLK and
disable DOR applies to CMOS modes only. The Power
Down Output State drop-down list sets the digital output
high, low, or to tri-state during power-down. For more
details on output driver power management control, refer
to the respective IC data sheet.
User Log
The User Log is in each tab. The User Log keeps track
of all settings when the Update Registers button is
pressed. When the user switches tabs, the contents are
updated between both tabs. The User Log can also be
used to take notes, and hitting the Copy Log button will
copy the log to the clipboard.
Detailed Description of Hardware
The MAX19505–MAX19507/MAX19515–MAX19517
evaluation kits (EV kits) are fully assembled and tested
circuit boards that contain all the components necessary
to evaluate the performance of this family of 8-bit and
10-bit analog-to-digital converters (ADCs).
The ADCs accept differential input signals; however,
on-board transformers (T1–T4) convert a readily available single-ended source output to the required differential
signal. The input signals of the ADCs can be measured
using a differential oscilloscope probe at headers J2 and J3.
Output drivers (U11 and U12) buffer the output signals of
the data converter. The digital outputs of each EV kit are
accessible at header J5.
Each EV kit is designed as a four-layer PCB to optimize
the performance of this family of ADCs. Separate analog,
digital, clock, and buffer power planes minimize noise
coupling between analog and digital signals. The 100Ω
differential microstrip transmission lines are used for
analog and clock inputs. The 50Ω microstrip transmission
lines are used for all digital outputs. The trace lengths of
the 100Ω differential input lines are matched to within a
few thousandths of an inch to minimize layout-dependent
input-signal skew.
Using the IO3232A with the EV Kit
The Logic Analyzer Pattern Generator (IO3200) is one
of the many instrument options to evaluate the performance of this specific family of evaluation kits. While it is
simple enough to use, this method does require the user
to download the IO3200 software from the following link:
www.linkinstruments.com
Maxim Integrated │ 7
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Connecting the IO3232A to the EV Kit
The IO3232A can be connected to the MAX195xx boards
using the following pin ordering. It is not essential to
match the pins exactly as specified below, as they are a
recommended connection sequence.
Configuring the EV Kits for
Single-Ended Clock Operation
To configure the MAX195xx EV kits for single-ended clock
operation, the following modifications must be made to
the clock circuit:
1) Remove 0Ω resistors at locations R47, R48, and R49.
Power Supplies
The MAX195xx EV kits operate from a single DC power
supply (VSUPPLY) and provide on-board regulation
to power the analog, digital, and clock-shaping circuit
blocks. The nominal voltage input for the VSUPPLY is at
3.6V. The maximum voltage supported by the MAX195xx
EV kits is 5V, and the minimum voltages are represented
in Table 1 and Table 2 based on the user’s desired regulated voltage. The analog and clock (AVDD) are regulated
to a desired voltage (1.8V, 2.5V, 3.0V, or 3.3V) through the
MAX8902A (U14), a pin-selectable linear regulator. The
digital output and logic circuitry (OVDD and VLOGIC) are
both regulated to a desired voltage (1.8V, 2.5V, 3.0V, or
3.3V) through the MAX8902A (U15). J1, J8, J9, and J10
are provided to select the desired output of U14 and U15.
See Table 2 and Table 3 for AVDD and OVDD/VLOGIC
supply options. Jumpers JU9 and JU10 are provided to
either disconnect or measure current through AVDD and
OVDD, respectively.
2) Install 0Ω resistors at locations R51 and R52.
3) Install a 49.9Ω ±1% resistor at location R50.
In single-ended clock configuration, potentiometer R46
can be utilized to control the duty cycle of the clock input
signal. Measure the clock input at J4 and adjust R46 until
the desired duty cycle is achieved.
Input Signal
Although this family of ADCs accepts differential analog
input signals, the EV kits only require single-ended analog
input signals. Insertion losses due to a series-connected
filter and the interconnecting cables decrease the amount
of power seen at the EV kit input. Account for these losses
when setting the signal generator amplitude. On-board
transformers (T1–T4) convert the single-ended analog input
signals and generate the recommended differential analog
signals at the ADCs’ differential input pins. The input circuit
supports input frequencies from 1MHz to 400MHz.
Clock Input
The data converter allows for either differential or singleended signals to drive the clock inputs. The MAX195xx
EV kits support both methods.
In single-ended operation, the clock signal is applied to
the ADC through a buffer (U10). In differential mode, an
on-board transformer converts a user-supplied singleended analog input and generates a differential analog
signal, which is then applied to the ADC’s input pins.
Table 1. J5 Header and IO3232A Pin
Relationships
J5 HEADER FROM EV KIT
DCLKA
IO3232A PINS
Ext. clk0 (interchangeable
with DCLKB)
Table 2. MAX8902A Output Voltage for
AVDD (J1 and J9)
J1
J9
AVDD
VSUPPLY MIN
OPEN
INSTALL
1.8V*
2.1V
OPEN
OPEN
2.5V
2.8V
INSTALL
INSTALL
3.0V
3.3V
INSTALL
OPEN
3.3V
3.6V
*Default
Table 3. MAX8902A Output Voltage for
OVDD and VLOGIC (J8 and J10)
J8
J10
OVDD/VLOGIC
VSUPPLY
MIN
DORA
PIN 10
D9A:D0A
PINS 9:0, respectively
OPEN
INSTALL
1.8V*
2.1V
D9B:D0B
PINS 25:16, respectively
OPEN
OPEN
2.5V
2.8V
DORB
PIN 26
INSTALL
INSTALL
3.0V
3.3V
DCLKB
Ext. clk0 (interchangeable
with DCLKA)
INSTALL
OPEN
3.3V
3.6V
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*Default
Maxim Integrated │ 8
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Output Signal
The MAX19505, MAX19506, and MAX19507 feature
two 8-bit, parallel, CMOS-compatible digital outputs that
transmit the converted analog input signals. The higher
resolution MAX19515, MAX19516, and MAX19517 feature two 10-bit, parallel, CMOS-compatible digital outputs
that transmit the converted analog input signals. Each set
of 8-bit or 10-bit digital outputs also includes a clock bit
(DCLKA/B) and overrange bit (DORA/B) to accommodate
data synchronization and error detection. See the Output
Bit Locations section for more details on how to configure
these 8-bit and 10-bit converter outputs.
Output Bit Locations
Two drivers (U11 and U12) buffer the digital outputs
of the individual ADCs. These drivers are able to drive
large capacitive loads, which may be present at the
logic analyzer connection. The outputs of the buffers are
connected to J5.
Serial Port Enable (SPEN)
The SPEN pin selects the means of programming
the internal registers of the MAX19505–MAX19507/
MAX19515–MAX19517 ADCs. SPEN is set high or low
based on the settings of jumper JU7, shown in Table 4.
When a shunt on JU7 is installed, the 3-wire serial port is
disabled and the part can be programmed through jumpers
JU1, JU2, and JU3 in parallel mode. When JU7 is left
open, SPEN is pulled to GND through R44. Refer to the
Table 4. Jumper JU7 Functions
respective IC data sheet for more information on SPEN
and parallel programming. Note that when the serial port
is enabled, jumpers JU1, JU2, and JU3 must be set to
pins 1-3 for proper operation.
Shutdown (SHDN)
The MAX19505–MAX19507/MAX19515–MAX19517
ADCs can also be placed in a low-power shutdown
mode through jumper JU6. This pin has different effects
depending on the state of SPEN. When in SPI programming mode, SHDN can select between two powermanagement states. When in parallel programming mode,
SHDN can enable/disable the IC.
When SPI programming is enabled (SPEN = 0), the SHDN
pin is a toggle switch between two power-management
states, shown in Figure 2 under the Power Management
group box of the software interface. When a shunt is
installed on JU6, SHDN is connected to AVDD and the
user can select the appropriate settings for CHA Active,
CHB Active, Standby, and A+B Adder mode under the
label **Use when SHDN = 1 (IC pin 7)**. When no shunt
is installed on JU6, SHDN is connected to GND through
R43 and the user can select the appropriate settings for
CHA Active, CHB Active, Standby, and A+B Adder
mode under the label **Use when SHDN = 0 (IC pin 7)**.
When parallel programming mode is enabled (SPEN = 1),
the SHDN pin enables/disables the IC according to the
settings in Table 5.
SHUNT POSITION
SPEN PIN
Installed
Connected to AVDD
Not installed*
Connected to GND though a 100kΩ pulldown resistor
3-WIRE SERIAL PORT
Disabled (parallel programming mode)
Enabled (SPI programming)
*Default position.
Table 5. Jumper JU6 Functions (SPEN = AVDD)
SHUNT POSITION
SHDN PIN
Installed
Connected to AVDD
Not installed*
Connected to GND through a 100kΩ pulldown resistor
POWER STATE
(SPEN = AVDD)
Complete power-down
CHA + CHB active
*Default position.
www.maximintegrated.com
Maxim Integrated │ 9
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Parallel Programming
Limited feature selection is available as an alternative to
full programmability through the serial port. If the serial
port is disabled by setting the SPEN pin high, the serial
port pins (CS, SCLK, SDIN) become feature selection
pins (OUTSEL, DIV, FORMAT) that require an analog
control network.
Jumpers JU1, JU2, JU3, and JU7 control the
feature selection when the serial port is disabled (parallel
programming is enabled). See Table 6 for functionality.
Table 6. Parallel Programming Feature Selection
SCLK/DIV
(JU1)
SDIN/FORMAT
(JU2)
CS/OUTSEL
(JU3)
SPEN
(JU7)
SCLK
SDIN
CS
0
Serial port active. Features are programmed
through the serial port.
X
0
X
1
Two’s complement
X
VDD
X
1
Offset binary
X
(Unconnected pin)
X
1
Gray code
0
X
X
1
Clock divide-by-1
VDD
X
X
1
Clock divide-by-2
(Unconnected pin)
X
X
1
Clock divide-by-4
X
X
0
1
CMOS (dual bus)
X
X
VDD
1
MUX CMOS (channel A data bus)
X
X
(Unconnected pin)
1
MUX CMOS (channel B data bus)
DESCRIPTION
X = Don’t care.
www.maximintegrated.com
Maxim Integrated │ 10
1
1
VINB
142-0701-201
2
4
3
5
2
4
3
5
OPEN
R16
C26
0.1UF
OPEN
R13
3
1
3
1
S
S
OPEN
R18
ADT1-1WT+
T3
P
R17
OPEN
OPEN
R15
ADT1-1WT+
T1
P
6
2
4
6
2
4
R22
75
R21
75
R20
75
R19
75
0
R41
0
R40
3
1
3
1
S
S
ADT1-1WT+
T4
P
ADT1-1WT+
T2
P
6
2
4
6
2
4
R25
121
R26
121
R24
121
R23
121
0
R31
0
R27
C31
100PF
TP2
C30
100PF
TP1
0
R34
0
R32
0
R33
0
R30
0
R28
0
R29
VCMB J3
VCMA J2
R38
0
OPEN
C35
R37
0
OPEN
C34
R36
0
OPEN
C33
R35
0
OPEN
C32
2
AVDD
2
AVDD
JU7
JU6
1
SYNC
142-0701-201
R44
100K
1
R43
100K
1
GND
REFIO
0
R39
R42
49.9
C29
0.1UF
CLKN
CLKP
INB-
VCMB
INB+
INA-
VCMA
INA+
5
7
SPEN
SHDN
REFIO
CLK-
6
CLK+
16
SYNC
15
14
INB-
CMB
11
10
INB+
9
INA-
CMA
2
4
INA+
3
1
AVDD
12
AVDD
U1
MAX19507ETM+
46
45
44
43
42
41
40
39
38
37
35
34
20
19
31
30
29
28
27
26
24
23
DCLKA
DORA
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
DCLKB
DORB
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
GND
17
47
GND
18
SCLK/DIV
EP
CS/OUTSEL
36
OVDD
I.C.
49
SDIN/FORMAT
25
OVDD
I.C.
8
13
AVDD
48
AVDD
OVDD
I.C.
21
AVDD
I.C.
22
R14
5
5
5
5
2
1
2
1
OPEN
2
4
3
5
C25
0.1UF
I.C.
32
www.maximintegrated.com
33
VINA
142-0701-201
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
DORB
DCLKB
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
DORA
DCLKA
SDIN
SCLK
CSB
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505/MAX19506/MAX19507 EV Kit Schematics (Sheet 1 of 5)
Maxim Integrated │ 11
1
VINB
142-0701-201
1
OPEN
R16
C26
0.1UF
OPEN
R13
C25
0.1UF
3
1
3
1
S
S
OPEN
R18
ADT1-1WT+
T3
P
R17
OPEN
OPEN
R15
ADT1-1WT+
T1
P
6
2
4
6
2
4
R22
75
R21
75
R20
75
R19
75
0
R41
0
R40
3
1
3
1
S
S
ADT1-1WT+
T4
P
ADT1-1WT+
T2
P
6
2
4
6
2
4
R25
121
R26
121
R24
121
R23
121
0
R31
0
R27
C31
100PF
TP2
C30
100PF
TP1
0
R34
0
R32
0
R33
0
R30
0
R28
0
R29
VCMB J3
VCMA J2
R38
0
OPEN
C35
R37
0
OPEN
C34
R36
0
OPEN
C33
R35
0
OPEN
C32
2
AVDD
2
AVDD
JU7
JU6
1
SYNC
142-0701-201
R44
100K
1
R43
100K
1
GND
REFIO
0
R39
R42
49.9
C29
0.1UF
CLKN
CLKP
INB-
VCMB
INB+
INA-
VCMA
INA+
5
7
SPEN
SHDN
REFIO
CLK-
6
CLK+
16
SYNC
15
14
INB-
CMB
11
10
INB+
9
INA-
CMA
2
4
INA+
3
AVDD
U1
OVDD
MAX19517ETM+
12
R14
OPEN
48
AVDD
VINA
142-0701-201
2
4
3
5
2
4
3
5
5
5
5
5
13
AVDD
47
46
45
44
43
42
41
40
39
38
37
35
34
33
32
20
19
31
30
29
28
27
26
24
23
22
21
CS/OUTSEL
SCLK/DIV
SDIN/FORMAT
DCLKA
DORA
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
DCLKB
DORB
D9B
D8B
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
GND
17
2
1
1
AVDD
AVDD
GND
18
2
1
36
OVDD
EP
49
2
4
3
5
25
OVDD
I.C.
www.maximintegrated.com
8
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
DORB
DCLKB
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
DORA
DCLKA
SDIN
SCLK
CSB
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19515/MAX19516/MAX19517 EV Kit Schematics (Sheet 1 of 5)
Maxim Integrated │ 12
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505/MAX19506/MAX19507 EV Kit Schematics (Sheet 2 of 5)
VLOGIC
31
42
VCC
18
VCC
48
2OE
41
2A1
2Y1
8
40
2A2
2Y2
9
38
2A3
2Y3
11
R4
47
37
2A4
2Y4
12
R5
47
25
3OE
36
3A1
3Y1
13
R6
47
35
3A2
3Y2
14
R7
47
33
3A3
3Y3
16
R8
47
32
3A4
3Y4
17
R9
47
24
4OE
30
4A1
4Y1
19
R10
47
29
4A2
4Y2
20
R11
47
27
4A3
4Y3
22
R12
47
26
4A4
4Y4
23
R45
47
1
1
4
4
3
3
6
6
5
5
8
8
7
7
10
10
9
9
12
12
11
11
14
14
13
13
16
16
15
15
18
18
17
17
20
20
19
19
22
22
21
21
24
24
23
23
26
25
25
U12
26
28
27
27
SN74AUC16244DGGR
28
30
30
29
29
32
32
31
31
GND
2
www.maximintegrated.com
42
VCC
31
VCC
18
VCC
37
1A3
1Y3
5
40
40
39
39
1A4
1Y4
6
42
42
41
41
44
44
43
43
46
46
45
45
48
48
47
47
44
43
2OE
2Y1
8
R58
47
2Y2
9
R59
47
2A3
2Y3
11
2A4
2Y4
12
3A1
3Y1
13
R62
47
3A2
3Y2
14
R63
47
33
3A3
3Y3
16
R70
47
32
3A4
3Y4
17
R71
47
24
4OE
30
4A1
4Y1
19
R72
47
29
4A2
4Y2
20
R73
47
27
4A3
4Y3
22
R74
47
4A4
4Y4
23
R75
47
35
26
GND
3OE
36
45
25
GND
37
39
38
GND
2A2
34
2A1
40
GND
41
28
D7B
37
GND
D6B
38
GND
D5B
35
38
21
D4B
35
3
GND
D3B
36
1Y2
1A2
GND
D2B
33
1Y1
1A1
46
4
D1B
33
15
D0B
34
36
10
DCLKB
34
2
1OE
47
48
DORB
VCC
7
VLOGIC
1
J5
PBC24DAAN
2
45
39
4
GND
6
GND
1Y4
GND
DCLKA
5
1A4
34
DORA
1Y3
GND
D7A
1A3
43
28
D6A
3
44
GND
D5A
2
1Y2
GND
D4A
1Y1
1A2
GND
D3A
1A1
46
21
D2A
1OE
15
D1A
SN74AUC16244DGGR
47
10
D0A
VCC
1
VCC
7
U11
Maxim Integrated │ 13
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19515/MAX19516/MAX19517 EV Kit Schematics (Sheet 2 of 5)
VLOGIC
31
42
VCC
18
VCC
2A1
2Y1
8
R1
47
40
2A2
2Y2
9
R3
47
38
2A3
2Y3
11
R4
47
37
2A4
2Y4
12
R5
47
25
3OE
36
3A1
3Y1
13
R6
47
35
3A2
3Y2
14
R7
47
33
3A3
3Y3
16
R8
47
32
3A4
3Y4
17
R9
47
24
4OE
30
4A1
4Y1
19
R10
47
29
4A2
4Y2
20
R11
47
27
4A3
4Y3
22
R12
47
26
4A4
4Y4
23
R45
47
1
1
4
4
3
3
6
6
5
5
8
8
7
7
10
10
9
9
12
12
11
11
14
14
13
13
16
16
15
15
18
18
17
17
20
20
19
19
22
22
21
21
24
24
23
23
26
25
25
U12
26
28
27
27
SN74AUC16244DGGR
28
30
30
29
29
32
32
31
31
GND
2
www.maximintegrated.com
42
VCC
31
VCC
18
VCC
5
40
40
39
39
1A4
1Y4
6
42
42
41
41
44
44
43
43
46
46
45
45
48
48
47
47
43
2OE
2Y1
8
R58
47
2Y2
9
R59
47
2A3
2Y3
11
R60
47
2A4
2Y4
12
R61
47
3A1
3Y1
13
R62
47
3A2
3Y2
14
R63
47
33
3A3
3Y3
16
R70
47
32
3A4
3Y4
17
R71
47
24
4OE
30
4A1
4Y1
19
R72
47
29
4A2
4Y2
20
R73
47
27
4A3
4Y3
22
R74
47
4A4
4Y4
23
R75
47
25
3OE
36
35
26
GND
37
45
38
GND
2A2
39
2A1
40
GND
41
34
D9B
1Y3
GND
D8B
37
1A3
44
28
D7B
37
GND
D6B
38
GND
D5B
35
38
21
D4B
35
3
GND
D3B
36
1Y2
1A2
GND
D2B
33
1Y1
1A1
46
4
D1B
33
15
D0B
34
36
10
DCLKB
34
2
1OE
47
48
DORB
VCC
7
VLOGIC
1
J5
PBC24DAAN
2
45
4
GND
2OE
41
GND
DCLKA
48
39
DORA
6
GND
D9A
1Y4
34
D8A
5
1A4
GND
D7A
1Y3
28
D6A
1A3
43
GND
D5A
3
44
GND
D4A
2
1Y2
GND
D3A
1Y1
1A2
21
D2A
1A1
46
15
D1A
1OE
47
10
D0A
VCC
1
VCC
7
U11
SN74AUC16244DGGR
Maxim Integrated │ 14
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
R53
OPEN
CLKP
CLKN
MAX19505–MAX19507/MAX19515–MAX19517 EV Kit Schematics (Sheet 3 of 5)
2
0
R49
D2
BAS70-04
Y2
R54
49.9
R55
49.9
C55
0.01UF
C54
0.01UF
1
A2
3
6
4
4
3
1
0
R47
R50
OPEN
1
CLK
142-0701-201
C53
0.1UF
R57
100
3
1
R46
10K
1
R56
100
R51
OPEN
2
4
3
5
3
AVDD
2
2
1
3
T5
R2
100K
PWB-2-BL
6
5
1
5
5
6
GND
A1
Y1
C52
0.1UF
U10
VCC
2
AVDD
3
U10
4
2
0
R48
OPEN
R52
J4
1
www.maximintegrated.com
Maxim Integrated │ 15
SCLK
CSB
SDIN
DNI
R64
0
9
8
7
6
9
8
7
6
1
2
3
4
5
R65
100
VSUPPLY
1
2
3
4
5
J6
897-43-005-00-100001
DS1
LTST-C190GKT
K
A
AVDD
C3
1UF
1
3
5
7
9
USB3V3
CLK
DI
2
3
R67
10K
J7
PEC05DAAN
2
4
6
8
10
NC
VCC
NC
USB3V3
VSS
CS
1
R66
10K
4
R69
2.2K
R68
10K
C2
10UF
SPI_SCLK
1
1
USB3V3
U9
93LC56BT-I/SN
DO
2
GND
SHDN
N.C.
5
OUT
IN
U2
USB3V3
MAX8511EXK33+
USB3V3
3
4
1
USB POWER
5
8
6
2
1
3 3
GND
USB3V3
L2
28
L1
28
SCLK
R82
12K
TEST
OSCO
OSCI
EECS
EECLK
EEDATA
SPI_SDIN
13
3
2
63
62
61
RESET#
REF
6
14
USB1V8
C82
0.1UF
USB1V8
1
1
3 3
AVDD
JU1
3
2
C5
8PF
4
1
1K
R81
DM
DP
VREGOUT
49
7
8
VREGIN
C81
0.1UF
50
C79
0.1UF
USB1V8
C80
3.3UF
C40
4.7UF
+
AVDD
C4
8PF
4
3
2
1
Y1
12MHZ
B3S-1000P
NO
USB3V3
C1
4.7UF
+
S1
2
1
COM
2
2
1
JU2
1
C84
0.1UF
26
27
28
29
30
32
33
34
38
39
40
41
43
44
45
46
48
52
53
54
55
57
58
59
60
36
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7
DDBUS0
DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7
PWREN#
SUSPEND#
SDIN
16
17
18
19
21
22
23
24
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
U3
FT4232HL
C83
0.1UF
USB3V3
FTDI USB INTERFACE
4
9
VPHY
VPLL
4 4
2 2
7
12
37
64
VCCCORE
VCCCORE
VCCCORE
AGND
CSBA_USB
SCLK_USB
MOSI_USB
C86
0.1UF
SPI_CSB
MOSI_USB
CSBA_USB
SCLK_USB
C85
0.1UF
USB3V3
USB3V3
C87
0.1UF
3 3
AVDD
10K
R83
20
31
42
56
10
10K
R84
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
GND
GND
GND
1
5
11
15
25
35
47
51
4 4
2 2
10K
R85
4 4
2 2
1
1
JU3
C88
0.1UF
CSB
USB3V3
DIR2
DIR3
DIR4
A1
A2
A3
A4
2
7
8
3
4
5
6
DIR1
1
14
13
12
11
B2
B3
B4
C89
0.1UF
B1
AVDD
U4
SN74AVC4T774PW
VCCB
15
GND
VCCA
OE
9
C43
0.1UF
USB3V3
16
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10
SPI_SCLK
SPI_SDIN
SPI_CSB
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OPEN
INSTALL
GND
VSUPPLY
INSTALL
INSTALL
GND
VSUPPLY
VSUPPLY
OPEN
OPEN
EN
SELA
3
4
C48
0.1UF
EP
IN
1
7
6
5
BYP
OUTS
SELB
GND
8
OUT
U14
MAX8902AATA+
3.6V
3.3V
2.8V
2.1V
C49
0.1UF
DS2
LTST-C190GKT
K
A
J1
VSUPPLY
C28
10UF
AVDD
3.3V
3.0V
2.5V
1.8V
C6
0.1UF
75
R76
C7
0.1UF
AVDD
1
2
INSTALL
9
OPEN
2
1
2
J9
C50
0.1UF
OVDD
C51
0.1UF
DS3
LTST-C190GKT
K
A
C75
0.01UF
JU9
75
R77
C76
10UF
C66
0.1UF
VLOGIC
AVDD
2
1
VSUPPLY MIN
C67
0.1UF
OVDD
C27
10UF
J8
VSUPPLY
EN
SELA
3
4
EP
IN
1
7
6
5
BYP
OUTS
SELB
GND
8
OUT
U15
MAX8902AATA+
C68
0.1UF
C69
0.1UF
DS4
LTST-C190GKT
K
A
C70
0.1UF
75
R78
1
2
AVDD/OVDD+VLOGIC
9
J9/J10
2
1
2
C71
0.1UF
VLOGIC
J10
VLOGIC
C72
0.1UF
C78
0.01UF
JU10
C73
0.1UF
C77
10UF
OVDD
2
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1
J1/J8
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1.0’’
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MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Top Layer
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MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Internal 2
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MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Internal 3
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MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Bottom Silkscreen
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MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Top Silkscreen
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MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Top Layer
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MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Internal 2
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MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Internal 3
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MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Bottom Layer
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MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Bottom Silkscreen
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Maxim Integrated │ 29
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Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
11/08
Initial release
1
7/09
Corrected connector name on DCEP board
5, 10
2
7/19
Updated to match Rev C and Rev D hardware, plus updated GUI
1–30
DESCRIPTION
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc. │ 30
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