MAX1994ETM+

19-2569; Rev 0; 10/02 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers ♦ +2V to +28V Battery Input Range ♦ Differential Remote Sense (BUCK1) ♦ Linear-Regulator Controller ♦ 200/300/550/1000kHz Switching Frequency ♦ 2.2mA (typ) ICC Supply Current ♦ 20µA (max) Shutdown Supply Current ♦ Independent Power-Good Outputs (PGOOD, LINGOOD) Ordering Information PART MAX1816ETM MAX1994ETM TEMP RANGE -40°C to +100°C -40°C to +100°C Quick-PWM is a trademark of Maxim Integrated Products, Inc. PIN-PACKAGE 48 Thin QFN 48 Thin QFN BST2 V+ 38 37 39 DL2 DH2 LX2 40 41 42 43 44 DH1 PERF DL1 PGND VDD 46 45 BST1 LX1 47 TOP VIEW 48 Pin Configuration ILIM1 1 36 ILIM2 CC CS1+ CS1- 2 35 CS2 3 34 4 33 OUT2 FB2 FBS GDS 5 32 REF 6 31 VCC AGND LINBSE MAX1816 MAX1994 30 9 28 10 27 SUS 11 26 DPSLP 12 25 24 23 22 LINGOOD LINFB TIME OVPSET LIN/SDN PGOOD TON 21 20 29 SKP1/SDN SKP2/SDN 19 8 18 7 17 GAIN OFS0 OFS1 OFS2 D0 Small Notebook Computers ♦ Voltage-Positioning Gain and Offset Control 16 3- to 4-Cell Li+ Battery to CPU Core Supply ♦ +0.70V to +2.00V Output Adjust Range (MAX1994) 15 Memory I/O and VID Supplies ♦ +0.60V to +1.75V Output Adjust Range (MAX1816) 14 Mobile CPU Core and Video Processors ♦ 5-Bit On-Board D/A Converter 13 Applications ♦ ±1% VOUT Accuracy D1 D2 D3 D4 S0 S1 BUCK1, BUCK2, and the linear regulator feature overvoltage protection (OVP). The detection threshold for BUCK1 is adjusted with an external resistive voltage-divider, while the OVP thresholds for BUCK2 and the linear regulator are fixed. Connecting the OVPSET pin to VCC disables OVP for BUCK1 and BUCK2, but not the linear regulator. The MAX1816 features an output-voltage adjustment range from 0.6V to 1.75V. Similarly, the MAX1994 is adjustable from 0.925V to 2.0V, using an alternate VID code set. While in suspend mode, the adjustment range is 0.7V to 1.075V for both the MAX1816 and MAX1994. Both parts are available in 48-pin thin QFN packages. Features ♦ Dual Quick-PWM Architecture THIN QFN 7mm × 7mm ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1816/MAX1994 General Description The MAX1816/MAX1994 are dual step-down controllers for notebook computer applications. BUCK1 is a CPU core regulator with dynamically adjustable output, ultrafast transient response, high DC accuracy, and high efficiency. BUCK2 is an adjustable step-down regulator for I/O and memory supplies. Both regulators employ Maxim’s proprietary Quick-PWM™ control architecture. This fastresponse, constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant” on-response to load transients, while maintaining a relatively constant switching frequency. The MAX1816/MAX1994 also have a linear-regulator controller for low-voltage auxiliary power supplies. The CPU regulator supports “active voltage positioning” to reduce output bulk capacitance and lower power dissipation. A programmable gain amplifier allows the use of lower value sense resistors. Four fixed-gain settings are available (0, 1.5, 2, and 4). A differential remotesense amplifier is also included to more accurately control the voltage at the load. Accuracy is further enhanced with an internal integrator. The MAX1816/MAX1994 include a specialized digital interface that makes them suitable for mobile CPU and video processor applications. The power-good (PGOOD) output for the core regulator is forced high during VID transitions, and the LINGOOD output for the linear regulator includes a 1ms (min) turn-on delay. MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers ABSOLUTE MAXIMUM RATINGS V+ to AGND............................................................-0.3V to +30V VCC, VDD to AGND...................................................-0.3V to +6V PGND, GDS to AGND .........................................................±0.3V SKP1/SDN, SKP2/SDN, LIN/SDN to AGND............-0.3V to +16V LINBSE, SUS, PERF, DPSLP, PGOOD, LINGOOD, CS1+, CS1-, FBS, D0–D4, OUT2 to AGND.....................................................-0.3V to +6V OFS0, OFS1, OFS2, ILIM1, ILIM2, FB2, REF, TON, TIME, OVPSET, S0, S1, GAIN, CC, LINFB to AGND ....................-0.3V to (VCC + 0.3V) DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V) DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) BST1 to LX1..............................................................-0.3V to +6V BST2 to LX2..............................................................-0.3V to +6V LX1, LX2, CS2 to AGND ............................................-2V to +30V REF Short Circuit to AGND.........................................Continuous LINBSE Short Circuit to +6V.......................................Continuous Continuous Power Dissipation (TA = +70°C) 48-Pin Thin QFN (derate 26.3mW/°C above +70°C) .2105mW Operating Temperature Range .........................-40°C to +100°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER Input Voltage Range CONDITIONS Battery voltage V+ TON = REF, open, or VCC TON = GND VCC, VDD BUCK1 DC Output Voltage Accuracy BUCK2 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 1) V+ = 4.5V to 28V, includes load regulation errors, OFS_ = GDS = AGND, CS1+ = CS1- = FBS V+ = 4.5V to 28V MIN UNITS 28 2 16 4.5 5.5 -1 +1 V % DAC codes from 0.700V to 2.000V (MAX1994) FB2 = GND 2.475 2.500 2.525 FB2 = VCC 1.782 1.800 1.818 FB2 = OUT2 0.990 1.000 1.010 1.0 FB2 GND Level Voltage level to enable internal feedback for BUCK2 with VOUT2 = 2.5V FB2 External Feedback Level Voltage level to enable external feedback for BUCK2 with FB2 regulated to 1.0V nominal 0.15 FB2 VCC Level Voltage level to enable internal feedback for BUCK2 with VOUT2 = 1.8V 2.10 GAIN = GND 2 MAX DAC codes from 0.600V to 1.750V (MAX1816) OUT2 Adjust Range Voltage-Positioning Gain TYP 2 V 5.5 V 0.05 V 1.90 V V 0 GAIN = REF 1.425 1.500 1.575 GAIN = open 1.900 2.000 2.100 GAIN = VCC 3.800 4.000 4.200 _______________________________________________________________________________________ V/V Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers (Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Current-Sense Differential Input Range (CS1+, CS1-) 200 mV Remote-Sense Differential Input Range (CS1+, FBS) 300 mV Remote-Sense Differential Input Range (GDS, AGND) 200 mV µA CS1+, FBS Input Bias Current -300mV < VCS1+ - VFBS < +300mV -60 +60 CS1- Input Bias Current -100mV < VCS1+ - VCS1- < +100mV, VCS1- = VFBS -60 +60 µA GDS Input Bias Current -3 +3 µA FB2 Input Bias Current -0.2 +0.2 OUT2 Input Resistance 70 TIME Frequency Accuracy BUCK1 On-Time (Note 2) 252kHz nominal, RTIME = 143kΩ -8 +8 53kHz nominal to 530kHz nominal, RTIME = 680kΩ to 68kΩ -12 +12 V+ = 5V, CS1- = 1.2V TON = GND (1000kHz) 230 260 290 TON = REF (550kHz) 165 190 215 TON = open (300kHz) 320 355 390 TON = VCC (200kHz) 465 515 565 TON = GND (715kHz) 630 720 810 TON = REF (390kHz) 495 550 605 TON = open (390kHz) 495 550 605 TON = VCC (260kHz) 740 V+ = 12V, CS1- = 1.2V V+ = 5V, OUT2 = 2.5V BUCK2 On-Time (Note 2) V+ = 12V, OUT2 = 2.5V µA kΩ % ns ns 825 910 TON = open, TON = VCC (Note 2) 425 500 TON = GND, TON = REF (Note 2) 325 375 Quiescent Supply Current (VCC) Measured at VCC, with FBS, OUT2, FB2, and LINFB forced above the no-load regulation point 2200 3800 µA Partial Shutdown Supply Current (Linear Regulator On Only) VSKP1/SDN = 0V, VSKP2/SDN = 0V, VLIN/SDN = 5V; measured at VCC, with FBS and LINFB forced above the no-load regulation point 425 650 µA Partial Shutdown Supply Current (BUCK1 and Linear Regulator) VSKP1/SDN = 5V, VSKP2/SDN = 0V, VLIN/SDN = 5V; measured at VCC, with FBS and LINFB forced above the no-load regulation point 1825 3000 µA Partial Shutdown Supply Current (BUCK2 Only) VSKP1/SDN = 0V, VSKP2/SDN = 5V, VLIN/SDN = 0V; measured at VCC, with OUT2 and FB2 forced above the regulation point 600 1100 µA Quiescent Supply Current (VDD) Measured at VDD, with FBS, OUT2, and FB2 forced above the no-load regulation point Y DOWN OFS PERF CONTROL STATE DPSLP MACHINE X10.8V GND Switching HIGH BUCK1 no-fault test mode Monitor BUCK1 only Disabled >10.8V GND Switching LOW BUCK1 no-fault test mode Monitor BUCK1 only X >10.8V VCC Switching Switching No-fault test mode Monitor both X >10.8V Float Switching Switching in forced PWM mode No-fault test mode Monitor both Enabled Float GND Switching in forced PWM mode HIGH BUCK1 in forced PWM mode Monitor BUCK1 only Disabled Float GND Switching in forced PWM mode LOW BUCK1 in forced PWM mode Monitor BUCK1 only X Float VCC Switching in forced PWM mode Switching BUCK1 in forced PWM mode, BUCK2 in skip mode Monitor both X Float Float Switching in forced PWM mode Switching in forced PWM mode BUCK1 and BUCK2 in forced PWM Mode Monitor both X GND Float HIGH Switching in forced PWM mode BUCK1 off, BUCK in forced PWM mode LOW X VCC Float Switching Switching in forced PWM mode BUCK1 in skip mode, BUVK2 in forced PWM mode Monitor both Enabled VCC or float VCC or float HIGH HIGH OVP and UVP faults LOW Disabled VCC or float VCC or float HIGH HIGH UVP faults only LOW X = Don’t care. inputs S0 and S1, which are four-level digital inputs (Table 6). All code transitions (even those asking for the exact same code) activate the slew-rate controller. In other words, up-going or down-going transitions from one code to another, soft-start and soft-stop are all handled in the same way. BUCK1 Output-Voltage Offset Control (SUS, PERF, DPSLP, and OFS_) The MAX1816/MAX1994 support three independent offsets to the voltage-positioned load line. The offsets are adjusted using resistive voltage-dividers at the OFS0–OFS2 inputs (see Figure 10). For inputs from 0 to 0.8V, a negative offset is added to the output that is ______________________________________________________________________________________ 33 MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers Table 5. Output Voltage vs. DAC Codes D4 D3 D2 D1 D0 VOUT (V) MAX1816 VOUT (V) MAX1994 0 0 0 0 0 1.750 2.000 0 0 0 0 1 1.700 0 0 0 1 0 1.650 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Table 6. Output Voltage vs. Suspend Mode DAC Codes S1 S0 VOUT (V) MAX1816/MAX1994 1.950 GND GND 1.075 1.900 GND REF 1.050 1.600 1.850 GND OPEN 1.025 0 1.550 1.800 GND VCC 1.000 1 1.500 1.750 REF GND 0.975 1 0 1.450 1.700 REF REF 0.950 1 1 1 1.400 1.650 REF OPEN 0.925 0 0 0 1.350 1.600 REF VCC 0.900 1 0 0 1 1.300 1.550 OPEN GND 0.875 0 1 0 1 0 1.250 1.500 OPEN REF 0.850 0 1 0 1 1 1.200 1.450 OPEN OPEN 0.825 0 1 1 0 0 1.150 1.400 OPEN VCC 0.800 0 1 1 0 1 1.100 1.350 VCC GND 0.775 0 1 1 1 0 1.050 1.300 VCC REF 0.750 0 1 1 1 1 1.000 No CPU VCC OPEN 0.725 1 0 0 0 0 0.975 1.275 VCC VCC 0.700 1 0 0 0 1 0.950 1.250 1 0 0 1 0 0.925 1.225 1 0 0 1 1 0.900 1.200 1 0 1 0 0 0.875 1.175 1 0 1 0 1 0.850 1.150 1 0 1 1 0 0.825 1.125 1 0 1 1 1 0.800 1.100 1 1 0 0 0 0.775 1.075 1 1 0 0 1 0.750 1.050 1 1 0 1 0 0.725 1.025 BUCK1 Output-Voltage Transition Timing 1 1 0 1 1 0.700 1.000 1 1 1 0 0 0.675 0.975 1 1 1 0 1 0.650 0.950 1 1 1 1 0 0.625 0.925 1 1 1 1 1 0.600 No CPU The MAX1816/MAX1994 are designed to perform output voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the regulator to perform nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. equal to 1/8th the voltage appearing at the selected OFS input (∆VOUT = -0.125 × VOFS_). For inputs from 1.2V to 2V, a positive offset is added to the output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the selected OFS input (∆V OUT = 0.125 × (V REF - V OFS_ )). With this scheme, both positive and negative offsets can be achieved with a single voltage-divider. The piecewise linear transfer function is shown in Figure 9. 34 The regions of the transfer function below zero, above 2.0V, and between 0.8V and 1.2V are undefined. OFS inputs are disallowed in these regions, and the respective effects on the output are not specified. The offset control inputs are selected using a combination of the three logic inputs (SUS, PERF, and DPSLP), which also define the operating mode for the MAX1816/MAX1994. Table 7 details which OFS input is selected based on these control inputs. Modern mobile CPUs operate at multiple clock frequencies that require multiple VID settings. It is common when transitioning from one clock frequency to another for the CPU to go into a low-power state before changing the output voltage and clock frequency. The change must be accomplished within a fixed time interval—often less than 100µs. ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers OUTPUT OFFSET VOLTAGE (V) 0.15 0.10 0.05 0 -0.05 -0.10  1  VOLD − VNEW t SLEW ≤ 4 µs +  1 +  f 25mV  SLEW -0.15 0 0.5 0.8 1.0 1.2 1.5 2.0 OFS_ INPUT VOLTAGE (V) Figure 9. Offset-Control Transfer Function REF OR VOUT1 REF OR VOUT1 OFS0    where fSLEW = 252kHz × 143kΩ / RTIME, VOLD is the original DAC setting, and VNEW is the new DAC setting. See Time Frequency Accuracy in the Electrical Characteristics table for fSLEW accuracy. The practical range of RTIME is 68kΩ to 680kΩ, corresponding to 1.9µs to 19µs per 25mV step. Although the DAC takes discrete 25mV steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output voltage transition is: IL ≅ COUT ✕ 25mV ✕ fSLEW OFS0 OFS1 OR OFS1 OFS1 OFS2 The slew-rate controller also performs a soft-start and soft-stop function. The soft-start function works by counting up from zero, in order to minimize turn-on surge currents. The soft-stop executes this process in reverse, eliminating the negative output voltages and the need for an external Schottky output clamp diode that would otherwise be required if DL1 were simply forced high. Setting BUCK2 Output Voltage Figure 10. Simplified Offset-Control Circuits At the beginning of an output voltage transition, the regulator is placed in forced-PWM mode and the PGOOD output is high. If there is a fault on BUCK2 during this period, PGOOD goes low. The output voltage follows the internal DAC code, which changes in 25mV increments until it reaches the programmed VID code. The regulator remains in forced-PWM mode for 32 clock cycles after the transition to ensure that the output settles properly. The PGOOD output is forced high for 4 clock cycles after the transition also to allow the output to settle. The slewrate clock frequency (set by the RTIME resistor) must be set fast enough to ensure that the longest transition is completed within the allotted time interval. BUCK2’s Dual Mode™ operation allows the selection of common voltages without requiring external components (Figure 1). In fixed mode, connect FB2 to AGND for 2.5V output, or connect FB2 to VCC for 1.8V output. In adjustable mode, the output voltage can be adjusted from 1.0V to 5.5V using a resistive voltage-divider from the BUCK2 output to AGND with the center tap connected to FB2 (Figure 11). The equation for adjusting the output voltage is:  R1  VOUT2 = VFB2 1+   R2  where VFB2 is 1.0V. Dual Mode is a trademark of Maxim Integrated Products, Inc. ______________________________________________________________________________________ 35 MAX1816/MAX1994 The output voltage transition is performed in 25mV steps, preceded by a 4µs delay and followed by one additional clock period. The total time for a transition depends on RTIME, the voltage difference, and the accuracy of the MAX1816/MAX1994s’ slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX1816/MAX1994 automatically control the current to the minimum level required to complete the transition in the calculated time. As long as the surge current is less than the current limit set by ILIM1, the transition time is given by: UNDEFINED MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers Table 7. Offset Selection Truth Table INPUTS MODE ACTIVE OFS INPUTS SUS PERF DPSLP OFS2 OFS1 Battery Sleep 0 0 0 1 0 0 Battery 0 0 1 0 1 0 Performance Sleep 0 1 0 0 0 1 Performance 0 1 1 0 0 0 Suspend 1 0 0 0 0 0 Suspend 1 0 1 0 0 0 Suspend 1 1 0 0 0 0 Suspend 1 1 1 0 0 0 OFS0 0 = Logic low or input not selected. 1 = Logic high or input selected. Output Overvoltage Protection Output overvoltage protection (OVP) is available on BUCK1, BUCK2, and the linear regulator. The LINFB input is always monitored for overvoltage. The FBS and OUT2 inputs are only monitored for overvoltages when OVP is enabled. When any output exceeds the desired OVP threshold, the fault latch is set and the regulator is turned off. In the fault mode, DL1 and DL2 are forced high, DH1 and DH2 are forced low, and the linear regulator is turned off. For BUCK1 and BUCK2, if the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. DL1 is also kept high continuously when VCC UVLO is active, as well as in shutdown mode (Table 4). The device remains in the fault mode until VCC is cycled, or either SKP_/SDN or LIN/SDN is toggled. The triggering of the reset condition occurs on the rising edge of the SKP_/SDN or LIN/SDN signals. For BUCK1, the default OVP threshold is 2V for the MAX1816 and 2.25V for the MAX1994. For BUCK2, the OVP threshold is 115% of the nominal voltage for OUT2 (FB2 if external feedback is used for BUCK2). The overvoltage detection level for FBS can be adjusted through an external resistive voltage-divider. Connecting OVPSET to a voltage between 1.0V and 2.0V sets the OVP threshold for FBS. For the MAX1816, the fault latch is set when VFBS > VOVPSET. For the MAX1994, the fault latch is set when VFBS > 1.125 ✕ VOVPSET. The OVP threshold on OUT2 is not adjustable and remains at the default value of 115%. Connecting OVPSET to VCC disables OVP for BUCK1 and BUCK2. The operation of the linear regulator is not affected by OVPSET. Overvoltage protection can be disabled using the NO FAULT test mode (see the NO FAULT Test Mode section). 36 VBATT DH2 MAX1816 MAX1994 VOUT DL2 CS2 OUT2 R1 FB2 R2 PGND AGND Figure 11. Adjusting BUCK2 Output Voltage with a Resistive Voltage-Divider Output Undervoltage Protection The output undervoltage protection (UVP) is available on BUCK1, BUCK2, and the linear regulator. The protection is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the output voltage is under 70% of the nominal value for BUCK1 and BUCK2, and under 90% for the linear regulator (see the Electrical Characteristics table for the respective UVP thresholds), the fault latch is set. In the fault mode, DL1 and DL2 are forced high, DH1 and DH2 are forced low, and the linear regulator is turned off. The controller does not restart until VCC power is cycled, or either SKP_/SDN or LIN/SDN is toggled. The triggering of the reset condition occurs on the rising edge of the SKP_/SDN or LIN/SDN signals. ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers UVLO The MAX1816/MAX1994 provide input undervoltage lockout (UVLO) protection. If the VCC voltage drops low enough to trip the UVLO comparator, it is assumed that there is not enough supply voltage to make valid decisions. In order to protect the output from overvoltage faults, DL1 and DL2 are forced high if OVP is enabled, DH_ is forced low, and the linear regulator is turned off. If OVP is disabled, DL1 is forced high, DL2 is forced low, DH_ is forced low, and the linear regulator is turned off. For BUCK1 (and also for BUCK2 if OVP is enabled), this condition rapidly forces the outputs to zero since the slew-rate controller is not active. The fault results in large negative inductor currents and possibly small negative output voltages. If VCC is likely to drop in this fashion, the outputs can be clamped with Schottky diodes to PGND to reduce the negative excursions. Thermal Fault Protection The MAX1816/MAX1994 feature a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor sets the fault latch, which pulls DL_ high, DH_ low, and turns off the linear regulator. The device remains in fault mode until the junction temperature cools by 15°C, and either VCC power is cycled, or SKP_/SDN or LIN/SDN is toggled. NO FAULT Test Mode The over/undervoltage protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a test mode is provided to disable the OVP, UVP, and thermal shutdown features, and clear the fault latch if it has been set. Test mode applies to BUCK1, BUCK2, and the linear regulator. In the test mode, BUCK1 operates as if SKP1/SDN was high (skip mode). Set the voltage on SKP1/SDN between 10.8V to 13.2V to enable the NO FAULT test mode. BUCK1/BUCK2 Design Procedure Firmly establish the input voltage range and maximum load current for BUCK1 and BUCK2 before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice, lower input voltages result in better efficiency. 2) Maximum Load Current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) ✕ 80%. 3) Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. 4) Inductor Operating Point. This choice provides tradeoffs between size and efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The MAX1816/MAX1994s’ pulseskipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the load current value at which PFM/PWM switchover occurs. The optimum point is usually found between 20% and 50% ripple current. ______________________________________________________________________________________ 37 MAX1816/MAX1994 To allow startup, UVP is ignored during the undervoltage blanking time (the first 256 cycles of the slew rate after startup for BUCK1, the first 4096 cycles for BUCK2 and the first 512 cycles for the linear regulator). UVP can be disabled using the NO FAULT test mode (see the NO FAULT Test Mode section). MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers 5) Inductor Ripple Current. The inductor ripple current also impacts transient response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:  V  (ILOAD1 − ILOAD2 )2 × L ×  K OUT + t OFF(MIN)  V   IN VSAG =   VIN − VOUT   − t OFF(MIN)  2 × COUT × VOUT × K  VIN     where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics table) and K is from Table 3. Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: L= VOUT × (VIN − VOUT ) VIN × fSW × LIR × ILOAD(MAX) Example: ILOAD(MAX) = 19A, VIN = 7V, VOUT = 1.25V, fSW = 300kHz, 30% ripple current or LIR = 0.30: L= 1.25V × (7V − 1.25V) = 0.60µH 7V × 300kHz × 0.30 × 19A Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK):  LIR  IPEAK = ILOAD(MAX) × 1+  2   Setting the Current Limit for BUCK1 Connect ILIM1 to VCC for a default 50mV (CS1+ to CS1-) current-limit threshold. For an adjustable threshold, connect a resistive voltage-divider from REF to GND, with ILIM1 connected to the center tap. The current-limit threshold is precisely 1/10th of the voltage at ILIM1. When adjusting the current limit, use 1% tolerance resistors for the divider and a 10µA divider current to prevent a significant increase of errors in the current-limit threshold. 38 The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore:  LIR  ILIMIT(MIN) > ILOAD(MAX) × 1−   2  The current-sense resistor value (R1 in Figure 1) is calculated according to the worst-case (minimum) currentlimit threshold voltage (see the Electrical Characteristics table) and the valley current-limit threshold ILIMIT(MIN) described above: RSENSE = 50mV × 0.8 ILIMIT(MIN) (Fixed Mode) × 0.1 × 0.8 V (Adjustable Mode) RSENSE = ILIM1 ILIMIT(MIN) where 0.8 is a factor for the worst-case low current-limit threshold. To protect against component damage during short-circuit conditions, use the calculated value of RSENSE to size the MOSFET switches and specify inductor saturation-current ratings according to the worst-case high current-limit threshold: IPEAK (MAX) = 50mV × 1.2 × (1 + LIR) RSENSE (Fixed Mode) × 0.1 × 1.2 V × (1 + LIR) IPEAK (MAX) = ILIM1 RSENSE (Adjustable Mode) where 1.2 is a factor for worst-case high current-limit threshold. Low-inductance resistors, such as surface-mount metal film, are recommended. Setting the Current Limit for BUCK2 Connect ILIM2 to VCC for a default 50mV CS2 to GND current-limit threshold. For an adjustable threshold, connect a resistive voltage-divider from REF to GND, with ILIM2 connected to the center tap. The currentlimit threshold is precisely 1/10th of the voltage at ILIM2. When adjusting the current limit, use 1% tolerance resistors for the divider and a 10µA divider current to prevent a significant increase of errors in the current-limit threshold. ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers  LIR  ILIMIT(MIN) > ILOAD(MAX) × 1−   2  where I LIMIT(MIN) equals the minimum current-limit threshold voltage divided by the current-sense resistor. The sense resistor (R2 in Figure 1) determines the achievable current-limit accuracy. There is a trade-off between current-limit accuracy and sense-resistor power dissipation. Most applications employ a current-sense voltage of 50mV to 100mV. Choose a sense resistor so that: RSENSE = RSENSE = 50mV × 0.8 (Fixed Mode) ILIMIT(MIN) VILIM 2 × 0.1 × 0.8 (Adjustable Mode) ILIMIT(MIN) where 0.8 is a factor for worst-case low current-limit threshold. Extremely cost-sensitive applications that do not require high-accuracy current sensing can use the on-resistance of the low-side MOSFET switch in place of the sense resistor by connecting CS2 to LX2. Use the worstcase maximum value for RDS(ON) from the MOSFET data sheet taking into account the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C temperature rise. Assume the current-sense resistor in the application circuit in Figure 1 is removed and CS2 is directly tied to LX2. The Q4 maximum RDS(ON) = 3.8mΩ at TJ = +25°C and 5.7mΩ at TJ = +125°C. The minimum current-limit threshold is: 500mV × 0.1× 0.8 = 7A ILIMIT(MIN) = 5.7mΩ and the required valley current limit is: ILIMIT(MIN) > 7A ✕ (1 - 0.30/2) = 5.95A since 7A is greater than the required 5.95A, the circuit can deliver the 7A full-load current. Output Capacitor Selection (BUCK1 and BUCK2) The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the OVP circuit. In CPU core voltage regulators and other applications where the output is subject to violent load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR ≤ VDIP ILOAD(MAX) In non-CPU applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output-voltage ripple: RESR ≤ VP − P LIR × ILOAD(MAX) The actual microfarad capacitance value required often relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OSCONs, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. The amount of overshoot due to stored inductor energy can be calculated as: VSOAR = L × IPEAK 2 2 × COUT × VOUT where IPEAK is the peak inductor current. ______________________________________________________________________________________ 39 MAX1816/MAX1994 The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore: MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers BUCK1 Stability Considerations BUCK1 is fundamentally different from previous QuickPWM controllers in two respects: it uses a current-sense amplifier to obtain the current feedback signal (ramp), and it uses differential remote sense to compensate for voltage drops along the high-current path. The regulator adds the differential remote-sense signal to the currentfeedback signal to correct the output voltage. As long as the amplitude of the resulting signal is greater than 1% of the output voltage, the regulator remains stable. Stability can be determined by comparing the zero formed with the current-sense feedback network to the switching frequency. The boundary condition of stability is given by the following expression: f fZ ≤ SW π fZ ≈ 1 RDROOP × (COUT1 + CREMOTE ) +  2π ×   RLOCAL × COUT1 + RREMOTE × CREMOTE  where COUT1 is the local output capacitance (Figure 1), CREMOTE is the remote output capacitance, RLOCAL is the ESR of the local capacitors, RREMOTE is the ESR of the remote capacitors, and RDROOP is the effective voltage-positioning resistance, which is determined by the voltage-positioning gain AVPS and current-sense resistor RSENSE: RDROOP = AVPS x RSENSE Like previous Quick-PWM controllers, larger values of ESR and sense resistance increase stability. The voltage-positioning gain A VPS effectively increases the sense resistance, which further enhances stability. The RC time constants of the local and remote capacitors affect the stability criteria. These two time constants are defined as follows: τLOCAL = (RDROOP + RLOCAL + RPCB_TRACE) x COUT1 τREMOTE = (RDROOP + RREMOTE) x CREMOTE where RPCB_TRACE is the PC board trace resistance shown in Figure 1. 40 When the local capacitance time constant is either much greater or much smaller than that of the remote capacitance, the stability criteria is: RDROOP × (COUT1 + CREMOTE ) + RLOCAL × COUT1 + RREMOTE × CREMOTE ≥ 1 2 × fSW In applications where these two time constants are approximately equal, the criteria for stable operation reduces to: (RDROOP + RLOCAL ) × COUT1 ≥ 2 ×1f and SW (RDROOP + RREMOTE ) × CREMOTE ≥ 2 ×1f SW The standard application circuit (Figure 1) operating at 300kHz easily achieves stable operation because the time constant of the local capacitors is much greater than that of the remote capacitors. In this example, COUT1 = 990µF, RLOCAL = 3.3mΩ, CREMOTE = 10µF, RREMOTE = 5mΩ, and RDROOP = 2 x 1mΩ = 2mΩ: 2mΩ × (990µF + 10µF) + 3.3mΩ × 990µF + 5mΩ × 10µF ≥ 1 2 × 300kHz 5.32µs ≥ 1.67µs When voltage positioning is not used (AVPS = 0) and the ESR of the output capacitors alone cannot meet the stability requirement, the current feedback signal must be generated from a different source. The current ramp signal at CS1+ and the output voltage must be summed at the FBS input. For stable operation, a 3.3µF feed-forward capacitor is added from the CS1+ input to FBS and a 10Ω resistor is inserted from the remote load to FBS forming an RC filter (Figure 12). The cutoff frequency of the RC filter should be approximately an order of magnitude lower than the regulator’s switching frequency to prevent sluggish transient response. To avoid input-bias current-induced offset errors, the resistor should be less than 20Ω. ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers RSENSE 1mΩ × (990µF + 10µF) + 3.3mΩ × 990µF + 5mΩ × 10µF ≥ CS1+ 3.3µF REMOTE LOAD COUT PC BOARD TRACE RESISTANCE CS1- 10Ω FBS GDS Figure 12. Output Feed Forward for Nonvoltage-Positioned Applications For nonvoltage-positioned applications using a feedforward circuit, the RC time constants of the local and remote capacitors are defined as: τLOCAL = (RSENSE + RLOCAL) x COUT1 τREMOTE = (RSENSE + RREMOTE + RPCB_TRACE) x CREMOTE The new stability criteria for nonvoltage-positioned applications using feed forward becomes: RSENSE × (COUT1 + CREMOTE ) + RLOCAL × COUT1 + RREMOTE × CREMOTE ≥ 1 2 × fSW for τ LOCAL much greater or much smaller than τREMOTE, and (RSENSE + RLOCAL ) × COUT1 ≥ 2 ×1f and SW (RSENSE + RREMOTE ) × CREMOTE ≥ 2 ×1f SW when τLOCAL and τREMOTE are approximately equal. If the voltage-positioning gain in the standard application circuit (Figure 1) is set to zero and the feed-forward compensation circuit shown in Figure 12 is used, stable operation can still be easily achieved. In this example, COUT1 = 990µF, RLOCAL = 3.3mΩ, CREMOTE = 10µF, RREMOTE = 5mΩ, RSENSE = 1mΩ, and RPCB_TRACE = 2mΩ, and the local time constant is much greater than the remote time constant. 1 2 × 300kHz 4.32µs ≥ 1.67µs Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output-voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient current feedback signal. Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. BUCK2 Stability Considerations The stability criterion for BUCK2 is the same as previous Quick-PWM controllers like the MAX1714. Stability is determined by comparing the value of the ESR zero to the switching frequency. The point of stability is given by the following expression: f fESR ≤ SW π 1 where fESR = 2π × RESR × COUT For good phase margin, it is recommended to increase the equivalent RC time constant by a factor of two. The standard application circuit (Figure 1) operating at 390kHz with COUT = 330µF and RESR = 10mΩ, easily meets this requirement. ______________________________________________________________________________________ 41 MAX1816/MAX1994 Therefore: PC BOARD TRACE RESISTANCE MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = ILOAD VOUT (VIN − VOUT ) VIN The RMS input currents for BUCK1 and BUCK2 can be calculated using the above equation. Use the sum of these two currents as the total RMS current. Note that this is a very conservative estimation because the two regulators are never in phase 100% of the time. The actual RMS current is always lower than the calculated value. For most applications, nontantalum chemistries (ceramic or OSCON) are preferred due to their resilience to inrush surge currents typical of systems with a switch or a connector in series with the battery. If the MAX1816/MAX1994 operate as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>12A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (Q1 in Figure1) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of Q1. Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of Q1. If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET (Q2) that has the lowest possible RDS(ON), comes in a moderate-sized package (i.e., two or more 8-pin SOs, DPAKs, or D2PAKs), and is reasonably priced. Ensure that the MAX1816/MAX1994 DL_ gate driver can drive Q2; in other words, check that the dV/dt caused by Q1 turning on does not pull up the gate of Q2 due to drain-to-gate capacitance, causing cross-conduction problems. Switching losses are not an 42 issue for the low-side MOSFET, since it is a zero-voltage switched device when used in the buck topology. MOSFET Power Dissipation The high-side MOSFET conduction power dissipation due to on-state channel resistance is: V PD(Q1_ Conduction) = OUT × ILOAD2 × RDS(ON)1 VIN Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often constrains how small the MOSFET can be. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to VIN(MAX), reconsider the MOSFET selection. Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation and thermal measurements: PD(Q1_ Switching) = CRSS × VIN(MAX)2 × fSW × ILOAD IGATE where CRSS is the reverse transfer capacitance of Q1 and IGATE is the peak gate-drive source/sink current (1.5A typ for BUCK1, 0.75A typ for BUCK2). For the low-side MOSFET (Q2), the worst-case power dissipation always occurs at maximum battery voltage:  VOUT  2 PD(Q2) = 1 −  × ILOAD × RDS(ON)2 V IN(MAX)   The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ILOAD = ILIMIT(HIGH ) + (LIR/2) ✕ ILOAD(MAX) ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers The MOSFETs must have a good-sized heat sink to handle the overload power dissipation. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. Choose a Shottky diode (D1) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency is not critical. Linear Regulator Design Procedure Output Voltage Selection Adjust the linear regulator’s output voltage by connecting a resistive voltage-divider from VLIN to AGND with the center tap connected to LINFB (Figure 1). Select R9 in the range of 10kΩ to 100kΩ. Calculate R8 with the following equation: R8 = R9 [(VLIN / 1.00V) - 1] Pass Transistor Selection The PNP pass transistor must meet specifications for current gain (hFE), input capacitance, emitter-collector saturation voltage, and power dissipation. The transistor’s current gain limits the guaranteed maximum output current to:  ILOAD(MAX) = IDRV  − VEB  hFE(MIN) REB  where IDRV is the minimum base-drive current, and REB is the pullup resistor connected between the transistor’s emitter and base. Furthermore, the transistor’s current gain increases the linear regulator’s DC loop gain (see the Linear Regulator Stability Requirements section), so excessive gain destabilizes the output. Therefore, transistors with current gain over 300A/A at the maximum output current are not recommended. The transistor’s input capacitance and input resistance also create a second pole, which could be low enough to make the output unstable when heavily loaded. The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports. Alternatively, the package’s power dissipation could limit the usable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor’s package and mounting must exceed the actual power dissipation in the device. The power dissipation equals the maximum load current times the maximum input-to-output voltage differential: P = ILOAD(MAX) x (VLDOIN - VLIN) = ILOAD(MAX) x VCE Linear Regulator Stability Requirements The MAX1816/MAX1994 linear-regulator controller uses an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, the pass transistor, the emitter-base resistor, and the output capacitor determine the loop stability. If the output capacitor and pass transistor are not properly selected, the linear regulator is unstable. The transconductance amplifier regulates the output voltage by controlling the pass transistor’s base current. Since the output voltage is a function of the load current and load resistance, the total DC loop gain is approximately: V  I h  A V(LDO) =  REF  1 +  BIAS FE   5.5  VT    ILOAD   where VT is 26mV at room temperature, IBIAS is the current though the emitter-base resistor (REB), and VREF = 1.0V. This bias resistor is typically 220Ω, providing approximately 3.2mA of bias current. The output capacitor and the load resistance create the dominant pole in the system. However, the pass transistor’s input capacitance creates a second pole in the system. Additionally, the output capacitor’s ESR generates a zero. To achieve stable operation, use the following equations to verify that the linear regulator is properly compensated: 1) First, determine the dominant pole set by the linear regulator’s output capacitor and the load resistor: fPOLE(CLDO) = 1 2πCLDORLOAD = ILOAD(MAX) 2πCLDOVLDO The unity gain crossover of the linear regulator is: fCROSSOVER = AV(LDO)fPOLE(CLDO) 2) Next, determine the second pole set by the emitterbase capacitance (including the transistor’s input capacitance), the transistor’s input resistance, and the emitter-base pullup resistor: ______________________________________________________________________________________ 43 MAX1816/MAX1994 where I LIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers R I + VThFE 1 fPOLE(CEB) = = EB LOAD 2πCEB (REB || RIN ) 2πCEB REB VThFE 3) A third pole is set by the linear regulator’s feedback resistance and the capacitance between LINFB and GND, including the stray capacitance: fPOLE(FB) = 1 2πCFB (R8 || R9) 4) If the second and third poles occur well after unity gain crossover, the linear regulator remains stable: fPOLE(CEB) > 2fPOLE(CLDO)AV(LDO) However, if the ESR zero occurs before the unity gain crossover, cancel the zero with the feedback pole by changing circuit components such that: fPOLE(FB) ≈ 1 2πCLDORESR For most applications where ceramic capacitors are used, the ESR zero always occurs after the crossover. Output Capacitor Selection Typically, more output capacitance provides the best performance, since this also reduces the output voltage drop immediately after a load transient. Connect at least a 10µF capacitor between the linear regulator’s output and ground, as close to the external pass transistor as possible. Depending on the selected pass transistor, larger capacitor values may be required for stability (see the Linear Regulator Stability Requirements section). Furthermore, the output capacitor’s ESR affects stability. Use output capacitors with an ESR less than 200mΩ to ensure stability and optimum transient response. Once the minimum capacitor value for stability is determined, verify that the linear regulator’s output does not contain excessive noise. Although adequate for stability, small capacitor values can provide too much bandwidth, making the linear regulator sensitive to noise. Larger capacitor values reduce the bandwidth, thereby reducing the regulator’s noise sensitivity. Applications Information Voltage Positioning Powering new mobile processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response require44 ment. Setting the no-load output voltage slightly higher allows a larger step down when the output current suddenly increases, and regulating at the lower output voltage under load allows a larger step up when the output current suddenly decreases. Allowing a larger step size means that the output capacitance can be reduced and the capacitor’s ESR can be increased. Adding a series output resistor positions the full-load output voltage below the actual DAC programmed voltage. Connect FB directly to the inductor side of the voltage-positioning resistor (R1, 1mΩ). The other side of the voltage-positioning resistor should be connected directly to the output filter capacitor with a short, wide PC board trace. With the gain pin floating (GAIN = 2), a 20A full-load current causes a 40mV drop in the output. This 40mV is a -3.2% droop. An additional benefit of voltage positioning is reduced power consumption at high load currents. Because the output voltage is lower under load, the CPU draws less current. The result is lower power dissipation in the CPU, although some extra power is dissipated in R1. For a nominal 1.25V, 20A output, reducing the output voltage by 3.2% gives an output voltage of 1.21V and an output current of 19.4A. Given these values, CPU power consumption is reduced from 25W to 23.5W. The additional power consumption of R1 is: 1mΩ ✕ (19.4A)2 = 0.38W And the overall power savings is as follows: 25W - (23.5W + 0.38W) = 1.12W In effect, 1.5W of CPU dissipation is saved, and the power supply dissipates some of the power savings, but both the net savings and the transfer of dissipation away from the hot CPU are beneficial. High-Current Master-Slave Applications The MAX1816/MAX1994 can be used in high-current applications using additional slave regulators. Figure 2 illustrates a 40A master-slave application using this technique. The MAX1994 is placed in forced PWM mode to simplify operation with the slave. Refer to the MAX1980 data sheet for a detailed description of the master-slave architecture and how to configure correctly the slave circuit. Dropout Performance The output voltage adjustment range for continuousconduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot (375ns max at 550kHz and 1000kHz). For best dropout performance, use the slower (200kHz) on-time settings. ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers A reasonable minimum value for h is 1.5, but this can be adjusted up or down to allow trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VIN(MIN) = (VOUT + VDROP1) + VDROP2 − VDROP1 T  OFF(MIN) × h 1−    K   where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths, respectively (see the On-Time One-Shot (TON) section), TOFF(MIN) is from the Electrical Characteristics table, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable V SAG . If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example VOUT = 1.2V fSW = 300kHz K = 3.3µs, worst-case K = 2.97µs TOFF(MIN) = 500ns VDROP1 = VDROP2 = 100mV h = 1.5 VIN(MIN) = (1.2V + 0.1V) + 0.1V − 0.1V = 1.74V  0.5µs × 1.5  1−    2.97µs  Calculate again with h = 1 gives the absolute limit of dropout: VIN(MIN) = (1.2V + 0.1V) + 0.1V − 0.1V = 1.56V  0.5µs × 1 1−    2.97µs  Since 1.56V is less than the lower limit of the input voltage range (2V), the practical minimum input voltage with reasonable output capacitance would be 2V. One-Stage (Battery Input) vs. Two-Stage (5V Input) Conversion The MAX1816/MAX1994 can be used with a direct battery connection (one stage) or can obtain power from a regulated 5V supply (two stage). Each approach has advantages, and careful consideration should go into the selection of the final design. The one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5V supply. The transient response of the single stage is better due to the ability to ramp up the inductor current faster. The total efficiency of a single stage is better than the two-stage approach. The two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the CPU for better regulation and lower I2R losses from PC board traces. Although the two-stage design has worse transient response than the single stage, this can be offset by the use of a voltage-positioned converter. Ceramic Output Capacitor Applications Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. They are also expensive and brittle, and their ultra-low ESR characteristic can result in excessively high ESR zero frequencies (affecting stability in nonvoltage-positioned circuits). In addition, their relatively low capacitance value can cause output overshoot when going abruptly from full-load to no-load conditions, unless the inductor value can be made small (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. In some cases, there may be no room for electrolytic capacitors, creating a need for a DC-DC design that uses nothing but ceramic capacitors. ______________________________________________________________________________________ 45 MAX1816/MAX1994 When working with low-input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN) as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP/∆IDOWN is an indicator of ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle and VSAG greatly increases, unless additional output capacitance is used. MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers The MAX1816/MAX1994 can take full advantage of the small size and low ESR of ceramic output capacitors in a voltage-positioned circuit. The addition of the positioning resistor increases the ripple at FB, lowering the effective ESR zero frequency of the ceramic output capacitor. Output overshoot (V SOAR) determines the minimum output capacitance requirement (see the Output Capacitor Selection section). Often the switching frequency is increased to 550kHz or 1000kHz, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 2% to 3% and about 5% at 1000kHz when compared to the 300kHz voltage-positioned circuit, primarily due to the high-side MOSFET switching losses. PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 13). Refer to the MAX1816/MAX1994 EV kit data sheet for a specific layout example. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) Isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. Use a separate PGND plane under the BUCK1 and BUCK2 sides (called PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2 ground planes. 2) Use a star ground connection on the power plane to minimize the crosstalk between BUCK1 and BUCK2. 3) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 4) Connect all analog grounds to a separate solid copper plane, which connects to the AGND pin of the MAX1816/MAX1994. This includes the V CC bypass capacitor, REF bypass capacitor, compensation components, the TIME resistor, as well as any other resistive dividers. 46 5) Tie AGND and PGND together close to the IC. Do not connect them together anywhere else. Carefully follow the grounding instructions in the Layout Procedure. 6) In high-current master-slave applications, the master controller should have a separate analog ground. Return the appropriate noise-sensitive components to this plane. Since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. A low value (≤10Ω) resistor is sufficient to link the two grounds. 7) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance full load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. 8) Keep the high-current gate-driver traces (DL_, DH_, LX_, and BST_) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. 9) CS1+, CS1-, CS2, and AGND connections for current limiting must be made using Kelvin-sense connections to guarantee the current-limit accuracy. Kelvin connections to LX2 and AGND must also be made if the synchronous rectifier R DS(ON) of BUCK2 is used for current limiting. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from the outside using the top copper layer, while connecting GND and LX inside (underneath) the 8-pin SO package. 10) When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 11) Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM_). Make all pinstrap control input connections (SKP_/SDN, ILIM_, etc.) to analog ground or VCC rather than power ground or VDD. ______________________________________________________________________________________ Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers MAX1816/MAX1994 COUT1 COUT1 POWER GROUND TOP LAYER VOUT1 VIA TO POWER GROUND REF CAP COUT1 POWER GROUND COUT1 VDD CAP COUT2 COUT2 L1 VOUT2 L2 MAX1816 MAX1994 LX1 ANALOG GROUND VCC CAP LX2 POWER GROUND BOTTOM LAYER CIN CIN CIN CIN CIN CIN INPUT (V+) LX1 LX2 Figure 13. Power-Stage PC Board Layout Example Layout Procedure 1) Place the power components first, with ground terminals adjacent (low-side MOSFET sources, CIN_, COUT_, D1/D2 anodes). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the backside in order to keep LX_, PGND_, and the DL_ drive lines short and wide. The DL_ gate traces must be short and wide, measuring 10 to 20 squares (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST_ diodes and capacitors, VDD bypass capacitor) together near the controller IC. 4) Make the MAX1816/MAX1994 controllers’ ground connections as shown in Figure 13. This diagram can be viewed as having three separate ground planes: input/output ground, where all the high- power components go; the power ground plane, where the PGND pin and VDD bypass capacitors go; and an analog ground plane where sensitive analog components go. The analog ground plane and power ground plane must meet only at a single point close to the IC. These two planes are then connected to the high-power output ground with a short connection from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical. Chip Information TRANSISTOR COUNT: 13,313 ______________________________________________________________________________________ 47 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32, 44, 48L QFN .EPS MAX1816/MAX1994 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers D2 D CL D/2 b D2/2 k E/2 E2/2 E CL (NE-1) X e E2 k L DETAIL A e (ND-1) X e CL CL L L e A1 A2 e A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 48 ______________________________________________________________________________________ REV. A 1 2 Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers COMMON DIMENSIONS EXPOSED PAD VARIATIONS ** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV. A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1816/MAX1994 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)