EVALUATION KIT AVAILABLE
MAX2140
General Description
The MAX2140 complete receiver is designed for satellite
digital audio radio services (SDARS). The device includes
a fully monolithic VCO and only needs a SAW at the IF
and a crystal to generate the reference frequency.
To form a complete SDARS radio, the MAX2140 requires
only a low-noise amplifier (LNA), which can be controlled
by a baseband controller. The small number of external
components needed makes the MAX2140-based platform
the lowest cost and the smallest solution for SDARS.
The receiver includes a self-contained RF AGC loop and
baseband-controlled IF AGC loop, effectively providing a
total dynamic range of over 92dB.
Channel selectivity is ensured by the SAW filter and by
on-chip monolithic lowpass filters.
The fractional-N PLL allows a very small frequency step,
making possible the implementation of an AFC loop.
Additionally, the reference is provided by an external
XTAL and on-chip oscillator. A reference buffer output is
also provided.
Complete SDARS Receiver
Features
●● Integrated Receiver, Requires Only One SAW Filter
●● Self-Contained RF AGC Loop
●● Differential I/Q Interface
●● Complete Integrated Frequency Generation
●● Bias Supply for External LNAs
●● Overcurrent Protection
●● Low-Power Standby Mode
●● Very Small 44-Pin Thin QFN Package
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX2140ETH
PART
-40°C to +85°C
44 Thin QFN-EP*
MAX2140ETH+
-40°C to +85°C
44 Thin QFN-EP*
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Block Diagram/Pin Configuration
●● Programmable gains
●● Lowpass filters tuning
●● Individual functional block shutdown
The MAX2140 minimizes the requirement on the baseband controller. No compensation or calibration procedures are required. The device is available in a 7mm x
7mm 44-pin thin QFN package.
Applications
●● Satellite Digital Audio Radio Services (SDARS)
●● 2.4GHz ISM Radios
SCL
I2CA1
I2CA2
VCC_BE4
IF2QO-
IF2QI-
IF2QO+
IF2QI+
QOUT-
QOUT+
circuit for a wide variety of conditions, providing features
such as:
SDA
A 2-wire interface (I2C-bus compatible) programs the
44
43
42
41
40
39
38
37
36
35
34
XM TUNER
VCC_FE0 1
33 VTUNE
RFIN+ 2
32 VCCREG
MAX2140
RFIN- 3
31 VCC_VCO
VCC_FE1 4
∑ ∆ - MOD
PFD
CHP
1/R
IFOUT- 6
29 CPOUT
28 LOCK
RFAGC_C 7
27 VCC_A
LPF
VCC_FE2 8
HPF
26 VCC_D
/4/8
QUAD
AGCPWM 9
IFIN+ 10
25 REFOUT
LPF
IFIN- 11
24 XTAL
HPF
13
14
15
16
17
18
19
20
21
22
VCC_BE1
VCC_BE2
VCC_BE3
VINANT
VOUTANT
IF2IO-
IF2II-
IF2IO+
IF2II+
IOUT-
IOUT+
23 VCC_XTAL
12
ACTUAL SIZE
7mm x 7mm
19-3123; Rev 4; 4/15
30 VCC_FE3
1/N
RF
AGC
IFOUT+ 5
MAX2140
Complete SDARS Receiver
Absolute Maximum Ratings
VCC_XX to GND....................................................-0.3V to +4.3V
VINANT to GND....................................................-0.3V to +5.6V
AGCPWM to GND.................................................-0.3V to +3.0V
Digital Input Current..........................................................±10mA
Maximum VSWR Without Damage......................................... 4:1
Maximum VSWR Without Oscillations.................................... 4:1
All Other Pins............................................ -0.3V to (VCC + 0.3V)
Continuous Power Dissipation (TA = +70°C)
44-Pin TQFN (derate 26.31mW/°C above +70°C).....2105mW
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
θJC......................................................................................1°C/W
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC Electrical Characteristics
(VCC = 3.1V to 3.6V; VINANT ≥ VCC, VOUTANT in open circuit, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, VVINANT =
3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage Range (Note 2)
Operating Supply Current
Lock Indicator High (Locked)
Lock Indicator Low (Unlocked)
Digital Input-Logic High
Digital Input-Logic Low
Input Current for Digital Control
Pins
Input Current for AGCPWM
Voltage Drop VINANT to
VOUTANT in Normal Operating
Mode
SYMBOL
CONDITIONS
VCC
VINANT
ICC
ISHDN
TYP
MAX
3.1
3.3
3.6
3.1
3.3
5.3
150
180
All blocks on
All blocks off
30
VIH_LK
VCC - 0.5
VIH
VCC - 0.5
VIL_LK
VIL
UNITS
V
mA
µA
V
0.5
V
V
0.5
V
IDIG
-1
+1
µA
IAGCPWM
-10
+290
µA
0.35
V
500
mA
30
mA
DROP
Maximum current sink at VOUTANT is
150mA
Current Sink at VOUTANT to Flag
Bit ACP = 1
IANTDC_H
VOUTANT shorted to ground (Note 4)
Current Sink at VOUTANT to Flag
Bit AND = 1
IANTDC_L
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MIN
VANTDC-
195
12
20
Maxim Integrated │ 2
MAX2140
Complete SDARS Receiver
AC Electrical Characteristics
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VVINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VVINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-84
dBm
GENERAL RECEIVER
Minimum Input RF Power to
Produce 20mVP-P (Differential) at
I and Q Baseband Outputs
PMIN
IF AGC is set at maximum gain,
bit HPF = 0 (Note 4)
-91
Maximum Input RF Power to
Produce 400mVP-P (Differential)
at I and Q Baseband Outputs
PMAX
RF AGC threshold: RF_AGC_TRIP =
-17dBm; IF AGC is set at minimum gain, bit
HPF = 0
+3
PLK_H
LO-related spurious > 2GHz
-66
LO-related spurious < 2GHz
-38
RF AGC is at maximum gain,
IF AGC is at reference gain
8.5
10.4
RF AGC is at maximum gain,
IF AGC is at reference gain -10dB
9.3
11.7
RF AGC is at maximum gain -5dB,
IF AGC is at reference gain
13.3
15.5
RF AGC is at maximum gain -10dB,
IF AGC is at reference gain
17.8
21.5
RF AGC is at maximum gain,
IF AGC is at reference gain
-32
RF AGC is at maximum gain,
IF AGC is at reference gain -5dB
-27
RF AGC is at maximum gain -30dB,
IF AGC is at reference gain -43dB
+9
RF AGC is at maximum gain -20dB,
IF AGC is at reference gain -53dB
+6
RF AGC is at maximum gain,
IF AGC is at reference gain
-9
RF AGC is at maximum gain -7dB,
IF AGC is at reference gain
-3
RF AGC is at maximum gain -25dB,
IF AGC is at reference gain
+12
LO to RF Input Leakage
Noise Figure (Notes 3, 5)
In-Band Input IP3 (Notes 5, 6)
Out-of-Band Input IP3
(Notes 5, 7)
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PLK_L
NF
I_IIP3
O_IIP3
dBm
dBm
dB
dBm
dBm
Maxim Integrated │ 3
MAX2140
Complete SDARS Receiver
AC Electrical Characteristics (continued)
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VVINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VVINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
In-Band Input IP2 (Notes 5, 6)
Out-of-Band Input IP2
(Notes 5, 7)
SYMBOL
I_IIP2
O_IIP2
CONDITIONS
+1
RF AGC is at maximum gain,
IF AGC is at reference gain -5dB
+6
RF AGC is at maximum gain,
IF AGC is at reference gain -25dB
+27
RF AGC is at maximum gain,
IF AGC is at reference gain
+38
RF AGC is at maximum gain -7dB,
IF AGC is at reference gain
+45
RF AGC is at maximum gain -25dB,
IF AGC is at reference gain
+60
OSR
Baseband frequencies = 100kHz (Note 4)
Image Rejection
IRej
Half IF Rejection
HRej
At fLO - fIF
LNA Gain Reduction
RFAGC_
Range
32
At fLO + 0.5 x fIF
(Note 4)
Minimum RF AGC Trip Point
RFAGC_min Bits RF4/3/2/1/0 = 00000 (BIN)
RF AGC Trip Point
RFAGC_int
Maximum RF AGC Trip Point
TYP
RF AGC is at maximum gain,
IF AGC is at reference gain
Opposite Sideband Rejection
RF AGC LOOP
MIN
Bits RF4/3/2/1/0 = 00010 (BIN) (Note 4)
30
MAX
dBm
dBm
39
dB
54
dB
53
dB
42
dB
-35
-37
RFAGC_max Bits RF4/3/2/1/0 = 10100 (BIN)
UNITS
dBm
-33
-29
-15
dBm
dBm
FRONT-END (FE) PROGRAMMABLE GAIN
FE Programmable Gain Range
FE_Rge
FE Programmable Gain Step
FE_Step
(Note 4)
19
22
26
dB
2
dB
IF FILTER INTERFACE
IF Output Differential Admittance
Yout, IF
Between pins IFOUT+, IFOUT-,
fIF = 259MHz and 467MHz
1/900
+ j0
S
Input Differential Impedance
Presented by the IC to the IF
Filter Output
Zin, IF
Between pins IFOUT+, IFOUT-,
fIF = 259MHz and 467MHz
150
+ j0
Ω
IF AGC LOOP
IF AGC Control Voltage for Max
Gain
IFAGC_VM
Applied at pin AGCPWM
0.2
V
IF AGC Control Voltage for Min
Gain
IFAGC_Vm
Applied at pin AGCPWM
2.5
V
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Maxim Integrated │ 4
MAX2140
Complete SDARS Receiver
AC Electrical Characteristics (continued)
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VVINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VVINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
IF AGC Gain-Control Range
SYMBOL
IFAGC_
Rge
CONDITIONS
(Note 4)
MIN
TYP
47
MAX
UNITS
64
dB
INTERNAL BASEBAND LOWPASS FILTERS
LPF In-Band Ripple
LPFA_rip
From 0 to 6.3MHz with respect to the
amplitude at 100kHz
0.7
LPFrej
At 10.25MHz with respect to the amplitude
at 2MHz
14
21
LPFrej
At 16MHz with respect to the amplitude at
2MHz
47
51
Gain Increase
BB_DG
From bit HPF = 0 to HPF = 1
Maximum I/QOUT± Pin Loading
IQ_load
Per each of the four pins
LPF Out-of-Band Rejection
(Note 4)
dB
dB
INTERNAL OUTPUT STAGE
4
dB
10//10
kΩ//pF
FREQUENCY GENERATION: VCO AND PLL
VCO Frequency Range
VCO Tuning Gain
VCO_Range Over VCHP range (Note 4)
VCO_Gain
1861
(Note 4)
At 1kHz within PLL band
Synthesized VCO Phase Noise
Synthesized VCO Phase-Noise
Jitter
Charge-Pump Voltage Range
Charge-Pump Current
Pin CHP Leakage Current
PLL Reference Division Ratio
Synthesized VCO Smallest
Fractional Step
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VCO_PN
VCO_jit
VCHP
ICHP
CHP_leak
PLLref
PLLstep
-80
At 100kHz outside PLL band
-101
Integrated from 100Hz to 100kHz, LO
frequency = 2079MHz
240
MHz/V
dBc/Hz
1.2
0.40
DegRMS
2.75
Bit CHP = 0
0.6
Bit CHP = 1
1.2
Programmable through I2C
MHz
-79
At 10kHz outside PLL band
Across VCHP range
2079
mA
5
1
V
nA
2
23
Hz
Maxim Integrated │ 5
MAX2140
Complete SDARS Receiver
AC Electrical Characteristics (continued)
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VVINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VVINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
SYMBOL
Synthesized VCO Spurs
VCOspur
CONDITIONS
MIN
0Hz < foffset < 10kHz
XTALrge
MAX
UNITS
(Note 9)
10kHz < foffset < 1MHz
(Note 9)
1MHz < foffset < 10MHz
XTAL Oscillator Frequency Range
TYP
dBc
-47
24
49
MHz
XTAL Oscillator Frequency Error
XTALerror
Using an external XTAL (Note 8)
-16
+16
ppm
XTAL Oscillator Input Voltage
XTALswing
Using an external TCXO
0.8
XTAL Oscillator Input Duty Cycle
XTALduty
Using an external TCXO
47
50
VCC
VP-P
Reference Buffer Output Voltage
REFV
0.95
1.10
45
50
Reference Buffer Output Duty
Cycle
Maximum REFOUT Pin Loading
REFduty
REFOUT_1d
Using the REFOUT pin loading specified
below (Note 4)
Using an external XTAL, not overdriven; bit
RFD = 0, using the REFOUT pin loading
specified below
REFOUT pin frequency = 24MHz
20
REFOUT pin frequency = 48MHz
8
53
%
VP-P
55
%
pF
Timing Characteristics
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL INTERFACE (NOTE 2)
Serial Clock Frequency
fSCL
200
kHz
Note 1: At TA = -40°C, minimum and maximum values are guaranteed by design and characterization.
Note 2: Minimum and maximum values are guaranteed by design and characterization, unless otherwise noted.
Note 3: At TA = +25°C, minimum and maximum values are guaranteed by design and characterization.
Note 4: At TA = +25°C and TA = +85°C, parameters are production tested.
Note 5: IF AGC reference level is defined as being the required voltage applied on pin AGCPWM, and the corresponding receiver IF
gain, to measure 20mVP-P at each I/Q differential output when the RF input power is -91dBm. If even for zero volts applied
on pin AGCPWM the I/Q differential outputs are below 20mVP-P when the RF input power is -91dBm, then the reference
level is defined as zero volts.
Note 6: In-band IP2 and IP3 are measured with two CW tones at RF input: f1 = 2339.55MHz, f2 = 2339.75MHz.
Note 7: Out-of-band IP2 and IP3 are measured with two CW tones at RF input: f1 = 2326.25MHz, f2 = 2330.25MHz.
Note 8: Error computed using a crystal with no error.
Note 9: No spur in the offset frequency range.
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Maxim Integrated │ 6
MAX2140
Complete SDARS Receiver
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAXIMUM RF AGC
-20
-25
2.3
2.4
-20
-25
-30
DIVIDER: /8
MAX2140 toc03
40
TA = +25°C
TA = -40°C
30
TA = +85°C
20
4
0
8
12
16
0
20
0
0.6
1.2
1.8
2.4
RF AGC ENGAGEMENT SETTING
CONTROL VOLTAGE (V)
RF AGC SETTLING TIME
WITH 20dB STEP
IF AGC ATTENUATION
vs. CONTROL VOLTAGE
IF AGC ATTENUATION
vs. CONTROL VOLTAGE
5dB/div
R4 = 100Ω
C32 = 0.1µF
60
50
TA = -40°C
40
30
TA = +85°C
20
TA = +25°C
10
START TIME: 0µs
STOP TIME: 200µs
0
0
0.6
1.2
1.8
2.4
3.0
CONTROL VOLTAGE (V)
0dB
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R4 = 5000Ω
C32 = 0.22µF
40
30
TA = -40°C
20
TA = +85°C
10
0
TA = +25°C
0
0.6
1.2
1.8
2.4
3.0
CONTROL VOLTAGE (V)
LPF FREQUENCY RESPONSE
10.250000MHz
-27.278dB
-100dB
1MHz
50
IF AGC ATTENUATION (dB)
RF AGC ATTACK
TIME
RF AGC DECAY
TIME
70
3.0
MAX2140 toc06
FREQUENCY (GHz)
0dBm
-50dBm
50
10
-35
-40
2.5
DIVIDER: /4
MAX2140 toc05
2.2
-15
60
MAX2140 toc07
-30
MINIMUM RF AGC
IF AGC ATTENUATION (dB)
-15
-10
RF AGC ATTENUATION (dB)
-10
RF AGC ATTENUATION
vs. CONTROL VOLTAGE
RF AGC ENGAGEMENT THRESHOLD
MAX2140 toc02
MAX2140 toc01
-5
MAX2140 toc04
INPUT RETURN LOSS (dB)
0
RF AGC ENGAGEMENT THRESHOLD (dBm)
INPUT RETURN LOSS
vs. FREQUENCY
16MHz
Maxim Integrated │ 7
MAX2140
Complete SDARS Receiver
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
REF
80ns
100ns/div
-50dBc/Hz
VCO PHASE NOISE vs. OFFSET FREQUENCY
REFOUT WAVEFORM (REF = 0, RFD = 0)
MAX2140 toc10
MAX2140 toc09
MAX2140 toc08
LPF GROUP DELAY vs. FREQUENCY
6.250000MHz
113.8ns
1MHz
16MHz
-150dBc/Hz
REFOUT WAVEFORM (REF = 1, RFD = 0)
MAX2140 toc11
200mV/div
10
FREQUENCY OFFSET (Hz)
20ns/div
1M
REFOUT WAVEFORM (REF = 1, RFD = 1)
MAX2140 toc12
500mV/div
10ns/div
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500mV/div
20ns/div
Maxim Integrated │ 8
MAX2140
Complete SDARS Receiver
Pin Description
PIN
NAME
FUNCTION
VCC_FE0, VCC_FE1,
VCC_FE2, VCC_BE1,
1, 4, 8,
VCC_BE2, VCC_BE3,
12–15, 23,
VINANT, VCC_XTAL, Power Supplies. Bypass to ground with capacitors as close to the pins as possible.
26, 27, 30,
VCC_D, VCC_A,
31, 40
VCC_FE3, VCC_VCO,
VCC_BE4
Differential RF Inputs. Accept RF input signal from the SDARS cabled antenna with a 50Ω to
100Ω balun.
2, 3
RFIN+, RFIN-
5, 6
IFOUT+, IFOUT-
7
RFAGC_C
RF AGC Power-Detector Output. Set the RF AGC attack and decay response times.
9
AGCPWM
IF AGC Control Voltage Input. Input from the filtered PWM AGC control signal from the SDARS
channel-decoder IC.
10, 11
IFIN+, IFIN-
Differential First IF Input
16
VOUTANT
Overcurrent-Protected Unregulated DC Supply Output. Provides DC power supply to the
antenna module.
17, 19, 37,
39
18, 20, 36,
38
21, 22, 34,
35
IF2IO-, IF2IO+,
IF2QO+, IF2QO-
IF2II-, IF2II+, IF2QI+,
IF2QI-
IOUT-, IOUT+,
QOUT+, QOUT-
Differential First IF Output. Connect an external SAW filter to the IF output.
Differential Baseband DC Blocking Outputs.
IF2IO- = Inverting in-phase baseband output. AC couple to pin 18.
IF2IO+ = Noninverting in-phase baseband output. AC couple to pin 20.
IF2QO+ = Noninverting quadrature baseband output. AC couple to pin 36.
IF2QO- = Inverting quadrature baseband output. AC couple to pin 38.
Differential Baseband DC Blocking Inputs.
IF2II- = Inverting in-phase baseband input. AC couple to pin 17.
IF2II+ = Noninverting in-phase baseband input. AC couple to pin 19.
IF2QI+ = Noninverting quadrature baseband input. AC couple to pin 37.
IF2QI- = Inverting quadrature baseband input. AC couple to pin 39.
Differential I/Q Baseband Outputs.
IOUT- = Inverting in-phase baseband output.
IOUT+ = Noninverting in-phase baseband output.
QOUT+ = Noninverting quadrature baseband output.
QOUT- = Inverting quadrature baseband output.
24
XTAL
25
REFOUT
Buffered System Clock Output. Provides clock signal to the SDARS channel-decoder IC.
28
LOCK
Digital Logic Output to the System Controller. Indicates the lock status of the internal PLL.
29
CPOUT
32
VCCREG
33
VTUNE
41, 42
I2CA2, I2CA1
43, 44
SCL, SDA
—
Exposed Pad
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Crystal Reference Input
VCO Charge-Pump Output
Regulated Supply Voltage for the VCO
High-Impedance VCO Tuning Input
I2C Input Signals. Define the MAX2140 I2C device address.
I2C-Compatible Programming Input. Connect to an I2C-compatible bus.
Exposed Paddle. Connect to ground.
Maxim Integrated │ 9
MAX2140
Detailed Description
Front End
Complete SDARS Receiver
IF2 access pins, given by the following equation:
fcutoff = 1/(2 x π x R x C) [Hz]
The front end of the MAX2140, which downconverts the
RF signal to IF, is defined from the differential RF inputs
(pins RFIN+ and RFIN-) to the output (pins IFOUT+ and
IFOUT-) to the SAW filter.
where R = 8000Ω, C = external capacitor to be connected.
The front end includes a self-contained analog RF AGC
loop. The engagement threshold of the loop can be
programmed from -35dBm to -15dBm referred to the
RF input in 1dB steps using the RF4–RF0 programming
bits. The time constant of the loop is set externally by the
capacitor connected to RFAGC_C.
Frequency Generation
The image reject first mixer ensures a good image and
half IF rejection.
The front-end gain can be reduced by programming
bits PM3–PM0 over a 22dB range, with a step of 2dB.
This allows the selections of SAW filters with different
insertion loss.
The IF output is nominally 900Ω differentially and requires
pullup inductors to VCC, which can be used as part of the
matching network to the SAW filter impedance.
Back End
The back end, which downconverts the IF signal to
quadrature baseband, is defined from the SAW filter
inputs (pins IFIN+ and IFIN-) to the baseband outputs
(pins IOUT+, IOUT-, QOUT+, QOUT-).
The back end contains an IF AGC loop, which is closed
by the baseband controller. The IF AGC control voltage
is applied at the AGCPWM pin. The gain can be reduced
over 53dB (typ) and exhibits a log-linear characteristic.
Finally, the HPF bit allows an increase to the back-end
gain by 4dB at the slight expense of a degraded inband linearity.
An on-chip VCO and a low-step fractional-N PLL ensure
the necessary frequency generation. The 1st mixer’s LO
is at the VCO frequency itself, while the 2nd mixer’s LO is
the VCO frequency divided by 4 or by 8 (bit D48). Hence,
the two possible IF frequencies for SDARS are 467MHz
and 259MHz. Typical applications are based on 259MHz
IF frequency.
The reference divider path in the PLL can either use an
external crystal and the on-chip crystal oscillator or an
external TCXO that can overdrive the on-chip crystal
oscillator. A reference division ratio of 1 or 2 is set by the
REF bit. The crystal oscillator (or TCXO) signal is available at pin REFOUT. The output is either at the same frequency as the reference signal, or divided by two, based
on the setting of bit RFD.
The VCO main division ratio is set by bits N6–N0 (for the
integer part) and bits F19–F00 (for the fractional part).
The minimum step is below 30Hz, small enough for effective AFC to be implemented by the baseband.
The charge-pump (pin CPOUT) is to be connected to the
VCO tuning input (pin VTUNE) through an appropriate
loop filter.
Overcurrent Protection
The back end also contains individual lowpass filters on
each channel. The lowpass-filter bandwidth is the useful SDARS downconverted bandwidth (6.25MHz). The
lowpass-filter performance is factory trimmed. The bit
IOT switches between the factory-trimmed set and the
control through the I2C-compatible bus using bits B4–B1.
Even when using the factory-trimmed set, the user can
still slightly modify the cutoff frequency (by ±250kHz) by
varying bits LP1/LP0.
This DC function allows external circuitry consuming up to
150mA and connected to the pin VOUTANT to sink current from a VCC line (pin VINANT) through overcurrentprotection circuitry.
Highpass filters are also inserted in the back-end signal
paths. Their purpose is to remove the DC offset. They
are designed for a low corner frequency so as not to
degrade the SDARS content. Their exact cutoff frequency
is set by the external capacitors connected between
This circuit also senses if the current drawn at the pin
VOUTANT is typically larger than 20mA, in which case
the bit AND from the READ byte status goes high (the
purpose is to inform the baseband controller if there is any
device drawing current from VOUTANT).
www.maximintegrated.com
When no overcurrent is present, a low dropout voltage
exists between pins VINANT and VOUTANT. In overcurrent conditions (including short-circuit from VOUTANT to
GND), the current is limited to approximately 300mA and
bit ACP in the READ byte status goes high.
Maxim Integrated │ 10
MAX2140
Complete SDARS Receiver
MAX2140 I2C-Compatible Programming Bit Definition:
Applications Information
BYTE PLLint:
Serial Interface and Control Registers
RFD = reference buffer division: RFD = 0 (/1) and
RFD = 1 (/2)
I2C Bit Description
MAX2140 Programming Bits:
The MAX2140 conforms to the Philips I2C standard,
400kbps (fast mode), and operates as a slave.
The MAX2140 addresses can be selected from three
values, which are determined by the logic state of the two
address-select pins I2CA1 and I2CA2. In all cases, the
MSB is transmitted (and read) first.
N6 to N0 is the binary-written main dividing ratio,
integer part.
BYTE PLLfrac2:
PLS = Reserved: use only PLS = 0
LI1/0 = Reserved: use only LI1 = LI0 = 0
INT = Integer N mode: INT = 1 (fractional) and INT =
0 (integer)
Table 1. MAX2140 Write Address Bytes
AS1
AS0
MSB
Low
High
1
1
0
ADDRESS BYTE
0
0
0
1
LSB
0
High
Low
1
1
0
0
0
1
0
0
High
High
1
1
0
0
0
1
1
0
Table 2. MAX2140 Read Address Bytes
AS1
AS0
MSB
ADDRESS BYTE
LSB
Low
High
1
1
0
0
0
0
1
1
High
Low
1
1
0
0
0
1
0
1
High
High
1
1
0
0
0
1
1
1
Table 3. MAX2140 Write Programming Bits
WRITE-TO MODE
RESET VALUE
ADDR (hex)
MSB
—
C2
C4
C6
1
1
1
PLLint
01010110
00
RFD
N6
N5
N4
N3
N2
N1
N0
PLLfrac2
00011110
01
PLS
LI1
LI0
INT
F19
F18
F17
F16
PLLfrac1
10010000
02
F15
F14
F13
F12
F11
F10
F09
F08
PLLfrac0
01101001
03
F07
F06
F05
F04
F03
F02
F01
F00
Control
01100000
04
REF
CHP
D48
SDR
ANT
SDF
SDB
SDP
CustomGain
00000100
05
RF4
RF3
RF2
RF1
RF0
LP1
LP0
HPF
PMA_Test
00000000
06
PM3
PM2
PM1
PM0
SDX
T2
T1
T0
LPFTrim
00000000
09
0
0
IOT
B4
B3
B2A
B2
B1
Unused2
00000000
08
0
0
0
0
0
0
0
0
Unused1
00000000
07
0
0
0
0
0
0
0
0
Unused0
00000000
10
0
0
0
0
0
0
0
0
Address
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CONTROL BYTE
1
1
1
0
0
0
0
0
0
0
0
0
LSB
0
1
1
1
0
1
0
0
0
Maxim Integrated │ 11
MAX2140
Complete SDARS Receiver
F19 to F16 is the upper-part binary-written main dividing ratio, fractional part multiplied by 220 = 1,048,576.
T2/T1/T0 = test bits: 000 (normal), 001 (main division),
010 (reference division), 011 (reserved),
BYTES PLLfrac1 and PLLfrac0:
100 (CHP low-Z), 101 (CHP source on), 110 (CHP sink
on), 111 (CHP high-Z)
F15 to F0 is the lower-part binary-written main dividing
ratio, fractional part multiplied by 220 = 1,048,576.
BYTE LPFTrim:
BYTE Control:
B4/B3/B2/B2A/B1 = Reserved for LPF trim. All = 0 in
normal operating mode
REF = reference division ratio: REF = 0 (/1) and REF
= 1 (/2)
IOT = LPF corner frequency setup: IOT = 0 (default
factory trim) and IOT = 1 (controllable through I2C).
IOT = 0 in normal operating mode
CHP = charge-pump current: CHP = 0 (0.6mA) and
CHP = 1 (1.2mA)
BYTE Status:
D48 = LO division ratio: D48 = 0 (/4) and D48 = 1 (/8)
SDR = shutdown RF AGC: SDR = 0 (on) and SDR =
1 (shutdown)
RF AGC = RF AGC status: RF AGC = 0 (is not
engaged) and RF AGC = 1 (engaged)
ANT = antenna overcurrent protection: ANT = 0 (on)
and ANT = 1 (shutdown)
ACP = antenna current protection: ACP = 0 (no overcurrent) and ACP = 1 (overcurrent)
SDF = shutdown front end: SDF = 0 (on) and SDF = 1
(shutdown)
AND = antenna detection: ANT = 0 (current < threshold) and ANT = 1 (current > threshold)
SDB = shutdown back end: SDB = 0 (on) and SDB =
1 (shutdown)
LD = lock detect: LD = 0 (out of lock) and LD = 1 (lock)
BYTE Reserved:
SDP = shutdown PLL: SDP = 0 (on) and SDP = 1
(shutdown)
Inactive at this time, all bits are 0
Register configuration for the LO generation
when the comparison frequency = 23.92MHz:
to generate 2078.893333MHz:
BYTE CustomGain:
RF4/RF3/RF2/RF1/RF0 = RF AGC engagement
threshold (dBm): see the RF AGC Settling Time graph
in the Typical Operating Characteristics.
PLLint = 01010110, PLLfrac2
PLLfrac1= 10010000, PLLfrac0
to generate 2067.777778MHz:
LP1/LP0 = change by 250kHz the LPF corner frequency: LP1/LP0 = 10 (nominal), LP1/LP0 = 11 (decrease),
LP1/LP0 = 00 (increase)
=
=
00011110,
01101001
PLLint = 01010110, PLLfrac2 = 00010111,
PLLfrac1 = 00100001, PLLfrac0 = 00000010
to generate 1871.004000 MHz:
HPF = HPF gain increase by 4dB: HPF = 0 (off) and
HPF = 1 (on)
PLLint = 01001110, PLLfrac2 = 00010011,
PLLfrac1 = 10000001, PLLfrac0 = 11111000
to generate 1861.000000MHz:
BYTE PMA_Test:
PM3/PM2/PM1/PM0 = PMA gain cutback (dB): PM3/
PM2/PM1/PM0DEC
PLLint = 01001101, PLLfrac2 = 00011100,
PLLfrac1 = 11010000, PLLfrac0 = 11101000
SDX = shutdown reference buffer: SDX = 0 (on) and
SDX = 1 (shutdown)
Table 4. MAX2140 Read Programming Bits
READ-FROM MODE
RESET VALUE
ADDRESS (hex)
MSB
—
C3
C5
C7
1
1
1
1
1
1
0
0
0
0
0
0
Reserved
00000000
00
0
0
0
0
0
0
0
0
Status
00000000
01
0
0
0
0
RFAGC
ACP
AND
LD
Address
www.maximintegrated.com
CONTROL BYTE
0
0
0
LSB
0
1
1
1
0
1
1
1
1
Maxim Integrated │ 12
MAX2140
Complete SDARS Receiver
I2C Functional Description
Power-Supply Layout
I2C Register Map:
This is the standard I2C protocol. The first byte is either
C6, C4, C2 (hex) dependent on the state of the I2CA_
pins, for a write-to-device operation and either C7, C5, C3
(hex) for a read-from operation (again dependent on the
state of pins I2CA_).
Write Operation:
The first byte is the device address plus the direction bit
(R/W = 0).
The second byte contains the internal address command
of the first address to be accessed.
The third byte is written to the internal register directed by
the command address byte.
The following bytes (if any) are written into successive
internal registers.
The transfer lasts until stop conditions are encountered.
The MAX2140 acknowledges every byte transfer.
Read Operation:
When either address C3, C5, C7 is sent, the MAX2140
sends back first the reserved byte then the status byte.
See Table 5 and Table 6 for read/write register operations.
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at a central VCC
node. The VCC traces branch out from this node, each
going to a separate VCC node in the MAX2140 circuit. At
the end of each trace is a bypass capacitor with impedance to ground less than 1Ω at the frequency of interest.
This arrangement provides local decoupling at each VCC
pin. Use at least one via per bypass capacitor for a lowinductance ground connection.
Matching Network Layout
The layout of a matching network can be very sensitive
to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as
close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and any other planes)
below the matching network components can be used.
On the high-impedance ports (e.g., IF inputs and outputs),
keep traces short to minimize shunt capacitance.
Chip Information
PROCESS: BiCMOS
Layout Issues
The MAX2140 EV kit can be used as a starting point for
layout. For best performance, take into consideration
power-supply issues, as well as the RF, LO, and IF layout.
Table 5. Example: Write Registers 1 to 3 with 0E, D8, 26
START
Device Address Write
(C2, C4, C6)
ACK
Register Address
00
ACK
DATA
0E
ACK DATA D8
ACK
DATA 26
ACK
STOP
Table 6. Example: Read from Status Registers (Sending an NACK Terminate Slave
Transmit Mode
START
Device Address Read
(C3, C5, C7)
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ACK
Read Reserved Register
ACK
Read Status Register
NACK
STOP
Maxim Integrated │ 13
MAX2140
Complete SDARS Receiver
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
44 TQFN-EP
T4477+2
21-0144
90-0127
www.maximintegrated.com
Maxim Integrated │ 14
MAX2140
Complete SDARS Receiver
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/04
Initial release
1
4/04
Updated Electrical Characteristics
PAGES
CHANGED
DESCRIPTION
—
2, 4
2
6/05
Added lead-free package to Ordering Information
1
3
10/05
Updated Electrical Characteristics
2
4
4/15
Made corrections in Absolute Maximum Ratings, Pin Description, and I2C Functional
Description section
2, 10, 14
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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