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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
General Description
Benefits and Features
The MAX22530–MAX22532 are galvanically isolated, 4channel, multiplexed, 12-bit, analog-to-digital converters
(ADC) in the MAXSafe™ family product line. An
integrated, isolated, DC-DC converter powers all fieldside circuitry, and this allows field-side diagnostics even
when no input signal is present.
•
Enable
Robust
Detection
of
Multichannel
Analog/Binary Inputs
• Withstands 3.5kVRMS Isolation for 60s (VISO) for
the SSOP Package
• Withstands 5kVRMS Isolation for 60s (VISO) for
the Wide SOIC Package
• 5.5mm of Creepage and Clearance for 20-pin or
28-pin SSOP Package
• 8mm of Creepage and Clearance for 16-pin Wide
SOIC Package
• Group II CTI Package Material
•
Reduces BOM and Board Space Through High
Integration
• Field-Side Self-Powered with Integrated DC-DC
Supply
• 12-bit, 20ksps Per-Channel ADC
• Programmable Threshold Comparators for each
Channel
• Isolation for both Data and DC-DC Supply
• Integrated 1.8V Reference
•
Increase System “Up Time” and Simplifies System
Design & Maintenance
• Field-Side ADC Functionality Diagnostics
• Field-Side Continuous Power Monitoring
• Communication System Self-Diagnostics
•
Flexible Control and Interface
• Programmable Upper and Lower Input Threshold
Enable Programmable Hysteresis
• Comparator Output (COUT_) Pins for Fastest
Response
• SPI Interface with CRC Option
• Precision Internal Reference ±1% (typ)
• -40°C to +125°C Operating Temperature Range
The MAX22530–MAX22532 family continually digitizes
the input voltage on the field-side of an isolation barrier
and transmits the data across the isolation barrier to the
logic-side of the devices where the magnitude of the
input voltage is compared to programmable thresholds.
The 12-bit ADC core has a sample rate of 20ksps (typ)
per-channel. ADC data is available through the SPI
interface either directly or filtered. Filtering averages the
most recent 4 readings depending on the setting.
Each input has a comparator with programmable high
and low thresholds, and an interrupt is asserted when
any input crosses its programmed level based on the
mode setting. The comparator output pin (COUT_) is
high when the input voltage is above the upper threshold
and low when it is below the lower threshold in digital
input mode. Response time of the comparator to an input
change is less than 75ms (typ) with filtering disabled.
With filtering enabled, the comparator uses the moving
average of the last 4 ADC readings.
The MAX22530 in a 16-pin wide SOIC package provides
8mm of creepage and clearance, and 5kVRMS isolation.
The MAX22531 in a 20-pin SSOP package and the
MAX22532 in a 28-pin SSOP package, both provide
5.5mm of creepage and clearance, and 3.5kVRMS
isolation. All package material has a minimum
comparative tracking index (CTI) of 400, which gives it a
group II rating in creepage tables.
All devices are rated for operation at ambient
temperatures between -40°C to +125°C.
Applications
•
•
•
•
•
High-Voltage Binary Input
Substation Automation
Distribution Automation
Process Automation
Motion Control
19-100989; Rev 0; 3/21
Safety Regulatory Approvals (Pending)
•
•
UL According to UL1577
cUL According to CSA Bulletin 5A
Ordering Information appears at the end of the data
sheet.
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Four-Channel Isolated ADC
NOTE *:
COUT1 AND COUT2 ARE FOR MAX22531
COUT1, COUT2, COUT3, AND COUT4 ARE FOR MAX22532
REF
VDDL = 3.3V
MAX22530/MAX22531/MAX22532
INPUT
REFERENCE
VREF = 1.8V
COUT_*
AIN1
AIN2
INT
12-BIT ADC
CS
AIN3
LOGIC AND SPI
INTERFACE
AIN4
AGND
MCU
SCLK
SDI
LOGIC
CONTROL
SDO
VDDPL = 3.3V
µPOWER ISOLATED
DC-DC
VDDF
CDDF
GNDF
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GNDL
Maxim Integrated | 2
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Absolute Maximum Ratings
VDDL to GNDL........................................................ -0.3V to 6V
VDDPL to GNDL...................................................... -0.3V to 6V
SDI,
,
(To GNDL) ........................................ -0.3V to 6V
SDO, COUT_ (To GNDL) ..................... -0.3V to (VDDL + 0.3V)
VDDF to GNDF ....................................................... -0.3V to 6V
REF, AIN_ to AGND ............................................... -0.3V to 2V
AGND to GNDF ................................................... -0.3V to 0.3V
Continuous Power Dissipation (Multilayer Board) (TA =
+70°C, derate 14.1mW/°C above +70°C. 16-pin Wide SOIC)
.................................................................................. 1127mW
Continuous Power Dissipation (Multilayer Board) (TA =
+70°C, derate 11.9mW/°C above +70°C. 20-pin SSOP)
..................................................................................... 964mW
Continuous Power Dissipation (Multilayer Board) (TA =
+70°C, derate 6.96mW/°C above +70°C. 28-pin SSOP)
................................................................................ 556.72mW
Operating Temperature Range ...................... -40°C to +125°C
Maximum Junction Temperature .................................. +150°C
Storage Temperature Range ......................... -65°C to +150°C
Lead Temperature (soldering, 10s) .............................. +300°C
Soldering Temperature (reflow).................................... +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
16 W SOIC
Package Code
W16MS+14
Outline Number
21-0042
Land Pattern Number
90-0107
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA)
68.8°C/W
Junction-to-Case Thermal Resistance (θJC)
41.6°C/W
20 SSOP
Package Code
A20MS+7
Outline Number
21-0056
Land Pattern Number
90-0094
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA)
216°C/W
Junction-to-Case Thermal Resistance (θJC)
49°C/W
28 SSOP
Package Code
A28MS+5
Outline Number
21-0056
Land Pattern Number
90-0095
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA)
143.70°C/W
Junction-to-Case Thermal Resistance (θJC)
47.90°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
www.maximintegrated.com
Maxim Integrated | 3
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDDL - VGNDL = 1.71V to 5.5V, VDDPL - VGNDL = 3.0V to 5.5V, CDDF = 1μF, CREF = 1μF. Limits are 100% tested at TA = +25°C.
Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note
1, Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
1
2.5
mA
1.6
1.66
V
LOGIC-SIDE POWER SUPPLY
Logic Power Supply
VDDL
Logic Supply Current
IDDL
Logic-Supply UVLO
Threshold
Logic-Supply UVLO
Hysteresis
VDDL_UVLO
1.5
VDDL_UHYS
Logic Power-Up Time
tLPU
Isolated DC-DC Supply
Isolated DC-DC Supply
Current
Isolated DC-DC Supply
UVLO Threshold
Isolated DC-DC Supply
UVLO Hysteresis
1.71
50
Valid SPI access
VDDPL
IDDPL
3.0
VDDPL = 3.3V
VDDPL_UVLO
2.7
VDDPL_UHYS
mV
0.6
1
ms
3.3
5.5
V
7
10
mA
2.8
2.95
V
100
mV
FIELD-SIDE PARAMETERS
VDDF Supply Voltage
Isolated DC-DC Power
Up Time
VDDF
tPWRUP
Internally generated
2.7
3.1
CDDF = 1 µF
5.5
V
10
ms
ADC AND COMPARATOR
Input-Voltage Range
VAIN
0
ADC Resolution
1.8
12
V
Bits
GE
VAIN = 98% VREF, excluding offset error
and reference error
-0.2
+0.2
%FS
Offset Error
OE
VAIN = 2% VREF, offset calculated
-0.1
+0.1
%FS
Differential Nonlinearity
DNL
±1.5
LSB
Integral Nonlinearity
INL
±2.0
LSB
+600
nA
22
ksps
Gain Error
Input-Leakage Current
Included in the gain and offset window
INLKG
-600
Throughput per Channel
18
AIN# step input to COUT transition (Note
3)
AIN# step input to COUT transition (Note
3)
Latency (No filtering)
Latency (4 Readings)
CMTI
(Note 4)
20
75
µs
300
µs
50
kV/µs
INTERNAL VOLTAGE REFERENCE
Nominal Output Voltage
VREF
VREF_TOL
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TA = +25°C
1.78
TA = -25°C to +85°C
-1.5
1.80
1.82
V
+1.5
%
Maxim Integrated | 4
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
(VDDL - VGNDL = 1.71V to 5.5V, VDDPL - VGNDL = 3.0V to 5.5V, CDDF = 1μF, CREF = 1μF. Limits are 100% tested at TA = +25°C.
Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note
1, Note 2)
PARAMETER
Output-Voltage
Accuracy
Output-Voltage
Temperature Drift
SYMBOL
CONDITIONS
TA = -40°C to +125°C
MAX
, COUT,
VIH
SCLK, SDI,
Input Logic-Low Voltage
VIL
SCLK, SDI,
Input Hysteresis
VHYST
SCLK, SDI,
Input Leakage Current
IIN_LKG
SCLK, SDI,
CIN
SCLK, SDI,
f = 1MHz
VOH
SDO, COUT, sourcing 4mA
VOL
SDO, COUT,
IOLKG
, SDO
UNITS
+2
50
Input Logic-High
Voltage
Output Logic-High
Voltage
Output Logic-Low
Voltage
Output High-Impedance
Leakage Current
TYP
-2
TCVOUT
LOGIC INTERFACE (SCLK, SDI, SDO,
Input Capacitance
MIN
ppm/°C
)
0.7 x
VDDL
V
0.3 x
VDDL
50
-1
,
V
mV
+1
2
µA
pF
VDDL0.4
, sinking 4mA
-1
V
0.4
V
+1
µA
10
MHz
SPI TIMING CHARACTERISTICS
SCLK Clock Frequency
fSCLK
SCLK Clock Period
tSCLK
100
ns
SCLK Pulse-Width High
tSCLKH
40
ns
SCLK Pulse-Width Low
tSCLKL
40
ns
tCS(LEAD)
20
ns
tCS(LAQ)
80
ns
SDI Hold Time
tDINH
20
ns
SDI Setup Time
tDINSU
20
ns
tDOUT(DIS)
40
ns
Fall-to-SCLK Rise
Time
SCLK Fall-toRise
Time
SDO Disable Time (
Rising to SDO ThreeState)
Output Data
Propagation Delay
Inter-Access Gap
tDO
tIAG
50
920
ns
ns
Note 1: All devices are 100% production tested at TA = +25C. Specifications for all temperature limits are guaranteed by design.
Note 2: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their
respective ground (GNDL or GNDF), unless otherwise noted.
Note 3: Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and COUTHI_ (register
address 0x9 to 0xC) upper threshold (THU) is set to maximum value (0xFFFh). Latency is the delay from the step at the
ADC input to the digital comparator output.
Note 4: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to
both rising and falling common-mode voltage edges. Tested with the transient generator connected between GNDF and
GNDL (VCM = 1000V).
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Maxim Integrated | 5
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Timing Diagram
tCSH0 tCSS0
tDS
t DH
tCL
tCH
tCP
t CSS1
t CSW
CS
SCLK
1
2
3
4
5
6
7
8
9
10
30
31
32
SDI
A5
A4
A3
A2
A1
A0
A0
W
B
D15
C2
C1
C0
NOTE B: BURST BIT
HIGH-Z
SDO
Figure 1. SPI Write Timing Diagram (with CRC Enabled)
tCSH0 tCSS0
tDS
tDH
tCL
tCH
tCP
tCSS1
tCSW
CS
SCLK
1
2
3
4
5
6
7
8
SDI
A5
A4
A3
A2
A1
A0
R
B
9
tDOT
HIGH-Z
SDO
10
N+6
N+7
NOTE B: BURST BIT
D15
D14
N+8
tDOH
C2
C1
tDOD
C0
HIGH-Z
Figure 2. SPI Read Timing Diagram (with CRC Enabled)
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Maxim Integrated | 6
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Insulation Characteristics
16-pin Wide SOIC
PARAMETER
SYMBOL
CONDITIONS
VALUE
UNITS
VPR
Method B1 = VIORM x 1.875
(t = 1s, partial discharge < 5pC)
2250
VP
VIORM
(Note 5)
1200
VP
VIOWM
Continuous RMS voltage (Note 5)
848
VRMS
VIOTM
(Note 5)
7000
VP
Maximum WithstandingIsolation Voltage
VISO
fSW = 60Hz, duration = 60s
(Note 5, Note 6)
5000
VRMS
Maximum Surge-Isolation
Voltage
VIOSM
Basic Insulation, 1.2/50μs pulse per
IEC61000-4-5
10000
VP
VIO = 500V, TA = 25°C
> 1012
VIO = 500V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500V, TS = 150°C
> 109
Partial Discharge Test Voltage
Maximum Repetitive-PeakIsolation Voltage
Maximum Working-Isolation
Voltage
Maximum Transient-Isolation
Voltage
Insulation Resistance
RIO
Barrier Capacitance Field Sideto-Logic Side
CIO
Minimum Creepage Distance
Minimum Clearance Distance
2
pF
CPG
8
mm
CLR
8
mm
Distance through insulation
0.015
mm
Material Group I (IEC 60112)
> 400
Internal Clearance
Comparative Tracking Index
CTI
fSW = 1MHz (Note 7)
Ω
Climate Category
40/125/21
Pollution Degree
(DIN VDE 0110, Table 1)
2
20-pin and 28-pin SSOP
PARAMETER
Partial Discharge Test Voltage
Maximum Repetitive-PeakIsolation Voltage
Maximum Working-Isolation
Voltage
Maximum Transient-Isolation
Voltage
Maximum WithstandingIsolation Voltage
Maximum Surge-Isolation
Voltage
Insulation Resistance
Barrier Capacitance Field Sideto-Logic Side
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SYMBOL
CONDITIONS
VALUE
UNITS
VPR
Method B1 = VIORM x 1.875
(t = 1s, partial discharge < 5pC)
1182
VP
VIORM
(Note 5)
630
VP
VIOWM
Continuous RMS voltage (Note 5)
445
VRMS
VIOTM
(Note 5)
5300
VP
3750
VRMS
10000
VP
VISO
VIOSM
RIO
CIO
fSW = 60Hz, duration = 60s
(Note 5, Note 6)
Basic Insulation, 1.2/50μs pulse per
IEC61000-4-5
VIO = 500V, TA = 25°C
> 1012
VIO = 500V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500V, TS = 150°C
> 109
fSW = 1MHz (Note 7)
2
Ω
pF
Maxim Integrated | 7
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Minimum Creepage Distance
CPG
5.5
mm
Minimum Clearance Distance
CLR
5.5
mm
Distance through insulation
0.015
mm
Material Group I (IEC 60112)
> 400
Internal Clearance
Comparative Tracking Index
CTI
Climate Category
40/125/21
Pollution Degree
(DIN VDE 0110, Table 1)
2
Note 5:
VISO, VIOWM, and VIORM are defined by the IEC 60747-5-5 standard.
Note 6:
Product is qualified at VISO for 60s and 100% production tested at 120% of VISO for 1s.
Note 7:
Capacitance is measured with all pins on field-side and logic-side tied together.
ESD and Transient Immunity Characteristics
PARAMETER
Surge
EFT
SYMBOL
VALUE (TYP)
AIN_ to GNDF
≥ 60kΩ input resistor, IEC 61000-4-5 1.2µs/50µs pulse
±7.2
AIN_ to AIN_
≥ 60kΩ input resistors, IEC 61000-4-5 1.2µs/50µs pulse
±4
AIN_ to GNDF
AIN_ Contact
ESD
CONDITIONS
AIN_ Air Gap
Any pin to Any pin
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Capacitive clamp to input cable pair (AIN_- GNDF) with 60kΩ
input divider resistor connected AIN_- GNDF, 1nF Y-CAP to
earth, IEC61000-4-4
≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC
61000-4-2
≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC
61000-4-2
Human Body Model
±4
UNITS
kV
kV
±8
±15
kV
±3
Maxim Integrated | 8
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Typical Operating Characteristics
(VDDL - VGNDL = 3.3V, VDDPL - VGNDL = 3.3V, CDDF = 1μF, CREF = 1μF, TA = +25°C, unless otherwise noted.)
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Maxim Integrated | 9
MAX22530–MAX22532
www.maximintegrated.com
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Maxim Integrated | 10
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Pin Configurations
TOP VIEW
REF
1
AGND
2
16 INT
15 CS
MAX22530
AIN1
3
AIN2
4
13 SDI
AIN3
5
12 SDO
14 SCLK
AIN4
6
11 VDDL
VDDF
7
10 VDDPL
GNDF
8
9
GNDL
16 W SOIC
TOP VIEW
REF
+
1
20 INT
AGND 2
AIN1
3
AIN2
4
19 CS
18 SCLK
MAX22531
17 SDI
16 SDO
AGND 5
AIN3
6
15 COUT2
AIN4
7
14 COUT1
13 VDDL
AGND 8
VDDF
12 VDDPL
9
11 GNDL
GNDF 10
20 SSOP
TOP VIEW
+
GNDF
1
NC
2
28 GNDL
27 NC
REF
3
26 INT
AGND
4
25 CS
AIN1
5
AGND
6
AIN2
7
22 SDO
AGND
8
21 COUT4
AIN3
9
20 COUT3
AGND 10
19 COUT2
AIN4 11
18 COUT1
MAX22532
24 SCLK
23 SDI
AGND 12
17 VDDL
VDDF 13
16 VDDPL
GNDF 14
15 GNDL
28 SSOP
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Maxim Integrated | 11
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Pin Descriptions
PIN
MAX22530 MAX22531 MAX22532
NAME
REF
SUPPLY
FUNCTION
POWER
Output of the DC-DC Converter. Bypass to GNDF with
1μF||0.01μF capacitors. The 0.01μF capacitor should be placed
as close as possible to the pin.
Field-Side Ground for Everything Except the ADC Front-End
and Voltage Reference
Power Input for the Logic-Side. Bypass with 1μF||0.01μF
capacitors to GNDL.
Power Input for the Isolated DC-DC Converter. The DC-DC
converter powers the field-side. Bypass with 1μF||0.01μF
capacitors to GNDL.
7
9
13
VDDF
8
10
1, 14
GNDF
11
13
17
VDDL
10
12
16
VDDPL
9
11
15, 28
GNDL
–
–
2, 27
N.C.
Not Connected
1
1
3
REF
External Filter Capacitor. Connect a 1μF||0.01μF capacitor from
REF to AGND.
VDDF
2
2
4
AGND
Analog Ground Reference for AIN_ and REF
VDDF
3
3
5
AIN1
4
4
7
AIN2
5
6
9
AIN3
6
7
11
AIN4
-
5, 8
6, 8, 10,
12
AGND
12
16
22
13
17
23
VDDF
VDDL
Power and Signal Ground for All Logic-Side Pins
ANALOG
Analog Input Channel 1 The ADC measures the voltage on this
pin with respect to AGND
Analog Input Channel 2. The ADC measures the voltage on this
pin with respect to AGND.
Analog Input Channel 3. The ADC measures the voltage on this
pin with respect to AGND.
Analog Input Channel 4. The ADC measures the voltage on this
pin with respect to AGND.
VDDF
VDDF
VDDF
VDDF
Analog Ground Reference for AIN_ and REF
VDDF
SDO
Serial Data Out for SPI Interface (MISO)
VDDL
SDI
Serial Data Input for SPI Interface (MOSI)
VDDL
Serial Clock for SPI Interface
VDDL
DIGITAL
14
18
24
SCLK
15
19
25
-
14
18
COUT1
-
15
19
COUT2
-
-
20
COUT3
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Chip Select for SPI Interface. Assert low to enable SPI functions
and SDO. SDO and COUT_ are high impedance when
is
high.
Digital Comparator Output. COUT1 is high when AIN1 is above
the upper threshold (COUTHI1) and low when AIN1 is below the
lower threshold (COUTLO1) in digital input mode. See the
Digital Status Mode section.
Digital Comparator Output. COUT2 is high when AIN2 is above
the upper threshold (COUTHI2) and low when AIN2 is below the
lower threshold (COUTLO2) in digital input mode. See the
Digital Status Mode section.
Digital Comparator Output. COUT3 is high when AIN3 is above
the upper threshold (COUTHI3) and low when AIN3 is below the
lower threshold (COUTLO3) in digital input mode. See the
Digital Status Mode section.
VDDL
VDDL
VDDL
VDDL
Maxim Integrated | 12
MAX22530–MAX22532
-
-
21
16
20
26
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Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
COUT4
Digital Comparator Output. COUT4 is high when AIN4 is above
the upper threshold (COUTHI4) and low when AIN4 is below the
lower threshold (COUTLO4) in digital input mode. See the
Digital Status Mode section.
Open-Drain Output that Asserts Low During a Number of
Different Error Conditions. The cause of the error is latched in
the INTERRUPT STATUS register. See the Diagnostic and
Fault Reporting Features section for details on clearing
.
VDDL
VDDL
Maxim Integrated | 13
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Functional Diagrams
MAX22530/MAX22531/MAX22532
REF
VDDL
REFERENCE
VREF = 1.8V
COUT4*
COUT3*
COUT2*
AIN1
COUT1*
AIN2
INT
12-BIT ADC
AIN3
LOGIC AND SPI
INTERFACE
AIN4
CS
SCLK
SDI
LOGIC CONTROL
SDO
AGND
VDDF
VDDPL
µPOWER ISOLATED DC-DC
AGND
GNDF
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NOTE *:
COUT1 AND COUT2 ARE FOR MAX22531
COUT1, COUT2, COUT3, AND COUT4 ARE FOR MAX22532
GNDL
Maxim Integrated | 14
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Detailed Description
The MAX22530–MAX22532 family consists up of 12-bit, 4-channel ADCs with either a 3.5kVRMS or 5kVRMS isolated SPI
interface depending upon the package option. Additional features include comparators with programmable upper and
lower threshold levels. The ADC and all field-side circuits are powered by an integrated, isolated, DC-DC converter that
allows field-side functionality to be verified even when there is no input signal or other field-side supply. This makes the
MAX22530–MAX22532 family ideally suited for high-density, multirange, group-isolated, binary-input modules, and
provides a complete solution to any system that requires monitoring inputs without a separate isolated power supply.
ADC
The devices’ ADC employs a 12-bit SAR architecture with a nominal sampling rate of 20ksps per channel and has an
input-voltage range of 0V to +1.8V with respect to AGND. After power-up, the ADC runs continually at the nominal
sampling rate. The 12-bit unfiltered ADC reading and filtered ADC reading are both available through the SPI interface.
Filtering averages the most recent 4 readings. For rapid response without requiring the SPI interface, the MAX22530–
MAX22532 family provides the output of a digital comparator (COUT_) that compares user-programmed thresholds to
the ADC reading or the filtered ADC reading. The comparator has two thresholds, the comparator output is high when the
input voltage is above the upper threshold and low when it is below the lower threshold in default digital-input mode. The
response time of the comparator is less than 75μs (typ) with filtering disabled. With filtering enabled, the comparator uses
the moving average of the last 4 ADC readings for a response time of 300μs (typ). The comparator output pin (COUT_)
changes based on the latest ADC reading, the upper threshold (COTHI_[11:0], register address 0x9, 0xA, 0xB and 0xC)
and the lower threshold (COTLO_[11:0], register address 0x10, 0xD, 0xE and 0xF) according to the CO_MODE_ setting.
If enabled, the interrupt pin
asserts whenever COUT_ changes.
Internal Voltage Reference
The MAX22530-MAX22532 family features a precision internal voltage reference. The 1.8V internal reference has a
maximum error of ±2% over the entire operating temperature range. The MAX22530-MAX22532 family is not intended to
be used with an external voltage reference.
Input Comparator with Programmable Thresholds and Two Operational Modes (CO_MODE)
The input signal can be recognized in two different ways; one is the digital input mode and the other is the digital status
mode. The mode of operation is set for each input channel in the COUTHI_ registers (address 0x9, 0xA, 0xB and 0xC)
with the CO_MODE bits.
Digital Input Mode
The Digital input mode (see Figure 3) treats the digitized input (from the ADC) as a digital signal of “1” or “0” with hysteresis
where the values for “1” and “0” are set by the upper- and lower-limit thresholds programmed into registers COUTHI_ and
COUTLO_ (see COUT_BLK in register map).
1. Upper limit and lower limit are used as hysteresis (like a Schmitt trigger input).
2. The status of COUT_ changes to “1” only when the ADC (or FADC) value crosses over the upper limit during a lowto-high transition, and to “0” when it crosses below the lower limit during a high-to-low transition.
3. The status of COUT_ can be “0” or “1” between the lower and upper limits based on the previous status.
ANALOG INPUT/
ADC1 OUTPUT
COTHI1
COTLO1
COUT1
0
1
0
1
0
NOTE: IN PRACTICE, THERE IS A DELAY BETWEEN ANALOG INPUT AND DIGITIZED ADC OUTPUT (CONVERSION TIME).
Figure 3. Digital Input Mode
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Digital Status Mode
The Digital status mode (see Figure 4) monitors the input in “Normal” status vs. “OVLO/UVLO” status:
1. The status of COUT_ is “0” when the digitized output of ADC (or FADC) is between the lower limit and the upper limit.
2. The status of COUT_ is “1” when the digitized output of ADC (or FADC) is higher than the upper limit or lower than the
lower limit.
ANALOG INPUT/
ADC1 OUTPUT
COTHI1
COTLO1
COUT1
1
0
1
0
1
0
1
0
1
0
1
NOTE: THERE IS A DELAY BETWEEN ANALOG INPUT AND DIGITIZED ADC OUTPUT (CONVERSION TIME).
Figure 4. Digital Status Mode
Isolated Power and Data Transfer
A simplified view of the isolated power and data transfer sections is shown in the Functional Diagram. The logic-side
supply VDDPL powers an integrated, inductively coupled DC-DC converter that generates a nominal field supply VDDF of
3.1V with just enough output current to power the field-side of the MAX22530–MAX22532 family. Note that VDDF is not
intended to power an external load.
Serial data is transferred by capacitively-isolated differential transceivers. To verify reliable communication through the
isolation barrier, a cyclic redundancy check (8-bit CRC) is embedded in the transmitted serial data streams. If a CRC fails,
the data is discarded, and no action is taken. If CRC fails, the SPICRC bits in the INTERRUPT STATUS register is set
and
is asserted if the ENCRC interrupt enable bit is set in the INTERRUPT ENABLE register.
Configuration and Monitoring
An SPI interface is used for transferring configuration, control, and diagnostic data as well as ADC readings between a
host (FPGA or microcontroller) and the MAX22530–MAX22532. The interface consists of four signals: SCLK,
, SDI
and SDO, and does not support daisy-chain configuration. An optional CRC improves reliability in the data communication
to and from the MAX22530–MAX22532. This feature, disabled by default after reset or power-up, can be enabled or
disabled at any time through the SPI interface. When enabled, it affects both read and write SPI transactions.
SPI Interface
SPI communication includes the following features (see Table 3):
•
•
•
Serial clock up to 10MHz
CRC function uses SMBus polynomial: C(x) = (x8 + x2 + x1 + 1) that is added if the ENCRC bit is set in the CONTROL
register.
Burst Mode for reading multiple registers
The functionality of each SPI pin can be summarized as follows:
•
Serial Clock (SCLK): Input for the master serial clock signal. The clock signal determines the speed of the data transfer
(up to 10MHz max). All receiving and transmitting is done synchronous to this clock.
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MAX22530–MAX22532
•
•
•
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Chip Select ( ): The
input enables the SPI interface. A logic-high on
forces SDO to high-impedance and any
SCLK transitions are ignored. During a
logic-low state, data is transferred on the edges of SCLK.
Serial Input (SDI): SDI or MOSI is the serial input port of the SPI shift register and data is clocked LSB first into the
shift register on the rising edge of SCLK. To provide sufficient setup/hold time, the driver should have SDI data
transitions at the falling edge of SCLK. On the rising edge of
, the input data is latched into the internal registers.
Serial Output (SDO): SDO or MISO is the serial output port of the SPI shift register, and is in a high-impedance state
until the
pin goes to a logic-low state and at the end of the BURST data bit. Data is clocked LSB first out of the
shift register on the falling edge of SCLK.
The MAX22530–MAX22532 offers burst and single-register SPI transactions. Single-register SPI transactions can be
used to access any register address and are 3-bytes long without CRC and 4-bytes long with CRC. The CRC byte is
calculated on the previous 3 bytes. The single-register SPI transaction format consists of a 6-bit register address, a
read/write bit, a burst mode bit, 16 bits of payload, and the optional CRC byte, as illustrated in Table 1 for write transaction
and in Table 2 for read transactions. Refer to Figure 1 and Figure 2 for SPI write and read timing diagrams.
Table 1. SPI Write Command
HEADER
A[5:0]
W/
=1
PAYLOAD
BURST = 0
Data D[15:0]
CRC (optional), C[7:0]
Note: The BURST bit in the header is ignored in SPI write transactions
Table 2. SPI Read Command
HEADER
A[5:0]
W/
=0
PAYLOAD
BURST = 0
Data D[15:0]
CRC (optional), C[7:0]
Burst mode can only be used for reading the filtered or unfiltered ADC data registers and the interrupt status register in
one SPI transaction. Burst SPI transactions are 11-bytes long without CRC and 12-bytes long with CRC. The CRC byte
is calculated on the previous 11 bytes. The burst SPI transaction format consists of the 6-bit register address for ADC1
or FADC1, a read/write bit, a burst mode bit, the contents of the four filtered or unfiltered ADC registers depending on the
6-bit address entered, the content of the interrupt status register, and the optional CRC byte, as illustrated in Table 3. The
burst bit is ignored for all other register addresses during read transactions.
The MAX22530–MAX22532 knows that it should receive 24, 32, 88, or 94 bits depending on the combination of CRC
setting and burst mode. If more SPI cycles than expected are received, the transaction is executed. If fewer SPI cycles
than expected are received, the transaction fails.
Table 3. SPI Burst Read Command
HEADER
A[5:0]
•
•
W/
=0
BURST = 1
PAYLOAD
F/ADC_1
D[15:0]
F/ADC_2
D[15:0]
F/ADC_3
D[15:0]
F/ADC_4
D[15:0]
INTERRUPT
STATUS[15:0]
8-bits CRC (optional),
C[7:0]
For burst read transactions, if Address A[5:0] is 0x01 (ADC_1), the data read is the unfiltered ADC data. If Address
A[5:0] is 0x05 (FADC_1), the data read is the filtered ADC data.
The burst bit is ignored for all other register addresses during read transactions.
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Diagnostic and Fault Reporting Features
The MAX22530–MAX22532 continuously monitor multiple possible fault conditions, and a hardware alert is provided
through the open drain
pin, which asserts low when an enabled fault is detected. The possible faults are: ADC
functionality error, SPI framing error, CRC errors from SPI communications, and loss of internal isolated data stream.
The bits in the INTERRUPT ENABLE (0x13) register determine how the
output responds to the various error
conditions and asserts the
output if the corresponding bit is enabled in the INTERRUPT ENABLE register.
If the corresponding bit in the INTERRUPT ENABLE register is not set, when an error is flagged,
is not asserted, but
the bit in the INTERRUPT STATUS register (0x12) is still latched and remains set until the register is read, which
automatically clears all bits in the INTERRUPT STATUS register. Note that if a fault condition still exists when the register
is read, the cleared fault bit is immediately set again.
In a typical application,
triggers an interrupt routine in the microcontroller or FPGA, which reads the INTERRUPT
STATUS register to determine the cause of the interrupt.
ADC Functionality Error
ADC functionality is checked by looking for changes in the ADC output. To ensure that a change should have occurred,
a special test measurement is made while injecting a small current at the input of the ADC. This special measurement
used for ADC functionality verification is interleaved between normal measurements and does not affect the ADC
sampling time. If the ADC reading does not change, or data is outside of the limits for at least four frames, an ADC
functional failure is declared and bit FADC (bit 11) in the INTERRUPT STATUS (0x12) register is set.
SPI Framing Error
After
transitions from low to high, if the number of bits clocked in while
was low is not 24, 32, 88, or 96 bits, an SPI
framing error is declared and bit SPIFRM (bit 9) in the INTERRUPT STATUS (0x12) register is set. The instruction in the
SPI shift register is not decoded and no register value is changed.
Loss of Data Stream
The field-side sends ADC data across the isolation barrier to the logic-side every 50μs except for the startup period. Fieldside loss-of-data (FLD) interrupts are masked for the first 100ms of operation after power-on or reset, and after that if an
internal monitoring signal is not received, an error is flagged. If the periodic field-side data is not received, a loss-of-datastream fault is declared and bit FLD (bit 10) in the INTERRUPT STATUS (0x12) register is set. It is possible to recover
from a loss of data stream fault by asserting a hard reset using bit REST (bit 0) in the CONTROL (0x14) register, which
causes field-side power to be rebooted and returns all of the registers to their default state, requiring the MAX22530–
MAX22532 to go through the startup configuration process.
CRC Error from Internal Communication
Internal communication across the isolation barrier includes a CRC code to ensure that corrupt data does not cause
system problems. If the CRC indicates an error, the received data is discarded. If six consecutive CRCs fail, a CRC fault
is declared and bit SPICRC (bit 8) in the INTERRUPT STATUS (0x12) register is set.
Control Modes
The CONTROL (0x14) register includes a number of bits which the host can program and which take immediate effect on
the device.
Hardware Reset Control
If the control bit REST is set to 1, the field-side power supply is shut down and restarted, and the main reset input to the
digital core is asserted, resulting in setting the digital core back to its power-on reset state and all registers are brought
back to their default values, including the control bit, REST.
Software Reset Control
The software reset is initiated by setting bit SRES to 1. Unlike the hardware reset that is effective immediately after
assertion, SRES takes affect after the completion of the frame, during which it is asserted. At that time, the digital core is
reset and all registers are brought back to their default values. The field-side power supply is not affected by SRES.
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Clear POR Control
The CLRPOR bit can be set to 1 to clear the ‘Wake Up from Power-On Reset’ POR bit in the PROD_ID (0x00) register.
Note that a hardware reset (REST) causes the POR bit to be reasserted, but a software reset, SRES, has no effect on
the status bit POR.
DISPWR Control
Setting bit DISPWR to 1 disables field-side power (VDDF), effectively stopping ADC conversions. The logic-side or digital
core is not affected.
Filter Clearing Control
The control bits FLT_CLR_1 to FLT_CLR_4 can be set to 1 to clear the ADC moving average filter for that specific channel
at the start of the frame following this assertion. Once the filter reset operation takes place the control bits remain set at
0 for normal operation.
Comparator Limit Control
The control bit ECOM can be set to 1 to apply the settings of COUTHI1 and COUTLO1 to all four channels regardless of
what values are programmed in the high and low threshold registers for the other three channels. Setting the ECOM bit
to 1 does not change what the host reads back from the threshold registers for channels 2 to 4.
CRC Control
If control bit ENCRC is 0, CRC functionality is not enabled, and SPI transactions are 24-bits in length. But if control bit
ENCRC is 1, CRC functionality is enabled making each SPI transaction 32-bits in length. At power-on, or after a hardware
or software reset, the default CRC is disabled. All SPI transactions following the write transaction that sets ENCRC must
have the 8-bit CRC suffix.
Interrupts
In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or
FPGA) by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT
ENABLE (0x13) register to assert the interrupt pin,
. The ADC core continually digitizes the inputs for the four channels
in succession, and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit
15), or by enabling the EOC to be shown on the
every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the
INTERRUPT STATUS (0x12) register is set to 1 and causes the
pin to be asserted for a duration of 10µs at the end
of channel 4 ADC (ADC_4) conversion. After 10µs the
pin is deasserted whether the INTERRUPT STATUS register
is read or not.
At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the
comparator status and comparator-related interrupts.
If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers
(ADC1 to ADC4, or FADC1 to FADC4. See ADC_STATUS BLK in register map section) in addition to the INTERRUPT
STATUS register. Bit 15 in each ADC_ register is the ADCs bit. If ADCs is 0 the register contents have been updated
(new conversion data) since the last read operation. By performing a data read operation, the ADCs bit is automatically
set to 1, indicating the data has not been refreshed since the last read operation. Upon receiving the
signal, the host
interrupt service routine can perform a burst read, which automatically clears the bits in the INTERRUPT STATUS register,
thereby deasserting the
pin.
If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to
being asserted) then data loss occurs, and the register contents are overwritten with new conversion data.
If the ADC_ data register refreshing event occurs while
is low (i.e., during an SPI transaction), the data refreshing
event is postponed until the deassertion of
. This scheme eliminates possible data corruption and data loss. However,
it assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the
duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_
data registers during the 50µs following the assertion of the end-of-conversion interrupt.
The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the
unfiltered (ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE
(bit 15) and CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
operation (Digital Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects
between unfiltered ADC data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel
can be read from register COUT STATUS (0x11).
In addition to the diagnostics bits, the comparator outputs can be programmed to assert the
pin if enabled. If a positive
edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit
(COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_
data is lower than the lower limit (COUTLO_).
Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is
changed during frame N, the new threshold value is used starting frame N+1.
To clear an interrupt and deactivate the
pin, the host must perform a read operation of the INTERRUPT STATUS
register. All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the CRC is
properly decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared fault bit
is immediately set again.
If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while
the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.
However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets
asserted while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This
means that the host should read the interrupt register upon assertion of
, or poll the interrupt registers several times
per conversion cycles to avoid missing interrupts.
In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or
FPGA) by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT
ENABLE (0x13) register to assert the interrupt pin,
. The ADC core continually digitizes the inputs for the four channels
in succession, and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit
15), or by enabling the EOC to be shown on the
every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the
INTERRUPT STATUS (0x12) register is set to 1 and causes the
pin to be asserted for a duration of 10µs at the end
of channel 4 ADC (ADC_4) conversion. After 10µs the
pin is deasserted whether the INTERRUPT STATUS register
is read or not.
At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the
comparator status and comparator-related interrupts.
If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers
(ADC1 to ADC4, or FADC1 to FADC4) in addition to the INTERRUPT STATUS register. Bit 15 in each ADC_ register is
the ADCs bit. If ADCs is 0 the register contents have been updated (new conversion data) since the last read operation.
By performing a data read operation, the ADCs bit is automatically set to 1, indicating the data has not been refreshed
since the last read operation. Upon receiving the
signal, the host interrupt service routine can perform a burst read,
which automatically clears the bits in the INTERRUPT STATUS register, thereby deasserting the
pin.
If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to
being asserted) then data loss occurs, and the register contents are overwritten with new conversion data.
If the ADC_ data register refreshing event occurs while
is low (i.e., during an SPI transaction), the data refreshing
event is postponed until the deassertion of
. This scheme eliminates possible data corruption and data loss. However,
it assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the
duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_
data registers during the 50µs following the assertion of the end-of-conversion interrupt.
The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the
unfiltered (ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE
(bit 15) and CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of
operation (Digital Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects
between unfiltered ADC data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel
can be read from register COUT STATUS.
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
In addition to the diagnostics bits, the comparator outputs can be programmed to assert the
pin if enabled. If a positive
edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit
(COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_
data is lower than the lower limit (COUTLO_).
Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is
changed during frame N, the new threshold value is used starting frame N+1.
To clear an interrupt and deactivate the
pin, the host must perform a read operation of the INTERRUPT STATUS
register (0x12). All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the
CRC is properly decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared
fault bit is immediately set again.
If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while
the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.
However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets
asserted while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This
means that the host should read the interrupt register upon assertion of
, or poll the interrupt registers several times
per conversion cycles to avoid missing interrupts.
Applications Information
Power Supply Decoupling
It is recommended to decouple both the VDDL and VDDPL supplies with 1μF capacitors in parallel with 0.01μF capacitors
to GNDL. Place the 0.01μF capacitors as close to VDDL and VDDPL as possible. The VDDF pin is the integrated DC-DC
converter output and it is recommended to decouple it with low-ESR capacitors of 1μF in parallel with 0.01μF to GNDF.
Place the 0.01μF capacitor as close to VDDF as possible.
Layout Considerations
The PCB designer should follow some critical recommendations to get the best performance from the design.
•
•
•
•
•
•
Keep the input/output traces as short as possible. To keep signal paths low inductance, avoid using vias.
Have a solid ground plane underneath the signal layer to minimize the noise.
Keep the area underneath the MAX22530–MAX22532 free from ground and signal planes. Any galvanic or metallic
connection between the field side and logic side defeats the isolation.
Ensure that the decoupling capacitors between VDDL, VDDPL and GNDL, and between VDDF and GNDF are located
as close as possible to the IC to minimize inductance.
Route important signal lines close to the ground plane to minimize possible external influences. On the field-side, it is
good practice to separate the ADC input and voltage reference ground AGND from the VDDF reference ground GNDF.
MAX22531 has two extra AGND pins, and MAX22532 has four extra AGND pins to provide analog ground reference
points for the respective AIN_ channels.
Radiated Emissions
The MAX22530–MAX22532 family features an integrated DC-DC converter to generate a nominal 3.1V supply, powering
the field side of the MAX22530–MAX22532. The DC-DC converter passes power from the logic side across the isolation
barrier through an internal transformer. Due to the isolated nature of the device, the split of the ground planes (GNDL and
GNDF) prevents the return current from flowing back to the logic side; thus, causing high-frequency signals to radiate
when crossing the isolation barrier. A spread-spectrum option is added to the DC-DC converter to reduce the radiated
emissions.
The MAX22530–MAX22532 can meet CISPR 22 and FCC radiated emission standards with proper PCB design. A
stitching capacitance of 50pF minimum is recommended to be built into the PCB to pass the CISPR 22 and FCC Class B
limits. See Figure 7 through Figure 8.
To achieve optimal radiated emission performance, the following layout guidelines are recommended:
•
Use at least a 4-layer PCB stackup with GNDL and GNDF ground planes on two adjacent internal layers.
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
•
Extend the GNDF and GNDL planes on two adjacent layers so they overlap each other; thus, creating a stitching
capacitance between GNDL and GNDF. See Figure 5 and Figure 6.
Calculate the stitching capacitance value by using the following equation, where A is the overlapping area between the
GNDL and GNDF planes.
C = A × ε0 × εr × d
where,
ε0 = Permittivity of free space (8.854 x 10-12 F/m),
εr = Relative permittivity of the PCB insulation material, and
d = Dielectric thickness between two adjacent layers.
•
•
•
Adjust the overlapping area A or the dielectric thickness d to achieve a minimum 50pF stitching capacitance. Make
sure that the creepage and clearance between the GNDF plane and the GNDL plane on the same layer as well as
between two different layers large enough to meet isolation standards for various applications.
Multiple GNDL and GNDF vias are recommended to be placed next to the GNDF and GNDL pins to provide a good
connection between the stitching capacitor and the device ground pins.
Apply edge guarding vias to stitch the GNDF and GNDL planes on all layers together to limit the emission from
escaping from the PCB edges.
MAX22530–MAX22532
d
GNDL
GNDF
GNDL
GNDF
GNDF
GNDL
A
GNDL
GNDF
L
7.36mm W SOIC
5.3mm SSOP
GNDL VIAS
GNDF VIAS
Figure 5. Stitching Capacitance Example on a 4- Layer PCB
GNDL
GNDL
INTERNAL LAYER-2
INTERNAL LAYER-3
GNDF
GNDF
Figure 6. Stitching Capacitance on Internal Layers
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Figure 7. MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan
Figure 8. MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan
Figure 9. MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Figure 10. MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan
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MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Register Map
SPI_Register_MAP
ADDRESS
NAME
MSB
LSB
ID_BLK
PROD_ID[15:8]
DEVICE_ID[7:0]
0x00
PROD_ID[7:0]
POR
DEVICE_REV[6:0]
ADC_STATUS BLK
ADC 1[15:8]
ADCS
–
–
–
ADC[11:8]
0x01
ADC 1[7:0]
ADC 2[15:8]
ADC[7:0]
ADCS
–
–
–
ADC[11:8]
0x02
ADC 2[7:0]
ADC 3[15:8]
ADC[7:0]
ADCS
–
–
–
ADC[11:8]
0x03
ADC 3[7:0]
ADC 4[15:8]
ADC[7:0]
ADCS
–
–
–
ADC[11:8]
0x04
ADC 4[7:0]
FADC 1[15:8]
ADC[7:0]
–
–
–
–
FADC[11:8]
0x05
FADC 1[7:0]
FADC 2[15:8]
FADC[7:0]
–
–
–
–
FADC[11:8]
0x06
FADC 2[7:0]
FADC 3[15:8]
FADC[7:0]
–
–
–
–
FADC[11:8]
0x07
FADC 3[7:0]
FADC 4[15:8]
FADC[7:0]
–
–
–
–
FADC[11:8]
0x08
FADC 4[7:0]
FADC[7:0]
COUT_BLK
COUTHI 1[15:8]
0x09
COUTHI 1[7:0]
www.maximintegrated.com
CO_MOD
CO_IN_S
E
EL
–
–
COTHI[11:8]
COTHI[7:0]
Maxim Integrated | 25
MAX22530–MAX22532
ADDRESS
NAME
COUTHI 2[15:8]
0x0A
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
MSB
LSB
CO_MOD
CO_IN_S
E
EL
–
–
COUTHI 2[7:0]
COUTHI 3[15:8]
0x0B
COTHI[7:0]
CO_MOD
CO_IN_S
E
EL
–
–
COUTHI 3[7:0]
COUTHI 4[15:8]
0x0C
COTHI[11:8]
COTHI[7:0]
CO_MOD
CO_IN_S
E
EL
–
–
COUTHI 4[7:0]
COUTLO 1[15:8]
COTHI[11:8]
COTHI[11:8]
COTHI[7:0]
–
–
–
–
COTLO[11:8]
0x0D
COUTLO 1[7:0]
COUTLO 2[15:8]
COTLO[7:0]
–
–
–
–
COTLO[11:8]
0x0E
COUTLO 2[7:0]
COUTLO 3[15:8]
COTLO[7:0]
–
–
–
–
COTLO[11:8]
0x0F
COUTLO 3[7:0]
COUTLO 4[15:8]
COTLO[7:0]
–
–
–
–
COTLO[11:8]
0x10
COUTLO 4[7:0]
COTLO[7:0]
CONTROL_STATUS
COUT STATUS[15:8]
–
–
–
–
–
–
–
–
COUT STATUS[7:0]
–
–
–
–
CO_4
CO_3
CO_2
CO_1
–
–
–
EOC
ADCF
FLD
SPIFRM
SPICRC
CO_POS_
CO_POS_
CO_POS_
CO_POS_
CO_NEG_
CO_NEG_
CO_NEG_
CO_NEG_
4
3
2
1
4
3
2
1
–
–
–
EEOC
EFADC
EFLD
ESPIFRM
ESPICRC
ECO_PO
ECO_PO
ECO_PO
ECO_PO
ECO_NE
ECO_NE
ECO_NE
ECO_NE
S_4
S_3
S_2
S_1
G_4
G_3
G_2
G_1
0x11
INTERRUPT
STATUS[15:8]
0x12
INTERRUPT STATUS[7:0]
INTERRUPT
ENABLE[15:8]
0x13
INTERRUPT ENABLE[7:0]
www.maximintegrated.com
Maxim Integrated | 26
MAX22530–MAX22532
ADDRESS
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
NAME
MSB
ENCRC
ECOM
–
–
FLT_CLR
FLT_CLR
FLT_CLR
FLT_CLR
_4
_3
_2
_1
CONTROL[15:8]
0x14
CONTROL[7:0]
LSB
–
–
–
–
DISPWR
CLRPOR
SRES
REST
Register Details
PROD_ID (0x0)
Device ID Register
BIT
15
14
13
12
11
Field
DEVICE_ID[7:0]
Reset
0x00
Access Type
7
6
5
4
3
Field
POR
DEVICE_REV[6:0]
Reset
0b0
0x01
Read Only
Read Only
BITFIELD
DEVICE_ID
BITS
15:8
POR
7
DEVICE_REV
9
8
2
1
0
Read Only
BIT
Access Type
10
6:0
DESCRIPTION
DECODE
Device ID
0x0: MAX22530/MAX22531/MAX22532
Power-On Reset
0x0: Normal Operation
0x1: Wake up from Power-On Reset
Revision Control of die
0x0: Initial Die Revision
ADC (0x1, 0x2, 0x3, 0x4)
ADC_ Data Register
BIT
Field
15
14
13
12
ADCS
–
–
–
www.maximintegrated.com
11
10
9
8
ADC[11:8]
Maxim Integrated | 27
MAX22530–MAX22532
0b0
–
–
–
0x000
Read Sets All
–
–
–
Read Only
7
6
5
4
Reset
Access Type
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
BIT
3
Field
ADC[7:0]
Reset
0x000
Access Type
BITFIELD
ADCS
1
0
Read Only
BITS
15
ADC
2
11:0
DESCRIPTION
DECODE
0x0: ADC has been updated since last read operation
0x1: ADC has not been updated since last read operation
ADC Data Read Check function
Unfiltered ADC Data
FADC (0x5, 0x6, 0x7, 0x8)
Filtered ADC_ Data Register
BIT
15
14
13
12
Field
–
–
–
–
FADC[11:8]
Reset
–
–
–
–
0x000
Access Type
–
–
–
–
Read Only
7
6
5
4
BIT
11
3
Field
FADC[7:0]
Reset
0x000
Access Type
BITFIELD
FADC
www.maximintegrated.com
10
2
9
8
1
0
Read Only
BITS
11:0
DESCRIPTION
Filtered ADC Data
Maxim Integrated | 28
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
COUTHI (0x9, 0xA, 0xB, 0xC)
BIT
15
14
13
12
Field
CO_MODE
CO_IN_SEL
–
–
COTHI[11:8]
Reset
0b0
0b0
–
–
0xB32
Write, Read
Write, Read
–
–
Write, Read
7
6
5
4
Access Type
BIT
11
3
Field
COTHI[7:0]
Reset
0xB32
Access Type
BITFIELD
10
2
9
8
1
0
Write, Read
BITS
DESCRIPTION
DECODE
CO_MODE
15
Comparator Output Operation Mode Selection
0x0: Digital Input Mode
0x1: Digital Status Mode
CO_IN_SEL
14
Comparator Input Selection
0x0: Unfiltered ADC data is used as input to the
comparator
0x1: Filtered ADC data is used as input to the comparator
Comparator Threshold High Value
0xB32h: 70% of range
COTHI
11:0
COUTLO (0x10, 0xD, 0xE, 0xF)
BIT
15
14
13
12
Field
–
–
–
–
COTLO[11:8]
Reset
–
–
–
–
0x4CC
Access Type
–
–
–
–
Write, Read
7
6
5
4
BIT
11
3
Field
COTLO[7:0]
Reset
0x4CC
Access Type
www.maximintegrated.com
10
2
9
8
1
0
Write, Read
Maxim Integrated | 29
MAX22530–MAX22532
BITFIELD
COTLO
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
BITS
DESCRIPTION
11:0
Comparator Threshold Low Value
DECODE
0x4CCh: 30% of range
COUT STATUS (0x11)
Digital Comparator COUT_ Status Register
BIT
15
14
13
12
11
10
9
8
Field
–
–
–
–
–
–
–
–
Reset
–
–
–
–
–
–
–
–
Access Type
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
Field
–
–
–
–
CO_4
CO_3
CO_2
CO_1
Reset
–
–
–
–
0b0
0b0
0b0
0b0
Access Type
–
–
–
–
Read Only
Read Only
Read Only
Read Only
BIT
BITFIELD
CO_4
CO_3
CO_2
CO_1
BITS
3
2
1
0
www.maximintegrated.com
DESCRIPTION
DECODE
Comparator Output status: when CO_MODE = 0/1
0x0: MODE 0: The ADC value is lower than COUTLO
value.
MODE 1: The ADC value is within COUTHI and COUTLO.
0x1: MODE 0: The ADC value is higher than COUTHI
value.
MODE 1: The ADC value is higher than COUTHI value or
lower than COUTLO value.
Comparator Output status: when CO_MODE = 0/1
0x0: MODE 0: The ADC value is lower than COUTLO
value.
MODE 1: The ADC value is within COUTHI and COUTLO.
0x1: MODE 0: The ADC value is higher than COUTHI
value.
MODE 1: The ADC value is higher than COUTHI value or
lower than COUTLO value.
Comparator Output status: when CO_MODE = 0/1
0x0: MODE 0: The ADC value is lower than COUTLO
value.
MODE 1: The ADC value is within COUTHI and COUTLO.
0x1: MODE 0: The ADC value is higher than COUTHI
value.
MODE 1: The ADC value is higher than COUTHI value or
lower than COUTLO value.
Comparator Output status: when CO_MODE = 0/1
0x0: MODE 0: The ADC value is lower than COUTLO
value.
MODE 1: The ADC value is within COUTHI and COUTLO.
0x1: MODE 0: The ADC value is higher than COUTHI
value.
MODE 1: The ADC value is higher than COUTHI value or
lower than COUTLO value.
Maxim Integrated | 30
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
INTERRUPT STATUS (0x12)
Interrupt Status Register
BIT
15
14
13
12
11
10
9
8
Field
–
–
–
EOC
ADCF
FLD
SPIFRM
SPICRC
Reset
–
–
–
0b0
0b0
0b0
0b0
0b0
Access Type
–
–
–
Read Clears
Read Clears
Read Clears
Read Clears
Read Clears
All
All
All
All
All
7
6
5
4
3
2
1
0
Field
CO_POS_4
CO_POS_3
CO_POS_2
CO_POS_1
CO_NEG_4
CO_NEG_3
CO_NEG_2
CO_NEG_1
Reset
0b0
0b0
0b0
0b0
0b0
0b0
0b0
0b0
Read Clears
Read Clears
Read Clears
Read Clears
Read Clears
Read Clears
Read Clears
Read Clears
All
All
All
All
All
All
All
All
BIT
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
EOC
12
Enable End of ADC Conversion Interrupt
0x0: No end of conversion event
0x1: End of conversion of one cycle of Channel 1 to 4
event detected
ADCF
11
ADC Functionality Interrupt
0x0: Correct ADC functionality: ADC Diagnostic values
are in range
0x1: Faulty ADC functionality: ADC Diagnostic values are
not in range
FLD
10
Field Data Interrupt
0x0: No data loss
0x1: Loss of data occurred
SPIFRM
9
SPI Frame Error Interrupt
0x0: No SPI frame error detected
0x1: At least one SPI frame error was detected
SPICRC
8
SPI CRC Error Interrupt
0x0: No SPI CRC error detected
0x1: At least one SPI CRC error was detected
CO_POS_4
7
Comparator Output 4 low-to-high transition interrupt
0x0: No positive edge was detected by Comparator 4
0x1: At least one positive edge was detected
by Comparator 4
CO_POS_3
6
Comparator Output 3 low-to-high transition interrupt
0x0: No positive edge was detected by Comparator 3
0x1: At least one positive edge was detected by
Comparator 3
CO_POS_2
5
Comparator Output 2 low-to-high transition interrupt
0x0: No positive edge was detected by Comparator 2
0x1: At least one positive edge was detected by
Comparator 2
CO_POS_1
4
Comparator Output 1low-to-high transition interrupt
0x0: No positive edge was detected by Comparator 1
0x1: At least one positive edge was detected by
Comparator 1
CO_NEG_4
3
Comparator Output 4 high-to-low transition interrupt
0x0: No negative edge was detected by Comparator 4
0x1: At least one negative edge was detected by
Comparator 4
CO_NEG_3
2
Comparator Output 3 high-to-low transition interrupt
0x0: No negative edge was detected by Comparator 3
0x1: At least one negative edge was detected by
Comparator 3
www.maximintegrated.com
Maxim Integrated | 31
MAX22530–MAX22532
BITFIELD
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
BITS
DESCRIPTION
DECODE
CO_NEG_2
1
Comparator Output 2 high-to-low transition interrupt
0x0: No negative edge was detected by Comparator 2
0x1: At least one negative edge was detected by
Comparator 2
CO_NEG_1
0
Comparator Output 1 high-to-low transition interrupt
0x0: No negative edge was detected by Comparator 1
0x1: At least one negative edge was detected by
Comparator 1
INTERRUPT ENABLE (0x13)
Interrupt Enable Register
BIT
15
14
13
12
11
10
9
8
Field
–
–
–
EEOC
EFADC
EFLD
ESPIFRM
ESPICRC
Reset
–
–
–
0b0
0b0
0b0
0b0
0b0
Access Type
–
–
–
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
7
6
5
4
3
2
1
0
Field
ECO_POS_4
ECO_POS_3
ECO_POS_2
ECO_POS_1
ECO_NEG_4
ECO_NEG_3
ECO_NEG_2
ECO_NEG_1
Reset
0b0
0b0
0b0
0b0
0b0
0b0
0b0
0b0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
BIT
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
EEOC
12
Enable End of ADC Conversion Interrupt
0x0: EOC Interrupt Disabled
0x1: FADC Interrupt
EFADC
11
Enable ADC Fault Interrupt
0x0: FADC Interrupt Disabled
0x1: FADC Interrupt Enabled
EFLD
10
Enable Loss Data Fault Interrupt
0x0: EFLD Interrupt Disabled
0x1: EFLD Interrupt Enabled
ESPIFRM
9
Enable SPI Frame Fault Interrupt
0x0: SPIFRM Interrupt Disabled
0x1: SPIFRM Interrupt Enabled
ESPICRC
8
Enable SPI CRC Fault Interrupt
0x0: SPICRC Interrupt Disabled
0x1: SPICRC Interrupt Enabled
ECO_POS_4
7
Enable COUT4 Positive Transition Interrupt
0x0: Disable CO_POS4 Interrupt
0x1: Enable CO_POS4 Interrupt
ECO_POS_3
6
Enable COUT3 Positive Transition Interrupt
0x0: Disable CO_POS3 Interrupt
0x1: Enable CO_POS3 Interrupt
ECO_POS_2
5
Enable COUT2 Positive Transition Interrupt
0x0: Disable CO_POS2 Interrupt
0x1: Enable CO_POS2 Interrupt
ECO_POS_1
4
Enable COUT1 Positive Transition Interrupt
0x0: Disable CO_POS1 Interrupt
0x1: Enable CO_POS1 Interrupt
ECO_NEG_4
3
Enable COUT4 Negative Transition Interrupt
0x0: Disable CO_NEG4 Interrupt
0x1: Enable CO_NEG4 Interrupt
www.maximintegrated.com
Maxim Integrated | 32
MAX22530–MAX22532
BITFIELD
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
BITS
DESCRIPTION
DECODE
ECO_NEG_3
2
Enable COUT3 Negative Transition Interrupt
0x0: Disable CO_NEG3 Interrupt
0x1: Enable CO_NEG3 Interrupt
ECO_NEG_2
1
Enable COUT2 Negative Transition Interrupt
0x0: Disable CO_NEG2 Interrupt
0x1: Enable CO_NEG2 Interrupt
ECO_NEG_1
0
Enable COUT1 Negative Transition Interrupt
0x0: Disable CO_NEG1 Interrupt
0x1: Enable CO_NEG1 Interrupt
CONTROL (0x14)
Control Register
BIT
15
14
13
12
11
10
9
8
Field
ENCRC
ECOM
–
–
–
–
–
–
Reset
0b0
0b0
–
–
–
–
–
–
Write, Read
Write, Read
–
–
–
–
–
–
7
6
5
4
3
2
1
0
Field
FLT_CLR_4
FLT_CLR_3
FLT_CLR_2
FLT_CLR_1
DISPWR
CLRPOR
SRES
REST
Reset
0b0
0b0
0b0
0b0
0b0
0b0
0b0
0b0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Access Type
BIT
Access Type
BITFIELD
BITS
DESCRIPTION
0x0: CRC not used (24-bit SPI transactions)
0x1: CRC used (32-bit SPI transactions)
ENCRC
15
ECOM
14
FLT_CLR_4
7
Clear ADC4 Moving Average Filter
0x0: Normal operation
0x1: Clear ADC4 filter
FLT_CLR_3
6
Clear ADC3 Moving Average Filter
0x0: Normal operation
0x1: Clear ADC3 filter
FLT_CLR_2
5
Clear ADC2 Moving Average Filter
0x0: Normal operation
0x1: Clear ADC2 filter
FLT_CLR_1
4
Clear ADC1 Moving Average Filter
0x0: Normal operation
0x1: Clear ADC1 filter
DISPWR
3
Disable Field Power VDDF
0x0: Normal Operation, Enable Field Power VDDF
0x1: Disable Field Power VDDF
CLRPOR
2
Clear POR bit
0x0: No action
0x1: Clear POR bit in PROD_ID Register
SRES
1
Soft Reset (Reset Logic Core & Registers)
0x0: Normal Operation
0x1: Soft Reset Enabled (Self-Clearing)
REST
0
Hard Reset (including field supply power off)
0x0: Normal Operation
0x1: Hard Reset (Self-Clearing)
www.maximintegrated.com
Enable SPI CRC
DECODE
Enable Common High and Low Thresholds for all
Channels
0x0: Each threshold needs to be individually programmed
0x1: All comparators use COUTHI1 and COUTLO1 as
threshold values
Maxim Integrated | 33
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Typical Application Circuits
High-Voltage DC Monitoring
UP TO 110VDC LINE MONITORING
+
VDC
60kΩ
1kΩ
1.8V
0.01µF
1µF
+
VDC
60kΩ
1kΩ
REFERENCE
0.01µF
60kΩ
1kΩ
VDDL
12-BIT ADC
AIN4
LOGIC AND SPI
INTERFACE
LOGIC CONTROL
+
VDC
60kΩ
1kΩ
0.01µF
3.1V
VDDF
AGND
1µF
0.01µF
GNDF
3.3V
VDD
0.01µF
AIN3
0.01µF
MICROCONTROLLER
MAX22530/MAX22531/MAX22532
AIN1
AIN2
+
VDC
0.01µF
µPOWER
ISOLATED DC-DC
1µF
INT
GPI
CS
CS
SCLK
SCLK
SDI
MOSI
SDO
MISO
VDDPL
3.0V TO 5.5V
0.01µF
GNDL
1µF
GNDL
NOTE: INPUT RESISTIVE DIVIDER SETS MAXIMUM DC LINE LEVEL
www.maximintegrated.com
Maxim Integrated | 34
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
3-Phase Motor Low Side Monitoring
VCC
Φ1
Φ2
Φ3
PHASE A
3-PHASE
MOTOR
PHASE C
PHASE B
RECTIFIED BUS VOTLAGE
(MOTOR SUPPLY)
1kΩ
Φ2
Φ1
Φ3
220kΩ
20mΩ,10A
20mΩ,10A
20mΩ,10A
1.8V
0.01µF
1µF
0.01µF
REFERENCE
0.01µF
VDDL
AIN1
AIN2
12-BIT ADC
AIN4
3.1V
LOGIC AND SPI
INTERFACE
LOGIC CONTROL
0.01µF
VDDF
AGND
3.3V
0.01µF
AIN3
0.01µF
MICROCONTROLLER
MAX22530/MAX22531/MAX22532
INT
GPI
CS
CS
SCLK
SCLK
SDI
MOSI
SDO
MISO
VDDPL
µPOWER
ISOLATED DC-DC
3.0V TO 5.5V
0.01µF
1µF
0.01µF
GNDF
VDD
1µF
GNDL
1µF
GNDL
Ordering Information
PART NUMBER
ISOLATION RATING (VRMS)
# OF COUT PINS
PIN-PACKAGE
MAX22530AWE+
5000
0
16-pin WSOIC
MAX22531AAP+*
3500
2
20-pin SSOP
MAX22532AAI+*
3500
4
28-pin SSOP
*Future product–contact Maxim for availability.
+ Denotes lead (Pb)-free/RoHS compliance.
www.maximintegrated.com
Maxim Integrated | 35
MAX22530–MAX22532
Field-Side Self-Powered,
4-Channel, 12-bit, Isolated ADC
Revision History
REVISION
NUMBER
0
REVISION
DATE
3/21
DESCRIPTION
Release for Market Intro
PAGES
CHANGED
—
MAXSafe is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2021 Maxim Integrated Products, Inc.
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