MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
General Description
The MAX270/MAX271 are digitally-programmed, dual
second-order continuous-time lowpass filters. Their typical dynamic range of 96dB surpasses most switched
capacitor filters which require additional filtering to
remove clock noise. The MAX270/MAX271 are ideal for
anti-aliasing and DAC smoothing applications and can
be cascaded for higher-order responses.
The two filter sections are independently programmable
by either microprocessor (FP) control or pin strapping.
Cutoff frequencies in the 1kHz to 25kHz range can be
selected.
The MAX270 has an on-board, uncommitted op amp,
while the MAX271 has an internal track-and-hold (T/H).
Applications
Lowpass Filtering
Anti-Aliasing Filter
Output Smoothing
Low-Noise Applications
Anti-Aliasing and Track-and-Hold (MAX271)
Features
S Continuous-Time Filtering - No Clock Required
S Dual 2nd-Order Lowpass Filters
S Sections Independently Programmable: 1kHz to
25kHz
S 96dB Dynamic Range
S No External Components
S Cascadable for Higher Order
S Low-Power Shutdown Mode
S Track-and-Hold (MAX271)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX270CPP
0NC to +70NC
20 PDIP
MAX270CWP
0NC to +70NC
20 Wide SO
MAX270EPP
-40NC to +85NC
20 PDIP
MAX270EWP
-40NC to +85NC
20 Wide SO
MAX271CNG
0NC to +70NC
20 PDIP
MAX271CWG
0NC to +70NC
20 Wide SO
MAX271ENG
-40NC to +85NC
20 PDIP
MAX271EWG
-40NC to +85NC
20 Wide SO
Devices are available in a lead(Pb)-free/RoHS-compliant package.
Specify lead-free by adding a plus (+) to the part number when
ordering.
Pin Configurations
Typical Operating Circuit
+5V
V+
IN INA
TOP VIEW
-5V
GND
OUTA
FILTER A
A/D WITH
T/H
ANTI-ALIASING
MAX270
OUT OUTB
DSB
INB
FILTER B
DAC
ANTI-ALIASING
AO
D0-D6
1
OP OUT
OP IN
20
2
V+
D6
19
3
OUTA
D5
18
4
SHDN
D4
17
D3
16
V-
CS
WR
Pin Configurations
continued at end
of data sheet.
MAX270
5
INA
6
V-
D2
15
7
INB
D1
14
8
OUTB
D0
13
9
GND
A0
12
10
WR
CS
11
µP OR PIN-STRAP CONTROL
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
PDIP/SO(W)
19-3701; Rev 2; 1/12
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
ABSOLUTE MAXIMUM RATINGS
SO (W) (derate 11.7mW/NC above +70NC)................... 941mw
Operating Temperature Ranges:
MAX27_C_ _........................................................ 0NC to +70NC
MAX27_E_ _..................................................... -40NC to +85NC
Storage Temperature Range............................. -65NC to +165NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow)
Lead(Pb)-free................................................................+260NC
Containing lead(Pb)......................................................+240NC
V+ to V-..................................................................-0.3V to +17V
V+ to GND.............................................................-0.3V to +8.5V
V- to GND............................................................... -0.3V to -8.5V
Input Voltage to GND, Any Input Pin.....(V- - 0.3V) to (V+ + 0.3V)
Duration of Output Short Circuit to GND....................Continuous
Continuous Power Dissipation (TA = +70NC)
MAX270
PDIP (derate 11.1mW/NC above +70NC)......................889mW
SO (W) (derate 10mW/NC above +70NC.......................800mW
MAX271
PDIP (derate 13.3mW/NC above +70NC)....................1067mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5V; TA = +25NC, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FILTER CHARACTERISTICS
Operating Frequency Range
(Note 1)
Programmed Cutoff Frequency (fC)
Range
Programmed Cutoff Frequency
Error
Filter Gain
Maximum Gain (Peaking)
Wideband Noise
2
MHz
1 to 25
kHz
fC code = 53 (2.536kHz typ)
Q2.9
fC code = 127 (25kHz typ)
Q9.5
fC code = 0 (1kHz typ),
TA = TMIN to TMAX
fIN = 1kHz
fC code = 127 (25kHz typ),
TA = TMIN to TMAX
fIN = 25kHz
-3.6
-2.4
-6
-0.5
fIN = 8kHz
-33
fIN = 200kHz
dB
-34
fC code = 0 (1kHz typ)
0.15
fC code = 127 (25kHz typ)
50Hz to 50kHz bandwidth
%
0.15
fC code = 0
(1kHz typ)
12
fC code = 127
(25kHz typ)
38
dB
FVRMS
DC CHARACTERISTICS
DC Output Signal Swing
OUTA, OUTB, OP OUT (MAX270)
OUTA, OUTB, T/H OUT (MAX271)
RLOAD = 5kI, TA = TMIN to TMAX
Offset Voltage at Outputs
OUTA, OUTB, OP OUT (MAX270)
OUTA, OUTB, T/H OUT (MAX271)
DC Input Leakage Current
INA, INB (MAX270)
INA, INB (MAX271)
2
TA = TMIN to TMAX
-3
+3
V
-2
+2
mV
-1
+1
FA
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V, V- = -5V; TA = +25NC, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC FILTER CHARACTERISTICS (MAX270)
Total Harmonic Distortion
THD
Signal Noise Plus Distortion
SINAD
Spurious-Free Dynamic Range
SFDR
fC code = 44 (2.01kHz typ), VIN = 3.5VP-P at
390.625Hz (Notes 2 and 3)
-70
73
dB
70
UNCOMMITTED AMPLIFIER (MAX270)
Slew Rate
1.2
V/Fs
Bandwidth
2
MHz
TRACK AND HOLD (MAX271)
Hold Settling Time
To 0.1% (Note 4)
500
ns
Acquisition Time
To 0.1% (Note 5)
1.8
Fs
1
mV
Droop Rate
TA = TMIN to TMAX
30
FV/Fs
Offset Voltage at T/H OUT
Includes filter offset
-6
+6
mV
T/H OUT Disabled Output Leakage
Current
TA = TMIN to TMAX, VT/H = 0V (Track Mode)
-10
+10
FA
Hold Step
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
-70
fC code = 44 (2.01kHz typ), VIN = 3.5VP-P at
390.625Hz, sampling rate = 50kHz
(Notes 2, 6, 7)
70
TA = TMIN to TMAX (Note 8)
2.4
dB
DIGITAL INPUTS
Digital Input High Voltage
Digital Input Low Voltage
V
0.8
TA = TMIN to TMAX, digital input held at Q5V,
includes MODE (MAX271)(Note 8)
Digital Input Current
-1
+1
FA
POWER REQUIREMENTS
Q2.375
to Q8
Supply Voltage Range
V
Supply Current
TA = TMIN to TMAX (Note 9)
6.5
mA
Shutdown Supply Current
TA = TMIN to TMAX (Note 10)
15
FA
Power-Supply Rejection Ratio at
1kHz
PSRR
fC code = 0 (1kHz typ), V+ = 5VDC +
10mVP-P at 1kHz
30
dB
All internal amplifiers limited to 2MHz bandwidth.
Only filter A tested for these parameters.
Spurious-Free Dynamic Range is the ratio of the fundamental to the largest of any harmonic or noise spur in dB.
Includes T/H propagation delays. With 5kω, parallel 100pF load.
±2V input step settling 0.1% with 5kω parallel 100pF load.
T/H pin toggled at sampling rate, 50% duty cycle.
THD and SFDR specifications for T/H include contributions from filter.
Digital pins include SHDN, WR, CS, A0, D0–D6 (MAX270) and SHDN, T/H, A/B, WR, T/H EN, CS, A0, A1, D0–D6, T/H
(MAX271).
Note 9: Input of uncommitted op amp disconnected with a 5kω feedback resistor from input to output.
Note 10: WR, CS, A0, D0–D6 held at +5V; VSHDN = 0V (MAX270). WR, CS, A0, A1, D0–D6, T/H, T/H, A/B, T/H, MODE held at
+5V; VSHDN = 0V (MAX271).
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Maxim Integrated
3
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
TIMING CHARACTERISTICS (Figure 2)
(V+ = +5V, V- = -5V; TA = +25NC, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS to WR Setup
tWS
0
ns
CS to WR Hold
tWH
0
ns
WR Pulse Width
tSV
100
ns
Address-Setup Time
tAS
30
ns
Address-Hold Time
tAH
10
ns
Data-Setup Time
tDS
30
ns
Data-Hold time
tDH
10
ns
Note 11: All input control signals specified with tr = tf = 5ns (10% to 90% of +5V) and timed from a +1.6V voltage level.
Typical Operating Characteristics
FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
MAX270 toc01
0
0
V+ = +5V
V- = -5V
fC CODE = 127 (25kHz TYP)
TA = +25˚C
TA = +125˚C
TA = +25˚C
TA = -55˚C
0.1
0
V+ = +5V
V- = -5V
fC CODE = 127 (25kHz TYP)
10
100
1k
PASSBAND FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
FILTER PHASE SHIFT vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
-1
V+ = +5V
V- = -5V
fC CODE = 0-127 (1-25kHz TYP)
TA = +25˚C
-2
-3
1
100
fIN/ fC
0
GAIN (dB)
TA = +125˚C
TA = +25˚C
TA = -55˚C
10
fIN/ fC
+0.5
MAX270 toc04
0.5
1.0
0
MAX270 toc06
1M
PHASE SHIFT (DEGREES)
100k
PASSBAND FILTER GAIN
vs. FREQUENCY
-2
V+ = +5V
V- = -5V
fC CODE = 0 (1kHz TYP)
-3
-80
fIN (Hz)
-1
V+ = +5V
V- = -5V
fC CODE = 0-127 (1-25kHz TYP)
TA = +25˚C
-60
MAX270 toc05
10k
-40
-1
-2
-80
1k
GAIN (dB)
-40
-60
GAIN (dB)
0.5
-20
GAIN (dB)
GAIN (dB)
-20
PASSBAND FILTER GAIN
vs. FREQUENCY
MAX270 toc02
0
MAX270 toc03
FILTER GAIN vs. FREQUENCY
-45
V+ = +5V
V- = -5V
fC CODE = 0-127
(1-25kHz TYP)
TA = +25˚C
-90
-135
-3
-180
25
100
1k
fIN (Hz)
4
10k
25k
0.001
0.01
0.1
fIN/ fC
1.0
0.01
0.1
1.0
10
fIN/ fC
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Typical Operating Characteristics (continued)
-20
V+ = +5V
V- = -5V
fC CODE = 44 (2.01kHz TYP)
fTEST = 390.625Hz
TA = +25˚C
VIN = 3.5VP-P
-20
GAIN (dB)
-3.5
V+ = +5V
V- = -5V
fC (FILTER A) = fC (FILTER B) =
0-127 (1-25kHz TYP)
FILTERS A AND B CASCADED
FIGURE 5
TA = +25˚C
-4.5
-5.5
-6.5
-7.5
0.01
-40
V+ = +5V
V- = -5V
fC (FILTER A) = fC (FILTER B) =
0-127 (1-25kHz TYP)
FILTERS A AND B CASCADED
FIGURE 5
TA = +25˚C
-60
-80
0.1
0.01
1.0
GAIN (dB)
-40
-2.5
1.0
-100
-120
190
0
1k
-78
390
44
2.01k
-73
1367
100
7.01k
-60
V+ = +5V
V- = -5V
fIN = 390.625Hz
fC CODE = 44 (2.01kHz TYP)
TA = +25˚C
-65
GAIN (dB)
THD PLUS
NOISE
(TYP)
-70
2k
3k
4k
MAX271 FILTER PLUS TRACK-AND-HOLD
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT FREQUENCY
MAX270 toc11
FILTER TOTAL HARMONIC DISTORTION
PLUS NOISE vs. INPUT AMPLITUDE
fC
(Hz)
(TYP)
1k
F (Hz)
FILTER TOTAL HARMONIC DISTORTION
PLUS NOISE vs.INPUT FREQUENCY
fC
CODE
0
10
fIN/ fC
fIN
(Hz)
-60
-80
fIN/ fC
MAX270 toc10
GAIN (dB)
-1.5
MAX270 toc09
-0.5
FILTER HARMONIC DISTORTION
0
MAX270 toc08
0
MAX270 toc07
+0.5
CASCADED FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
fIN
(Hz)
fC
CODE
fC
(Hz)
(TYP)
SFDR
(dB)
195
0
1k
73.5
781
72
4.01k
69.5
1562.5
105
8.08k
66
3906
124
19.4k
61.5
MAX270 toc12
CASCADED FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
-75
-67
-80
4875
127
25k
-66
-85
0.2
V+ = +5V
V- = -5V
fIN = 390Hz
fC CODE = 44 (2.01kHz TYP)
TA = +25˚C
SFDR (dB)
55
65
MAX270 toc13
MAX271 FILTER PLUS TRACK-AND-HOLD
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT AMPLITUDE
1.0
VIN (VP-P)
8.0
V+ = 5V, V- = -5V; VIN = 3.5VP-P;
T/H SWITCHED AT 50kHz, 50% DUTY CYCLE; TA = +25˚C
MAX271 FILTER PLUS TRACK-AND-HOLD
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING FREQUENCY
fSAMPLE
(Hz)
fIN
(Hz)
fC
CODE
fC
(Hz)
SFDR
(dB)
100k
781
72
4.01k
72
200k
1562
105
8.08k
72
500k
3906
124
19.4k
64
MAX270 toc14
V+ = 5V, V- = -5V; VIN = 3.5VP-P; TA = +25˚C
75
-85
0.5
8.0
1.0
VIN (VP-P)
Maxim Integrated
V+ = 5V, V- = -5V; VIN = 3.5VP-P;
T/H SWITCHED AT 50kHz, 50% DUTY CYCLE; TA = +25˚C
5
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Detailed Description
Figures 1a, 1b, and 1c show the MAX270/MAX271 functional diagrams. Both the MAX270 and MAX271 contain
two independent, second-order, Sallen-Key, lowpass
filter sections, A and B to provide a frequency vs. gain
rolloff of approximately 40dB/decade. These are not
switched-capacitor filters, but have a continuous-time
design similar to discrete active filters built around op
amps. The MAX270/MAX271 eliminate clock noise and
aliasing problems which limit low-noise performance of
switched-capacitor filters; resulting dynamic range is
over 96dB.
Each filter section contains two banks of programmable
capacitors, controlled by an internal 7-bit memory, which
set filter cutoff frequencies (fC) from 1kHz to 25kHz. The
filters provide two program modes. In FP mode, cutoff
frequencies are programmed by writing 7-bit data to one
of two memory addresses (one for each filter section).
Alternately, a pin-strap programming mode programs
both filter sections simultaneously. In this mode, both
memory latches are transparent (not addressable), and
data pins D0–D6 may be pin-strapped (hard-wired) to
set a common fC for both filter sections.
The filters are trimmed at the wafer level, setting 0 for
a maximum of 0.15dB passband peaking for fC programmed to 1kHz. Maximum passband peaking at other
codes is typically less than 0.15dB. Filter Q is not userprogrammable.
The MAX270 includes an uncommitted op amp (noninverting input grounded); the MAX271 has an on-chip T/H
that tracks and holds the output of either filter section
(selectable). The held output is provided at T/H OUT. T/H
functions are controlled by writing control bits to internal
registers (in FP mode) or by control pins directly (in pinstrap mode).
Pin Description
MAX270
PIN
NAME
FUNCTION
1
OP OUT
2
V+
3
OUTA
Filter A Output
4
SHDN
Shutdown Control. Low level
disconnects OUTA, OUTB, and OP OUT
and places device into shutdown mode.
5
INA
6
V-
Uncommitted Op Amp Output
Positive Supply Voltage
Filter A Input
Negative Supply Voltage
7
INB
8
OUTB
Filter B Output
Filter B Input
9
GND
Ground
10
WR
Write Control Input. A low level writes
data D0–D6 to program memory
addressed by A0. High level latches
data.
11
CS
Chip-Select Input. Must be low for WR
input to be recognized.
12
A0
Three-Level Address Input
Logic High: Addresses filter A
Logic Low: Addresses filter B
Connect to V-: Pin-strap mode
1319
D0–D6
7-Bit Data Inputs. Allows programming
of 128 cutoff frequencies in a 1kHz to
25kHz range.
20
OP IN
Uncommitted Op Amp Input
Note: All digital input levels are TTL and CMOS compatible,
unless otherwise noted.
The MAX270 and MAX271 provide a low quiescent current shutdown mode controlled by the SHDN pin, which
turns off internal amplifiers and disconnects all outputs,
reducing quiescent operating current to less than 15FA.
When the MAX271 is in FP mode, shutdown mode is
selected by writing control bits to memory (the SHDN
pin is disabled).
6
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Pin Description (continued)
MAX271
PIN
NAME
FUNCTION, FP MODE (MODE = GND OR V-)
1
T/H OUT
Track-and-Hold Output
2
V+
Positive Supply Voltage
3
OUTA
Filler A Signal Output
4
SHDN
—
5
INA
6
V-
7
INB
8
MODE
Negative Supply Voltage
Filter B Signal Input
Selects FP mode when connected to GND or V- and pin-strap mode when connected to V+.
9
OUTB
Filter B Signal Output
GND
Ground
11
T/H A/B
WR
13
T/H EN
14
CS
SHUTDOWN Control. A low level disconnects outputs
and places device into shutdown mode
Filter A Signal Input
10
12
FUNCTION, FP MODE (MODE = GND OR V+)
—
Track-and-Hold Input Control. A high/low level internally
connects OUTNOUTB to input of Track-and-Hold
WRITE Control Input. A low level writes data
D0-D6 program memory addressed by A1, A0
(or performs function as described for address
inputs). High level latches data.
—
X
Track-and-Hold Output Control. Low level disconnects
T/H OUT. Connect pin high for normal operation
Chip Select Input. Must be low for WR input to
be recognized.
—
—
15, 16
A1, A0
Address and FP Control Inputs.
0, 0 Programs fC, filter A
0, 1 Programs fC, filter B
1,0 Controls T/H functions:
D0 performs T/H En pin function
D1 performs T/H A/B pin function.
1,1 Controls device shutdown:
D0 performs SHDN pin function
Note: The WR pin must be strobed low to initiate
a program/function (Figure 2).
17-23
D0–D6
7-bit Data Inputs. Allows programming of
128 cutoff frequencies (also performs control
functions as described above).
24
T/H
7-bit Data Inputs. Program memory latches are transparent in this mode. Connect pins high or low to
program filters A and B simultaneously to the same fC.
Track-and-Hold Control. Low level causes T/H OUT to track selected filter output. Filter output level held at
T/H OUT synchronous with T/H rising transition.
X = Pin has no function in this mode.
Note: All digital input levels are TTL and CMOS compatible, unless otherwise noted.
Maxim Integrated
7
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
D0-D6
13-19
V+
V-
GND
2
6
9
3 OUTA
EN
INA 5
fC LATCH A
fC LATCH B
8 OUTB
EN
INB 7
OP IN 20
1 OP OUT
EN
LATCH
CONTROL
MAX270
11
10
CS
WR A0
4
12
SHDN
Figure 1a. MAX270 Block Diagram
D0-D6
17-23
V+
V-
GND
2
6
10
3 OUTA
INA 5
EN
1 T/H OUT
EN
fC LATCH A
MAX271
fC LATCH B
INB 7
LATCH
CONTROL
D1
D0
9 OUTB
EN
µP MODE
CONTROL
µP
MODE
16
15
14
12
4
A0
A1
CS
WR
SHDN* T/H*
A/B
*PIN HAS NO FUNCTION IN µP MODE.
11
24
13
8 MODE
T/H
T/H*
EN
TO V+
Figure 1b. MAX271 Block Diagram—µP Mode
8
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
D0-D6
17-23
V+
V-
GND
2
6
10
3 OUTA
INA 5
EN
1 T/H OUT
EN
DIRECT
CONTROL
INB 7
9 OUTB
EN
PIN-STRAP
MODE
MAX270
16
15
14
12
4
11
SHDN* T/H*
A/B
A0* A1* CS* WR*
*PIN HAS NO FUNCTION IN PIN-STRAP MODE.
24
13
8
T/H
T/H*
EN
MODE
TO GND OR V-
Figure 1c. MAX271 Block Diagram—Pin-Strap Mode
Filter Programming
Cutoff Frequency
fC is the frequency of 3dB attenuation in the filter
response.
Table 1 shows how data pins D0–D6 allow programming
of 128 cutoff frequencies from 1kHz to 25kHz.
The equations for calculating fC from the programmed
code are as follows:
fC =
87.5
x 1kHz
87.5 − CODE
for codes 0 − 63
(fC = 1kHz to 3.57kHz)
fC =
262.5
x 1kHz
137.5 − CODE
for codes 64 − 127
(fC = 3.57kHz to 25kHz)
Maxim Integrated
where CODE is the data on pins D0–D6 (0–127). D6 is
the most significant bit (MSB).
Actual cutoff frequencies are subject to some error for
each programmed code. Highest accuracy occurs at
CODE = 0 where filters are trimmed for a 1kHz cutoff frequency. At higher codes, CODE vs. fC errors
increase; the frequency error at CODE = 127 {highest
code) remains typically within Q9.5%. This means that
the actual filter cutoff frequency, when programmed to
CODE = 127, falls between 22.63kHz and 27.38kHz.
9
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Table 1. Programmed Cutoff Frequency Codes (typ)
PROGRAMMED
CODE
fC (kHz)
PROGRAMMED
CODE
fC (kHz)
PROGRAMMED
CODE
fC
(kHz)
PROGRAMMED
CODE
fC (kHz)
0
1.000
32
1.576
64
3.571
96
6.325
1
1.011
33
1.605
65
3.620
97
6.481
2
1.023
34
1.635
66
3.671
98
6.645
3
1.035
35
1.666
67
3.723
99
6.818
4
1.047
36
1.699
68
3.777
100
7.008
5
1.060
37
1.732
69
3.832
101
7.191
6
1.073
38
1.767
70
3.888
102
7.394
7
1.087
39
1.804
71
3.947
103
7.608
8
1.100
40
1.842
72
4.007
104
7.835
9
1.114
41
1.881
73
4.069
105
8.076
10
1.129
42
1.923
74
4.133
106
8.333
11
1.143
43
1.966
75
4.200
107
8.606
12
1.158
44
2.011
76
4.268
108
8.898
13
1.174
45
2.058
77
4.338
109
9.210
14
1.190
46
2.108
78
4.411
110
9.545
15
1.206
47
2.160
79
4.487
111
9.905
16
1.223
48
2.215
80
4.565
112
10.294
17
1.241
49
2.272
81
4.646
113
10.714
18
11.259
50
2.333
82
4.729
114
11.170
19
1.277
51
2.397
83
4.816
115
11.666
20
1.296
52
2.464
84
4.906
116
12.209
21
1.315
53
2.536
85
5.000
117
12.804
22
1.335
54
2.611
86
5.097
118
13.461
23
1.356
55
2.692
87
5.198
119
14.189
24
1.378
56
2.777
88
5.303
120
15.000
25
1.400
57
2.868
89
5.412
121
15.909
26
1.422
58
2.966
90
5.526
122
16.935
27
1.446
59
3.070
91
5.645
123
18.103
28
1.470
60
3.181
92
5.769
124
19.444
29
1.495
61
3.301
93
5.898
125
21.000
30
1.521
62
3.431
94
6.034
126
22.826
31
1.548
63
3.571
95
6.176
127
25.000
Programmed code is the data on pins D0–D6 (0–127). D6 is the MSB.
10
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270 Control Interlace
The A0 pin is a three-level input that selects the memory
addresses for updating cutoff frequency data in FP mode:
A0
SELECTS
Logic Low
Filter B
Logic High
Filter A
tWH
tWS
CS
tWR
WR
Figure 2 shows µP-mode interface timing.
tAS
tAH
tDS
tDH
ADDRESS
(A0, A1)
Connecting A0 to the negative supply selects pin-strap
mode. Pin-strap mode allows filter programming with
no timing requirements. Internal memory latches are
disabled, permitting filters A and B to be programmed
directly to fC data strapped on D0–D6. This mode disables CS and WR controls, and filters A and B are programmed to the same fC.
DATA
(D0-D6)
NOTE : ALL DIGITAL INPUTS ARE LEVEL-SENSITIVE. WHEN WR AND CS ARE BOTH LOW,
THE DATA INPUT LATCHES ARE TRANSPARENT. AND THE FILTERS ARE
PROGRAMMED TO THE DATA ON D0–D6
A low level on the SHDN pin shuts down all amplifiers
and disconnects OUTA, OUTB, and OP OUT. Current
consumption drops to less than 15µA in this mode.
Figure 2. MAX270/MAX271 Digital Timing Diagram
In FP mode, SHDN, T/H A/B, and T/H EN pins are disabled. T/H remains enabled and performs the T/H tracking/holding function.
MAX271 Control Interlace
Connecting the MODE pin to GND or V- selects the
µP mode. In this mode, addressable program memory
controls filter cutoff frequency programming and all T/H
functions, except T/H. See the Figure 2 for timing characteristics. Table 2 describes available functions:
Tying MODE to V+ selects pin-strap mode. In this mode,
both memory latches are transparent, and data on D0–D6
controls the fC of filters A and 8 directly (filters A and 8
are programmed to the same fC). Pin strap D0–D6 for
operation without FP. A0, A1, CS, and WR are disabled.
Table 2. MAX271 µP-Mode Interface
A1
A0
0
0
06
05
04
03
02
01
D0
0
1
1
0
X
X
X
X
X
X
0
T/H OUT disabled
1
0
X
X
X
X
X
X
1
T/H OUT enabled
1
0
X
X
X
X
X
0
X
Selects OUTB as input to T/H
1
0
X
X
X
X
X
1
X
Selects OUTA as input to T/H
1
1
X
X
X
X
X
X
0
Filter shutdown mode. All outputs floated, 15μA
max supply current
1
1
X
X
X
X
X
X
1
Removes filter from shutdown mode
7-bit fC data
FUNCTION
Selects filter A
7-bit fC data
Selects filter B
X = Don't care
Maxim Integrated
11
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Digital Threshold Levels
All digital inputs are TTL and CMOS compatible, unless
otherwise stated. Inputs are CMOS gates with less than
1µA leakage current and 8pF capacitance loading.
Typical logic voltage thresholds are a function of the V+
supply voltage as shown below (voltages are referenced
to GND).
V+ (V)
LOGIC THRESHOLD
VOLTAGE (V)
8
+2.4
7
+2.3
6
+2.0
5
+1.75
4
+1.5
2.5
+1.0
Note: For +5V single-supply operation, where incoming logic
signals are referenced to V-, typical logic thresholds are +3.5V.
Therefore, a CMOS (rail-to-rail) logic interface is recommended.·
MAX271 Track-and-Hold
The MAX271 T/H is functionally equivalent to a switched
200pF capacitor buffered by a unity-gain amplifier (Figures
1b and 1c). When the T/H pin is driven low, the output of
filter A or filter B (whichever is selected via control interface) internally connects to the amplifier, and T/H OUT
follows the filter output. The offset at T/H OUT (±6mV max)
is the combined offset of the filter amplifier and the T/H
buffer. When T/H is pulled high, the switch disconnects
the filter signal from the T/H. The T/H capacitor holds the
stored charge, and that voltage is buffered at T/H OUT.
A low level at T/H EN disconnects T/H OUT, enabling multiplexed operation (Figure 3). T/H A/B selects between
OUTA and OUTB as the T/H input. In FP mode, the T/H
EN and T/H OUT functions are controlled by writing control bits to program memory, with T/H EN and T/H OUT
pins disabled.
See the Typical Operating Characteristics graphs for T/H
dynamic accuracy.
CH1
Filter Performance
All MAX270/MAX271 internal amplifier and output stages
for filter sections. uncommitted op amp, and T/H are
identical. The outputs are designed to drive 5kω in parallel with a maximum capacitance of 100pF. At higher load
levels, the output swing becomes asymmetric. All outputs
can be short circuited to GND for an indefinite duration.
The MAX270/MAX271 operating frequency range is
limited to approximately 2MHz by the bandwidth of the
internal amplifiers.
Filter Noise
Wideband filter noise over a 50kHz bandwidth is
12µVRMS and 38µVRMS per section for fC programmed
to 1kHz and 25kHz, respectively. A dynamic range of
over 96dB results.
INA
T/H OUT
CHANNEL
SELECT
A
Y0
B
Y1
C
Y2
74HC238
Y7
12
CH2
INA
T/H OUT
T/H EN
CH3
INA
Filter Input Impedance
At DC, the input impedance at INA and INB is equal to
the DC input impedance of the amplifier, which is about
5Mω. At higher frequencies, internal capacitors contribute to an effective input impedance that may fall as low
as 100kω at 25kHz.
OUTPUT
T/H EN
T/H OUT
T/H EN
Figure 3. MAX271 Multiplexed Operation
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Applications Information
single supply, the MAX270 A0 pin must be configure with
a voltage divider (Figure 4).
Power-Supply Configurations
Lowest quiescent current in shutdown mode is achieved
when A0 is either at V+ or V-.
The MAX270/MAX271 power supplies must be properly
bypassed. Best performance is achieved if V+ and V- are
bypassed to GND with 4.7µF electrolytic (tantalum is preferred) and 0.1µF ceramic capacitors in parallel. These
should be as close as possible to the chip supply pins.
Independent fC Programming Without a µP
Figure 6 shows how filter sections A and B may be programmed to different cutoff frequencies without the use
of a µP. The MAX690 µP supervisory circuit provides the
proper programming sequence when the circuit is powered up by controlling the 74HC373 data buffer and the
MAX270 addressing pin to load independent fC data for
filters A and B.
Single supplies in the range of 4.75V to 16V may be
used to power the MAX270/MAX271 as shown in Figure
4. Digital logic may be referenced to V- (system ground),
but will not maintain TTL compatibility. CMOS (rail-torail) logic recommended. For µP-mode operation with a
+5V
10kI
µP
MODE
+5V
10kI
0V
PIN-STRAP
MODE
SINGLE-SUPPLY OPERATION
A0
(MAX270)
+5V
V+
4.7kI
MAX270
4.7µF
GND
4.7kI
4.7µF
0.1µF
0.1µF
V-
BIPOLAR-SUPPLY OPERATION
+5V
V+
MAX270
MAX271
4.7µF
0.1µF
4.7µF
0.1µF
GND
V-
-5V
Figure 4. Power-Supply Configurations
Maxim Integrated
13
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
INPUT
SIGNAL
5
3
7
19
18
17
16
15
14
13
INA
OUTB
OUTA
SHDN
V+
INB
D6
D5
MAX270
A0
V-
OUPUT fC = 1kHz
80dB/dec. ROLLOFF
8
4
+5V
2
12
-5V
6
D4
D3
CS
D2
WR
D1
OP IN
D0
GND
11
10
20
9
Figure 5. Cascading Filter Sections
+5V
0.1µF
+5V
4.7kI
OP OUT
OUTB
OC
VCC
1Q
8Q
1D
8D
100kI
+5V
V+
D6
OUTA
VOUT
VBATT
SIGNAL B +5V
D5
SHDN
MAX270
100kI
VCC
RESET
INA
MAX690
GND
PFI
0.1µF
WDI
-5V
PFO
V-
D4
D3
D2
INB
D1
SIGNAL A
OUTB
D0
+5V
GND
6
D6
D5
D4
D3
D2
D1
TO D0
100kI
5
0
4
1
100kI
7D
6
74HC373
100kI
2Q
3
TO D1
2
TO D2
7Q
TO D6
100kI
3Q
6Q
TO D5
100kI
1
2
0
3
3D
6D
5
100kI
D0
A0
WR
2D
4D
5D
4Q
5Q
TO D3
TO D4
GND
CS
4
C
+5V
FILTER SECTION A
FILTER SECTION B
STRAP PINS HIGH/LOW TO SET FILTER tC DATA.
FILTER DATA RELOADED ON EACH POWER-UP.
Figure 6. Independent fC Programming without a µP
14
Maxim Integrated
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Chip Information
Pin Configurations (continued)
PROCESS: BiCMOS
TOP VIEW
1
T/H OUT
T/H
24
2
V+
D6
23
3
OUTA
D5
22
4
SHDN
D4
21
5
INA
D3
20
6
V-
D2
19
7
INB
D1
18
8
MODE
D0
17
MAX271
9
OUTB
A0
16
10
GND
A1
15
11
T/H A/B
CS
14
12
WR
T/H EN
13
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 PDIP
P20-2
21-0043
—
20 SO (W)
W20-3
21-0042
90-0108
24 PDIP
N24-3
21-0043
—
24 SO (W)
W24-2
21-0042
90-0182
PDIP/SO(W)
Maxim Integrated
15
MAX270/MAX271
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
Revision History
REVISION
NUMBER
REVISION
DATE
0
4/91
Initial release
1
8/91
Revised Electrical Characteristics
2
1/12
Revised Ordering Information and Absolute Maximum Ratings.
DESCRIPTION
PAGES
CHANGED
—
2
1, 2
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
16
© 2012
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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