MAX32520-BNS+

Click here for production status of specific part numbers. MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller General Description Benefits and Features DeepCover® embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible. ● High-Efficiency Microcontroller for Secure Element IoT • Arm Cortex-M4F with FPU Up to 120MHz • 16KB Unified Code Cache • 2MB PUF Encrypted Flash Memory with Cache Provides Ultimate Firmware IP Protection • Low Latency On-the-Fly Decryption of Flash Execution • 136KB SRAM + 34KB ECC • 8KB User-Programmable OTP The DeepCover secure microcontroller MAX32520 provides an interoperable, secure, and cost-effective solution to build new generations of trusted embedded systems and communication devices such as IoT, IoT gateways, and wireless access points. The MAX32520 incorporates Maxim's patented ChipDNA™ PUF technology. ChipDNA technology involves a physically unclonable function (PUF) that enables cost-effective protection against invasive physical attacks. Using the random variation of semiconductor device characteristics that naturally occur during wafer fabrication, the ChipDNA circuit generates a unique output value that is repeatable over time, temperature, and operating voltage. Attempts to probe or observe ChipDNA operation modifies the underlying circuit characteristics, preventing discovery of the unique value used by the chip cryptographic functions. The MAX32520 utilizes the ChipDNA output as key content to cryptographically secure all device stored data including user firmware. User firmware encryption provides ultimate software IP protection. The ChipDNA can also generate a private key for the ECDSA signing operation. The MAX32520 integrates an Arm® Cortex® -M4 processor, 2MB of Flash, 136KB of system RAM + 34KB ECC, 8KB of one-time-programmable (OTP) memory and 128KB of boot ROM. The MAX32520 provides a FIPS/NIST compliant TRNG, environmental and tamper detection circuitry to facilitate system-level security. ● Secure Element • PUF-Based Keys • For Internal Flash Encryption • For Strong Device Authentication • Secure Boot Loader with Public Key Authentication and Serial Flash Emulation • AES, SHA, and ECDSA Accelerators • Hardware True Random Number Generator • SP800-90B Compliant Entropy Source • SP800-90A Compliant DRBG • Die Shield • Temperature and Voltage Tamper Monitor • External Tamper Sensor with Random Dynamic Pattern ● Power Management Maximizes Operating Time for Battery Applications • Single 3.3V/2.5V/1.8V Supply • Down to 3.2µA Backup Mode • 15µs Wake-Up Time from Standby Mode • Clock Gating, Power Gating, Registers, and Memory Retention Modes Multiple high-speed interfaces are supported including SPI, UART, and an I2C. The four on-chip timers also support PWM output generation for direct control of external devices. One of the SPI ports has a serial flash emulation mode allowing direct code fetching enabling secure boot for a host microcontroller. ● Multiple Peripherals for System Control • One UART • One I2C Interface • QSPI • Four Timers with PWM Capability • Up to 27 General-Purpose I/O Pins with Selectable Output Driver Strength • 4-Channel DMA Controller • 4-Pin JTAG Applications Ordering Information appears at end of data sheet. ● Embedded Connected Systems ● Secure Industrial Appliances, Sensors, and Controllers ● IoT Nodes and Gateways ● Embedded Communication Equipment (Routers, Gateways, etc.) ● Set-Top Boxes 19-100583; Rev 0; 6/19 Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DeepCover is a registered trademark and ChipDNA is a trademark of Maxim Integrated Products, Inc. MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Simplified Block Diagram POWER-ON RESET, BROWNOUT MONITOR, SUPPLY VOLTAGE MONITORS REG VSSA SINGLE OUTPUT VOLTAGE REGULATION & POWER CONTROL VDDA FLASH 2MB DUAL BANK MEMORY DECRYPTION UNIT CACHE 16KB SRAM 170KB (SEC-DED) ROM 128KB OTP 8KB CORE I/O ANALOG 4-CH DUAL DMA 2 × WATCHDOG TIMER www.maximintegrated.com 1 × 2-WIRE UART 1 x SPI MASTER/SLAVE (4 CS) 1 x SPI/QSPI MASTER/ SLAVE (2 CS) SERIAL FLASH EMULATION SHARED PAD FUNCTIONS TIMERS/PWM CAPTURE/ COMPARE MEMORY CACHE VDD Tx/Rx FIFO NVIC Tx/Rx FIFO 8kHz 1 × I2C MASTER/SLAVE Tx/Rx FIFO RSTN 7.3728MHz ARM® CORTEX® -M4 WITH FPU 120MHz MULTI-LAYER BUS MATRIX – AHB/APB 120MHz Tx/Rx FIFO MAX32520 SPI I 2C UART JTAG GPIO/ ALTERNATE FUNCTION UP TO 27 EXTERNAL INTERRUPTS EXTERNAL TAMPER 4 × 32-BIT TIMERS SECURITY ENVIRONMENTAL, EXTERNAL SENSORS & DIE MESH CHIP DNA PHYSICALLY UNCLONABLE FUNCTION(PUF) FLASH ENCRYPTION KEY ECDSA SIGNING KEY TRNG SP-800-90B, SP-800-90A AES 128, 192, 256 SHA-1/256/384/512 DES, 3DES FAULT DETECTORS ECDSA (UP TO P-521) RSA (SOFT) (UP TO 4096) Maxim Integrated | 2 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 32 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 30 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics—I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 32 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 30 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Arm Cortex-M4 with FPU Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Internal Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Internal ROM and Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ChipDNA Physically Unclonable Function (PUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 True Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Flash Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Cryptographic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AES Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ECDSA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SHA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Debug and Development Interface (SWD/JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Standard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 www.maximintegrated.com Maxim Integrated | 3 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller TABLE OF CONTENTS (CONTINUED) Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DeepSleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Wake-Up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Security Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Internal Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 External Tamper Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Secure Serial Boot/External Code Flash with JEDEC Flash Command Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Extended Secure Serial Boot/External Code Flash with Secure System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 www.maximintegrated.com Maxim Integrated | 4 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller LIST OF FIGURES Figure 1. SPI Master Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. SPI Slave Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. Timer Block Diagram, 32-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 www.maximintegrated.com Maxim Integrated | 5 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller LIST OF TABLES Table 1. Wake-Up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 www.maximintegrated.com Maxim Integrated | 6 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Absolute Maximum Ratings Continuous Power Dissipation (TA = +70°C) (Single-layer board, derate 21.3mW/°C above +70°C) ................................ 1702.1mW Continuous Power Dissipation TQFN (Multilayer Board) (TA = +70°C, derate 34.5mW/°C above +70°C.).................. 2758.6 mW Operating Temperature Range .......................... -40°C to +105°C Storage Temperature Range .............................. -65°C to +150°C VDD.......................................................................... -0.3V to 3.6V VDDA ........................................................................ -0.3V to 3.6V RSTN, GPIO ................................................. -0.3V to VDD + 0.5V VSSA ......................................................................................1mA VSS ....................................................................................100mA Output Current (sink) by Any GPIO Pin ...............................25mA Output Current (source) by Any GPIO Pin ......................... -25mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 32 TQFN Package Code T3255+8C Outline Number 21-0140 Land Pattern Number 90-0013 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) 47°C/W Junction to Case (θJC) 1.70°C/W Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 29°C/W Junction to Case (θJC) 1.70°C/W 30 WLP Package Code W302N2+1 Outline Number 21-100380 Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 49.38°C/W Junction to Case (θJC) N/A For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Input Supply Voltage, Digital VDD 1.71 1.8 3.6 V Input Supply Voltage, Analog VDDA 1.71 1.8 3.6 V www.maximintegrated.com Maxim Integrated | 7 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP VDD = 1.8V 10.6 IDD_ACT Total current into VDD pins, fSYS_CLK = 120MHz, CPU in Active mode, executing While(1) from cache, inputs tied to VSS, outputs source/sink 0mA VDD = 3.3V 10.7 VDD = 1.8V 2.16 VDD Current, Sleep Mode IDD_SLP Total current into VDD pins, fSYS_CLK = 120MHz, CPU in Sleep mode, inputs tied to VSS, outputs source/sink 0mA VDD = 3.3V 2.35 VDD Fixed Current, DeepSleep Mode IDD_FDSL Standby state with full retention VDD = 1.8V 65 VDD = 3.3V 69 VDD Current, Active Mode VDD Current, Backup Mode IDD_BK Total current into VDD pins, inputs tied to VSS, AES keys retained, outputs source/sink 0mA 72KB ECC memory retention, VDD = 1.8V 4.72 72KB ECC memory retention, VDD = 3.3V 6.74 No memory retention, VDD = 1.8V 3.22 No memory retention, VDD = 3.3V 5.25 32KB ECC memory retention, VDD = 1.8V 3.84 32KB ECC memory retention, VDD = 3.3V 5.87 64KB ECC memory retention, VDD = 1.8V 4.4 64KB ECC memory retention, VDD = 3.3V 6.5 MAX UNITS mA mA μA μA CLOCKS System Clock Frequency www.maximintegrated.com fSYS_CLK 0.0625 120,000 kHz Maxim Integrated | 8 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1/ System Clock Period tSYS_CLK fSYS_CL ns K Nano-ring Oscillator Frequency fNANO High-Speed Oscillator Frequency fHSCLK 7MHz Oscillator Frequency f7MCLK 8 115.5 120 kHz 124.5 7.3728 MHz MHz GENERAL-PURPOSE I/O Input Low Voltage for All GPIO VIL 0.3 x VDD V Input Low Voltage for RSTN VIL_RSTN 0.3 x VDD V Input High Voltage for All GPIO VIH 0.7 x VDD V Input High Voltage for RSTN VIH_RSTN 0.7 x VDD V Output Low Voltage for All GPIO Combined IOL, All GPIO Output High Voltage for All GPIO Combined IOH, All GPIO Input Hysteresis (Schmitt) VOL IOL_TOTAL VOH IOH_TOTAL VDD = 1.71V GPIOn_DS_SEL[1:0] = 00, IOL = 1mA 0.2 0.4 GPIOn_DS_SEL[1:0] = 01, IOL = 2mA 0.2 0.4 GPIOn_DS_SEL[1:0] = 10, IOL = 4mA 0.2 0.4 GPIOn_DS_SEL[1:0] = 11, IOL = 8mA 0.2 0.4 V GBD VDD = 1.71V 48 GPIOn_DS_SEL[1:0] = 00, IOL = -1mA VDD 0.4 GPIOn_DS_SEL[1:0] = 01, IOL = -2mA VDD 0.4 GPIOn_DS_SEL[1:0] = 10, IOL = -4mA VDD 0.4 GPIOn_DS_SEL[1:0] = 11, IOL = -8mA VDD 0.4 V GBD -48 VIHYS mA 300 mA mV Input Leakage Current Low IIL VDD = 3.6V, VIN = 0V, internal pullup disabled -1 +1 μA Input Leakage Current High IIH VDD = 3.6V, VIN = 3.6V, internal pulldown disabled -1 +1 μA www.maximintegrated.com Maxim Integrated | 9 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.) PARAMETER Input Pullup Resistor RSTN SYMBOL CONDITIONS MIN RPU_R Input Pullup/Pulldown Resistor for All GPIO TYP MAX UNITS 25 kΩ RPU1 Normal resistance 25 kΩ RPU2 Highest resistance 1 MΩ ENVIRONMENTAL SENSORS VDD Overvoltage Threshold VDD_OV 3.8 V VTM_LOTHSEL = [00] 1.56 1.66 1.76 VTM_LOTHSEL = [01] 2.1 2.2 2.3 VTM_LOTHSEL = [1x] 2.7 2.8 2.9 THTR GBD 115 125 135 TLTR1 GBD -70 -60 -50 TLTR2 GBD -50 -40 -30 MIN TYP MAX UNITS 60 MHz VDD Undervoltage Threshold VDD_UV High-Temperature Threshold Low-Temperature Threshold 3.6 V °C °C Electrical Characteristics—SPI (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MASTER MODE SPI Master Operating Frequency fMCK SPI Master SCK Period tMCK SCK Output PulseWidth High/Low fSYS_CLK = 120MHz, fMCK(MAX) = fSYS_CLK/2 1/fMCK ns tMCH, tMCL tMCK/2 ns MOSI Output Hold Time After SCK Sample Edge tMOH tMCK/2 ns MOSI Output Valid to Sample Edge tMOV tMCK/2 ns MOSI Output Hold Time After SCK Low Idle tMLH tMCK/2 ns MISO Input Valid to SCK Sample Edge Setup tMIS 5 ns MISO Input to SCK Sample Edge Hold tMIH tMCK/2 ns SLAVE MODE SPI Slave Operating Frequency fSCK SPI Slave SCK Period tSCK 1/fSCK SCK Input Pulse-Width High/Low tSCH, tSCL tSCK/2 www.maximintegrated.com 50 MHz ns Maxim Integrated | 10 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Electrical Characteristics—SPI (continued) (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SSx Active to First Shift Edge tSSE 10 ns MOSI Input to SCK Sample Edge Rise/Fall Setup tSIS 5 ns MOSI Input from SCK Sample Edge Transition Hold tSIH 1 ns MISO Output Valid After SCLK Shift Edge Transition tSOV 5 ns SCK Inactive to SSx Inactive tSSD 10 ns SSx Inactive Time tSSH 1/fSCK μs MISO Hold Time After SSx Deassertion tSLH 10 ns Electrical Characteristics—I2C (TIming specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STANDARD MODE Standard mode, from VIH(MIN) to VIL(MAX) Output Fall Time tOF 150 ns SCL Clock Frequency fSCL 0 Low Period SCL Clock tLOW 4.7 μs High Time SCL Clock tHIGH 4.0 μs Setup Time for Repeated Start Condition tSU;STA 4.7 μs Hold Time for Repeated Start Condition tHD;STA 4.0 μs Data Setup Time tSU;DAT 300 ns Data Hold Time 100 kHz tHD;DAT 10 ns Rise Time for SDA and SCL tR 800 ns Fall Time for SDA and SCL tF 200 ns Setup Time for a Stop Condition tSU;STO 4.0 μs tBUS 4.7 μs tVD;DAT 3.45 μs Bus Free Time Between a Stop and Start Condition Data Valid Time www.maximintegrated.com Maxim Integrated | 11 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Electrical Characteristics—I2C (continued) (TIming specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL Data Valid Acknowledge Time tVD;ACK CONDITIONS MIN TYP MAX 3.45 UNITS μs FAST MODE Output Fall Time tOF Pulse Width Suppressed by Input Filter tSP From VIH(MIN) to VIL(MAX) 150 ns 75 ns SCL Clock Frequency fSCL 0 Low Period SCL Clock tLOW 1.3 400 kHz μs High Time SCL Clock tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU;STA 0.6 μs Hold Time for Repeated Start Condition tHD;STA 0.6 μs Data Setup Time tSU;DAT 125 ns Data Hold Time tHD;DAT 10 ns Rise Time for SDA and SCL tR 30 ns Fall Time for SDA and SCL tF 30 ns Setup Time for a Stop Condition tSU;STO 0.6 μs tBUS 1.3 μs Data Valid Time tVD;DAT 0.9 μs Data Valid Acknowledge Time tVD;ACK 0.9 μs Bus Free Time Between a Stop and Start Condition FAST MODE PLUS Output Fall Time tOF Pulse Width Suppressed by Input Filter tSP From VIH(MIN) to VIL(MAX) 80 ns 75 ns SCL Clock Frequency fSCL 0 Low Period SCL Clock tLOW 0.5 1000 kHz μs High Time SCL clock tHIGH 0.26 μs Setup Time for Repeated Start Condition tSU;STA 0.26 μs Hold Time for Repeated Start Condition tHD;STA 0.26 μs Data Setup Time tSU;DAT 50 ns Data Hold Time tHD;DAT 10 ns www.maximintegrated.com Maxim Integrated | 12 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Electrical Characteristics—I2C (continued) (TIming specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise Time for SDA and SCL tR 50 ns Fall Time for SDA and SCL tF 30 ns Setup Time for a Stop Condition tSU;STO Bus Free Time Between a Stop and Start Condition 0.26 μs 0.5 tBUS μs Data Valid Time tVD;DAT 0.45 μs Data Valid Acknowledge Time tVD;ACK 0.45 μs SHIFT SAMPLE SHIFT SAMPLE SSx (SHOWN ACTIVE LOW) SCK CKPOL/CKPHA 0/1 OR 1/0 SCK CKPOL/CKPHA 0/0 OR 1/1 MOSI/SDIOx (OUTPUT) MISO/SDIOx (INPUT) tMCK tMCH tMCL tMOH MSB tMOV LSB MSB-1 tMIS MSB tMLH tMIH MSB-1 LSB Figure 1. SPI Master Mode Timing Diagram www.maximintegrated.com Maxim Integrated | 13 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller SHIFT SAMPLE SHIFT SAMPLE tSSE SSx (SHOWN ACTIVE LOW) tSSH tSSD tSCK SCK CKPOL/CKPHA 0/1 OR 1/0 tSCH tSCL SCK CKPOL/CKPHA 0/0 OR 1/1 tSIS MOSI/SDIOx (INPUT) tSIH MSB MSB-1 LSB tSOV MISO/SDIOx (OUTPUT) MSB tSLH MSB-1 LSB Figure 2. SPI Slave Mode Timing Diagram STOP START REPEAT START START tBUS SDA tOF tR tSU;STO tSP tSU;DAT tSU;STA tHIGH SCL tHD;STA tHD;DAT tVD;DAT tVD;ACK tLOW Figure 3. I2C Timing Diagram www.maximintegrated.com Maxim Integrated | 14 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller Pin Configuration P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 TOP VIEW P1.7 32 TQFN 24 23 22 21 20 19 18 17 RSTN 25 16 P0.15 P1.8 26 15 P0.14 VDD 27 14 P0.13 13 P0.12 REG 28 MAX32520 VSSA 29 12 P0.11 VDDA 30 11 P0.10 P1.9 31 EP* + 10 P0.9 9 P1.10 32 P0.8 8 P0.7 7 P0.6 6 P0.5 5 P0.4 4 P0.3 3 P0.2 2 P0.1 P0.0 1 5mm x 5mm *EP = EXPOSED PAD Pin Description FUNCTION MODE PIN NAME Primary Signal (Default) Alternate Function 1 Alternate Function 2 FUNCTION 1 P0.0 P0.0 UART_RXD — P0.0: GPIO0 Port 0 UART_RXD: UART Data Input 2 P0.1 P0.1 UART_TXD — P0.1: GPIO1 Port 0 UART_TXD: UART Data Output UART SPI 3 P0.2 P0.2 SPI0_DIO0 (MOSI0) SFSPIS_DIO0 (SFSI) P0.2: GPIO2 Port 0 SPI0_DIO0: Quad SPI I/O 0 (SPI0 Master Out Slave In) SFSPIS_DIO0: Serial Flash SPI Slave I/O 0 (SFSPI Slave In) 4 P0.3 P0.3 SPI0_DIO1 (MISO0) SFSPIS_DIO1 (SFSO) P0.3: GPIO3 Port 0 SPI0_DIO1: Quad SPI I/O 1 (SPI0 Master In Slave Out) SFSPIS_DIO1: Serial Flash SPI I/O 1 (SFSPI Slave Out) 5 P0.4 P0.4 SCK0 SFSPIS_SCK P0.4: GPIO4 Port 0 SCK0: SPI0 Clock SFSPIS_SCK: Serial Flash SPI Clock 6 P0.5 P0.5 SSEL0_0 SFSPIS_SS0 P0.5: GPIO5 Port 0 SSEL0_0: SPI0 Slave Select 0 SFSPIS_SS0: Serial Flash SPI Slave Select 0 www.maximintegrated.com Maxim Integrated | 15 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller 32 TQFN FUNCTION MODE PIN NAME Primary Signal (Default) Alternate Function 1 Alternate Function 2 FUNCTION 7 P0.6 P0.6 SSEL0_1 SFSPIS_SS1 P0.6: GPIO6 Port 0 SSEL0_1: SPI0 Slave Select 1 SFSPIS_SS1: Serial Flash SPI Slave Select 1 8 P0.7 P0.7 SPI0_DIO2 SFSPIS_DIO2 P0.7: GPIO7 Port 0 SPI0_DIO2: Quad SPI I/O 2 SFSPIS_DIO2: Serial Flash SPI I/O 2 9 P0.8 P0.8 SPI0_DIO3 SFSPIS_DIO3 P0.8: GPIO8 Port 0 SPI0_DIO3: Quad SPI I/O3 SFSPIS_DIO3: Serial Flash SPI I/O 3 12 P0.11 P0.11 MISO1 — P0.11: GPIO11 Port 0 MISO1: SPI1 Master In Slave Out 13 P0.12 P0.12 MOSI1 — P0.12: GPIO12 Port 0 MOSI1: SPI1 Master Out Slave In 14 P0.13 P0.13 SCK1 — P0.13: GPIO13 Port 0 SCK1: SPI1 Clock 15 P0.14 P0.14 SSEL1_0 — P0.14: GPIO14 Port 0 SSEL1_0: SPI1 Slave Select 0 16 P0.15 P0.15 SSEL1_1 — P0.15: GPIO15 Port 0 SSEL1_1: SPI1 Slave Select 1 10 P0.9 P0.9 SDA — P0.9: GPIO9 Port 0 SDA: I2C Data 11 P0.10 P0.10 SCL — P0.10: GPIO10 Port 0 SCL: I2C Clock 17 P1.0 P1.0 TCLK0 — P1.0: GPIO0 Port 1 TCLK0: Timer 0 Clock I/O 18 P1.1 P1.1 TCLK1 — P1.1: GPIO1 Port 1 TCLK1: Timer 1 Clock I/O 23 P1.6 P1.6 TCLK2 SSEL1_2 P1.6: GPIO6 Port 1 TCLK2: Timer 2 Clock I/O SSEL1_2: SPI1 Slave Select 2 24 P1.7 P1.7 TCLK3 SSEL1_3 P1.7: GPIO7 Port 1 TCLK3: Timer 3 Clock I/O SSEL1_3: SPI1 Slave Select 3 19 P1.2 P1.2 TDI — P1.2: GPIO2 Port 1 TDI: JTAG Test Data Input 20 P1.3 P1.3 TDO — P1.3: GPIO3 Port 1 TDO: JTAG Test Data Output 21 P1.4 P1.4 TMS/SWDIO — P1.4: GPIO4 Port 1 TMS/SWDIO: JTAG Mode Select / Single Wire Debug I/O I²C TIMER JTAG www.maximintegrated.com Maxim Integrated | 16 MAX32520 ChipDNA Secure Arm Cortex M4 Microcontroller 32 TQFN FUNCTION MODE PIN NAME Primary Signal (Default) Alternate Function 1 Alternate Function 2 FUNCTION 22 P1.5 P1.5 TCK/SWCLK — P1.5: GPIO5 Port 1 TCK/SWCLK: JTAG Test Clock / Single Wire Debug Clock EXTERNAL TAMPER 26 P1.8 P1.8 EXT_SENS_OU T — P1.8: GPIO8 Port 1 EXT_SENS_OUT: External Sensor Output 31 P1.9 P1.9 EXT_SENS_IN — P1.9: GPIO9 Port 1 EXT_SENS_IN: External Sensor Input 32 P1.10 P1.10 TAMPER_OUT — P1.10: GPIO10 Port 1 TAMPER_OUT: External Tamper Detection Output. This pin is active when external tamper is detected. POWER AND SYSTEM 27 VDD VDD — — VDD: Core and I/O supply voltage. Bypass VDD with 1μf and 100nF capacitors with ESR