MAX32620/MAX32621
General Description
DARWIN is a new breed of low-power microcontrollers built
to thrive in the rapidly evolving Internet of Things (IoT).
They are smart, with the biggest memories in their class
and a massively scalable memory architecture. They run
forever, thanks to wearable-grade power technology. They
are also tough enough to withstand the most advanced
cyberattacks. DARWIN microcontrollers are designed to
run any application imaginable—in places where you
would not dream of sending other microcontrollers.
Generation U microcontrollers are perfect for wearables
and IoT applications that cannot afford to compromise
power or performance. The MAX32620/MAX32621 feature an Arm® Cortex®-M4 with FPU CPU that delivers
high-efficiency signal processing, ultra-low power consumption and ease of use.
Flexible power modes, an intelligent PMU, and dynamic
clock and power gating optimize performance and power
consumption for each application. Internal oscillators run
at 96MHz for high-performance or 4MHz to maximize
battery life in applications requiring always-on monitoring.
Multiple SPI, UART, I2C, 1-Wire® master, and USB interfaces are provided. The four-input, 10-bit ADC with selectable references can monitor external sensors.
All versions provide a hardware AES engine. The
MAX32621 is provides a secure trust protection unit
(TPU) with a modular arithmetic accelerator (MAA) for
fast ECDSA, a hardware PRNG entropy generator, and a
secure boot loader. The MAX32620L provides a reduced
1MB of flash memory.
This data sheet applies to revision C and later. Legacy
mode operation provides compatibility with revision A.
Applications
●●
●●
●●
●●
●●
Sport Watches
Fitness Monitors
Wearable Medical Patches
Portable Medical Devices
Sensor Hub
Arm and Cortex are registered trademarks of Arm Limited (or its
subsidiaries) in the US and/or elsewhere.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Ordering Information appears at end of data sheet.
19-7679; Rev 4; 10/18
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Benefits and Features
●● High-Efficiency Microcontroller for Wearable Devices
• Internal Oscillator Operates Up to 96MHz
• Low Power 4MHz Option for Always-On Monitoring
• 2MB/1MB Flash Memory
• 256KB SRAM
• 8KB Instruction Cache
• 1.2V Core Supply Voltage
• 1.8V to 3.3V I/O
• Optional 3.3V ±5% USB Supply Voltage
• Wide Operating Temperature: -30°C to +85°C
●● Power Management Maximizes Uptime for Battery
Applications
• 122µW/MHz Active Executing from Cache
• 62µW/MHz Active Executing from Flash
• Wake-Up to 96MHz Clock or 4MHz Clock
• 1.06µW Low Power Mode (LP0) Mode with RTC
• 2.67µW Ultra-Low Power Data Retention Sleep
Mode (LP1) with Fast 5µs (typ) Wakeup on 96MHz
• 28μW/MHz Low Power Mode (LP2) Current
●● Optimal Peripheral Mix Provides Platform Scalability
• Three SPI Masters, One SPI Slave
• Four UARTs
• Up to Three I2C Masters, One I2C Slave
• 1-Wire® Master
• Up to 49 General-Purpose I/O Pins
• SPI Execute in Place (SPIX) Engine for Memory
Expansion with Minimal Footprint
• Full-Speed USB 2.0 with Internal Transceiver
• Sixteen Pulse Train Engines
• Six 32-Bit or 12 16-Bit Timers
• Three Watchdog Timers with Independent Sources
• Four-Input, 10-Bit Sigma-Delta ADC Operating at
7.8kS/s, 5.5V, and 1.8V Tolerant Inputs
• AES-128, -192, -256 Hardware Engine
• RTC Calibration Output
• JTAG 1149.1 Compatible with Serial Wire Debug
●● Secure Valuable IP and Data with Robust Internal
Hardware Security (MAX32621 Only)
• Trust Protection Unit (TPU) Provides ECDSA and
Modular Arithmetic Acceleration Support
• True Random Number Generator (TRNG)
• Secure Boot Loader
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
MAX32620/MAX32621 Block Diagram
MAX32620/MAX32621
96 MHz
SRSTN
NVIC
6 × 32 BIT TIMERS
MEMORY
16 × PULSE TRAIN
ENGINE
JTAG SWD (Serial
Wire Debug)
256KB SRAM
PERIPHERAL
MANAGEMENT UNIT
VOLTAGE
REGULATION &
POWER CONTROL
32KHz OUTPUT
32KHz
CRYSTAL
2 × WINDOWED
WATCHDOG TIMER
RECOVERY
WATCHDOG TIMER
3 × SPI MASTER
TIMERS/PWM
CAPTURE/COMPARE
3 × I2C MASTER
DP
VDDB
EXTERNAL
INTERRUPTS
1 × I2C SLAVE
(MAX. 3 PORTS)
INDIVIDUALLY
SELECTABLE
VDDIO OR VDDIOH
SUPPLY
FOR EACH PIN
4 × UART
1-WIRE MASTER
REAL-TIME
CLOCK
UP TO 49
GPIO/
SPECIAL
FUNCTION
SPI
SPI XIP
I 2C
UART
1-Wire
1 × SPI XIP
WAKE UP TIMER
1.2V
CRC 16/32
DM
GPIO AND
SHARED PAD
FUNCTIONS
1 × SPI SLAVE
8KB CACHE
16B FIFOS
VDDIOH
VDDIO
VDD12
VDD18
VRTC
VSS
VDDA
VSSA
POR,
BROWNOUT
MONITOR,
SUPPLY VOLTAGE
MONITORS
BUS MATRIX – AHB, APB, IBUS, DBUS…
RSTN
32B FIFOS
2MB/1MB FLASH
32B FIFOS
TCK / SWCLK
TMS / SWDIO
TDO
TDI
GPIO WITH
INTERRUPTS
ARM CORTEX-M4
WITH FPU CORE
4 MHz
AES-128,-192,-256
USB 2.0 FULL
SPEED
CONTROLLER
VREF
VDDIO
VDDIOH
UNIQUE ID
TRUST PROTECTION UNIT (TPU)
MAA
SECURE NV KEY
TRNG
MAX32621 ONLY
www.maximintegrated.com
10-BIT
ΣΔ ADC
÷5
÷5
÷2
÷4
AIN0
AIN1
AIN2
AIN3
VDDB
VDD18
VDD12
VRTC
Maxim Integrated │ 2
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Absolute Maximum Ratings
(All voltages with respect to VSS, unless otherwise noted.)
VDD18 .................................................................-0.3V to +1.89V
VDD12..................................................................-0.3V to +1.26V
VDDA with respect to VSSA.................................-0.3V to +1.89V
VRTC....................................................................-0.3V to +1.89V
VDDB.....................................................................-0.3V to +3.6V
VREF......................................................................-0.3V to +3.6V
32KIN, 32KOUT.........................................-0.3V to VRTC + 0.2V
RSTN, SRSTN, GPIO, DP, DM, JTAG..................-0.3V to +3.6V
AIN[1:0].................................................................-0.3V to +5.5V
AIN[3:2].................................................................-0.3V to +3.6V
VDDIO....................................................................-0.3V to +3.6V
VDDIOH..................................................................-0.3V to +3.6V
Total current VDD18, VDDIO(sink)......................................100mA
Total current VSS...............................................................100mA
Output current (sink) by Any I/O pin................................... 25mA
Output current (source) by Any I/O pin..............................-25mA
Continuous Power Dissipation (TA = +70°C)
TQFP (multilayer board)
(derate 45.5mW/°C above +70°C)..........................3636.4mW
Operating Temperature Range............................ -30°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
Package Thermal Characteristics (Note 1)
TQFP-EP
Junction-to-Ambient Thermal Resistance (θJA)...........22°C/W
Junction-to-Case Thermal Resistance (θJC)..................2°C/W
WLP
Junction-to-Ambient Thermal Resistance (θJA)...........36°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
Supply Voltage
SYMBOL
MIN
TYP
MAX
VDD18
1.71
1.8
1.89
VDD12
1.14
1.2
1.26
VDDA
1.71
1.8
1.89
VRTC
1.71
1.8
1.89
VDDB
3.04
3.3
3.60
VDDIO
1.71
1.8
3.60
VDDIOH must be ≥ VDDIO
1.71
1.8
3.60
1.1
VDDIOH
CONDITIONS
V
Power-Fail Reset Voltage
VRST
Monitors VDD18
Power On Reset Voltage
VPOR
Monitors VDD18
1.5
V
RAM Data Retention Voltage
VDRV
VDD12 supply, retention in LP1
0.93
V
Measured on the VDD12 pin and executing
code from cache memory, all inputs are tied to
VSS or VDDIO, outputs do not source/sink any
current, PMU disabled
102
µA/
MHz
VDD12 Dynamic Current,
LP3 Mode
www.maximintegrated.com
IDD12_DLP3
1.70
UNITS
V
Maxim Integrated │ 3
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Electrical Characteristics (continued)
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
VDD12 Current,
LP3 Mode
VDD18 Current,
LP3 Mode
VRTC Current,
LP3 Mode
VDD12 Dynamic Current,
LP2 Mode
VDD12 Current,
LP2 Mode
VDD18 Current,
LP2 Mode
VRTC Current,
LP2 Mode
www.maximintegrated.com
SYMBOL
IDD12_LP3
IDD18_LP3
IRTC_LP3
IDD12_DLP2
IDD12_LP2
IDD18_LP2
IRTC_LP2
CONDITIONS
MIN
TYP
96MHz oscillator selected as system clock,
measured on the VDD12 pin and executing
code from cache memory, all inputs are tied to
VSS or VDDIO, outputs do not source/sink any
current
96
4MHz oscillator selected as system clock
measured on the VDD12 pin and executing
code from cache memory, all inputs are tied to
VSS or VDDIO, outputs do not source/sink any
current
49
96MHz oscillator selected as system clock,
measured on the VDD18 pin and executing
code from cache memory, all inputs are tied to
VSS or VDDIO, outputs do not source/sink any
current
366
4MHz oscillator selected as system clock,
measured on the VDD18 pin and executing
code from cache memory, all inputs are tied to
VSS or VDDIO, outputs do not source/sink any
current.
33
MAX
UNITS
µA
µA
RTC disabled
1.15
µA
RTC enabled
1.55
µA
Measured on the VDD12 pin, Arm in sleep
mode, PMU with two channels active
23
µA/
MHz
96MHz oscillator selected as system clock,
measured on the VDD12 pin, Arm in sleep
mode, system clock stopped
96
4MHz oscillator selected as system clock,
measured on the VDD12 pin, Arm in sleep
mode, system clock stopped
49
96MHz oscillator selected as system clock,
Arm in sleep mode, PMU with two channels
active, all inputs are tied to VSS or VDDIO,
outputs do not source/sink any current
366
4MHz oscillator selected as system clock, Arm
in sleep mode, PMU with two channels active,
all inputs are tied to VSS or VDDIO, outputs do
not source/sink any current
33
µA
µA
RTC disabled
1.15
µA
RTC enabled
1.55
µA
Maxim Integrated │ 4
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Electrical Characteristics (continued)
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD12 Current,
LP1 Mode
IDD12_LP1
Standby state with full data retention
1.11
µA
VDD18 Current,
LP1 Mode
IDD18_LP1
Standby state with full data retention
120
nA
VRTC Current,
LP1 Mode
IRTC_LP1
RTC disabled
244
nA
RTC enabled
594
nA
VDD12 Current,
LP0 Mode
IDD12_LP0
14
nA
VDD18 Current,
LP0 Mode
IDD18_LP0
120
nA
VRTC Current,
LP0 Mode
IRTC_LP0
RTC disabled
105
nA
RTC Operating Current
LP2 Mode Resume Time
RTC enabled
505
nA
IRTC_LP23
LP3, LP2 modes
0.7
µA
IRTC_LP01
LP1, LP0 modes
0.35
µA
tLP2_ON
0
µs
LP1 Mode Resume Time
tLP1_ON
5
µs
LP0 Mode Resume Time
tLP0_ON
11
µs
CLOCKS
Factory default
94
96.0
98
MHz
95.76
96.0
96.24
MHz
fRCCLK
0.001
4
4.1
MHz
fCK
0.371
97.92
MHz
Internal Relaxation Oscillator
Frequency
fINTCLK
Internal RC Oscillator
Frequency
System Clock Frequency
System Clock Period
tCK
RTC Input Frequency
f32KIN
RTC Power Up Time
tRTC_ ON
Firmware trimmed, required for USB
compliance
1/fCK
32kHz watch crystal, 6pF, ESR < 70kΩ
32.768
kHz
250
ms
GENERAL PURPOSE I/O
Input Low Voltage for SRSTN,
and All Port Pins
VIL
Legacy VDD18 I/O supply, includes JTAG
0.3 x
VDD18
VDDIO selected as I/O supply, includes JTAG
0.3 x
VDDIO
VDDIOH selected as I/O supply
Input Low Voltage for RSTN
www.maximintegrated.com
0.3 x
VDDIOH
Legacy VDD18 I/O supply
0.3 x
VRTC
VDDIO or VDDIOH selected as I/O supply
0.3 x
VRTC
VIL
V
V
Maxim Integrated │ 5
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Electrical Characteristics (continued)
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
Input High Voltage for SRSTN,
and All Port Pins
SYMBOL
VIH
CONDITIONS
Legacy VDD18 I/O supply, includes JTAG
0.7 x
VDD18
VDDIO selected as I/O supply, includes JTAG
0.7 x
VDDIO
VDDIOH selected as I/O supply
Input High Voltage for RSTN
Input Hysteresis (Schmitt)
Output Low Voltage for All Port
Pins
Combined IOL, All GPIO
Output High Voltage for All
Port Pins
www.maximintegrated.com
MIN
0.7 x
VRTC
VDDIO or VDDIOH selected as I/O supply
0.7 x
VRTC
VIHYS
VOL
UNITS
V
V
100
mV
IOL = 4mA (normal drive), legacy VDD18 I/O
supply, includes JTAG
0.2
0.4
IOL = 24mA (high drive), legacy VDD18 I/O
supply, includes JTAG
0.2
0.4
IOL = 4mA (normal drive), VDDIO = VDDIOH =
1.71V, VDDIO selected as I/O supply, includes
JTAG
0.2
0.4
IOL = 24mA (high drive), VDDIO = VDDIOH =
1.71V, VDDIO selected as I/O supply
0.2
0.4
IOL = 900μA, VDDIO = 1.71V, VDDIOH = 2.97V,
VDDIOH selected as I/O supply
0.2
0.45
IOL_TOTAL
VOH
MAX
0.7 x
VDDIOH
Legacy VDD18 I/O supply
VIH
TYP
48
IOH = -2mA (normal drive), legacy VDD18 I/O
supply, includes JTAG
VDD18
- 0.4
IOH = -8mA (high drive), legacy VDD18 I/O
supply, includes JTAG
VDD18
- 0.4
IOH = -2mA (normal drive), VDDIO = VDDIOH =
1.7V, VDDIO selected as I/O supply, includes
JTAG
VDDIO
- 0.4
IOH = -8mA (high drive), VDDIO = VDDIOH =
1.7V, VDDIO selected as I/O supply, includes
JTAG
VDDIO
- 0.4
IOH = -300μA, VDDIOH = 2.97V, VDDIOH
selected as I/O supply
VDDIO
- 0.4
IOH = -2mA, VDDIO = 1.71V, VDDIOH = 2.97V,
VDDIO selected as I/O supply
VDDIO
- 0.45
V
mA
V
Maxim Integrated │ 6
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Electrical Characteristics (continued)
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
Combined IOH, All GPIO
Input/Output Pin Capacitance
for All Port Pins
Input Leakage Current Low
SYMBOL
MIN
TYP
IOH_TOTAL
CIO
IIL
IIH
Input Leakage Current High
CONDITIONS
IOFF
IIH3V
MAX
UNITS
48
mA
3
pF
VDD18 = 1.89V VIN = 0V,
internal pullup disabled, legacy VDD18 I/O
supply
-100
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
selected as I/O supply, VIN = 0V, internal
pullup disabled
-100
+100
VDD18 = 1.89V, VIN = 1.89V, internal pulldown
disabled, legacy VDD18 I/O supply
-100
+100
VDDIO = 1.89V, VDDIOH = 3.6V, VIN = 3.6V,
internal pulldown disabled, VDDIOH selected
as I/O supply
-100
+100
VDD18 = 0V, VIN < 1.89V, legacy VDD18 I/O
supply
-1
+1
VDDIO = 0V, VDDIOH = 0V, VDDIO selected as
I/O supply, VIN < 1.89V
-1
+1
VDD18 = 1.71V, VIN = 3.60V, legacy VDD18 I/O
supply
-2
+2
VDDIO = VDDIOH = 1.71V, VDDIO selected as
I/O supply, VIN =3.6V
-2
+100
nA
nA
µA
µA
+2
Input Pullup Resistor, SRSTN,
TMS, TCK, TDI
RPU_VDDIO
Pullup to VDDIO
25
kΩ
Input Pullup Resistor RSTN
RPU_VRTC
Pullup to VRTC
25
kΩ
Normal resistance mode
25
kΩ
Highest resistance mode
1
MΩ
8
kB
Input Pullup/Pulldown All
GPIO
RPU_GPIO
FLASH MEMORY
Page Size
Flash Erase Time
Flash Programming Time Per
Word
tM_ERASE
Mass erase
30
ms
tP_ERASE
Page erase
30
ms
60
µs
tPROG
Flash Endurance
Data Retention
www.maximintegrated.com
tRET
TA = +85°C
10
kcycles
10
years
Maxim Integrated │ 7
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
USB Electrical Characteristics
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2.0
UNITS
Single-Ended Input High Voltage DP, DM
VIHD
Single-Ended Input Low Voltage DP, DM
VILD
Output Low Voltage DP, DM
VOLD
RL = 1.5kΩ from DP to 3.6V
Output High Voltage DP, DM
VOHD
RL = 15kΩ from DP and DM to VSS
2.8
V
V
Differential Input Sensitivity DP, DM
VDI
DP to DM
0.2
Common-Mode Voltage Range
VCM
Includes VDI range
0.8
Single-Ended Receiver Threshold
VSE
Single-Ended Receiver Hysteresis
VSEH
Differential Output Signal
Cross-Point Voltage
VCRS
DP, DM Off-State Input Impedance
RDRV
DP Pullup Resistor
RPU
0.8
V
0.3
V
2.5
0.8
2.0
200
CL = 50pF, GBD
RLZ
Driver Output Impedance
V
V
mV
1.3
2.0
300
V
kΩ
Steady-state drive
28
44
Idle
0.9
1.575
1.425
3.090
Receiving
V
Ω
kΩ
USB TIMING
DP, DM Rise Time (Transmit)
tR
CL = 50pF, GBD
4
20
ns
DP, DM Fall Time (Transmit)
tF
CL = 50pF, GBD
4
20
ns
tR, tF
CL = 50pF, GBD
90
110
%
Rise/Fall Time Matching (Transmit)
ADC Electrical Characteristics
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
fACLK
ADC Clock Period
tACLK
www.maximintegrated.com
MAX
10
ADC Clock Rate
Input Voltage Range
TYP
VAIN
UNITS
bits
0.1
8
1/fACLK
MHz
µs
AIN[3:0], ADC_CHSEL = 0–3,
BUF_BYPASS = 1
VSSA
VDDA
AIN[1:0], ADC_CHSEL = 4–5,
BUF_BYPASS = 1
VSSA
5.5V
AIN[3:0], ADC_CHSEL = 0–3,
BUF_BYPASS = 0
50mV
VDDA 50mV
AIN[1:0], ADC_CHSEL = 4-5,
BUF_BYPASS = 0
50mV
5.5V
V
Maxim Integrated │ 8
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
ADC Electrical Characteristics (continued)
(Limits are tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
Input Impedance
RAIN
Input Dynamic Current, Switched
Capacitance
IAIN
Analog Input Capacitance
CAIN
CONDITIONS
MIN
TYP
MAX
UNITS
AIN[1:0], ADC_HSEL = 4–5, ADC active
45
kΩ
ADC active, ADC buffer bypassed
4.5
µA
ADC active, ADC buffer enabled
50
nA
Fixed capacitance to ground
1
pF
Dynamically switched capacitance
250
nF
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Offset Error
VOS
±1
LSb
Gain Error
GE
±2
LSb
240
µA
53
µA
ADC Active Current
Input Buffer Active Current
ADC Setup Time
IADC
IINBUF
tADC_SU
ADC Output Latency
tADC
ADC Sample Rate
fADC
ADC Input Leakage
IADC_LEAK
Signal to Noise Ratio
Signal to Noise and Distortion
Total Harmonic Distortion
Spurious Free Dynamic Range
VFS
LSb
±1
LSb
Any power-up of: ADC clock, ADC
bias, reference buffer, or input buffer to
CpuAdcStart
10
µs
Any power-up of: ADC clock
or ADC bias to CpuAdcStart
48
tACLK
1025
tACLK
7.80
ksps
AIN0 or AIN1, ADC inactive or channel
not selected
0.12
4
nA
AIN2 or AIN3, ADC inactive or channel
not selected
0.02
1.0
nA
ADC_CHSEL = 4 or 5, not including
ADC offset/gain error
AIN0/AIN1 Resistor Divider Error
Full-Scale Voltage
ADC active, reference buffer enabled,
input buffer disabled
±2
ADC code = 0x3FF
±2
LSb
1.20
V
SNR
58.5
dB
SINAD
58.5
dB
THD
-68.5
dB
74
dB
Bandgap Temperature Coefficient
VTEMPCO
SFDR
Box method
30
ppm/°C
Reference Input Capacitance
CREF_IN
Dynamically switched capacitance, ADC_
XREF=1, ADC active
250
fF
External Reference Voltage
VREF_EXT
ADC_XREF = 1
Reference Dynamic Current
IREF_EXT
ADC_XREF=1, ADC active
www.maximintegrated.com
1.17
1.23
4.1
1.29
V
µA
Maxim Integrated │ 9
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Electrical Characteristics—SPI Master/SPIX Master
(Timing specifications are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
48
MHz
Master Operating
Frequency
fMCK
Master SCLK Period
tMCK
SCLK Output Pulse-Width
High
tMCH
tMCK/2
ns
SCLK Output Pulse-Width
Low
tMCL
(tMCK/2) - 4
ns
MOSI Output Hold Time
After SCLK Sample Edge
tMOH
(tMCK/2) - 4
ns
MOSI Output Valid to
Sample Edge
tMOV
(tMCK/2) - 4
ns
MISO Input Valid to SCLK
Sample Edge Setup
tMIS
1
ns
MISO Input to SCLK
Sample Edge
tMIH
SHIFT
1/fMCK
ns
1
SAMPLE
SHIFT
ns
SAMPLE
SS
tMCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tMCL
tMCH
tMOH
tMOV
MSB
MOSI/
SDIO (OUTPUT)
tMIS
MISO/
SDIO (INPUT)
MSB
LSB
MSB-1
tMIH
MSB-1
LSB
Figure 1. SPI Master and SPI XIP Master Timing
www.maximintegrated.com
Maxim Integrated │ 10
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Electrical Characteristics—SPI Slave
(Timing specifications are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
Slave Operating
Frequency, Write
fSCK_W
Slave Operating
Frequency
fSCK_R
SCLK Period
CONDITIONS
MIN
TYP
MAX
Standard SPI mode
48
Fast SPI mode
48
Standard SPI mode
22.7
Fast SPI mode
45.5
tSCK
1/fSCK
UNITS
MHz
MHz
ns
Electrical Characteristics—I2C Bus
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range
are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C BUS
Standard mode, VDDIO selected as
I/O supply
Input High Voltage
Input Low Voltage
Input Hysteresis
(Schmitt)
Output Logic-Low
(Open Drain or Open
Collector)
VIH_I2C
VIL_I2C
VIHYS_I2C
VOL_I2C
Standard mode, VDDIOH selected as
I/O supply
Fast mode, VDDIO selected as I/O
supply
0.7 ×
VDDIO
0.7 ×
VDDIOH
0.7 ×
VDDIO
VDDIO +
0.5
Fast mode, VDDIOH selected as I/O
supply
0.7 ×
VDDIOH
VDDIOH
+ 0.5
Standard mode, VDDIO selected as
I/O supply
-0.5
0.3 ×
VDDIO
Standard mode, VDDIOH selected as
I/O supply
-0.5
0.3 ×
VDDIOH
Fast mode, VDDIO selected as I/O
supply
-0.5
0.3 ×
VDDIO
Fast mode, VDDIOH selected as I/O
supply
-0.5
0.3 ×
VDDIOH
Fast mode, VDDIO selected as I/O
supply
Fast mode, VDDIOH selected as I/O
supply
0.05 x
VDDIO
V
V
V
0.05 x
VDDIOH
Standard mode, IIL = 3mA
0
0.4
Fast mode, IIL = 3mA
0
0.4
Fast mode, IIL = 2mA, VDDIO selected
as I/O supply
0
0.2 x
VDDIO
Fast mode, IIL = 2mA, VDDIOH
selected as I/O supply
0
0.2 x
VDDIOH
Standard mode
0
100
Fast mode
0
400
V
I2C TIMING
SCL Clock Frequency
www.maximintegrated.com
fSCL
kHz
Maxim Integrated │ 11
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Typical Operating Characteristics
(VDD18 = 1.8V, VDD18 = 1.8V.)
IDD12 vs. FREQUENCY
(INTERNAL 96MHz OSCILLATOR)
12
toc01
400
350
IDD12 (μA)
IDD12 (mA)
8
6
300
250
200
4
150
100
2
50
0
20
40
60
80
0
100
0
1
TOTAL POWER vs. FREQUENCY
(INTERNAL 96MHz OSCILLATOR)
14
8
6
LP2
4
TOTAL POWER =
(IDD18 x 1.8V) + (IDD12 x 1.2V)
600
LP3
10
3
TOTAL POWER vs. FREQUENCY
(INTERNAL 4MHz OSCILLATOR)
700
TOTAL POWER (μW)
TOTAL POWER (mW)
toc03
TOTAL POWER =
(IDD18 x 1.8V) + (IDD12 x 1.2V)
12
2
4
FREQUENCY (MHz)
FREQUENCY (MHz)
2
0
toc02
450
10
0
IDD12 vs. FREQUENCY
(INTERNAL 4MHz OSCILLATOR)
500
toc04
LP3
500
400
LP2
300
200
100
0
20
40
60
FREQUENCY (MHz)
www.maximintegrated.com
80
100
0
0
1
2
3
4
FREQUENCY (MHz)
Maxim Integrated │ 12
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
N.C.
N.C.
N.C.
N.C.
32KIN
32KOUT
N.C.
VSS
VRTC
VSS
VDDB
VSS
VDDIO*
DP
DM
N.C.
P4.7
P4.6
P4.5
P4.4
P4.2
P4.3
P4.0
P4.1
TOP VIEW
N.C.
Pin Configuration
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
N.C.
76
N.C.
77
49
P5.0
N.C.
78
48
P5.1
P3.7
79
47
P5.2
P3.6
80
46
VDDIOH*
P3.5
81
45
P5.3
P3.4
82
44
P5.4
P3.3
83
43
N.C.
P3.2
84
42
VSS
P3.1
85
41
AIN3
P3.0
86
40
TDI
N.C.
87
P2.7
88
P2.6
89
37
AIN1
VSS
90
36
TMS
VDD18
91
35
AIN0
P2.5
92
34
VREF
P2.4
93
33
VSSA
P2.3
94
32
N.C.
P2.2
95
31
TCK
P2.1
96
30
P5.5
P2.0
97
N.C.
98
P1.7
99
50
MAX32620
MAX32621
*EP = EXPOSED PAD
+
AIN2
TDO
29
VDDA
28
P5.6
27
P5.7
26
N.C.
N.C.
P6.0
RSTN
SRSTN
VDD12
P0.0
VSS
P0.1
P1.4
P0.2
P1.5
P0.3
VSS
P1.6
www.maximintegrated.com
P0.4
VDDIO*
* VDD18 in legacy mode
39
38
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P0.5
8
P0.6
7
P0.7
6
N.C.
5
P1.0
4
P1.1
3
P1.2
2
P1.3
1
N.C.
N.C. 100
N.C.
100 TQFP-EP
Maxim Integrated │ 13
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Pin Configuration (continued)
MAX32620
MAX32621
TOP VIEW (BUMP SIDE DOWN)
1
2
3
4
5
6
7
8
9
A
N.C.
VSSA
VREF
AIN0
AIN1
AIN2
AIN3
VDDIOH*
N.C.
B
SRSTN
RSTN
VDDA
TCK
TMS
TDO
TDI
VSS
32KIN
C
P0.1
P0.0
P6.0
P5.7
P5.5
P5.4
P5.2
VRTC
32KOUT
D
P0.4
P0.5
P0.3
P0.2
P5.6
P5.3
P5.0
VDDB
VSS
E
P1.0
P0.7
P0.6
P1.1
P1.5
P3.1
P5.1
DP
VDDIO*
F
VDD12
P1.3
P1.2
P1.4
P3.0
P3.5
P3.7
DM
P4.7
G
VSS
P1.6
P1.7
P2.4
P2.6
P3.4
P4.4
P4.6
P4.5
H
VDDIO*
P2.1
P2.2
P2.5
P2.7
P3.2
P4.1
P4.3
P4.2
J
N.C.
P2.0
P2.3
VDD18
VSS
P3.3
P3.6
P4.0
N.C.
+
81 WLP
* VDD18 IN LEGACY MODE
www.maximintegrated.com
Maxim Integrated │ 14
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Pin Description
PIN
TQFP-EP
WLP
NAME
FUNCTION
POWER
61
D8
VDDB
USB Transceiver Supply Voltage. This pin must be bypassed to VSS with a 1.0µF capacitor
as close as possible to this pin.
8
F1
VDD12
1.2V Supply Voltage. This pin must be bypassed to VSS with a 1.0µF capacitor as close as
possible to this pin.
59
C8
VRTC
RTC Supply Voltage. This pin must be bypassed to VSS with a 1.0µF capacitor as close as
possible to this pin.
29
B3
VDDA
Analog Supply Voltage. This pin must be bypassed to VSSA with a 1.0µF capacitor as close
as possible to this pin.
91
J4
VDD18
1.8V Supply Voltage. This pin must be bypassed to VSS with a 1.0µF capacitor as close as
possible to this pin.
2, 63
E9, H1
VDDIO
I/O Supply Voltage. 1.8V ≤ VDDIO ≤ 3.6V. See EC table for VDDIO specification. This pin
must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. This
pin can be connected to VDD18 for legacy I/O support.
46
A8
VDDIOH
I/O Supply Voltage, High. 1.8V ≤ VDDIOH ≤ 3.6V, always with VDDIO ≤ VDDIOH. See EC table
for VDDIOH specification. This pin must be bypassed to VSS with a 1.0μF capacitor as close as
possible to the package. This pin can be connected to VDD18 for legacy I/O support.
34
A3
VREF
ADC Reference. This pin should be left unconnected if an external reference is not used.
3, 7, 42,
58, 60,
62, 90
B8, D9,
G1, J5
VSS
Digital Ground.
33
A2
VSSA
Analog Ground. This pin must be connected to VSS.
EP
—
EP
55
B9
32KIN
56
C9
32KOUT
64
E8
DP
USB D+ Signal. This bidirectional pin carries the positive differential data or single-ended
data. This pin is weakly pulled high internally when the USB is disabled.
65
F8
DM
USB D- Signal. This bidirectional pin carries the negative differential data or single-ended
data. This pin is weakly pulled high internally when the USB is disabled.
B4
TCK
JTAG Clock
Serial Wire Debug Clock
This pin has an internal 25kΩ pullup to VDDIO.
Exposed Pad (TQFP Only). This pad must be connected to VSS. Refer to Application Note
3273: Exposed Pads: A Brief Introduction for additional information.
CLOCKS
32kHz Crystal Oscillator Input/Output. Connect a 6pF 32kHz crystal between 32KIN and
32KOUT for RTC operation. Optionally, an external clock source can be driven on 32KIN if
the 32KOUT pin is left unconnected. A 32kHz crystal or external clock source is required for
proper USB operation.
USB
JTAG
31
www.maximintegrated.com
Maxim Integrated │ 15
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
TQFP-EP
WLP
36
B5
TMS
JTAG Test Mode Select
Serial Wire Debug I/O
This pin has an internal 25kΩ pullup to VDDIO.
38
B6
TDO
JTAG Test Data Output
40
B7
TDI
JTAG Test Data Input.
This pin has an internal 25kΩ pullup to VDDIO.
RESET
22
23
B2
B1
RSTN
SRSTN
Hardware Reset, Active-Low Input. The device remains in reset while this pin is in its
active state. When the pin transitions to its inactive state, the device performs a POR
reset (resetting all logic on all supplies except for real-time clock circuitry) and begins
execution. This pin has an internal 25kΩ pullup to the VRTC supply. This pin should be left
unconnected if the system design does not provide a reset signal to the device.
Software Reset, Active-Low Input/Output. The device remains in software reset while this
pin is in its active state. When the pin transitions to its inactive state, the device performs
a reset to the Arm core, digital registers and peripherals (resetting most of the core logic
on the VDD12 supply). This reset does not affect the POR only registers, RTC logic, Arm
debug engine or JTAG debugger allowing for a soft reset without having to reconfiguring all
registers.
After the device senses SRSTN as a logic 0, the pin automatically reconfigures as an
output sourcing a logic 0. The device continues to output for 6 system clock cycles and
then repeats the input sensing/output driving until SRSTN is sensed inactive. This pin is
internally connected with an internal 25kΩ pullup to the VRTC supply. This pin should be left
unconnected if the system design does not provide a reset signal to the device.
GENERAL-PURPOSE I/O AND SPECIAL FUNCTIONS
21
C2
P0.0
20
C1
P0.1
19
D4
P0.2
18
D3
P0.3
17
D1
P0.4
16
D2
P0.5
15
E3
P0.6
14
E2
P0.7
12
E1
P1.0
11
E4
P1.1
10
F3
P1.2
9
F2
P1.3
6
F4
P1.4
5
E5
P1.5
4
G2
P1.6
99
G3
P1.7
www.maximintegrated.com
General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 1 for
details.
General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 1 for
details.
Maxim Integrated │ 16
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Pin Description (continued)
PIN
NAME
TQFP-EP
WLP
97
J2
P2.0
96
H2
P2.1
95
H3
P2.2
94
J3
P2.3
93
G4
P2.4
92
H4
P2.5
89
G5
P2.6
88
H5
P2.7
86
F5
P3.0
85
E6
P3.1
84
H6
P3.2
83
J6
P3.3
82
G6
P3.4
81
F6
P3.5
80
J7
P3.6
79
F7
P3.7
74
J8
P4.0
73
H7
P4.1
72
H9
P4.2
71
H8
P4.3
70
G7
P4.4
69
G9
P4.5
68
G8
P4.6
67
F9
P4.7
49
D7
P5.0
48
E7
P5.1
47
C7
P5.2
45
D6
P5.3
44
C6
P5.4
30
C5
P5.5
28
D5
P5.6
27
C4
P5.7
24
C3
P6.0
www.maximintegrated.com
FUNCTION
General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 1 for
details.
General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 1 for
details.
General-Purpose I/O, Port 4. Most port pins have multiple special functions. See Table 1 for
details.
General-Purpose I/O, Port 5. Most port pins have multiple special functions. See Table 1 for
details.
General-Purpose I/O, Port 6.0. Most port pins have multiple special functions. See Table 1
for details.
Maxim Integrated │ 17
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Pin Description (continued)
PIN
TQFP-EP
WLP
NAME
FUNCTION
ANALOG INPUT PINS
35
A4
AIN0
ADC Input 0. 5V-tolerant input.
37
A5
AIN1
ADC Input 1. 5V-tolerant input.
39
A6
AIN2
ADC Input 2
41
A7
AIN3
ADC Input 3
N.C.
No Connection
NO CONNECTS
1, 13, 25,
26, 32, 43,
50–54, 57,
A1, A9,
66, 75–78,
J1, J9
87, 98,
100
Table 1. MAX32620/MAX32621 GPIO Special Function Cross Reference
GPIO
PRIMARY
FUNCTION
SECONDARY
FUNCTION
PULSE TRAIN
OUTPUT
TIMER
INPUT
GPIO
OUTPUT
P0.0
P0.1
UART0A_RX
UART0B_TX
PT_PT0
TIMER_TMR0
GPIO_INT(P0)
UART0A_TX
UART0B_RX
PT_PT1
TIMER_TMR1
GPIO_INT(P0)
P0.2
UART0A_CTS
UART0B_RTS
PT_PT2
TIMER_TMR2
GPIO_INT(P0)
P0.3
UART0A_RTS
UART0B_CTS
PT_PT3
TIMER_TMR3
GPIO_INT(P0)
P0.4
SPIM0_SCK
PT_PT4
TIMER_TMR4
GPIO_INT(P0)
P0.5
SPIM0_MOSI/
SDIO0
PT_PT5
TIMER_TMR5
GPIO_INT(P0)
P0.6
SPIM0_MISO/
SDIO1
PT_PT6
TIMER_TMR0
GPIO_INT(P0)
P0.7
SPIM0_SS0
PT_PT7
TIMER_TMR1
GPIO_INT(P0)
P1.0
SPIM1_SCK
SPIX_SCK
PT_PT8
TIMER_TMR2
GPIO_INT(P1)
P1.1
SPIM1_MOSI/
SDIO0
SPIX_SDIO0
PT_PT9
TIMER_TMR3
GPIO_INT(P1)
P1.2
SPIM1_MISO/
SDIO1
SPIX_SDIO1
PT_PT10
TIMER_TMR4
GPIO_INT(P1)
P1.3
SPIM1_SS0
SPIX_SS
PT_PT11
TIMER_TMR5
GPIO_INT(P1)
P1.4
SPIM1_SDIO2
SPIX_SDIO2
PT_PT12
TIMER_TMR0
GPIO_INT(P1)
P1.5
SPIM1_SDIO3
SPIX_SDIO3
PT_PT13
TIMER_TMR1
GPIO_INT(P1)
P1.6
I2CM0/SA_SDA
PT_PT14
TIMER_TMR2
GPIO_INT(P1)
P1.7
I2CM0/SA_SCL
PT_PT15
TIMER_TMR3
GPIO_INT(P1)
P2.0
UART1A_RX
UART1B_TX
PT_PT0
TIMER_TMR4
GPIO_INT(P2)
P2.1
UART1A_TX
UART1B_RX
PT_PT1
TIMER_TMR5
GPIO_INT(P2)
www.maximintegrated.com
TERTIARY
FUNCTION
QUATERNARY
FUNCTION
Maxim Integrated │ 18
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Table 1. MAX32620/MAX32621 GPIO Special Function Cross Reference (continued)
GPIO
SPECIAL FUNCTIONS
P2.2
UART1A_CTS
UART1B_RTS
PT_PT2
TIMER_TMR0
GPIO_INT(P2)
P2.3
UART1A_RTS
UART1B_CTS
PT_PT3
TIMER_TMR1
GPIO_INT(P2)
P2.4
SPIM2A_SCK
PT_PT4
TIMER_TMR2
GPIO_INT(P2)
P2.5
SPIM2A_MOSI/
SDIO0
PT_PT5
TIMER_TMR3
GPIO_INT(P2)
P2.6
SPIM2A_MISO/
SDIO1
PT_PT6
TIMER_TMR4
GPIO_INT(P2)
P2.7
SPIM2A_SS0
PT_PT7
TIMER_TMR5
GPIO_INT(P2)
P3.0
UART2A_RX
UART2B_TX
PT_PT8
TIMER_TMR0
GPIO_INT(P3)
P3.1
UART2A_TX
UART2B_RX
PT_PT9
TIMER_TMR1
GPIO_INT(P3)
P3.2
UART2A_CTS
UART2B_RTS
PT_PT10
TIMER_TMR2
GPIO_INT(P3)
P3.3
UART2A_RTS
UART2B_CTS
PT_PT11
TIMER_TMR3
GPIO_INT(P3)
P3.4
I2CM1/SB_SDA
SPIM2A_SS1
PT_PT12
TIMER_TMR4
GPIO_INT(P3)
P3.5
I2CM1/SB_SCL
SPIM2A_SS2
PT_PT13
TIMER_TMR5
GPIO_INT(P3)
P3.6
SPIM1_SS1
SPIX_SS1
PT_PT14
TIMER_TMR0
GPIO_INT(P3)
P3.7
SPIM1_SS2
SPIX_SS2
PT_PT15
TIMER_TMR1
GPIO_INT(P3)
P4.0
OWM_I/O
SPIM2A_SR0
PT_PT0
TIMER_TMR2
GPIO_INT(P4)
P4.1
OWM_PUPEN
SPIM2A_SR1
PT_PT1
TIMER_TMR3
GPIO_INT(P4)
P4.2
SPIM0_SDIO2
PT_PT2
TIMER_TMR4
GPIO_INT(P4)
P4.3
SPIM0_SDIO3
PT_PT3
TIMER_TMR5
GPIO_INT(P4)
P4.4
SPIM0_SS1
PT_PT4
TIMER_TMR0
GPIO_INT(P4)
P4.5
SPIM0_SS2
PT_PT5
TIMER_TMR1
GPIO_INT(P4)
P4.6
SPIM0_SS3
PT_PT6
TIMER_TMR2
GPIO_INT(P4)
P4.7
SPIM0_SS4
PT_PT7
TIMER_TMR3
GPIO_INT(P4)
P5.0
Reserved
SPIM2B_SCK
PT_PT8
TIMER_TMR4
GPIO_INT(P5)
P5.1
Reserved
SPIM2B_
MOSI/SDIO0
PT_PT9
TIMER_TMR5
GPIO_INT(P5)
P5.2
Reserved
SPIM2B_
MISO/SDIO1
PT_PT10
TIMER_TMR0
GPIO_INT(P5)
P5.3
Reserved
SPIM2B_SS0
PT_PT11
TIMER_TMR1
GPIO_INT(P5)
UART3A_RX
UART3B_TX
P5.4
Reserved
SPIM2B_
SDIO2
PT_PT12
TIMER_TMR2
GPIO_INT(P5)
UART3A_TX
UART3B_RX
P5.5
Reserved
SPIM2B_
SDIO3
PT_PT13
TIMER_TMR3
GPIO_INT(P5)
UART3A_CTS
UART3B_RTS
P5.6
Reserved
SPIM2B_SR
PT_PT14
TIMER_TMR4
GPIO_INT(P5)
UART3A_RTS
UART3B_CTS
P5.7
I2CM2/SC_SDA
SPIM2B_SS1
PT_PT15
TIMER_TMR5
GPIO_INT(P5)
P6.0
I2CM2/SC_SCL
SPIM2B_SS2
PT_PT0
TIMER_TMR0
GPIO_INT(P5)
www.maximintegrated.com
Maxim Integrated │ 19
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
MAX32620/MAX32621
Detailed Description
●●
Debug access port: JTAG or serial wire
●●
NVIC support:
The MAX32620/MAX32621 is a low-power, mixed signal
microcontroller that includes the Arm Cortex-M4 with FPU
core with a maximum operating frequency of 96MHz. An
internal 4MHz oscillator supports minimal power consumption for applications requiring always-on monitoring. The
MAX32621 is a secure version, incorporating a trust protection unit (TPU) with encryption and advanced security
features.
Application code executes from an onboard 2MB/1MB
program flash memory, with 256KB SRAM available
for general application use. An 8KB instruction cache
improves execution throughput, and a transparent code
scrambling scheme protects customer intellectual property residing in the program flash memory. Additionally,
a SPI execute in place (SPIX) external memory interface
allows application code and data (up to 16MB) to be
accessed from an external SPI memory device.
A 10-bit sigma-delta ADC is provided with a multiplexer
front end for four external input channels (two of which
are 5.5V tolerant) and internal channels to monitor supply
voltages. Built-in limit monitors allow converted input samples to be compared against user-configurable high and
low limits, with an option to trigger an interrupt and wake
the CPU from a low power mode if attention is required.
• 52 interrupts to be grouped by firmware into 8
levels of priority
●● DSP supports Single Instruction Multiple Data
(SIMD) Path DSP extensions, providing:
•
•
•
•
•
4 parallel 8 bit add/sub
2 parallel 16 bit add/sub
2 parallel MACs
32 or 64 bit accumulate
Signed, unsigned, data with or without saturation
Power Operating Modes
Low Power Mode 0 (LP0)
This mode places the core and peripheral logic in a static,
low-power state. All features of the device are disabled
except:
●● Power sequencer
●● RTC (if enabled)
●● Key data retention registers
●● Power-on reset
●● Voltage supply monitoring
Data retention in this mode can be maintained using only
the VRTC supply, with all other voltage supplies disabled.
A wide variety of communications and interface peripherals are provided, including a USB 2.0-compliant slave
interface, three master SPI interfaces, four UART interfaces with multidrop support, three master I2C interfaces,
and a slave I2C interface.
Low Power Mode 1 (LP1)
Arm Cortex-M4 with FPU Core
Low Power Mode 2 (LP2)
The Arm Cortex-M4 with FPU core is ideal for the emerging category of wearable medical and wellness applications. The architecture combines high-efficiency signal
processing functionality with low power, low cost, and
ease of use.
This configuration allows the ADC and some peripherals to operate while the Arm core is in sleep mode. The
peripheral management unit provides intelligent, dynamic
clocking of any enabled peripherals, ensuring the lowest
power consumption possible.
●●
Floating Point Unit (FPU)
●●
Memory Protection Unit
Low Power Mode 3 (LP3)
●●
Full debug support level
•
•
•
•
•
Debug Access Port (DAP)
Breakpoints
DWT
Flash patch
Halting debug
www.maximintegrated.com
This mode places the core logic in a static, low-power
state which supports a fast wakeup feature. Data retention in this mode can be maintained using only the VRTC
supply, with all other voltage supplies disabled.
During this state, the CPU is executing application code
and all digital and analog peripherals are fully powered
and awake. Dynamic clocking disables peripherals not in
use, providing the optimal mix of high-performance and
low power consumption.
Maxim Integrated │ 20
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Analog to Digital Converter (ADC)
Clocking Scheme
An optional feature allows samples captured by the ADC
to be automatically compared against user-programmable
high and low limits. Up to four channel limit pairs can be
configured in this way. The comparison allows the ADC
to trigger an interrupt (and potentially wake the CPU
from a low power sleep mode) when a captured sample
goes outside the preprogrammed limit range. Since this
comparison is performed directly by the sample limit
monitors, it can be performed even while the main CPU is
suspended in a low-power mode.
An external 32.768kHz timebase is required when using
the RTC or USB features of the device. The time base
can be generated by attaching a 32kHz crystal. An external clock source can also be applied to the 32KIN pin.
The external clock source must meet the electrical/timing
requirements in the EC table.
The 10-bit sigma-delta ADC provides four external inputs and
can also be configured to measure all internal power supplies.
It operates at a maximum of 7.8ksps. AIN0 and AIN1 are 5.5V
tolerant, making them suitable for monitoring batteries.
The ADC reference can be the internal 1.2V bandgap or
an external reference.
The ADC measures:
●●
●●
●●
●●
●●
●●
●●
●●
AIN[3:2] (up to 3.3V)
AIN[1:0] (up to 5.5V)
VDD12
VDD18
VDDB
VRTC
VDDIO
VDDIOH
Pulse Train Engine
Sixteen independent pulse train generators provide either
a square wave or a repeating pattern from 2 bits to 32
bits in length.
Each pulse train generator is independently configurable.
The pulse train generators provide the following:
●● Independently enabled
●● Multiple pin configurations allow for flexible layout
●● Pulse trains can be started/synchronized independently
or as a group
●● Frequency of each enabled pulse train generator is
also set separately, based on a divide down (divide
by 2, divide by 4, divide by 8, and so on) of the input
pulse train module clock
●● Multiple repetition options for pulse train mode
• Single shot (nonrepeating pattern of 2-32 bits)
• Pattern repeats user-configurable number of times
or indefinitely
• End of one pulse train’s loop count can restart one
or more other pulse trains
www.maximintegrated.com
The high-frequency internal relaxation oscillator operates
at a nominal frequency of 96MHz. It is the primary clock
source for the digital logic and peripherals. The 4MHz
internal oscillator can be selected to optimize active
power consumption. Wakeup is possible from either the
4MHz or the 96MHz internal oscillator.
Interrupt Sources
The Arm nested vector interrupt controller (NVIC) provides
high speed, deterministic interrupt response, interrupt
masking, and multiple interrupt sources. Each peripheral
is connected to the NVIC and can have multiple interrupt
flags to indicate the specific source of the interrupt within
the peripheral.
The NVIC provides:
●● Up to 52 distinct interrupt sources (including internal
and external interrupts)
●● Eight priority levels
●● A dedicated interrupt for each port
Real-Time Clock
A real-time clock (RTC) keeps the time of day in absolute
seconds. The time base can be generated by connecting a 32kHz crystal between 32KIN and 32KOUT or an
external clock source can be applied to the 32KIN pin.
The external clock source must meet the electrical/timing
requirements in the EC table. The 32kHz output can be
directed to a GPIO for observation and use.
The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by
application software. A time-of-day alarm and independent subsecond alarm can cause an interrupt or wake the
device from stop mode.
The wake-up timer allows the device to remain in low
power mode for extended periods of time. The minimum
wake-up interval is 244µs.
Maxim Integrated │ 21
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
XTAL DRIVER OR
EXTERNAL CLOCK
32KIN
32kHz
CRYSTAL
32KOUT
32kHz
RTC
OSCILLATOR
NANO-RING
OSCILLATOR
~8kHz
32.768kHz
OUTPUT CLOCK
GPIO
REAL-TIME
CLOCK
POWER
SEQUENCER
ALWAYS-ON DOMAIN
(96MHz SYSCLK ONLY)
48MHz
DIVIDE BY 2
FIRMWARE
FREQUENCY
CALIBRATION FOR USB
INTERNAL
96MHz
OSCILLATOR
CLOCK
SCALER
INTERNAL
4MHz
OSCILLATOR
SYSTEM
CLOCK
SELECT
INTERNAL 44MHz
CRYPTOGRAPHIC
OSCILLATOR
CORE
CLOCK
SCALER
15kHz–96MHz
ADC
CLOCK
SCALER
8MHz
44MHz
USB PHY
ARM
CORTEX-M4
WITH FPU
CORE
ADC
TPU
TRUST PROTECTION UNIT (OPTIONAL)
Figure 2. MAX32620/MAX32621 Clock Scheme (TPU on MAX32621 Only)
32-BIT TIMER BLOCK
APB
BUS
32-BIT COMPARE
REGISTER
APB
CLOCK
TIME INTERRUPT
REGISTER
TIMER CONTROL
REGISTER
COMPARE
INTERRUPT
PWM AND TIMER
OUTPUT
CONTROL
32-BIT TIMER
(WITH PRESCALER)
32-BIT
PWM/COMPARE
COMPARE
TIMER
INTERRUPT
TIMER
OUTPUT
TIMER
INPUT
Figure 3. Timer Block Diagram, 32-Bit Mode
www.maximintegrated.com
Maxim Integrated │ 22
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
General Purpose I/O and Special
Function Pins
caused the system reset. The clock source options for
the WDT include:
General-purpose I/O (GPIO) pins are controlled directly
by firmware or one or more peripheral modules connected
to that pin. GPIO are logically divided into 8-pin ports.
Each 8-bit port provides a dedicated interrupt.
The alternate functions for each pin are shown in Table 1.
The following features are independently configurable for
each GPIO pin:
●● GPIO or special function mode operation
●●
Scaled-system clock
●●
RTC clock
●●
Power management clock
A third watchdog timer (WDT2) is provided for recovery
from runaway code or system unresponsiveness. When
enabled, this watchdog must be reset prior to timeout,
resulting in a watchdog timeout. The WDT2 flag is set on
reset if a watchdog expiration caused the system reset.
●● Normal and fast output drive strength
WDT2 is unique in that is in the always-on domain, and
continues to run even in LP1 or LP0. The timeout period
for WDT2 can be programmed as long as 8 seconds.
The granularity of the timeout period is intended only for
system recovery.
●● Open-drain output or high-impedance input
Programmable Timers
●● VDDIO or VDDIOH supply voltage
●● VDDI18 GPIO supply voltage supported for legacy
operation
●● Configurable strong or weak internal pullup/pulldown
resistors
●● Simple output-only functions
• Output from pulse trains (0 through 15)
• Output from timers running in 32-bit mode
Some peripherals have optional pin assignments, allowing for greater flexibility during PCB layout. These optional
pin assignments are identified with the letter B, C, or D
after the peripheral name. On the MAX32620/MAX32621,
the UART0_RX signal is mapped to the P0.0 pin. If the B
configuration is chosen, the UART0_RX signal is mapped
to the P0.1 pin.
CRC Module
The CRC hardware module provides fast calculations and
data integrity checks by application software. The CRC
module supports both the CRC-16-CCITT and CRC-32
(X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5
+X4 +X2 +X1 +1) polynomials.
Watchdog Timers
Two independent watchdog timers (WDT0 and WDT1)
with window support are provided. The WDT has multiple
clock source options to ensure system security. It uses
a 32-bit timer with prescaler to generate the watchdog
reset. When enabled, the WDT must be reset prior to
timeout or within a window of time if window mode is
enabled. Failure to reset the WDT during the programmed
timing window results in a watchdog timeout. WDT resets
can cause firmware or power-on resets. The WDT0 or
WDT1 flags are set on reset if a watchdog expiration
www.maximintegrated.com
Six 32-bit timers provide timing, capture/compare, or
generation of pulse-width modulated (PWM) signals.
Each timer can be split into two 16-bit timers, enabling 12
standard 16-bit timers.
The 32-bit timer features:
●●
32-bit up/down auto-reload
●●
Programmable 16-bit prescaler
●●
PWM output generation
●●
Capture, compare, and capture/compare capability
●●
External input pin for timer input, clock gating or
capture, limited to an input frequency of 1/4 of the
peripheral clock frequency
●●
Timer output pin
●●
Configurable as 2x 16-bit general purpose timers
●●
Timer interrupt
Serial Peripherals
USB Controller
The integrated USB controller is compliant with the fullspeed (12Mb/s) USB 2.0 specification. The integrated
USB physical interface (PHY) reduces board space and
system cost. An integrated voltage regulator allows for
smart switching between the main supply and VDDB when
connected to a USB host controller.
The USB controller supports DMA for the endpoint buffers. A total of 7 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0.
Maxim Integrated │ 23
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
An external 32kHz crystal or clock source is required
for USB operation, even if the RTC function is not used.
Although the USB timing is derived from the internal
96MHz oscillator, the default accuracy is not sufficient for
USB operation. Firmware trimming of the 96MHz oscillator
using the 32kHz timebase as a reference is necessary to
comply with USB timing requirements.
●●
●●
●●
●●
●●
I2C Master and Slave Ports
The I2C interface is a bidirectional, 2-wire serial bus that
provides a medium-speed communications network. It
can operate as a one-to-one, one-to-many or many-tomany communications medium.
Three I2C interfaces allow for up to three I2C master
engines and one I2C-selectable slave engine, which
interface to a wide variety of I2C-compatible peripherals.
These engines support both Standard-mode and Fastmode I2C standards. The slave engine shares the same
I/O port as the master engines and is selectable through
the I/O configuration settings. It provides the following
features:
Up to 2 slave ready lines
Programmable interface timing
Programmable SCK frequency and duty cycle
Programmable SCK alternate timing
SS (slave select) assertion and deassertion timing
with respect to leading/trailing SCK edge
Serial Peripheral Interface—Slave
The SPI slave (SPIS) port provides a highly configurable,
flexible, and efficient interface to communicate with a wide
variety of SPI master devices. The SPI slave interface
provides the following features:
•
•
•
•
•
Supports SPI modes 0 and 3
Full-duplex operation in single-bit, 4-wire mode
Slave select polarity fixed (active low)
Dual and Quad I/O supported
High-speed AHB access to transmit and receive using
32-byte FIFOs
• Four interrupts to monitor FIFO levels
Serial Peripheral Interface—Execute in
Place (SPIX) Master
●●
Master or slave mode operation
●●
Supports standard (7-bit) or expanded (10-bit) addressing
●●
Support for clock stretching to allow slower slave
devices to operate on higher speed busses
●●
Multiple transfer rates:
Standard-mode: 100kbps
Fast-mode: 400kbps
The SPIX allows the CPU to transparently execute
instructions stored in an external SPI flash. Instructions
fetched through the SPIX master are cached just like
instructions fetched from internal program memory. The
SPIX master can also be used to access large amounts of
external static data that would otherwise reside in internal
data memory.
●●
Internal filter to reject noise spikes
UART
●●
Receiver FIFO depth of 16 bytes
●●
Transmitter FIFO depth of 16 bytes
Serial Peripheral Interface—Master
The SPI master-mode-only (SPIM) interface operates
independently in a single or multiple slave system and is
fully accessible to the user application.
The SPI ports provide a highly configurable, flexible and
efficient interface to communicate with a wide variety of
SPI slave devices. The three SPI master ports (SPI0,
SPI1, SPI2) support the following features:
●●
●●
●●
●●
●●
Supports all four SPI modes (0,1,2,3) for single-bit
communication
3 or 4 wire mode for single-bit slave device communication
Full-duplex operation in single-bit, 4-wire mode
Dual and quad I/O supported
Up to 5 slave select lines per port
www.maximintegrated.com
All four universal asynchronous receiver-transmitter
(UART) interfaces support full-duplex asynchronous communication with optional hardware flow control (HFC)
modes to prevent data overruns. If HFC mode is enabled
on a given port, the system uses two extra pins to implement the industry-standard request to send (RTS) and
clear to send (CTS) methodology. Each UART is individually programmable.
●●
2-wire interface or 4-wire interface with flow control
●●
2x 32-byte send/receive FIFOs, one for transmit and
receive
●●
Full-duplex operation for asynchronous data transfers
●●
Programmable interrupt for receive and transmit
●●
Independent baud-rate generator
●●
Programmable 9th bit parity support
●●
Start/stop bit support
●●
Hardware flow control using RTS/CTS
●●
Maximum baud rate 1843.2kB
Maxim Integrated │ 24
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
1-Wire Master
Peripheral Management Unit (PMU)
Maxim’s DeepCover® 1-Wire security solutions provide
a cost-effective solution to authenticate medical sensors and peripherals, preventing counterfeit products.
The integrated 1-Wire master communicates with slave
devices via the bidirectional, multidrop 1-Wire bus. All of
the devices on the 1-Wire bus share one signal which carries data communication and also supplies power to the
slave devices. The single contact serial interface is ideal
for communication networks requiring minimal interconnect. Features of the 1-Wire bus include:
●● Single contact for control and operation
●● Unique factory identifier for any 1-Wire device
●● Power is distributed to all slave device (parasitic power)
●● Multiple device capability on a single line
●● Supports 1-Wire standard (15.6kbps) and overdrive
(110 kbps) speeds
The incorporation of the 1-Wire master enables the creation of 1-Wire enhanced of consumable and reusable
accessories. The following benefits can be added to products by the addition of only one contact:
●● OEM authenticity is verifiable with SHA-256 and
ECDSA
●● External tracking is eliminated because calibration
data can be securely stored within accessory
●● Reuse of single-use accessories can be prevented
●● Counterfeit products can be identified and use denied
using the unique, factory identifier
●● Environmental temperature and humidity sensing
Trust Protection Unit (TPU)
(MAX32621 Only)
The TPU enhances cryptographic data security for valuable intellectual property (IP) and data. High-speed,
hardware-based cryptographic accelerators perform
mathematical computations that support cryptographic
algorithms, including:
●●
●●
●●
●●
●●
AES-128
AES-192
AES-256
1024-bit DSA
2048-bit (CRT)
The device provides a true random number generator
which can be used to create cryptographic keys for any
application. A user-selectable entropy source further
increases the randomness and key strength.
The PMU is a DMA-based link list processing engine that
performs operations and data transfers involving memory
and/or peripherals in the advanced peripheral bus (APB)
and advanced high-performance bus (AHB) peripheral
memory space while the main CPU is in a sleep state.
This allows low-overhead peripheral operations to be
performed without the CPU, significantly reducing overall
power consumption. Using the PMU with the CPU in a
sleep state provides a lower-noise environment critical for
obtaining optimum ADC performance.
Key features of the PMU engine include:
●●
Six independent channels with round-robin scheduling allows for multiple parallel operations
●●
Programmed using SRAM-based PMU opcodes
●●
PMU action can be initiated from interrupt conditions
from peripherals without CPU
●●
Integrated AHB bus master
●●
Coprocessor-like state machine
Additional Documentation
Engineers must have the following documents to fully use
this device:
●●
This data sheet, containing pin descriptions, feature
overviews, and electrical specifications
●●
The device-appropriate user guide, containing
detailed information and programming guidelines for
core features and peripherals
●●
Errata sheets for specific revisions noting deviations
from published specifications.
Development and Technical Support
Contact technical support for information about highly
versatile, affordable development tools, available from
Maxim Integrated and third-party vendors.
●●
Evaluation kits
●●
Software development kit
●●
Compilers
●●
Integrated development environments (IDEs)
●●
USB interface modules for programming and
debugging
The secure bootloader protects against unauthorized
access to program memory.
DeepCover is a registered trademark of Maixm Integrated
Products, Inc.
www.maximintegrated.com
Maxim Integrated │ 25
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Typical Application Circuit—Wearable Cardiac Monitor
MAX14690N PMIC
MAX32620/MAX32621
I2C
PMIC CONTROL
RTC
USB PHY
VRTC
POWER
MANAGER
96MHZ OSCILLATOR
GPIO VOLTAGE
SELECT
4MHZ
OSCILLATOR
CHARGER
VBUS
1.8V LDO1
VDDB
3.3V LDO2
AIN
ADC
CONTROL
Li-ION
MONITOR
VDDA
VDD18
1.8V BUCK2
VDDIO
3.0V LDO3
VDDIOH
VDD12
1.2V BUCK1
ARM CORTEX-M4
WITH FPU CORE
VDD
SPI
2MB FLASH
STANDBY
PFN1
EM9301 BLE RADIO
SPI BRIDGE
256 KB SRAM
24MHz
32kHz
AFE CONTROL
SPI
MAX30003
BIOPOTENTIAL AFE
ECGP
EXTERNAL
EMI
FILTERS
AVDD
DVDD
VDD18
www.maximintegrated.com
OVDD
PHYSICAL
ELECTRODES
ECGN
Maxim Integrated │ 26
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Ordering Information
FLASH
(MB)
SRAM
(KB)
TRUST PROTECTION
UNIT
PIN-PACKAGE
MAX32620ICQ+
2
256
No
100 TQFP
MAX32620IWG+
2
256
No
81 WLP
MAX32620IWG+T
2
256
No
81 WLP
MAX32620IWGL+
1
256
No
81 WLP
MAX32620IWGL+T
1
256
No
81 WLP
MAX32621ICQ+
2
256
Yes
100 TQFP
MAX32621IWG+
2
256
Yes
81 WLP
MAX32621IWG+T
2
256
Yes
81 WLP
PART
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN
NO.
81 WLP
W813D3+1
21-0776
Refer to
Application
Note 1891
100
TQFP-EP
C100E+3
21-0116
90-0154
www.maximintegrated.com
Maxim Integrated │ 27
MAX32620/MAX32621
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 256KB SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/15
Initial release
1/17
Added 4MHz clock option to EC table, added new GPIO VDDIO/VDDIOH option
while supporting legacy VDD18 I/O supply to EC table, pin configuration, and
pin description, absolute maximum rating for VRTC changed from 3.6V to 1.89V,
VAIN(MIN) typo corrected from VSS to VSSA, RSTN pin supply corrected from
VDD18 to VRTC, added I2C and SPI timings, updated feature descriptions to
conform to MAX32625/MAX32626 style, corrected Table 1 title, corrected part
number in detailed description, added text in General Description describing
differences between “C” and “A” revisions of the device, corrected RTC frequency
to 32.768kHz, changed instances of WTD to WDT, corrected instances of TA
= +20°C to TA = +25°C, changed page 1 typical values from current to power,
updated IDDxx typical values, removed redundant feature list on page 26,
removed references to SPI bridge from I/O Matrix as the feature was never
implemented, recommended VDD12 bypass capacitor changed from 100nF to
1.0µF, corrected Arm Cortex trademark usage in text and figures, IIH3V min/max
from ±1 to ±2, VRST(MIN) from 1.62V to 1.61V, fINTCLK min/max from 94.08/97.92
to 94/98MHz, corrected fRCCLK(MIN) from 3.9 to 0.001MHz to clarify effect of
clock divider option, but no change to device, moved 1-Wire Master I/O to Table
1, added MAX32620IWGL+ and MAX32620IWGL+T part numbers
1–8, 10–16, 18–26
5/17
Changed references to PRNG to TRNG (true random number generator) in
General Description, Benefits and Features, MAX32620/MAX32621 Block
Diagram, and Trust Protection Unit (TPU) (MAX32621 Only) sections; changed
32KIN, 32KOUT in Absolute Maximum Ratings from “-0.3V to +3.6V” to “-0.3V to
VRTC + 0.2V;” and removed future product designation from MAX32620IWGL+
and MAX32620IWGL+T in Ordering Information
1–3, 25, 27
1
2
2.1
3
4
PAGES
CHANGED
DESCRIPTION
—
Updated Arm trademark and appearance
1–28
3/18
Updated General Description and changed TQFP instances to TQFP-EP
1–28
10/18
Updated title, Benefits and Features, Figure 1, Pin Configuration (continued),
Programmable Timers, switched order of Serial Peripheral Interface—Execute in
Place (SPIX) Master, and Serial Peripheral Interface, updated Trust Protection
Unit (TPU) (MAX32621 Only), Additional Documentation, and Development and
Technical Support sections
1–28
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2018 Maxim Integrated Products, Inc. │ 28
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