MAX32625/MAX32626
General Description
DARWIN is a new breed of low-power microcontrollers
built to thrive in the rapidly evolving Internet of Things (IoT).
They are smart, with the biggest memories in their class
and a massively scalable memory architecture. They run
forever, thanks to wearable-grade power technology. They
are also tough enough to withstand the most advanced
cyberattacks. DARWIN microcontrollers are designed
to run any application imaginable—in places where you
wouldn’t dream of sending other microcontrollers.
Generation U microcontrollers are perfect for wearables
and IoT applications that cannot afford to compromise
power or performance. The MAX32625/MAX32626 feature an Arm® Cortex®-M4 with FPU CPU that delivers
high-efficiency signal processing, ultra-low power consumption and ease of use.
Flexible power modes, an intelligent PMU, and dynamic
clock and power gating optimize performance and power
consumption for each application. Internal oscillators run
at 96MHz for high-performance or 4MHz to maximize
battery life in applications requiring always-on monitoring.
Multiple SPI, UART, I2C, 1-Wire® master, and USB interfaces are provided. The four-input, 10-bit ADC with selectable references can monitor external sensors.
All versions provide a hardware AES engine. The
MAX32626 provides a secure trust protection unit (TPU)
with a modular arithmetic accelerator (MAA) for fast
ECDSA, a hardware PRNG entropy generator, and a
secure boot loader. The MAX32625L provides a reduced
256KB of flash memory and 128KB of SRAM.
Applications
●●
●●
●●
●●
●●
Sports Watches
Fitness Monitors
Wearable Medical Patches
Portable Medical Devices
Sensor Hubs
Ordering Information appears at end of data sheet.
Arm and Cortex are registered trademarks of Arm Limited
(or its subsidiaries) in the US and/or elsewhere.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
19-8596; Rev 6; 2/20
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Benefits and Features
●● High-Efficiency Microcontroller for Wearable Devices
• Internal Oscillator Operates Up to 96MHz
• Low Power 4MHz Oscillator System Clock Option
for Always-On Monitoring Applications
• 512KB Flash Memory (256KB “L” Version)
• 160KB SRAM (128KB “L” Version)
• 8KB Instruction Cache
• 1.2V Core Supply Voltage
• 1.8V to 3.3V I/O
• Optional 3.3V ±5% USB Supply Voltage
• Wide Operating Temperature: -30°C to +85°C
●● Power Management Maximizes Uptime for Battery
Applications
• 106μA/MHz Active Current Executing from Cache
• 49μA/MHz Active Current Executing from Flash
• Wake-Up to 96MHz Clock or 4MHz Clock
• 600nA Low Power Mode (LP0) Current with RTC
Enabled
• 2.56μW Ultra-Low Power Data Retention Sleep
Mode (LP1) with Fast 5μs Wake-Up on 96MHz
Clock Source
• 27μA/MHz Low Power Mode (LP2) Current
●● Optimal Peripheral Mix Provides Platform Scalability
• SPI Execute in Place (SPIX) Engine for Memory
Expansion with Minimal Footprint
• Three SPI Masters, One SPI Slave
• Three UARTs
• Up to Two I2C Masters, One I2C Slave
• 1-Wire Master
• Full-Speed USB 2.0 Device with Internal Transceiver
• Sixteen Pulse Train (PWM) Engines
• Six 32-Bit Timers and 3 Watchdog Timers
• Up to 40 General-Purpose I/O Pins
• 10-Bit Delta-Sigma ADC Operating at 7.8ksps
• AES -128, -192, -256
• RTC Calibration Output
●● Secure Valuable IP and Data with Robust Internal
Hardware Security (MAX32626 Only)
• Trust Protection Unit (TPU) Provides ECDSA and
Modular Arithmetic Acceleration Support
• True Random Number Generator
• Secure Boot Loader
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
63 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
68 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics—ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics—USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Characteristics—SPI Master / SPIX Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics—SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics—I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAX32625/MAX32626 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ARM Cortex-M4 with FPU Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low Power Mode 0 (LP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low Power Mode 1 (LP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low Power Mode 2 (LP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low Power Mode 3 (LP3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pulse Train Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Real-Time Clock and Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General-Purpose I/O and Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CRC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C Master and Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI (Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Maxim Integrated │ 2
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
TABLE OF CONTENTS (CONTINUED)
SPI (Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI (Execute in Place (SPIX) Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1-Wire Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Peripheral Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trust Protection Unit (TPU) (MAX32626 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
General-Purpose I/O Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIST OF FIGURES
Figure 1. SPI Master and SPI XIP Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. MAX32625/MAX32626 Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. 32-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LIST OF TABLES
Table 1. General-Purpose I/O Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
www.maximintegrated.com
Maxim Integrated │ 3
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Simplified Block Diagram
MAX32625/MAX32626
96 MHz
SRSTN
NVIC
6 × 32 BIT TIMERS
MEMORY
16 × PULSE TRAIN
ENGINE
JTAG SWD (Serial
Wire Debug)
160KB SRAM
PERIPHERAL
MANAGEMENT UNIT
VOLTAGE
REGULATION &
POWER CONTROL
2 × WINDOWED
WATCHDOG TIMER
RECOVERY
WATCHDOG TIMER
32KHz OUTPUT
32KHz
CRYSTAL
DP
VDDB
TIMERS/PWM
CAPTURE/COMPARE
2 × I2C MASTER
1 × I2C SLAVE
UP TO 40
GPIO/
SPECIAL
FUNCTION
SPI
SPI XIP
I2C
UART
1-Wire
1 × SPI XIP
EXTERNAL
INTERRUPTS
(MAX. 2 PORTS)
3 × UART
1-WIRE MASTER
REAL-TIME
CLOCK
INDIVIDUALLY
SELECTABLE
VDDIO OR VDDIOH
SUPPLY
FOR EACH PIN
AES-128,-192,-256
WAKE UP TIMER
DM
3 × SPI MASTER
GPIO AND
SHARED PAD
FUNCTIONS
1 × SPI SLAVE
8KB CACHE
16B FIFOS
VDDIOH
VDDIO
VDD12
VDD18
VRTC
VSS
POR,
BROWNOUT
MONITOR,
SUPPLY VOLTAGE
MONITORS
BUS MATRIX – AHB, APB, IBUS, DBUS…
RSTN
32B FIFOS
512KB FLASH
32B FIFOS
TCK / SWCLK
TMS / SWDIO
TDO
TDI
GPIO WITH
INTERRUPTS
ARM CORTEX-M4
WITH FPU
4 MHz
USB 2.0 FULL
SPEED
CONTROLLER
CRC 16/32
VDDIO
VDDIOH
UNIQUE ID
TRUST PROTECTION UNIT (TPU)
MAX32626
MAA
SECURE NV KEY
TRNG
SECURE BOOTLOADER
(MAX32626BL ONLY)
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10-BIT
ΣΔ ADC
÷5
÷5
÷2
÷4
AIN0
AIN1
AIN2
AIN3
VDDB
VDD18
VDD12
VRTC
Maxim Integrated │ 4
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Absolute Maximum Ratings
VDD18..................................................................-0.3V to +1.89V
VDD12..................................................................-0.3V to +1.32V
VRTC....................................................................-0.3V to +1.89V
VDDB.....................................................................-0.3V to +3.6V
VDDIO....................................................................-0.3V to +3.6V
VDDIOH..................................................................-0.3V to +3.6V
32KIN, 32KOUT....................................................-0.3V to +3.6V
RSTN, SRSTN, DP, DM, GPIO, JTAG..................-0.3V to +3.6V
AIN[1:0].................................................................-0.3V to +5.5V
AIN[3:2].................................................................-0.3V to +3.6V
Total Current into All VDDIO and VDDIOH
Power Pins Combined (Sink)........................................100mA
Total Current into VSS.......................................................100mA
Output Current (Sink) by Any I/O Pin..................................25mA
Output Current (Source) by Any I/O Pin............................-25mA
Continuous Package Power Dissipation TQFN (multilayer board)
TA = +70°C (derate 49.5mW/°C above +70°C).......3960.4mW
Operating Temperature Range............................ -30°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
(All voltages with respect to VSS, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
63 WLP
PACKAGE CODE
W6333B+1
Outline Number
21-100084
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Single Layer Board:
Junction-to-Ambient (θJA)
N/A
Junction-to-Case Thermal Resistance (θJC)
N/A
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θJA)
35.87ºC/W
Junction-to-Case Thermal Resistance (θJC)
N/A
68 TQFN-EP
PACKAGE CODE
T6888+1
Outline Number
21-0510
Land Pattern Number
90-0354
Thermal Resistance, Single Layer Board:
Junction-to-Ambient (θJA)
N/A
Junction-to-Case Thermal Resistance (θJC)
N/A
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θJA)
20.20ºC/W
Junction-to-Case Thermal Resistance (θJC)
1ºC/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packaging. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 5
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics
(Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -30°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD18
1.71
1.8
1.89
VDD12
1.14
1.2
1.26
VRTC
1.75
1.8
1.89
1.71
1.8
3.6
1.71
1.8
3.6
1.14
1.2
1.26
V
1.7
V
POWER SUPPLIES
Supply Voltage
VDDIO
VDDIOH
1.2V Internal Regulator
VDDIOH must be ≥ VDDIO
VREG12
Power-Fail Reset
Voltage
VRST
Monitors VDD18
Power-On Reset
Voltage
VPOR
Monitors VDD18
VDRV
VDD12 supply, retention in LP1
RAM Data Retention Voltage
VDD12 Dynamic
Current, LP3 Mode
VDD12 Fixed Current, LP3
Mode
VDD18 Fixed Current, LP3
Mode
VDD12 Dynamic
Current, LP2 Mode
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IDD12_DLP3
IDD12_FLP3
IDD18_FLP3
IDD12_DLP2
1.61
V
1.5
V
0.930
mV
Measured on the VDD12 pin and executing code from cache memory, all inputs
are tied to VSS or VDD18, outputs do not
source/sink any current, PMU disabled
106
μA/MHz
96MHz oscillator selected as system clock,
measured on the VDD12 pin and executing code from cache memory, all inputs
are tied to VSS or VDD18, outputs do not
source/sink any current
87
4MHz oscillator selected as system clock,
measured on the VDD12 pin and executing code from cache memory, all inputs
are tied to VSS or VDD18, outputs do not
source/sink any current
39
96MHz oscillator selected as system clock,
measured on the VDD18 pin and executing code from cache memory, all inputs
are tied to VSS or VDD18, outputs do not
source/sink any current
366
4MHz oscillator selected as system clock,
measured on the VDD18 pin and executing code from cache memory, all inputs
are tied to VSS or VDD18, outputs do not
source/sink any current
33
Measured on the VDD12 pin, ARM in sleep
mode, PMU with two channels active
27
μA
μA
μA/MHz
Maxim Integrated │ 6
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -30°C are guaranteed by design and are not production tested.)
PARAMETER
VDD12 Fixed Current, LP2
Mode
VDD18 Fixed Current, LP2
Mode
SYMBOL
IDD12_FLP2
IDD18_FLP2
CONDITIONS
MIN
TYP
96MHz oscillator selected as system clock,
measured on the VDD12 pin, ARM in sleep
mode, PMU with two channels active
87
4MHz oscillator selected as system clock,
measured on the VDD12 pin, ARM in sleep
mode, PMU with two channels active
39
96MHz oscillator selected as system clock,
measured on the VDD18 pin, ARM in sleep
mode, PMU with two channels active
366
4MHz oscillator selected as system clock,
measured on the VDD18 pin, ARM in sleep
mode, PMU with two channels active
33
MAX
UNITS
μA
μA
VDD12 Fixed Current, LP1
Mode
IDD12_FLP1
Standby state with full data retention
1.06
μA
VDD18 Fixed Current, LP1
Mode
IDD18_FLP1
Standby state with full data retention
120
nA
VRTC Fixed Current, LP1
Mode
IDDRTC_FLP1
RTC enabled, retention regulator powered
by VDD12
594
nA
VDD12 Fixed Current, LP0
Mode
IDD12_FLP0
14
nA
VDD18 Fixed Current, LP0
Mode
IDD18_FLP0
120
nA
VRTC Fixed Current, LP0
Mode
IDDRTC_FLP0
LP2 Mode Resume Time
tLP2_ON
0
μs
LP1 Mode Resume Time
tLP1_ON
5
μs
LP0 Mode Resume Time
tLP0_ON
11
μs
RTC enabled
505
RTC disabled
105
Polling flash ready
nA
GENERAL-PURPOSE I/O
VDDIO selected as I/O supply, pin configured as GPIO
0.3 ×
VDDIO
Input Low Voltage for All
GPIO
VIL_GPIO
Input Low Voltage for RSTN
VIL_RSTN
0.3 x
VRTC
Input Low Voltage for
SRSTN
VIL_SRSTN
0.3 x
VDDIO
Input High Voltage for All
GPIO
www.maximintegrated.com
VIH_GPIO
VIH_GPIOH
VDDIOH selected as I/O supply, pin configured as GPIO
VDDIO selected as I/O supply, pin configured as GPIO
VDDIOH selected as I/O supply, pin configured as GPIO
0.3 ×
VDDIOH
0.7 ×
VDDIO
0.7 ×
VDDIOH
V
V
V
Maxim Integrated │ 7
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -30°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
Input High Voltage for RSTN
VIH_RSTN
0.7 x
VRTC
V
Input High Voltage for
SRSTN
VIH_SRSTN
0.7 x
VDDIO
V
Output Low Voltage for All
GPIO
Output High Voltage for All
GPIO
VOL_GPIO
VOH_GPIO
CONDITIONS
MIN
TYP
MAX
IOL = 4mA, VDDIO = VDDIOH = 1.71V,
VDDIO selected as I/O supply, normal drive
configuration, pin configured as GPIO
0.2
0.4
IOL = 24mA, VDDIO = VDDIOH = 1.71V,
VDDIO selected as I/O supply, fast drive
configuration, pin configured as GPIO
0.2
0.4
IOL = 900μA, VDDIO = 1.71V, VDDIOH =
2.97V, VDDIOH selected as I/O supply, pin
configured as GPIO
0.2
0.4
IOH = -2mA, VDDIO = VDDIOH = 1.71V,
VDDIO selected as I/O supply, normal drive
configuration, pin configured as GPIO
VDDIO 0.4
IOH = -8mA, VDDIO = VDDIOH = 1.71V,
VDDIO selected as I/O supply, fast drive
configuration, pin configured as GPIO
VDDIO 0.4
IOH = -900μA, VDDIOH = 3.6V, VDDIOH
selected as I/O supply, pin configured as
GPIO
VDDIOH
- 0.4
IOH = -2mA, VDDIO = 1.71V, VDDIOH =
3.6V, VDDIO selected as I/O supply, pin
configured as GPIO
VDDIO 0.50
UNITS
V
V
Combined IOL, All GPIO
IOL_TOTAL
48
mA
Combined IOH, All GPIO
IOH_TOTAL
-48
mA
Input Hysteresis (Schmitt)
Input/Output Pin
Capacitance for All Pins
Input Leakage Current Low
Input Leakage Current High
www.maximintegrated.com
VIHYS
300
mV
CIO
3
pF
IIL
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
selected as I/O supply, VIN = 0V, internal
pullup disabled
-100
+100
nA
IIH
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
selected as I/O supply, VIN = 3.6V, internal
pulldown disabled
-100
+100
nA
IOFF
VDDIO = 0V, VDDIOH = 0V, VDDIO selected
as I/O supply, VIN < 1.89V
-1
+1
IIH3V
VDDIO = VDDIOH = 1.71V, VDDIO selected
as I/O supply, VIN = 3.6V
-2
+2
μA
Maxim Integrated │ 8
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -30°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Pullup Resistor to
SRSTN, TMS, TCK, TDI
RPU_VDDIO
Pullup to VDDIO
25
kΩ
Input Pullup Resistor to
RSTN
RPU_VRTC
Pullup to VRTC
25
kΩ
RPU_NORM
Normal resistance, pin configured as GPIO
25
kΩ
RPU_HIGH
Highest resistance, pin configured as GPIO
1
MΩ
Input Pullup/Pulldown Resistor for All GPIO
JTAG
Input Low Voltage for TCK,
TMS, TDI
VIL
0.3 x
VDDIO
Input High Voltage for TCK,
TMS, TDI
VIH
Output Low Voltage for TDO
VOL
Output High Voltage for
TDO
VOH
VDDIO 0.4
System Clock Frequency
fSYS_CLK
0.001
System Clock Period
tSYS_CLK
0.7 x
VDDIO
V
V
0.2
0.4
V
V
CLOCKS
fINTCLK
Internal RC Oscillator Frequency
fRCCLK
RTC Input Frequency
f32KIN
RTC Operating Current
RTC Power-Up Time
1/fSYS_
Firmware trimmed, required for USB compliance
94
96
98
95.76
96
96.24
3.9
4
4.1
32kHz watch crystal, 6pF, ESR < 70kΩ
32.768
IRTC_LP23
LP2 or LP3 mode
0.7
IRTC_LP01
LP0 or LP1 mode
0.35
tRTC_ ON
MHz
ns
CLK
Factory default
Internal Relaxation Oscillator Frequency
98
MHz
MHz
kHz
μA
250
ms
8
KB
FLASH MEMORY
Page Size
Flash Erase Time
Flash Programming Time
Per Word
tM_ERASE
Mass erase
30
tP_ERASE
Page erase
30
tPROG
60
Flash Endurance
Data Retention
www.maximintegrated.com
tRET
TA = +25°C
ms
μs
10
kcycles
10
years
Maxim Integrated │ 9
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics—ADC
(Internal bandgap reference selected and ADC_SCALE = ADC_REFSCL = 1 unless otherwise specified. Specifications marked GBD
are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
MAX
UNITS
8
MHz
10
ADC Clock Rate
fADC_CLK
ADC Clock Period
tADC_CLK
Input Voltage Range
TYP
VAIN
Input Dynamic Current,
Switched Capacitance
IAIN
Analog Input Capacitance
CAIN
0.1
Bits
1/fADC_
μs
CLK
AIN0-AIN3, ADC_CHSEL = 0–3,
BUF_BYPASS = 0
0.05
VDD18
AIN0–AIN1, ADC_CHSEL = 4–5,
BUF_BYPASS = 0
0.05
5.5
AIN0–AIN3, ADC_CHSEL = 0–3,
BUF_BYPASS = 1
VSS
VDD18
AIN0-AIN1, ADC_CHSEL = 4–5,
BUF_BYPASS = 1
VSS
5.5
V
ADC active, ADC buffer bypassed
4.5
μA
ADC active, ADC buffer enabled
50
nA
1
pF
250
nF
Fixed capacitance to VSS
Dynamically switched capacitance
Integral Nonlinearity
INL
±2
LSB
Differential Nonlinearity
DNL
±1
LSB
Offset Error
VOS
±1
LSB
Gain Error
GE
±2
LSB
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
Total Harmonic Distortion
SNR
58.5
dB
SINAD
58.5
dB
THD
-68.5
dB
Spurious Free Dynamic
Range
SFDR
74
dB
ADC Active Current
IADC
240
µA
53
μA
Input Buffer Active Current
ADC Setup Time
IINBUF
tADC_SU
ADC Output Latency
tADC
ADC Sample Rate
fADC
ADC Input Leakage
www.maximintegrated.com
ADC active, reference buffer enabled,
input buffer disabled
IADC_LEAK
Any power-up of ADC clock, ADC bias,
reference buffer or input buffer, to
CpuAdcStart
10
µs
Any power-up of ADC clock or ADC bias
to CpuAdcStart
48
tACLK
1025
tACLK
7.8
AIN0 or AIN1, ADC inactive or channel
not selected
0.12
4
AIN2 or AIN3, ADC inactive or channel
not selected
0.02
1
ksps
nA
Maxim Integrated │ 10
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics—ADC (continued)
(Internal bandgap reference selected and ADC_SCALE = ADC_REFSCL = 1 unless otherwise specified. Specifications marked GBD
are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
AIN0/AIN1 Resistor Divider
Error
Full-Scale Voltage
Bandgap Temperature
Coefficient
VFS
VTEMPCO
CONDITIONS
MIN
TYP
MAX
UNITS
ADC_CHSEL = 4 or 5, not including ADC
offset/gain error
±2
LSB
ADC code = 0x3FF
1.2
V
Box method
30
ppm/°C
Electrical Characteristics—USB
(VDD18 = VRST to 1.89V, TA = -30°C to +85°C.)
PARAMETER
SYMBOL
USB PHY Supply Voltage
VDDB
Single-Ended Input High
Voltage DP, DM
VIHD
Single-Ended Input
Low Voltage DP, DM
VILD
CONDITIONS
MIN
TYP
MAX
3.3
UNITS
V
2
V
0.8
V
0.3
V
Output Low Voltage DP, DM
VOLD
RL = 1.5kΩ from DP to 3.6V
Output High Voltage DP, DM
VOHD
RL = 15kΩ from DP and DM to VSS
2.8
V
V
Differential Input
Sensitivity DP, DM
VDI
DP to DM
0.2
Common-Mode Voltage
Range
VCM
Includes VDI range
0.8
2.5
V
Single-Ended Receiver
Threshold
VSE
0.8
2
V
Single-Ended Receiver
Hysteresis
VSEH
Differential Output Signal
Cross-Point Voltage
VCRS
DP, DM Off-State Input
Impedance
Driver Output Impedance
200
CL = 50pF, GBD
RLZ
RDRV
1.3
mV
2
300
Steady-state drive
DP Pullup Resistor
RPU
Idle
DP Pullup Resistor
RPU
Receiving
V
kΩ
28
44
Ω
0.9
1.575
kΩ
1.425
3.09
kΩ
USB TIMING
DP, DM Rise Time (Transmit)
tR
CL = 50pF, GBD
4
20
ns
DP, DM Fall Time (Transmit)
tF
CL = 50pF, GBD
4
20
ns
tR, tF
CL = 50pF, GBD
90
110
%
Rise/Fall Time Matching
(Transmit)
www.maximintegrated.com
Maxim Integrated │ 11
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics—SPI Master/SPIX Master
(Timing specifications are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
48
MHz
Master Operating
Frequency
fMCK
Master SCLK Period
tMCK
SCLK Output PulseWidth High
tMCH
tMCK/2
ns
SCLK Output PulseWidth Low
tMCL
(tMCK/2)
-4
ns
MOSI Output Hold Time
After SCLK Sample
Edge
tMOH
(tMCK/2)
-4
ns
MOSI Output Valid to
Sample Edge
tMOV
(tMCK/2)
-4
ns
MISO Input Valid to
SCLK Sample Edge
Setup
tMIS
1
ns
MISO Input to SCLK
Sample Edge
tMIH
SHIFT
1/fMCK
ns
1
SAMPLE
SHIFT
ns
SAMPLE
SS
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
tMCL
SCK
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV
MSB
MOSI/SDIO
(OUTPUT)
tMIS
MISO/SDIO
(INPUT)
MSB
LSB
MSB-1
tMIH
MSB-1
LSB
Figure 1. SPI Master and SPI XIP Master Timing
www.maximintegrated.com
Maxim Integrated │ 12
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Electrical Characteristics—SPI Slave
(AC Electrical Specifications are guaranteed by design and are not production tested, VDD18 = VRST to 1.89V, TA = -30°C to +85°C.)
PARAMETER
SYMBOL
Slave Operating
Frequency
fSCK
SCLK Period
tSCK
CONDITIONS
MIN
TYP
MAX
Standard SPI mode
22.7
Fast SPI mode
45.5
1/fSCK
UNITS
MHz
ns
Electrical Characteristics—I2C Bus
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range
are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested.)
PARAMETER
I2C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUS
Standard mode, VDDIO selected as I/O
supply
Input High Voltage
VIH_I2C
Standard mode, VDDIOH selected as I/O
supply
0.7 ×
VDDIOH
Fast mode, VDDIO selected as I/O supply
0.7 ×
VDDIO
VDDIO +
0.5
0.7 ×
VDDIOH
VDDIOH +
0.5
Standard mode, VDDIO selected as I/O
supply
-0.5
0.3 ×
VDDIO
Standard mode, VDDIOH selected as I/O
supply
-0.5
0.3 ×
VDDIOH
Fast mode, VDDIO selected as I/O supply
-0.5
0.3 ×
VDDIO
Fast mode, VDDIOH selected as I/O
supply
-0.5
0.3 ×
VDDIOH
Fast mode, VDDIOH selected as I/O
supply
Input Low Voltage
Input Hysteresis
(Schmitt)
Output Logic-Low
(Open Drain or Open
Collector)
VIL_I2C
VIHYS_I2C
VOL_I2C
0.7 ×
VDDIO
Fast mode, VDDIO selected as I/O supply
Fast mode, VDDIOH selected as I/O
supply
0.05 x
VDDIO
0
Fast mode, IIL = 3mA
V
V
0.05 x
VDDIOH
Standard mode, IIL = 3mA
V
0.4
0
0.4
Fast mode, IIL = 2mA, VDDIO selected as
I/O supply
0
0.2 x
VDDIO
Fast mode, IIL = 2mA, VDDIOH selected
as I/O supply
0
0.2 x
VDDIOH
Standard mode
0
100
Fast mode
0
400
V
I2C TIMING
SCL Clock Frequency
www.maximintegrated.com
fSCL
kHz
Maxim Integrated │ 13
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Pin Configurations
MAX32625/MAX32626
TOP VIEW (BUMP SIDE DOWN)
1
2
3
4
5
6
7
8
9
A
P0.2
P0.0
SRSTN
AIN0
AIN1
AIN2
AIN3
VDD18
32KIN
B
P0.5
P0.1
RSTN
TCK
TMS
TDO
TDI
VSS
32KOUT
C
VDDIOH
P0.7
P0.4
P0.3
P4.5
P4.6
P4.7
VSS
VRTC
D
VSS
P1.2
P1.0
P0.6
P3.3
P3.4
P4.4
VDDIO
VDDB
E
VDD12
P1.4
P1.3
P1.1
P2.5
P3.0
P4.1
DP
DM
F
P1.6
P1.5
P1.7
P2.3
P2.6
P3.1
P3.6
P4.2
P4.3
G
P2.0
P2.1
P2.2
P2.4
P2.7
P3.2
P3.5
P3.7
P4.0
+
63 WLP
www.maximintegrated.com
Maxim Integrated │ 14
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
P4.6
VRTC
32KOUT
32KIN
36
35
VDDIO
42
37
DP
43
38
DM
44
VDDB
P4.5
VDDIOH
P4.4
46
39
P4.3
47
40
P4.2
48
VSS
P4.1
49
41
P4.0
50
45
P3.7
TOP VIEW
51
Pin Configurations (continued)
VSS
52
34
P3.6
P3.5
53
33
54
32
P3.4
55
31
VDD18
AIN3
P3.3
56
30
TDI
P3.2
57
29
AIN2
P3.1
58
28
TDO
P3.0
P2.7
59
27
AIN1
26
TCK
P2.6
61
25
AIN0
P2.5
62
24
TMS
VSS
P2.4
63
23
64
22
VDD18
SRSTN
P2.3
65
21
RSTN
P2.2
66
20
P0.0
P2.1
67
19
P2.0
68
VDDIOH
P0.1
MAX32625/MAX32626
60
EP = EXPOSED PAD
14
15
16
17
P0.5
P0.4
P0.3
P0.2
11
P1.0
12
10
P1.1
13
9
P0.6
8
VDD12
P1.2
18
P0.7
7
P1.3
VDDIO
P1.5
6
3
5
2
P1.6
VSS
P1.4
1
P1.7
4
+
VSS
P4.7
68 TQFN-EP
www.maximintegrated.com
Maxim Integrated │ 15
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Pin Description
PIN
68 TQFNEP
NAME
A8
23, 32
VDD18
B8, C8, D1
5, 34, 41, 52,
63
VSS
C1
19, 46
VDDIOH
C9
37
VRTC
RTC Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as
close as possible to the package.
D8
3, 42
VDDIO
I/O Supply Voltage. 1.8V ≤ VDDIO ≤ 3.6V. See EC table for VDDIO specification.
This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to
the package.
D9
40
VDDB
USB Transceiver Supply Voltage. This pin must be bypassed to VSS with a 1.0μF
capacitor as close as possible to the package.
E1
8
VDD12
1.2V Nominal Supply Voltage. This pin must be bypassed to VSS with a 1.0μF
capacitor as close as possible to the package.
—
—
EP
Exposed Pad (TQFN-EP Only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
32kHz Crystal Oscillator Input. Connect a 6pF 32kHz crystal between 32KIN and
32KOUT for RTC operation. Optionally, an external clock source can be driven
on 32KIN if the 32KOUT pin is left unconnected. A 32kHz crystal or external clock
source is required for proper USB operation.
63 WLP
FUNCTION
POWER PINS
1.8V Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as
close as possible to the package.
Digital Ground
I/O Supply Voltage, High. 1.8V ≤ VDDIOH ≤ 3.6V, always with VDDIOH ≥ VDDIO.
See EC table for VDDIOH specification. This pin must be bypassed to VSS with a
1.0μF capacitor as close as possible to the package.
CLOCK PINS
A9
35
32KIN
B9
36
32KOUT
E8
43
DP
USB DP Signal. This bidirectional pin carries the positive differential data or singleended data. This pin is weakly pulled high internally when the USB is disabled.
E9
44
DM
USB DM Signal. This bidirectional pin carries the negative differential data or singleended data. This pin is weakly pulled high internally when the USB is disabled.
B4
26
TCK/SWCLK
JTAG Clock
Serial Wire Debug Clock
This pin has an internal 25kΩ pullup to VDDIO.
B5
24
TMS/SWDIO
JTAG Test Mode Select
Serial Wire Debug I/O
This pin has an internal 25kΩ pullup to VDDIO.
32kHz Crystal Oscillator Output
USB PINS
JTAG PINS
www.maximintegrated.com
Maxim Integrated │ 16
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Pin Description (continued)
PIN
63 WLP
68 TQFNEP
NAME
FUNCTION
B6
28
TDO
JTAG Test Data Output
B7
30
TDI
JTAG Test Data Inputt. This pin has an internal 25kΩ pullup to VDDIO.
RESET PINS
A3
B3
22
21
SRSTN
RSTN
Software Reset, Active-Low Input/Output. The device remains in software reset
while this pin is in its active state. When the pin transitions to its inactive state, the
device performs a reset to the ARM core, digital registers and peripherals (resetting
most of the core logic on the VDD12 supply). This reset does not affect the POR
only registers, RTC logic, ARM debug engine or JTAG debugger allowing for a soft
reset without having to reconfigure all registers.
After the device senses SRSTN as a logic 0, the pin automatically reconfigures
as an output sourcing a logic 0. The device continues to output for 6 system clock
cycles and then repeats the input sensing/output driving until SRSTN is sensed
inactive.
This pin is internally connected with an internal 25kΩ pullup to the VDDIO supply.
This pin should be left unconnected if the system design does not provide a reset
signal to the device.
Hardware Power Reset (Active-Low) Input. The device remains in reset while this
pin is in its active state. When the pin transitions to its inactive state, the device
performs a POR reset (resetting all logic on all supplies except for real-time clock
circuitry) and begins execution. This pin is internally connected with an internal
25kΩ pullup to the VRTC supply. This pin should be left unconnected if the system
design does not provide a reset signal to the device.
GENERAL-PURPOSE I/O AND SPECIAL FUNCTIONS (See Table 1. General-Purpose I/O Matrix)
A2
20
P0.0
GPIO Port 0.0
B2
18
P0.1
GPIO Port 0.1
A1
17
P0.2
GPIO Port 0.2
C4
16
P0.3
GPIO Port 0.3
C3
15
P0.4
GPIO Port 0.4
B1
14
P0.5
GPIO Port 0.5
D4
13
P0.6
GPIO Port 0.6
C2
12
P0.7
GPIO Port 0.7
D3
11
P1.0
GPIO Port 1.0
E4
10
P1.1
GPIO Port 1.1
D2
9
P1.2
GPIO Port 1.2
E3
7
P1.3
GPIO Port 1.3
E2
6
P1.4
GPIO Port 1.4
F2
4
P1.5
GPIO Port 1.5
F1
2
P1.6
GPIO Port 1.6
F3
1
P1.7
GPIO Port 1.7
G2
67
P2.1
GPIO Port 2.1
G3
66
P2.2
GPIO Port 2.2
www.maximintegrated.com
Maxim Integrated │ 17
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Pin Description (continued)
PIN
63 WLP
68 TQFNEP
NAME
FUNCTION
F4
65
P2.3
GPIO Port 2.3
G4
64
P2.4
GPIO Port 2.4
E5
62
P2.5
GPIO Port 2.5
F5
61
P2.6
GPIO Port 2.6
G5
60
P2.7
GPIO Port 2.7
E6
59
P3.0
GPIO Port 3.0
F6
58
P3.1
GPIO Port 3.1
G6
57
P3.2
GPIO Port 3.2
D5
56
P3.3
GPIO Port 3.3
D6
55
P3.4
GPIO Port 3.4
G7
54
P3.5
GPIO Port 3.5
F7
53
P3.6
GPIO Port 3.6
G8
51
P3.7
GPIO Port 3.7
G9
50
P4.0
GPIO Port 4.0
E7
49
P4.1
GPIO Port 4.1
F8
48
P4.2
GPIO Port 4.2
F9
47
P4.3
GPIO Port 4.3
D7
45
P4.4
GPIO Port 4.4
C5
39
P4.5
GPIO Port 4.5
C6
38
P4.6
GPIO Port 4.6
C7
33
P4.7
GPIO Port 4.7
ANALOG INPUT PINS
A4
25
AIN0
ADC Input 0. 5V Tolerant Input
A5
27
AIN1
ADC Input 1. 5V Tolerant Input
A6
29
AIN2
ADC Input 2
A7
31
AIN3
ADC Input 3
www.maximintegrated.com
Maxim Integrated │ 18
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Detailed Description
Power Operating Modes
MAX32625/MAX32626
Low Power Mode 0 (LP0)
The MAX32625/MAX32626 is an ultra-low power, highefficiency, mixed-signal microcontroller based on the ARM
Cortex-M4 with FPU with a maximum operating frequency
of 96MHz with a hardware AES engine. An internal 4MHz
oscillator supports minimal power consumption for applications requiring always-on monitoring. The MAX32626 is a
secure version of the MAX32625, incorporating a trust protection unit (TPU) with advanced security features.
This mode places the core and peripheral logic in a static,
low-power state. All features of the device are disabled
except:
Application code executes from an internal 512KB program flash memory with up to 160KB SRAM available for
general-application use. An 8KB instruction cache
improves execution throughput, and a transparent code
scrambling scheme is used to protect customer intellectual
property residing in the internal program flash memory.
Additionally, a SPI execute in place (SPIX) external memory interface allows application code and data (up to 16MB)
to be accessed from an external SPI memory device.
●● Voltage supply monitoring
The MAX32625L is a lower-cost version of the MAX32625,
providing 256KB of flash and 128KB of SRAM.
Low Power Mode 2 (LP2)
A 10-bit delta-sigma ADC is provided with a multiplexer
front end for four external input channels (two of which are
5.5V tolerant) and internal channels to monitor internal
voltages. Built-in limit monitors allow converted input samples to be compared against user-configurable high and
low limits with an option to trigger an interrupt and wake
the CPU from a low power mode if attention is required.
A wide variety of communications and interface peripherals are provided. Other communications peripherals
include a USB 2.0 slave interface, three master SPI interfaces, one slave SPI interface, three UART interfaces with
multidrop support, up to two master I2C interfaces, and
one slave I2C interface.
●● Power sequencer
●● RTC clock (if enabled)
●● Key data retention registers
●● Power-on reset
Data retention in this mode can be maintained using only
the VRTC supply with all other voltage supplies disabled.
Low Power Mode 1 (LP1)
This mode places the core logic in a static, low-power
state that supports a fast wake-up feature. Data retention
in this mode can be maintained using only the VRTC supply with all other voltage supplies disabled.
This configuration allows the ADC and some peripherals to operate while the ARM core is in sleep mode. The
peripheral management unit provides intelligent, dynamic
clocking of any enabled peripherals, ensuring the lowest
possible power consumption.
Low Power Mode 3 (LP3)
During this state, the CPU is executing application code
and all digital and analog peripherals are fully powered
and awake. Dynamic clocking disables peripherals not in
use, providing the optimal mix of high performance and
low power consumption.
Analog-to-Digital Converter
ARM Cortex-M4 with FPU Processor
The 10-bit delta-sigma ADC provides 4 external inputs
and can also measure all internal power supplies. It operates at a maximum of 7.8ksps. AIN0 and AIN1 are 5V
tolerant, making them suitable for monitoring batteries.
The ARM Cortex-M4 with FPU DSP supports single
instruction multiple data (SIMD) path DSP extensions,
providing:
An optional feature allows samples captured by the ADC
to be automatically compared against user-programmable
high and low limits. Up to four channel limit pairs can be
configured in this way. The comparison allows the ADC
to trigger an interrupt (and potentially wake the CPU
from a low power sleep mode) when a captured sample
goes outside the preprogrammed limit range. Since this
comparison is performed directly by the sample limit
monitors, it can be performed even while the main CPU is
suspended in a low power mode.
The ARM Cortex-M4 with FPU processor is ideal for the
emerging category of wearable medical and wellness
applications. The architecture combines high-efficiency
signal processing functionality with the low power, low
cost, and ease-of-use benefits.
●●
●●
●●
●●
●●
4 parallel 8-bit add/sub
2 parallel 16-bit add/sub
2 parallel MACs
32- or 64-bit accumulate
Signed, unsigned data with or without saturation
www.maximintegrated.com
Maxim Integrated │ 19
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
The ADC measures:
●● AIN[3:2] (up to 3.3V)
●● AIN[1:0] (up to 5.5V)
●● VDD12
●● VDD18
●● VDDB
●● VRTC
●● VDDIO
●● VDDIOH
●● Pulse trains can be started/synchronized independently or as a group
Pulse Train Engine
16 independent pulse train generators can provide either
a square wave or a repeating pattern from 2 bits to 32 bits
in length. Any single pulse train generator or any desired
group of pulse train generators can be synchronized at
the bit level allowing for multibit patterns
Each pulse train generator is independently configurable.
The pulse train generators provide the following features:
●● Independently enabled
●● Multiple pin configurations allow for flexible layout
●● Frequency of each enabled pulse train generator is
also set separately, based on a divide down (divide
by 2, divide by 4, divide by 8, and so on) of the input
pulse train module clock
●● Multiple repetition options for pulse train mode
• Single shot (nonrepeating pattern of 2–32 bits)
• Pattern repeats user-configurable number of times
or indefinitely
• End of one pulse train's loop count can restart one
or more other pulse trains
Clocking Scheme
The high-frequency internal relaxation oscillator operates
at a nominal frequency of 96MHz. It is the primary clock
source for the digital logic and peripherals. Select the
4MHz internal oscillator to optimize active power consumption. Wake-up is possible from either the 4MHz or
the 96MHz internal oscillator.
An external 32.766kHz time base is required when using
the RTC or USB features of the device.
Figure 2. MAX32625/MAX32626 Clock Scheme
www.maximintegrated.com
Maxim Integrated │ 20
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Interrupt Sources
●● Configurable strong or weak internal pullup/pulldown
resistors
The ARM nested vector interrupt controller (NVIC) provides
high speed, deterministic interrupt response, interrupt
masking, and multiple interrupt sources. Each peripheral
is connected to the NVIC and can have multiple interrupt
flags indicating the specific source of the interrupt within
the peripheral. The NVIC provides:
●● Up to 43 distinct interrupt sources (including internal
and external interrupts)
●● 8 priority levels
●● A dedicated interrupt for each port
Real-Time Clock and Wake-Up Timer
A real-time clock (RTC) keeps the time of day in absolute
seconds. The time base can be generated by connecting a 32kHz crystal between 32KIN and 32KOUT or an
external clock source can be applied to the 32KIN pin.
The external clock source must meet the electrical/timing
requirements in the Electrical Characteristics table. The
32kHz output can be directed on a GPIO for observation
and use.
The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by
application software. A time-of-day alarm and independent subsecond alarm can cause an interrupt or wake the
device from stop mode.
The wake-up timer allows the device to remain in low
power mode for extended periods of time. The minimum
wake-up interval is 244μs.
The VRTC supply supports SRAM retention in power
mode LP0.
General-Purpose I/O and
Special Function Pins
General-purpose I/O (GPIO) pins are controlled directly
by firmware or one or more peripheral modules connected
to that pin. GPIO are logically divided into 8-pin ports.
Each 8-bit port provides a dedicated interrupt.
The alternate functions for each pin are shown in Table 1.
The following features are independently configurable for
each GPIO pin:
●● GPIO or special function mode operation
●● VDDIO or VDDIOH supply voltage
●● Normal and fast output drive strength
●● Open-drain output or high impedance input
www.maximintegrated.com
●● Simple output-only functions
• Output from pulse trains (0 through 15)
• Output from timers running in 32-bit mode
Some peripherals have optional pin assignments, allowing for greater flexibility during PCB layout. These optional
pin assignments are identified with the letter "B," "C," or
"D" after the peripheral name. For example, if the "A" configuration is chosen for UART0, the UART0_RX signal is
mapped to the P0.0 pin. If the "B" configuration is chosen,
the UART0_RX signal is mapped to the P0.1 pin.
CRC Module
A CRC hardware module provides fast calculations and
data integrity checks by application software. The CRC
module supports both the CRC-16-CCITT and CRC-32
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 +
X7 + X5 + X4 + X2 + X + 1) polynomials.
Watchdog Timers
Two independent watchdog timers (WDT0 and WDT1)
with window support are provided. The watchdog timers
are independent and have multiple clock source options
to ensure system security. The watchdog uses a 32-bit
timer with prescaler to generate the watchdog reset.
When enabled, the watchdog timers must be fed prior
to timeout or within a window of time if window mode
is enabled. Failure to reset the watchdog timer during
the programmed timing window results in a watchdog
timeout. The WDT0 or WDT1 flags are set on reset if a
watchdog expiration caused the system reset. The clock
source options for the watchdog timers include:
●● Scaled-system clock
●● Real-time clock
●● Power-management clock
A third watchdog timer (WDT2) is provided for recovery
from runaway code or system unresponsiveness. When
enabled, this watchdog must be reset prior to timeout,
resulting in a watchdog timeout. The WDT2 flag is set on
reset if a watchdog expiration caused the system reset.
WDT2 is unique in that is in the always-on domain, and
continues to run even in LP1 or LP0. The timeout period
for WDT2 can be programmed as long as 8 seconds.
The granularity of the timeout period is intended only for
system recovery.
Maxim Integrated │ 21
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Programmable Timers
Serial Peripherals
Six 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals. Each of
the 32-bit timers can also be split into two 16-bit timers,
enabling 12 standard 16-bit timers.
The 32-bit timer provide a number of features:
●● 32-bit up/down autoreload
●● Programmable prescaler
●● PWM output generation
●● Capture, compare, and capture/compare capability
●● External input pin for timer input, clock gating or
capture, limited to an input frequency of 1/4 of the
peripheral clock frequency
●● Timer output pin
●● Configurable as 2x 16-bit general-purpose timers
●● Timer interrupt
USB
The integrated USB slave controller is compliant with the
full-speed (12Mb/s) USB 2.0 specification. The integrated
USB physical interface (PHY) reduces board space and
system cost. The USB is powered by the VDDB supply.
The USB controller supports DMA for the endpoint buffers. A total of 7 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0.
An external 32kHz crystal or clock source is required
for USB operation, even if the RTC function is not used.
Although the USB timing is derived from the internal
96MHz oscillator, the default accuracy is not sufficient
for USB operation. Periodic firmware adjustments of
the 96MHz oscillator, using the 32kHz timebase as a
reference, are necessary to comply with the USB timing
requirements.
Figure 3. 32-Bit Timer
www.maximintegrated.com
Maxim Integrated │ 22
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
I2C Master and Slave
●● Programmable SCK alternate timing
The I2C interface is a bidirectional, two-wire serial bus
that provides a medium-speed communications network.
It can operate as a one-to-one, one-to-many, or many-tomany communications medium.
Two I2C interfaces allow combinations of up to two I2C
master engines and/or one I2C-selectable slave engine to
connect to a wide variety of I2C-compatible peripherals.
These engines support both standard-mode and fastmode I2C standards. The slave engine shares the same
I/O port as the master engines and is selected through
the I/O configuration settings. It provides the following
features:
●● Master or slave mode operation
●● Supports standard (7-bit) addressing or 10-bit
addressing
●● Support for clock stretching to allow slower slave
devices to operate on higher speed busses
●● SS assertion and deassertion timing with respect to
leading/trailing SCK edge
SPI (Slave)
The SPI slave (SPIS) port provides a highly configurable,
flexible, and efficient interface to communicate with a wide
variety of SPI master devices. The SPI slave interface
provides the following features:
●● Supports SPI modes 0 and 3
●● Full-duplex operation in single-bit, 4-wire mode
●● Slave select polarity fixed (active low)
●● Dual and quad I/O supported
●● High-speed AHB access to transmit and receive
using 32-byte FIFOs
●● Four interrupts to monitor FIFO levels
SPI (Execute in Place (SPIX) Master)
●● Transmitter FIFO depth of 16 bytes
The SPI execute in place (SPIX) master allows the CPU
to transparently execute instructions stored in an external
SPI flash. Instructions fetched through the SPIX master
are cached just like instructions fetched from internal
program memory. The SPIX master can also be used to
access large amounts of external static data that would
otherwise reside in internal data memory.
SPI (Master)
UART
●● Multiple transfer rates
• Standard mode: 100KBps
• Fast mode: 400KBps
●● Internal filter to reject noise spikes
●● Receiver FIFO depth of 16 bytes
The SPI master-mode-only (SPIM) interface operates
independently in a single or multiple slave system and is
fully accessible to the user application.
The SPI ports provide a highly configurable, flexible, and
efficient interface to communicate with a wide variety of
SPI slave devices. The three SPI master ports (SPI0,
SPI1, SPI2) support the following features:
●● Supports all four SPI modes (0, 1, 2, 3) for single-bit
communication
●● High-speed AHB access to transmit and receive
using 32-byte Rx FIFO and 16-byte Tx FIFO
All three universal asynchronous receiver-transmitter
(UART) interfaces support full-duplex asynchronous
communication with optional hardware flow control (HFC)
modes to prevent data overruns. If HFC mode is enabled
on a given port, the system uses two extra pins to
implement the industry standard request to send (RTS)
and clear to send (CTS) methodology. Each UART is
individually programmable.
●● 2-wire interface or 4-wire interface with flow control
●● 32-byte send/receive FIFO
●● Full-duplex operation for asynchronous data transfers
●● 3- or 4-wire mode for single-bit slave device
communication
●● Programmable interrupt for receive and transmit
●● Full-duplex operation in single-bit, 4-wire mode
●● Dual and quad I/O supported
●● Programmable 9th bit supports even/odd parity or
multi-drop mode
●● Up to 5 slave select lines per port
●● User-selectable UART slave address
●● Up to 2 slave ready lines
●● Start/stop bit support
●● Programmable interface timing
●● Hardware flow control using RTS/CTS
●● Programmable SCK frequency and duty cycle
●● Maximum baud rate: 1843.2KB
www.maximintegrated.com
●● Independent baud-rate generator
Maxim Integrated │ 23
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
1-Wire Master
●● PMU action can be initiated from interrupt conditions
from peripherals without CPU
●● Integrated AHB bus master
●● Coprocessor-like state machine
Maxim's DeepCover® 1-Wire security solutions provide
a cost-effective solution to authenticate medical sensors and peripherals, preventing counterfeit products.
The integrated 1-Wire master communicates with slave
devices through the bidirectional, multidrop 1-Wire bus.
All of the devices on the 1-Wire bus share one signal that
carries data communication and also supplies power to
the slave devices. The single contact serial interface is
ideal for communication networks requiring minimal interconnect. Features of the 1-Wire bus include:
●● Single contact for control and operation
●● Unique factory identifier for any 1-Wire device
●● Power is distributed to all slave device
(parasitic power)
●● Multiple device capability on a single line
●● Supports 1-Wire standard (15.6KBps) and overdrive
(110KBps) speeds
The incorporation of the 1-Wire master enables the
creation of 1-Wire enhanced consumable and reusable
accessories. The following benefits can be added to products by the addition of only one contact:
●● OEM authenticity is verifiable with SHA-256 and
ECDSA
●● External tracking is eliminated because calibration
data can be securely stored within an accessory
●● Reuse of single-use accessories can be prevented
●● Counterfeit products can be identified and use denied
using the unique, factory identifier
●● Environmental temperature and humidity sensing
Peripheral Management Unit (PMU)
The PMU is a DMA-based link list processing engine that
performs operations and data transfers involving memory
and/or peripherals in the advanced peripheral bus (APB)
and advanced high-performance bus (AHB) peripheral
memory space while the main CPU is in a sleep state.
This allows low-overhead peripheral operations to be
performed without the CPU, significantly reducing overall
power consumption. Using the PMU with the CPU in a
sleep state provides a lower-noise environment critical for
obtaining optimum ADC performance.
Key features of the PMU engine include:
●● Six independent channels with round-robin
scheduling allows for multiple parallel operations
●● Programmed using PMU opcodes stored in SRAM
Additional Documentation
Engineers must have the following documents to fully use
this device:
●● This data sheet, containing pin descriptions, feature
overviews, and electrical specifications
●● The device-appropriate user guide, containing detailed information and programming guidelines for
core features and peripherals
●● Errata sheets for specific revisions noting deviations
from published specifications
Development and Technical Support
Contact technical support for information about highly
versatile, affordable development tools, available from
Maxim Integrated and third-party vendors.
●●
●●
●●
●●
●●
Evaluation kits
Software development kit
Compilers
Integrated development environments (IDEs)
USB interface modules for programming and debugging
Trust Protection Unit (TPU) (MAX32626 Only)
The TPU enhances cryptographic data security for valuable intellectual property (IP) and data. High-speed,
hardware-based cryptographic accelerators perform
mathematical computations that support cryptographic
algorithms, including:
●●
●●
●●
●●
●●
AES-128
AES-192
AES-256
1024-bit DSA
2048-bit (CRT)
The device provides a true random number generator
(TRNG) that can be used to create cryptographic keys for
any application. A user-selectable entropy source further
increases the randomness and key strength.
The secure bootloader protects against unauthorized
access to program memory.
DeepCover is a registered trademark of Maxim Integrated
Products, Inc.
www.maximintegrated.com
Maxim Integrated │ 24
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
MAX32625/MAX32626
Applications Information
General-Purpose I/O Matrix
Table 1. General-Purpose I/O Matrix
SECONDARY FUNCTION
PULSE TRAIN
OUTPUT
TIMER INPUT
GPIO
INTERRUPT
UART0A_RX
UART0B_TX
PT_PT0
TIMER_TMR0
GPIO_INT(P0)
UART0A_TX
UART0B_RX
PT_PT1
TIMER_TMR1
GPIO_INT(P0)
UART0A_CTS
UART0B_RTS
PT_PT2
TIMER_TMR2
GPIO_INT(P0)
UART0A_RTS
UART0B_CTS
PT_PT3
TIMER_TMR3
GPIO_INT(P0)
GPIO
PRIMARY FUNCTION
P0.0
P0.1
P0.2
P0.3
P0.4
SPIM0A_SCK
PT_PT4
TIMER_TMR4
GPIO_INT(P0)
P0.5
SPIM0A_MOSI/SDIO0
PT_PT5
TIMER_TMR5
GPIO_INT(P0)
P0.6
SPIM0A_MISO/SDIO1
PT_PT6
TIMER_TMR0
GPIO_INT(P0)
P0.7
SPIM0A_SS0
PT_PT7
TIMER_TMR1
GPIO_INT(P0)
P1.0
SPIM1A_SCK
SPIX0A_SCK
PT_PT8
TIMER_TMR2
GPIO_INT(P1)
P1.1
SPIM1A_MOSI/SDIO0
SPIX0A_SDIO0
PT_PT9
TIMER_TMR3
GPIO_INT(P1)
P1.2
SPIM1A_MISO/SDIO1
SPIX0A_SDIO1
PT_PT10
TIMER_TMR4
GPIO_INT(P1)
P1.3
SPIM1A_SS0
SPIX0A_SS0
PT_PT11
TIMER_TMR5
GPIO_INT(P1)
P1.4
SPIM1A_SDIO2
SPIX0A_SDIO2
PT_PT12
TIMER_TMR0
GPIO_INT(P1)
P1.5
SPIM1A_SDIO3
SPIX0A_SDIO3
PT_PT13
TIMER_TMR1
GPIO_INT(P1)
P1.6
I2CM0A_SDA /
I2CS0A_SDA
PT_PT14
TIMER_TMR2
GPIO_INT(P1)
P1.7
I2CM0A_SCL /
I2CS0A_SCL
PT_PT15
TIMER_TMR3
GPIO_INT(P1)
P2.0
UART1A_RX
UART1B_TX
PT_PT0
TIMER_TMR4
GPIO_INT(P2)
P2.1
UART1A_TX
UART1B_RX
PT_PT1
TIMER_TMR5
GPIO_INT(P2)
P2.2
UART1A_CTS
UART1B_RTS
PT_PT2
TIMER_TMR0
GPIO_INT(P2)
P2.3
UART1A_RTS
UART1B_CTS
PT_PT3
TIMER_TMR1
GPIO_INT(P2)
P2.4
SPIM2A_SCK
PT_PT4
TIMER_TMR2
GPIO_INT(P2)
P2.5
SPIM2A_MOSI/SDIO0
PT_PT5
TIMER_TMR3
GPIO_INT(P2)
P2.6
SPIM2A_MISO/SDIO1
PT_PT6
TIMER_TMR4
GPIO_INT(P2)
P2.7
SPIM2A_SS0
PT_PT7
TIMER_TMR5
GPIO_INT(P2)
P3.0
UART2A_RX
UART2B_TX
PT_PT8
TIMER_TMR0
GPIO_INT(P3)
P3.1
UART2A_TX
UART2B_RX
PT_PT9
TIMER_TMR1
GPIO_INT(P3)
P3.2
UART2A_CTS
UART2B_RTS
PT_PT10
TIMER_TMR2
GPIO_INT(P3)
P3.3
UART2A_RTS
UART2B_CTS
PT_PT11
TIMER_TMR3
GPIO_INT(P3)
P3.4
I2CM1A_SDA / I2CS0B_SDA
SPIM2A_SS1
PT_PT12
TIMER_TMR4
GPIO_INT(P3)
P3.5
I2CM1A_SCL / I2CS0B_SCL
SPIM2A_SS2
PT_PT13
TIMER_TMR5
GPIO_INT(P3)
P3.6
SPIM1A_SS1
SPIX_SS1
PT_PT14
TIMER_TMR0
GPIO_INT(P3)
P3.7
SPIM1A_SS2
SPIX_SS2
PT_PT15
TIMER_TMR1
GPIO_INT(P3)
P4.0
OWM_I/O
SPIM2A_SR0
PT_PT0
TIMER_TMR2
GPIO_INT(P4)
P4.1
OWM_PUPEN
SPIM2A_SR1
PT_PT1
TIMER_TMR3
GPIO_INT(P4)
P4.2
SPIM0A_SDIO2
SPIS0A_SDIO2
PT_PT2
TIMER_TMR4
GPIO_INT(P4)
www.maximintegrated.com
Maxim Integrated │ 25
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
MAX32625/MAX32626
Table 1. General-Purpose I/O Matrix (continued)
GPIO
PRIMARY FUNCTION
SECONDARY FUNCTION
PULSE TRAIN
OUTPUT
TIMER INPUT
GPIO
INTERRUPT
P4.3
SPIM0A_SDIO3
SPIS0A_SDIO3
PT_PT3
TIMER_TMR5
GPIO_INT(P4)
P4.4
SPIM0A_SS1
SPIS0A_SCLK
PT_PT4
TIMER_TMR0
GPIO_INT(P4)
P4.5
SPIM0A_SS2
SPIS0A_MOSI/SDIO0
PT_PT5
TIMER_TMR1
GPIO_INT(P4)
P4.6
SPIM0A_SS3
SPIS0A_MISO/SDIO1
PT_PT6
TIMER_TMR2
GPIO_INT(P4)
P4.7
SPIM0A_SS4
SPIS0A_SS0
PT_PT7
TIMER_TMR3
GPIO_INT(P4)
Typical Application Circuit
MAX14690N PMIC
MAX32625/MAX32626
I 2C
PMIC CONTROL
RTC
USB PHY
VRTC
POWER
MANAGER
96MHZ OSCILLATOR
GPIO VOLTAGE
SELECT
4MHZ OSCILLATOR
CHARGER
VBUS
1.8V LDO1
VDDB
3.3V LDO2
AIN
ADC
CONTROL
Li-ION
MONITOR
VDDA
VDD18
1.8V BUCK2
VDDIO
3.0V LDO3
VDDIOH
VDD12
1.2V BUCK1
ARM CORTEX-M4
WITH FPU CORE
VDD
SPI
2MB FLASH
STANDBY
PFN1
EM9301 BLE RADIO
SPI BRIDGE
512 KB SRAM
24MHz
32kHz
AFE CONTROL
SPI
MAX30003
BIOPOTENTIAL AFE
ECGP
EXTERNAL
EMI
FILTERS
AVDD
DVDD
VDD18
www.maximintegrated.com
OVDD
PHYSICAL
ELECTRODES
ECGN
Maxim Integrated │ 26
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
MAX32625/MAX32626
Ordering Information
PART
FLASH (KB)
SRAM (KB)
TRUST PROTECTION UNIT (TPU)
PIN-PACKAGE
MAX32625IWY+
512
160
No
63 WLP
MAX32625IWY+T
512
160
No
63 WLP
MAX32625ITK+
512
160
No
68 TQFN-EP
MAX32625ITK+T
512
160
No
68 TQFN-EP
MAX32625IWYL+
256
128
No
63 WLP
MAX32625IWYL+T
256
128
No
63 WLP
MAX32625ITKL+
256
128
No
68 TQFN-EP
MAX32625ITKL+T
256
128
No
68 TQFN-EP
MAX32626IWY+
512
160
Yes
63 WLP
MAX32626IWY+T
512
160
Yes
63 WLP
MAX32626ITK+
512
160
Yes
68 TQFN-EP
MAX32626ITK+T
512
160
Yes
68 TQFN-EP
MAX32626ITKBL+
512
160
Yes (includes secure boot)
68 TQFN-EP
MAX32626ITKBL+T
512
160
Yes (includes secure boot)
68 TQFN-EP
MAX32626IWYBL+*
512
160
Yes (includes secure boot)
63 WLP
MAX32626IWYBL+T*
512
160
Yes (includes secure boot)
63 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—contact factory for availability.
www.maximintegrated.com
Maxim Integrated │ 27
MAX32625/MAX32626
Ultra-Low-Power Arm Cortex-M4 with
FPU-Based Microcontroller (MCU) with
512KB Flash and 160KB SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
0
8/16
Initial release
6/17
Corrected ARM trademarks, clarified 1-Wire master functions are listed in GPIO
matrix table, added Typical Application Circuit diagram, corrected Figure 1. SPI
Master and SPI XIP Master Timing, explained VRTC supply supports SRAM retention
in LP0, corrected pin 46 from VDDIO to VDDIOH on 68 TQFN-EP Pin Configuration
drawing to match Pin Description table (no change to fit or function), added EP to Pin
Description, changed PRNG to TRNG
2
8/17
Updated Simplified Block Diagram, removed future product references
3
10/17
Removed future product references
4
3/18
Updated General Description, updated Arm trademarks, corrected TQFN instances to
TQFN-EP
1
4.1
PAGES
CHANGED
DESCRIPTION
—
1, 15, 16,
19, 24, 26
4, 27
27
Corrected typo in General Description
1–28
1
5
10/18
Updated title, General Description, Benefits and Features, Additional Documentation,
Development and Technical Support, and Trust Protection Unit (TPU) (MAX32626
Only) sections
1–28
6
2/20
Updated Simplified Block Diagram and Ordering Information
4, 27
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc. │ 28
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