EVALUATION KIT AVAILABLE
MAX32630–MAX32632
General Description
DARWIN is a new breed of low-power microcontrollers
built to thrive in the rapidly evolving Internet of Things (IoT).
They are smart, with the biggest memories in their class
and a massively scalable memory architecture. They run
forever, thanks to wearable-grade power technology. They
are also tough enough to withstand the most advanced
cyberattacks. DARWIN microcontrollers are designed
to run any application imaginable—in places where you
wouldn’t dream of sending other microcontrollers.
Generation U microcontrollers are perfect for wearables
and IoT applications that cannot afford to compromise
power or performance. The MAX32630–MAX32632 feature an Arm® Cortex®-M4 with FPU CPU that delivers
ultra-low power, high-efficiency signal processing functionality with significantly reduced power consumption
and ease of use.
Flexible power modes, an intelligent peripheral management
unit (PMU), dynamic clock gating and firmware-controlled
power gating optimizes power for the specific application.
Multiple SPI, UART, I2C, 1-Wire® master, and USB interfaces are provided. The four-input, 10-bit ADC with selectable references can monitor external sensors.
The MAX32631/MAX32632 are secure versions of the
MAX32630. They provide a trust protection unit (TPU) with
encryption and advanced security features. These include
a modular arithmetic accelerator (MAA) for fast ECDSA,
a true random number generator, and a hardware AES
engine. The MAX32632 also provides a secure bootloader
for additional security and life-cycle management.
Applications
●● Sports Watches
●● Fitness Monitors
●● Wearable Medical Patches
●● Portable Medical Devices
●● Sensor Hubs
Ordering Information appears at end of data sheet.
Arm and Cortex are registered trademarks of Arm Limited (or its
subsidiaries) in the US and/or elsewhere.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
19-8478; Rev 5; 10/18
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Benefits and Features
●● High-Efficiency Microcontroller for Wearable Devices
• Internal Oscillator Operates Up to 96MHz
• Low Power 4MHz Oscillator System Clock Option
for Always-On Monitoring Applications
• 2MB Flash Memory
• 512KB SRAM
• 8KB Instruction Cache
• 1.2V CPU Core Supply Voltage
• 1.8V to 3.3V I/O
• Optional 3.3V ±5% USB Supply Voltage
●● Power Management Maximizes Uptime for Battery
Applications
• 106μA/MHz Active Current Executing from Cache
• Wakeup to 96MHz Clock or 4MHz Clock
• 600nA Low Power Mode (LP0) Current with RTC
Enabled
• 3.5μW/MHz Ultra-Low Power Data Retention Sleep
Mode (LP1) with Fast 5μs Wakeup to 96MHz
●● Optimal Peripheral Mix Provides Platform Scalability
• SPIX Execute in Place (XIP) Engine for Memory
Expansion with Minimal Footprint
• Up to Three SPI Masters, One SPI Slave
• Four UARTs
• Up to Three I2C Masters, One I2C Slave
• 1-Wire Master
• Full-Speed USB 2.0 Engine with Internal
Transceiver
• Sixteen Pulse Train (PWM) Engines
• Six 32-Bit Timers and 3 Watchdog Timers
• Up to 66 General-Purpose I/O Pins
• One 10-Bit Delta-Sigma ADC Operating at 7.8ksps
• RTC Calibration Output
●● Secure Valuable IP and Data with Robust Internal
Hardware Security (MAX32631 and MAX32632 Only)
• Trust Protection Unit (TPU) Including MAA
Supports ECDSA and Modular Arithmetic
• True Random Number Generator
• AES-128, -192, -256
• Secure Bootloader (MAX32632 Only)
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Simplified Block Diagram
MAX32630–MAX32632
NVIC
6 × 32 BIT TIMERS
MEMORY
16 × PULSE TRAIN
ENGINE
JTAG SWD (SERIAL
WIRE DEBUG)
32KOUT
32KIN
DP
DM
VDDB
1 × SPI SLAVE
8KB CACHE
PERIPHERAL
MANAGEMENT UNIT
VOLTAGE
REGULATION &
POWER CONTROL
3 × WINDOWED
WATCHDOG TIMERS
CLOCK
GENERATION
96MHz INT OSC/
SYSTEM CLOCK
RTC & WAKE-UP
TIMERS
1 × SPI XIP
16B FIFOS
VDDA
VSSA
VDDIOH
VDDIO
VDD12
VDD18
VRTC
VSS
3×
SPI MASTER
512KB SRAM
BUS MATRIX – AHB, APB, IBUS, DBUS…
RSTN
32B
FIFOS
2MB FLASH
POR,
BROWNOUT
MONITOR,
SUPPLY VOLTAGE
MONITORS
3 × I2C MASTER 1
× I2C SLAVE
Maximum of 3
Ports
32B
FIFOS
TCK/SWCLK
TMS/SWDIO
TDO
TDI
GPIO WITH
INTERRUPTS
ARM CORTEX-M4
96MHz
SRSTN
SHARED PAD
FUNCTIONS
TIMERS/PWM
CAPTURE/COMPARE
UP TO 66 GPIO/SPECIAL
FUNCTION
USB
SPI
SPI XIP
I 2C
UART
1-WIRE
RTC OUTPUT
EXTERNAL
INTERRUPTS
4 × UART
1-WIRE MASTER
CRC 16/32
USB 2.0 FULL
SPEED
CONTROLLER
EXT REF
1.2V
UNIQUE ID
VREF
TRUST PROTECTION UNIT (TPU)
MAX32631 AND MAX32632
AIN0
AIN1
AIN2
AIN3
AES-128, -192, -256
MAA
SECURE NV KEY
TRNG
10-BIT
ΣΔ ADC
÷5
÷5
SECURE BOOTLOADER
(MAX32630 ONLY)
÷2
www.maximintegrated.com
÷4
VDDB
VDD18
VDD12
VRTC
Maxim Integrated │ 2
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Absolute Maximum Ratings
(All voltages with respect to VSS, unless otherwise noted.)
VDD18..................................................................-0.3V to +1.89V
VDD12..................................................................-0.3V to +1.26V
VDDA relative to VSSA.........................................-0.3V to +1.89V
VRTC....................................................................-0.3V to +1.89V
VDDB.....................................................................-0.3V to +3.6V
VREF......................................................................-0.3V to +3.6V
32KIN, 32KOUT....................................................-0.3V to +3.6V
RSTN, SRSTN, DP, DM, GPIO, JTAG..................-0.3V to +3.6V
AIN[1:0].................................................................-0.3V to +5.5V
AIN[3:2].................................................................-0.3V to +3.6V
VDDIO....................................................................-0.3V to +3.6V
VDDIOH..................................................................-0.3V to +3.6V
Total Current into All VDD18 Power Pins (sink).................100mA
Total Current into VSS.......................................................100mA
Output Current (sink) by Any I/O Pin..................................25mA
Output Current (source) by Any I/O Pin.............................-25mA
Continuous Package Power Dissipation TQFP (multilayer board)
TA = +70°C (derate 45.5mW/°C above +70°C).......3636.4mW
Operating Temperature Range............................ -20°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
100 WLP
Package Code
W1004D4+1
Outline Number
21-100043
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Single-Layer Board
Junction-to-Ambient (θJA)
N/A
Junction-to-Case Thermal Resistance (θJC)
N/A
Thermal Resistance, Four-Layer Board
Junction-to-Ambient (θJA)
38.9°C/W
Junction-to-Case Thermal Resistance (θJC)
N/A
100 TQFP-EP
Package Code
C100E+3
Outline Number
21-0116
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Single-Layer Board
Junction-to-Ambient (θJA)
N/A
Junction-to-Case Thermal Resistance (θJC)
N/A
Thermal Resistance, Four-Layer Board
Junction-to-Ambient (θJA)
22°C/W
Junction-to-Case Thermal Resistance (θJC)
2°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 3
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Electrical Characteristics
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
VDD18
1.71
1.8
1.89
VDD12
1.14
1.2
1.26
VDDA
1.71
1.8
1.89
VRTC
1.75
1.8
1.89
VDDIO
VDDIOH
1.71
1.8
3.6
VDDIOH must be ≥ VDDIO
1.71
1.8
3.6
1.62
Power Fail Reset
Voltage
VRST
Monitors VDD18
Power-On Reset Voltage
VPOR
Monitors VDD18
RAM Data Retention Voltage
VDRV
VDD12 Dynamic Current,
LP3 Mode
VDD12 Fixed Current,
LP3 Mode
VDD18 Fixed Current,
LP3 Mode
VDD12 Dynamic Current,
LP2 Mode
VDD12 Fixed Current,
LP2 Mode
www.maximintegrated.com
IDD12_DLP3
IDD12_FLP3
IDD18_FLP3
IDD12_DLP2
IDD12_FLP2
1.7
UNITS
V
V
1.5
V
0.93
V
Measured on the VDD12 pin and executing
code from cache memory, all inputs are tied
to VSS or VDD18, outputs do not source/sink
any current, PMU disabled
106
μA/MHz
Measured on the VDD12 pin and executing
code from cache memory, all inputs are tied
to VSS or VDD18, outputs do not source/sink
any current, 96MHz oscillator selected as
system clock
173
Measured on the VDD12 pin and executing
code from cache memory, all inputs are tied
to VSS or VDD18, outputs do not source/sink
any current, 4MHz oscillator selected as
system clock
72
Measured on the VDD18 + VDDA device pins
and executing code from cache memory, all
inputs are tied to VSS or VDD18, outputs do
not source/sink any current, 96MHz oscillator
selected as system clock
366
Measured on the VDD18 + VDDA device pins
and executing code from cache memory, all
inputs are tied to VSS or VDD18, outputs do
not source/sink any current, 4MHz oscillator
selected as system clock
33
Measured on the VDD12 pin, Arm in sleep
mode, PMU with two channels active
27
Measured on the VDD12 pin, Arm in sleep
mode, PMU with two channels active,
96MHz oscillator selected as system clock
173
Measured on the VDD12 pin, Arm in sleep
mode, PMU with two channels active,
4MHz oscillator selected as system clock
72
μA
μA
μA/MHz
μA
Maxim Integrated │ 4
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
VDD18 Fixed Current,
LP2 Mode
SYMBOL
IDD18_FLP2
CONDITIONS
MIN
TYP
Measured on the VDD18 + VDDA device
pins, Arm in sleep mode, PMU with two
channels active, 96MHz oscillator selected
as system clock
366
Measured on the VDD18 + VDDA device
pins. Arm in sleep mode, PMU with two
channels active, 4MHz oscillator selected
as system clock
33
MAX
UNITS
μA
VDD12 Fixed Current,
LP1 Mode
IDD12_FLP1
Standby state with full data retention
1.86
μA
VDD18 Fixed Current,
LP1 Mode
IDD18_FLP1
Standby state with full data retention
120
nA
RTC enabled, retention regulator powered
by VDD12
505
nA
VRTC Fixed Current,
LP1 Mode
IDDRTC_
FLP1
VDD12 Fixed Current,
LP0 Mode
IDD12_FLP0
14
nA
VDD18 Fixed Current,
LP0 Mode
IDD18_FLP0
120
nA
RTC enabled
505
RTC disabled
105
VRTC Fixed Current,
LP0 Mode
IDDRTC_
LP2 Mode Resume Time
tLP2_ON
0
μs
LP1 Mode Resume Time
tLP1_ON
5
μs
LP0 Mode Resume Time
tLP0_ON
11
μs
FLP0
Polling flash ready
nA
JTAG
Input Low Voltage for TCK,
TMS, TDI
VIL
0.3 x
VDDIO
Input High Voltage for TCK,
TMS, TDI
VIH
Output Low Voltage for TDO
VOL
Output High Voltage for TDO
VOH
VDDIO 0.4
System Clock Frequency
fCK
0.001
System Clock Period
tCK
0.7 x
VDDIO
V
V
0.2
0.4
V
98
MHz
CLOCKS
Factory default
Internal Relaxation Oscillator
Frequency
fINTCLK
Internal RC Oscillator
Frequency
fRCCLK
RTC Input Frequency
f32KIN
www.maximintegrated.com
1/fCK
Firmware trimmed, required for USB
compliance
32kHz watch crystal
ns
94
96
98
95.76
96
96.24
3.9
4
4.1
32.768
MHz
MHz
kHz
Maxim Integrated │ 5
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
RTC Operating Current
RTC Power-Up Time
SYMBOL
CONDITIONS
MIN
TYP
IRTC_LP23
LP2 or LP3 mode
0.7
IRTC_LP01
LP0 or LP1 mode
0.35
tRTC_ ON
MAX
UNITS
μA
250
ms
GENERAL-PURPOSE I/O
0.3 ×
VDDIO
VDDIO selected as I/O supply
Input Low Voltage for All
GPIO Pins
VIL
Input Low Voltage for RSTN
VIL
0.3 x
VRTC
Input Low Voltage for
SRSTN
VIL
0.3 x
VDDIO
0.3 ×
VDDIOH
VDDIOH selected as I/O supply
VDDIO selected as I/O supply
0.7 ×
VDDIO
V
V
Input High Voltage for All
GPIO Pins
VIH
Input High Voltage for RSTN
VIH
0.7 x
VRTC
V
Input High Voltage for
SRSTN
VIH
0.7 x
VDDIO
V
Input Hysteresis (Schmitt)
Output Low Voltage for All
GPIO Pins
Combined IOL, All GPIO Pins
VDDIOH selected as I/O supply
VIHYS
VOL
300
0.2
0.4
VDDIO = VDDIOH = 1.71V, VDDIO selected
as I/O supply, IOL = 24mA, fast drive
configuration
0.2
0.4
VDDIO = 1.71V VDDIOH = 2.97V, VDDIOH
selected as I/O supply, IOL = 300μA
0.2
0.45
IOL_TOTAL
Ouput High Voltage for All
GPIO Pins
Combined IOH, All GPIO Pins
www.maximintegrated.com
VOH
48
IOH_TOTAL
V
mA
VDDIO 0.4
IOH = -8mA, VDDIO = VDDIOH = 1.71V,
VDDIO selected as I/O supply, fast drive
VDDIO 0.4
IOH = -300μA, VDDIOH = 3.6V, VDDIOH
selected as I/O supply
VDDIOH
- 0.45
VDDIO = 1.71V, VDDIOH = 3.6V. VDDIO
selected as I/O supply, IOH = -2mA
VDDIO 0.45
configuration
VOH
mV
VDDIO = VDDIOH = 1.71V, VDDIO selected
as I/O supply, IOL = 4mA, normal drive
configuration
IOH = -2mA, VDDIO = VDDIOH = 1.71V,
VDDIO selected as I/O supply, normal drive
configuration
Output High Voltage for All
GPIO Pins
V
0.7 ×
VDDIOH
V
V
-48
mA
Maxim Integrated │ 6
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
Input/Output Pin Capacitance
for All Pins
CIO
Input Leakage Current Low
Input Leakage Current High
Input Pullup Resistor RSTN,
SRSTN, TMS, TCK, TDI
Input Pullup/Pulldown
Resistor for All GPIO Pins
CONDITIONS
MIN
TYP
MAX
3
UNITS
pF
IIL
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
selected as I/O supply, VIN = 0V, internal
pullup disabled
-100
+100
nA
IIH
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
selected as I/O supply, VIN = 3.6V, internal
pulldown disabled
-100
+100
nA
IOFF
VDDIO = 0V, VDDIOH = 0V, VDDIO selected
as I/O supply, VIN < 1.89V
-1
+1
IIH3V
VDDIO = VDDIOH = 1.71V, VDDIO selected
as I/O supply, VIN = 3.6V
-2
μA
RPU
+2
25
kΩ
RPU1
Normal resistance
25
kΩ
RPU2
Highest resistance
1
MΩ
2MB flash
8
kB
tM_ERASE
Mass erase
30
tP_ERASE
Page erase
30
FLASH MEMORY
Page Size
Flash Erase Time
Flash Programming Time
per Word
tPROG
60
Flash Endurance
Data Retention
tRET
ms
TA = +85°C
μs
10
kcycles
10
years
ADC Electrical Characteristics
(Internal bandgap reference selected, ADC_SCALE = ADC_REFSCL = 1, unless otherwise specified. Specifications marked GBD are
guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
fACLK
ADC Clock Period
tACLK
www.maximintegrated.com
MAX
10
ADC Clock Rate
Input Voltage Range
TYP
VAIN
0.1
UNITS
Bits
8
1/fACLK
MHz
μs
AIN[3:0], ADC_CHSEL = 0–3,
BUF_BYPASS = 0
0.05
VDDA 0.05
AIN[1:0], ADC_CHSEL = 4–5,
BUF_BYPASS = 0
0.05
5.5
AIN[3:0], ADC_CHSEL = 0–3,
BUF_BYPASS = 1
VSSA
VDDA
AIN[1:0], ADC_CHSEL = 4–5,
BUF_BYPASS = 1
VSSA
5.5
V
Maxim Integrated │ 7
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
ADC Electrical Characteristics (continued)
(Internal bandgap reference selected, ADC_SCALE = ADC_REFSCL = 1, unless otherwise specified. Specifications marked GBD are
guaranteed by design and not production tested.)
PARAMETER
Input Impedance
Input Dynamic Current
Analog Input
Capacitance
SYMBOL
RAIN
IAIN
CAIN
CONDITIONS
MIN
TYP
MAX
UNITS
AIN[1:0], ADC_CHSEL = 4-5, ADC active
45
kΩ
Switched capactiance input current, ADC
active, ADC buffer bypassed
4.5
μA
Switched capacitance input current, ADC
active, ADC buffer enabled
50
nA
1
pF
250
fF
Fixed capacitance to VSSA
Dynamically switched capacitance
Integral Nonlinearity
INL
±2
LSb
Differential Nonlinearity
DNL
±1
LSb
Offset Error
VOS
±1
LSb
Gain Error
GE
±2
LSb
Signal to Noise Ratio
SNR
58.5
dB
SINAD
58.5
dB
THD
68.5
dB
Spurious Free Dynamic
Range
SFDR
74
dB
ADC Active Current
IADC
240
µA
53
μA
Signal to Noise and Distortion
Total Harmonic
Distortion
Input Buffer Active Current
ADC Setup Time
IINBUF
tADC_SU
ADC Output Latency
tADC
ADC Sample Rate
fADC
ADC Input Leakage
IADC_LEAK
AIN0/AIN1 Resistor
Divider Error
Full-Scale Voltage
ADC active, reference buffer enabled, input
buffer disabled
VFS
Any powerup of: ADC clock, ADC bias,
reference buffer or input buffer to
CpuAdcStart
10
µs
Any power-up of: ADC clock or ADC bias to
CpuAdcStart
48
tACLK
1025
tACLK
7.8
ksps
AIN0 or AIN1, ADC inactive or channel not
selected
0.12
4
AIN2 or AIN3, ADC inactive or channel not
selected.
0.02
1
ADC_CHSEL = 4 or 5, not including ADC
offset/gain error
±2
LSb
ADC code = 0x3FF
1.2
V
nA
External Reference Voltage
VREF_EXT
ADC_XREF = 1
Bandgap Temperature
Coefficient
VTEMPCO
Box method
30
ppm
Reference Dynamic Current
IREF_EXT
ADC_XREF = 1, ADC active
4.1
μA
Dynamically switched capacitance, ADC_
XREF = 1, ADC active
250
fF
Reference Input Capacitance
www.maximintegrated.com
CREFIN
1.17
1.23
1.29
V
Maxim Integrated │ 8
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
SPI MASTER/SPIX MASTER Electrical Characteristics
(Guaranteed by design and not production tested.)
PARAMETER
SYMBOL
Operating Frequency
fMCK
SCLK Period
tMCK
CONDITIONS
MIN
TYP
1/fMCK
MAX
UNITS
48
MHz
ns
SCLK Output Pulse-Width
High/Low
tMCH, tMCL
tMCK/2
ns
MOSI Output Hold Time
After SCLK Sample Edge
tMOH
tMCK/2
ns
MOSI Output Valid to
Sample Edge
tMOV
tMCK/2
ns
MISO Input Valid to SCLK
Sample Edge Setup
tMIS
3
ns
MISO Input to SCLK
Sample Edge
tMIH
SHIFT
0
SAMPLE
SHIFT
ns
SAMPLE
SS
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
tMCL
SCK
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV
MSB
MOSI/SDIO
(OUTPUT)
tMIS
MISO/SDIO
(INPUT)
MSB
LSB
MSB-1
tMIH
MSB-1
LSB
Figure 1. SPI Master/SPIX Master Communications Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 9
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
USB Electrical Characteristics
(Guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.3
3.63
V
USB PHY Supply Voltage
VDDB
2.97
Single-Ended Input High
Voltage DP, DM
VIHD
2
Single-Ended Input Low Voltage DP, DM
VILD
V
0.8
V
0.3
V
Output Low Voltage DP, DM
VOLD
RL = 1.5kΩ from DP to 3.6V
Output High Voltage DP, DM
VOHD
RL = 15kΩ from DP and DM to VSS
2.8
V
Differential Input Sensitivity
DP, DM
VDI
DP to DM
0.2
V
Common-Mode Voltage
Range
VCM
Includes VDI range
0.8
2.5
V
Single-Ended Receiver
Threshold
VSE
0.8
2.0
V
Single-Ended Receiver
Hysteresis
VSEH
Differential Output Signal
Cross-Point Voltage
VCRS
DP, DM Off-State Input
Impedance
Driver Output Impedance
DP Pull-up Resistor
200
CL = 50pF
1.3
RLZ
RDRV
RPU
mV
2.0
300
kΩ
Steady-state drive
28
44
Idle
0.9
1.575
1.425
3.09
Receiving
V
Ω
kΩ
USB Timing Electrical Characteristics
(AC Electrical Specifications are guaranteed by design and are not production tested, VDD18= VRST to 1.89V, VDDB = 3.63V, TA=-20°C
to +85°C, Guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MAX
UNITS
4
20
ns
CL = 50pF
4
20
ns
CL = 50pF
90
110
%
DP, DM Rise Time
(Transmit)
tR
CL = 50pF
DP, DM Fall Time
(Transmit)
tF
tR,tF
Rise/Fall Time Matching
(Transmit)
www.maximintegrated.com
MIN
TYP
Maxim Integrated │ 10
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Electrical Characteristics—I2C BUS
(Guaranteed by design and not production tested.)
PARAMETER
SCL Clock Frequency
SYMBOL
fSCL
CONDITIONS
VIH_I2C
TYP
100
Fast mode
400
Fast mode, VDDIO selected as I/O supply
Input High Voltage
MIN
Standard mode
Fast mode, VDDIOH selected as I/O supply
Standard mode, VDDIO selected as I/O
supply
Standard mode, VDDIOH selected as I/O
supply
VIL_I2C
Output Logic-Low (Open
Drain or Open Collector)
www.maximintegrated.com
VIHYS_I2C
VOL_I2C
kHz
0.7 ×
VDDIOH
V
0.7 ×
VDDIO
0.7 ×
VDDIOH
0.3 ×
VDDIO
0.3 ×
VDDIOH
Fast mode, VDDIOH selected as I/O supply
Standard mode, VDDIO selected as I/O
supply
0.3 ×
VDDIO
Standard mode, VDDIOH selected as I/O
supply
Input Hysteresis (Schmitt)
UNITS
0.7 ×
VDDIO
Fast mode, VDDIO selected as I/O supply
Input Low Voltage
MAX
V
0.3 ×
VDDIOH
Fast-mode
300
VDDIO = VDDIOH = 1.71V, VDDIO selected
as I/O supply, IOL = 4mA, normal drive
configuration
0.2
VDDIO = 1.71V VDDIOH = 2.97V, VDDIOH
selected as I/O supply, IOL = 300μA
0.2
mV
0.4
V
0.45
Maxim Integrated │ 11
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Typical Operating Characteristics
(VDD12 = 1.2V, VDD18 = 1.8V.)
IDD12 vs. FREQUENCY
(INTERNAL 96MHz OSCILLATOR)
12
toc01
IDD12 vs. FREQUENCY
(INTERNAL 4MHz OSCILLATOR)
600
10
500
8
400
6
300
4
200
2
100
0
0
20
40
60
80
0
100
0
1
FREQUENCY (MHz)
8
6
LP2
4
2
0
4
toc04
TOTAL POWER =
(IDD18 x 1.8V) + (IDD12 x 1.2V)
600
LP3
10
3
TOTAL POWER vs. FREQUENCY
(INTERNAL 4MHz OSCILLATOR)
700
TOTAL POWER (μW)
TOTAL POWER (mW)
toc03
TOTAL POWER =
(IDD18 x 1.8V) + (IDD12 x 1.2V)
12
2
FREQUENCY (MHz)
TOTAL POWER vs. FREQUENCY
(INTERNAL 96MHz OSCILLATOR)
14
toc02
VDD12 = 1.2V
IDD12 (μA)
IDD12 (mA)
VDD12 = 1.2V
LP3
500
400
LP2
300
200
100
0
20
40
60
FREQUENCY (MHz)
www.maximintegrated.com
80
100
0
0
1
2
3
4
FREQUENCY (MHz)
Maxim Integrated │ 12
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Pin Configuration
100 WLP
TOP VIEW (BUMPS ON BOTTOM)
1
2
3
4
5
6
7
8
9
10
A
N.C.
VDDIOH
VSSA
VREF
AIN0
AIN1
AIN2
AIN3
VDD18
N.C.
B
P8.1
SRSTN
RSTN
VDDA
TCK
TMS
TDO
TDI
VSS
32KIN
C
P8.0
P0.1
P0.0
P6.0
P5.7
P5.5
P5.4
P5.2
VRTC
32KOUT
D
P7.7
P0.4
P0.5
P0.3
P0.2
P5.6
P5.3
P5.0
VDDB
VSS
E
P7.6
P1.0
P0.7
P0.6
P1.1
P1.5
P3.1
P5.1
DP
VDDIO
F
P7.5
VDD12
P1.3
P1.2
P1.4
P3.0
P3.5
P3.7
DM
P4.7
G
P7.4
VSS
P1.6
P1.7
P2.4
P2.6
P3.4
P4.4
P4.6
P4.5
H
P7.3
VDDIO
P2.1
P2.2
P2.5
P2.7
P3.2
P4.1
P4.3
P4.2
J
P7.2
VSS
P2.0
P2.3
VDD18
VSS
P3.3
P3.6
P4.0
P6.1
K
N.C.
P7.1
P7.0
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
N.C.
+
100 WLP
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Maxim Integrated │ 13
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Pin Configuration (continued)
N.C.
N.C.
N.C.
32KIN
VRTC
32KOUT
VSS
VDDB
VSS
VSS
VDDIO
DP
DM
P4.7
P4.6
P4.5
P4.3
P4.4
P4.2
P3.7
P4.1
P6.1
P4.0
VSS
TOP VIEW
VDDIO
100 TQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P3.6 76
50 P5.0
P3.5 77
49 P5.1
P6.2 78
48 P5.2
P3.4 79
47 VDD18
P6.3 80
46 P5.3
P3.3 81
45 P5.4
P3.2 82
44 VSS
P6.4 83
43 AIN3
P3.1 84
42 TDI
P3.0 85
41 AIN2
P6.5 86
40 TDO
P2.7 87
39 AIN1
MAX32630/MAX32631
P2.6 88
38 TMS
P2.5 89
37 AIN0
P6.6 90
36 VREF
VDD18 91
35 VSSA
VSS 92
34 TCK
P2.4 93
33 P5.5
EP = EXPOSED PAD
P2.2 94
32 VDDA
P6.7 95
31 P5.6
P2.3 96
30 P5.7
P7.0 97
29 P6.0
P2.1 98
28 VSS
P7.1 99
27 VDDIOH
26 SRSTN
P0.0
RSTN
P0.1
P0.2
P0.3
VSS
P7.4
P0.4
P1.6
P0.5
P7.3
P0.6
VDDIO
P0.7
P1.4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P1.0
8
P1.1
7
P1.2
6
VSS
5
P7.5
4
P1.3
3
VDD12
2
P1.5
1
P7.2
+
P1.7
P2.0 100
100 TQFP-EP
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Maxim Integrated │ 14
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Pin Description
100 WLP
100 TQFP-EP
NAME
FUNCTION
POWER PINS
D9
58
VDDB
USB Transceiver Supply Voltage. This pin must be bypassed to VSS with a 1.0μF
capacitor as close as possible to the package.
F2
11
VDD12
1.2V Nominal Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package.
C9
56
VRTC
RTC Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as
close as possible to the package.
B4
32
VDDA
Analog Supply Voltage. This pin must be bypassed to VSSA with a 1.0μF capacitor as
close as possible to this pin.
J5, A9
47, 91
VDD18
1.8V Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as
close as possible to the package.
H2, E10
4, 61
VDDIO
I/O Supply Voltage. 1.8V ≤ VDDIO ≤ 3.6V. See the Electrical Characteristics table for
the VDDIO specification. This pin must be bypassed to VSS with a 1.0μF capacitor as
close as possible to the package.
A2
27, 75
VDDIOH
I/O Supply Voltage, High. 1.8V ≤ VDDIOH ≤ 3.6V, always with VDDIOH ≥ VDDIO. See the
Electrical Characteristics table for the VDDIOH specification. This pin must be bypassed
to VSS with a 1.0μF capacitor as close as possible to the package.
A4
36
VREF
ADC Reference. This pin must be left unconnected if an external reference is not used.
B9, D10,
G2, J6, J2
7, 12, 28, 44,
57, 59, 60, 74,
92
VSS
Digital Ground
A3
35
VSSA
Analog Ground
—
—
EP
55
32KOUT
Exposed Pad (TQFP-EP Only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information
CLOCK PINS
C10
B10
32kHz Crystal Oscillator Output
32kHz Crystal Oscillator Input. Connect a 6pF 32kHz crystal between 32KIN and
32KOUT for RTC operation. Optionally, an external clock source can be driven on
32KIN if the 32KOUT pin is left unconnected. A 32kHz crystal or external clock source
is required for proper USB operation.
54
32KIN
E9
62
DP
USB DP Signal. This bidirectional pin carries the positive differential data or singleended data. This pin is weakly pulled high internally when the USB is disabled.
F9
63
DM
USB DM Signal. This bidirectional pin carries the negative differential data or singleended data. This pin is weakly pulled high internally when the USB is disabled.
B5
34
TCK/SWCLK
JTAG Clock or Serial Wire Debug Clock. This pin has an internal 25KΩ pullup to
VDDIO.
B6
38
TMS/SWDIO
JTAG Test Mode Select or Serial Wire Debug I/O. This pin has an internal 25KΩ pullup
to VDDIO.
B7
40
TDO
JTAG Test Data Output
B8
42
TDI
JTAG Test Data Input. This pin has an internal 25kΩ pullup to VDDIO.
USB PINS
JTAG PINS
www.maximintegrated.com
Maxim Integrated │ 15
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Bump Description (continued)
100 WLP
100 TQFP-EP
NAME
FUNCTION
RSTN
Hardware Power Reset (Active-Low) Input. The device remains in reset while this pin is in
its active state. When the pin transitions to its inactive state, the device performs a POR
reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin is internally connected with an internal 25kΩ pullup to the VRTC supply.
This pin should be left unconnected if the system design does not provide a reset signal to
the device.
RESET PINS
B3
25
Software Reset, Active-Low Input/Output. The device remains in software reset while this
pin is in its active state. When the pin transitions to its inactive state, the device performs
a reset to the Arm CPU, digital registers and peripherals (resetting most of the core logic
on the VDD12 supply). This reset does not affect the POR only registers, RTC logic, Arm
debug engine or JTAG debugger
allowing for a soft reset without having to reconfigure all registers.
B2
26
SRSTN
After the device senses SRSTN as a logic 0, the pin automatically reconfigures as an
output
sourcing a logic 0. The device continues to output for 6 system clock cycles and then
repeats the input sensing/output driving until SRSTN is sensed inactive.
This pin is internally connected with an internal 25kΩ pullup to the VDDIO supply. This pin
should be left unconnected if the system design does not provide a reset signal to the
device.
GENERAL-PURPOSE I/O AND SPECIAL FUNCTIONS (See the Applications Information section for GPIO Matrix)
C3
24
P0.0
GPIO Port 0.0
C2
23
P0.1
GPIO Port 0.1
D5
22
P0.2
GPIO Port 0.2
D4
21
P0.3
GPIO Port 0.3
D2
20
P0.4
GPIO Port 0.4
D3
19
P0.5
GPIO Port 0.5
E4
18
P0.6
GPIO Port 0.6
E3
17
P0.7
GPIO Port 0.7
E2
16
P1.0
GPIO Port 1.0
E5
15
P1.1
GPIO Port 1.1
F4
14
P1.2
GPIO Port 1.2
F3
10
P1.3
GPIO Port 1.3
F5
3
P1.4
GPIO Port 1.4
E6
9
P1.5
GPIO Port 1.5
G3
6
P1.6
GPIO Port 1.6
G4
1
P1.7
GPIO Port 1.7
J3
100
P2.0
GPIO Port 2.0
H3
98
P2.1
GPIO Port 2.1
H4
94
P2.2
GPIO Port 2.2
J4
96
P2.3
GPIO Port 2.3
G5
93
P2.4
GPIO Port 2.4
H5
89
P2.5
GPIO Port 2.5
www.maximintegrated.com
Maxim Integrated │ 16
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Bump Description (continued)
100 WLP
100 TQFP-EP
NAME
G6
88
P2.6
GPIO Port 2.6
FUNCTION
H6
87
P2.7
GPIO Port 2.7
F6
85
P3.0
GPIO Port 3.0
E7
84
P3.1
GPIO Port 3.1
H7
82
P3.2
GPIO Port 3.2
J7
81
P3.3
GPIO Port 3.3
G7
79
P3.4
GPIO Port 3.4
F7
77
P3.5
GPIO Port 3.5
J8
76
P3.6
GPIO Port 3.6
F8
71
P3.7
GPIO Port 3.7
J9
73
P4.0
GPIO Port 4.0
H8
70
P4.1
GPIO Port 4.1
H10
69
P4.2
GPIO Port 4.2
H9
68
P4.3
GPIO Port 4.3
G8
67
P4.4
GPIO Port 4.4
G10
66
P4.5
GPIO Port 4.5
G9
65
P4.6
GPIO Port 4.6
F10
64
P4.7
GPIO Port 4.7
D8
50
P5.0
GPIO Port 5.0
E8
49
P5.1
GPIO Port 5.1
C8
48
P5.2
GPIO Port 5.2
D7
46
P5.3
GPIO Port 5.3
C7
45
P5.4
GPIO Port 5.4
C6
33
P5.5
GPIO Port 5.5
D6
31
P5.6
GPIO Port 5.6
C5
30
P5.7
GPIO Port 5.7
C4
29
P6.0
GPIO Port 6.0
J10
72
P6.1
GPIO Port 6.1
K9
78
P6.2
GPIO Port 6.2
K8
80
P6.3
GPIO Port 6.3
K7
83
P6.4
GPIO Port 6.4
K6
86
P6.5
GPIO Port 6.5
K5
90
P6.6
GPIO Port 6.6
K4
95
P6.7
GPIO Port 6.7
K3
97
P7.0
GPIO Port 7.0
K2
99
P7.1
GPIO Port 7.1
J1
2
P7.2
GPIO Port 7.2
H1
5
P7.3
GPIO Port 7.3
G1
8
P7.4
GPIO Port 7.4
F1
13
P7.5
GPIO Port 7.5
www.maximintegrated.com
Maxim Integrated │ 17
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Bump Description (continued)
100 WLP
100 TQFP-EP
NAME
E1
-
P7.6
GPIO Port 7.6
FUNCTION
D1
-
P7.7
GPIO Port 7.7
C1
-
P8.0
GPIO Port 8.0
B1
-
P8.1
GPIO Port 8.1
ANALOG INPUT PINS
A5
37
AIN0
ADC Input 0. 5V tolerant input.
A6
39
AIN1
ADC Input 1. 5V tolerant input.
A7
41
AIN2
ADC Input 2
A8
39
AIN3
ADC Input 3
NO CONNECT PINS
A1
51
N.C.
Not Connected.
A10
52
N.C.
Not Connected.
K1
53
N.C.
Not Connected.
K10
-
N.C.
Not Connected.
Detailed Description
The MAX32630–MAX32632 are low-power, mixed signal
microcontrollers based on the Arm Cortex-M4 with FPU
CPU with a maximum operating frequency of 96MHz.
The MAX32631 and MAX32632 are secure versions of
the MAX32630. They incorporate a trust protection unit
(TPU) with encryption and advanced security features.
Additionally, the MAX32632 provides a secure bootloader.
Application code executes from an onboard 2MB program
flash memory, with up to 512KB SRAM available for general application use. An 8KB instruction cache improves
execution throughput, and a transparent code scrambling
scheme is used to protect customer intellectual property
residing in the program flash memory. Additionally, a SPI
execute in place (XIP) external memory interface allows
application code and data (up to 16MB) to be accessed
from an external SPI memory device.
A 10-bit delta-sigma ADC is provided with a multiplexer
front end for four external input channels (two of which are
5V tolerant) and six internal channels. Dedicated divided
supply input channels allow direct monitoring of onboard
power supplies such as VDD12, VDD18, VDDB, and VRTC
by the ADC. Built-in limit monitors allow converted input
samples to be compared against user-configurable high
and low limits, with an option to trigger an interrupt and
wake the CPU from a low power mode if attention is
required.
www.maximintegrated.com
A wide variety of communications and interface peripherals are provided, including a USB 2.0 slave interface,
three master SPI interfaces, one slave SPI interface, four
UART interfaces with multidrop support, three master I2C
interfaces, and a slave I2C interface.
Arm Cortex-M4 with FPU CPU
The Arm Cortex-M4 with FPU CPU is ideal for the emerging
category of wearable medical and wellness applications.
The architecture combines high-efficiency signal processing functionality with low power, low cost, and ease of use.
The DSP supports single instruction multiple data (SIMD)
path DSP extensions, providing:
●● Four parallel 8-bit add/sub
●● Floating point single precision
●● Two parallel 16-bit add/sub
●● Two parallel MACs
●● 32- or 64-bit accumulate
●● Signed, unsigned, data with or without saturation.
Analog-to-Digital Converter
The 10-bit delta-sigma ADC provides 4 external inputs and
can also be configured to measure all internal power supplies.
It operates at a maximum of 7.8ksps. AIN0 and AIN1 are 5V
tolerant, making them suitable for monitoring batteries.
An optional feature allows samples captured by the ADC
to be automatically compared against user-programmable
high and low limits. Up to four channel limit pairs can be
Maxim Integrated │ 18
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
configured in this way. The comparison allows the ADC
to trigger an interrupt (and potentially wake the CPU
from a low-power sleep mode) when a captured sample
goes outside the preprogrammed limit range. Since this
comparison is performed directly by the sample limit
monitors, it can be performed even while the main CPU is
suspended in a low power mode.
generator is also set separately, based on a divide down
(divide by 2, divide by 4, divide by 8, etc.) of the input
pulse train module clock.
The ADC reference is selectable:
●● Internal bandgap
●● External reference
●● VDD18. This option disables the reference buffer to
minimize power consumption.
Pulse Train Engine
Sixteen independent pulse train generators provide either
a square wave or a repeating pattern from 2 bits to 32
bits in length. The frequency of each enabled pulse train
Any single pulse train generator or any desired group of
pulse train generators can be restarted at the beginning of
their patterns and synchronized with one another ensuring simultaneous startup. Additionally, each pulse train
can operate in a single shot mode.
Clocking Scheme
The high-frequency internal relaxation oscillator operates
at a nominal frequency of 96MHz. It is the primary clock
source for the digital logic and peripherals. Select a 4MHz
internal oscillator to optimize active power consumption.
Wakeup is possible from either the 4MHz internal oscillator or the 96MHz internal oscillator.
XTAL DRIVER OR
EXTERNAL CLOCK
32KIN
32kHz
CRYSTAL
32KOUT
32kHz
RTC
OSCILLATOR
NANO-RING
OSCILLATOR
~8kHz
32.768kHz
OUTPUT CLOCK
GPIO
REAL-TIME
CLOCK
POWER
SEQUENCER
ALWAYS-ON DOMAIN
(96MHz SYSCLK ONLY)
48MHz
DIVIDE BY 2
FIRMWARE
FREQUENCY
CALIBRATION FOR
USB
INTERNAL
96MHz
OSCILLATOR
CPU
CLOCK
SCALER
CLOCK
SCALER
INTERNAL
4MHz
OSCILLATOR
ADC
CLOCK
SCALER
SYSTEM
CLOCK
SELECT
INTERNAL 44MHz
CRYPTOGRAPHIC
OSCILLATOR
44MHz
15kHz–96MHz
8MHz
USB PHY
ARM
CORTEX-M4
WITH FPU CPU
ADC
TPU
TRUST PROTECTION UNIT (OPTIONAL)
Figure 2. MAX32630–MAX32632 Clock Scheme
www.maximintegrated.com
Maxim Integrated │ 19
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
An external 32.768kHz timebase is required when using
the RTC or USB features of the device. The time base
can be generated by attaching a 32kHz crystal connected
between 32KIN and 32KOUT, or an external clock source
can also be applied to the 32KIN pin. The external clock
source must meet the electrical/timing requirements in the
EC table. The 32kHz output can be directed out to pin P1.7
and remains active in all low power modes including LP0.
The CRC module supports both the CRC-16-CCITT and
CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10
+ X8 + X7 + X5 + X4 + X2 + X + 1) polynomials.
Interrupt Sources
The Arm nested vector interrupt controller (NVIC) provides a high-speed, deterministic interrupt response,
interrupt masking, and multiple interrupt sources. Each
peripheral is connected to the NVIC and can have multiple interrupt flags to indicate the specific source of the
interrupt within the peripheral. 55 distinct interrupts can
be grouped by firmware into 8 levels of priority (including
internal and external interrupts). There are 9 interrupts for
the GPIO ports, one for each port.
Real-Time Clock and Wake-Up Timer
A real-time clock (RTC) keeps the time of day in absolute
seconds. The 32-bit seconds register can count up to
approximately 136 years and be translated to calendar
format by application software. A time-of-day alarm and
independent subsecond alarm can cause an interrupt or
wake the device from stop mode The minimum wake-up
interval is 244μs. The VRTC supply supports SRAM retention in power mode LP0.
CRC Module
Watchdog Timers
Two independent watchdog timers (WDT0 and WDT1)
with window support are provided. The watchdog timers
are independent and have multiple clock source options
to ensure system security. The watchdog uses a 32-bit
timer with prescaler to generate the watchdog reset. When
enabled, the watchdog timers must be written prior to timeout or within a window of time if window mode is enabled.
Failure to write the watchdog timer during the programmed
timing window results in a watchdog timeout. The WDT0
or WDT1 flags are set on reset if a watchdog expiration
caused the system reset. The clock source options for the
watchdog timers WDT0 and WDT1 include:
●● Scaled system clock
●● Real-time clock
●● Power management clock
A third watchdog timer (WDT2) is provided for recovery
from runaway code or system unresponsiveness. This
recovery watchdog uses a 16-bit timer to generate the
watchdog reset. When enabled, this watchdog must be
written prior to timeout, resulting in a watchdog timeout.
The WDT2 flag is set on reset if a watchdog expiration
caused the system reset. The clock source for the recovery watchdog is the 8kHz nano ring, and the granularity
of the timeout period is intended only for system recovery.
A CRC hardware module is included to provide fast calculations and data integrity checks by application software.
32-BIT TIMER BLOCK
APB
BUS
32-BIT COMPARE
REGISTER
APB
CLOCK
TIME INTERRUPT
REGISTER
TIMER CONTROL
REGISTER
COMPARE
INTERRUPT
PWM AND TIMER
OUTPUT
CONTROL
32-BIT TIMER
(WITH PRESCALER)
32-BIT
PWM/COMPARE
COMPARE
TIMER
INTERRUPT
TIMER
OUTPUT
TIMER
INPUT
Figure 4. Timer Block Diagram, 32-Bit Mode
www.maximintegrated.com
Maxim Integrated │ 20
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Programmable Timers
●● Master or slave mode operation
●● Supports standard (7-bit) addressing or 10-bit addressing
●● Support for clock stretching to allow slower slave
devices to operate on higher speed busses
●● Multiple transfer rates
●● Standard-mode: 100kbps
●● Fast-mode: 400kbps
●● Internal filter to reject noise spikes
●● Receiver FIFO depth of 16 bytes
●● Transmitter FIFO depth of 16 bytes
Six 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals. Each of
the 32-bit timers can also be split into two 16-bit timers,
enabling 12 standard 16-bit timers.
32-bit timer features:
●● 32-bit up/down autoreload
●● Programmable 16-bit prescaler
●● PWM output generation
●● Capture, compare, and capture/compare capability
●● GPIOs can be assigned as external timer inputs,
clock gating or capture, limited to an input frequency
of 1/4 of the peripheral clock frequency
●● Timer output pin
●● Configurable as 2x 16-bit general purpose timers
●● Timer interrupt
Serial Peripherals
USB Controller
The integrated USB slave controller is compliant with the
full-speed (12Mb/s) USB 2.0 specification. The integrated
USB physical interface (PHY) reduces board space and
system cost. An integrated voltage regulator enables
smart switching between the main supply and VDDB when
connected to a USB host controller.
The USB controller supports DMA for the endpoint buffers. A total of 7 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0.
An external 32kHz crystal or clock source is required
for USB operation, even if the RTC function is not used.
Although the USB timing is derived from the internal 96MHz
oscillator, the default accuracy is not sufficient for USB
operation. Periodic firmware adjustments of the 96MHz
oscillator, using the 32kHz timebase as a reference, are
necessary to comply with the USB timing requirements.
I2C Master and Slave Ports
The I2C interface is a bidirectional, two-wire serial bus
that provides a medium-speed communications network.
It can operate as a one-to-one, one-to-many or manyto-many communications medium. Three I2C master
engines and one I2C-selectable slave engine interface
to a wide variety of I2C-compatible peripherals. These
engines support both Standard-mode and Fast-mode I2C
standards. The slave engine shares the same I/O port
as the master engines and is selectable through the I/O
configuration settings. It provides the following features:
Serial Peripheral Interface—Master
The SPI master-mode-only (SPIM) interface operates
independently in a single or multiple slave system and is
fully accessible to the user application.
The SPI ports provide a highly configurable, flexible, and
efficient interface to communicate with a wide variety of
SPI slave devices. The three SPI master ports (SPI0,
SPI1, SPI2) support the following features:
●● SPI modes (0, 3) for single-bit communication
●● 3- or 4-wire mode for single-bit slave device communication
●● Full-duplex operation in single-bit, 4-wire mode
●● Dual and Quad I/O supported
●● Up to 5 slave select lines per port
●● Up to 2 slave ready lines
●● Programmable interface timing
●● Programmable SCK frequency and duty cycle
●● High-speed AHB access to transmit and receive using
32-byte FIFOs
●● SS assertion and deassertion timing with respect to
leading/trailing SCK edge
Serial Peripheral Interface—Slave
The SPI slave (SPIS) port provide a highly configurable,
flexible, and efficient interface to communicate with a wide
variety of SPI master devices. The SPI slave interface
supports the following features:
●● Supports SPI modes 0 and 3
●● Full-duplex operation in single-bit, 4-wire mode
●● Slave select polarity fixed (active low)
●● Dual and Quad I/O supported
●● High-speed AHB access to transmit and receive using
32-byte FIFOs
●● Four interrupts to monitor FIFO levels
www.maximintegrated.com
Maxim Integrated │ 21
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Serial Peripheral Interface Execute in Place (SPIX)
Master
flash memory, providing assurance that only the intended
customer firmware is executed at boot time.
The SPI execute in place (SPIX) master allows the CPU
to transparently execute instructions stored in an external
SPI flash. Instructions fetched through the SPIX master
are cached just like instructions fetched from internal
program memory. The SPIX master can also be used to
access large amounts of external static data that would
otherwise reside in internal data memory.
The code verification public key is also personalized by
the customer and certified by Maxim, allowing the customer to take ownership of the device.
UART
All four universal asynchronous receiver-transmitter
(UART) interfaces support full-duplex asynchronous communication with optional hardware flow control (HFC)
modes to prevent data overruns. If HFC mode is enabled
on a given port, the system uses two extra pins to implement the industry standard request to send (RTS) and
clear to send (CTS) methodology. Each UART is individually programmable.
●●
●●
●●
●●
●●
●●
●●
●●
●●
●●
2-wire interface or 4-wire interface with flow control
32-byte send/receive FIFO
Full-duplex operation for asynchronous data transfers
Programmable interrupt for receive and transmit
Independent baud-rate generator
Programmable 9th bit parity support
Multidrop support
Start/stop bit support
Hardware flow control using RTS/CTS
Maximum baud rate 1843.2kbps
Trust Protection Unit (TPU) (MAX32631/MAX32632)
The TPU enhances cryptographic data security for valuable intellectual property (IP) and data. High-speed,
hardware-based cryptographic accelerators perform
mathematical computations that support cryptographic
algorithms, including:
●● AES-128
●● AES-192
●● AES-256
●● 1024-bit DSA
●● 2048-bit (CRT)
The device provides a true random number generator
that can be used to create cryptographic keys for any
application.
The MAX32632 also provides a secure bootloader that
uses the FIPS186-4 ECDSA algorithm and has a low
impact on performance. It guarantees the authenticity
and integrity of digitally signed code and data in internal
www.maximintegrated.com
Peripheral Management Unit (PMU)
The PMU is a DMA-based link list processing engine that
performs operations and data transfers involving memory
and/or peripherals in the advanced peripheral bus (APB)
and advanced high-performance bus (AHB) peripheral
memory space while the main CPU is in a sleep state.
This allows low-overhead peripheral operations to be
performed without the CPU, significantly reducing overall
power consumption. Using the PMU with the CPU in a
sleep state provides a lower noise environment critical for
obtaining optimum ADC performance.
Key features of the PMU engine include:
●● Six independent channels with round-robin scheduling allows for multiple parallel operations
●● Programmed using SRAM-based PMU op codes
●● PMU action can be initiated from interrupt conditions
from peripherals without CPU
●● Integrated AHB bus master
●● Coprocessor-like state machine
Additional Documentation
Engineers must have the following documents to fully use
this device:
●● This data sheet, containing pin descriptions, feature
overviews, and electrical specifications
●● The device-appropriate user guide, containing detailed information and programming guidelines for
core features and peripherals
●● Errata sheets for specific revisions noting deviations
from published specifications
Development and Technical Support
Contact technical support for information about highly
versatile, affordable development tools, available from
Maxim Integrated and third-party vendors.
●● Evaluation kits
●● Software development kit
●● Compilers
●● Integrated development environments (IDEs)
●● USB interface modules for programming and debugging
Maxim Integrated │ 22
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Applications Information
Table 1. General-Purpose I/O Matrix
PRIMARY
FUNCTION
SECONDARY
FUNCTION
TERTIARY
FUNCTION
QUATERNARY
FUNCTION
PULSE
TRAIN
TIMER
INPUT
GPIO
INTERRUPT
P0.0
UART0A_RX
UART0B_TX
PT_PT0
TIMER_TMR0 GPIO_INT(P0)
P0.1
UART0A_TX
UART0B_RX
PT_PT1
TIMER_TMR1 GPIO_INT(P0)
P0.2
UART0A_CTS
UART0B_RTS
PT_PT2
TIMER_TMR2 GPIO_INT(P0)
P0.3
UART0A_RTS
UART0B_CTS
PT_PT3
TIMER_TMR3 GPIO_INT(P0)
P0.4
SPIM0A_SCK
PT_PT4
TIMER_TMR4 GPIO_INT(P0)
P0.5
SPIM0A_MOSI/SDIO0
PT_PT5
TIMER_TMR5 GPIO_INT(P0)
P0.6
SPIM0A_MISO/SDIO1
PT_PT6
TIMER_TMR0 GPIO_INT(P0)
P0.7
SPIM0A_SS0
PT_PT7
TIMER_TMR1 GPIO_INT(P0)
P1.0
SPIM1A_SCK
SPIX0A_SCK
PT_PT8
TIMER_TMR2 GPIO_INT(P1)
P1.1
SPIM1A_MOSI/SDIO0
SPIX0A_SDIO0
PT_PT9
TIMER_TMR3 GPIO_INT(P1)
P1.2
SPIM1A_MISO/SDIO1
SPIX0A_SDIO1
PT_PT10
TIMER_TMR4 GPIO_INT(P1)
P1.3
SPIM1A_SS0
SPIX0A_SS0
PT_PT11
TIMER_TMR5 GPIO_INT(P1)
P1.4
SPIM1A_SDIO2
SPIX0A_SDIO2
PT_PT12
TIMER_TMR0 GPIO_INT(P1)
P1.5
SPIM1A_SDIO3
SPIX0A_SDIO3
PT_PT13
TIMER_TMR1 GPIO_INT(P1)
P1.6
I2CM0A/S0A_SDA
PT_PT14
TIMER_TMR2 GPIO_INT(P1)
P1.7
I2CM0A/S0A_SCL
PT_PT15
TIMER_TMR3 GPIO_INT(P1)
P2.0
UART1A_RX
UART1B_TX
PT_PT0
TIMER_TMR4 GPIO_INT(P2)
P2.1
UART1A_TX
UART1B_RX
PT_PT1
TIMER_TMR5 GPIO_INT(P2)
P2.2
UART1A_CTS
UART1B_RTS
PT_PT2
TIMER_TMR0 GPIO_INT(P2)
P2.3
UART1A_RTS
UART1B_CTS
PT_PT3
TIMER_TMR1 GPIO_INT(P2)
P2.4
SPIM2A_SCK
PT_PT4
TIMER_TMR2 GPIO_INT(P2)
P2.5
SPIM2A_MOSI/SDIO0
PT_PT5
TIMER_TMR3 GPIO_INT(P2)
P2.6
SPIM2A_MISO/SDIO1
PT_PT6
TIMER_TMR4 GPIO_INT(P2)
P2.7
SPIM2A_SS0
PT_PT7
TIMER_TMR5 GPIO_INT(P2)
P3.0
UART2A_RX
UART2B_TX
PT_PT8
TIMER_TMR0 GPIO_INT(P3)
P3.1
UART2A_TX
UART2B_RX
PT_PT9
TIMER_TMR1 GPIO_INT(P3)
P3.2
UART2A_CTS
UART2B_RTS
PT_PT10
TIMER_TMR2 GPIO_INT(P3)
P3.3
UART2A_RTS
UART2B_CTS
PT_PT11
TIMER_TMR3 GPIO_INT(P3)
P3.4
I2CM1A/S0B_SDA
SPIM2A_SS1
PT_PT12
TIMER_TMR4 GPIO_INT(P3)
P3.5
I2CM1A/S0B_SCL
SPIM2A_SS2
PT_PT13
TIMER_TMR5 GPIO_INT(P3)
P3.6
SPIM1A_SS1
SPIX_SS1
PT_PT14
TIMER_TMR0 GPIO_INT(P3)
P3.7
SPIM1A_SS2
SPIX_SS2
PT_PT15
TIMER_TMR1 GPIO_INT(P3)
P4.0
OWM_I/O
SPIM2A_SR0
PT_PT0
TIMER_TMR2 GPIO_INT(P4)
P4.1
OWM_PUPEN
SPIM2A_SR1
PT_PT1
TIMER_TMR3 GPIO_INT(P4)
P4.2
SPIM0A_SDIO2
SPIS0A_SDIO2
PT_PT2
TIMER_TMR4 GPIO_INT(P4)
P4.3
SPIM0A_SDIO3
SPIS0A_SDIO3
PT_PT3
TIMER_TMR5 GPIO_INT(P4)
P4.4
SPIM0A_SS1
SPIS0A_SCLK
PT_PT4
TIMER_TMR0 GPIO_INT(P4)
www.maximintegrated.com
Maxim Integrated │ 23
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Table 1. General-Purpose I/O Matrix (continued)
PRIMARY
FUNCTION
SECONDARY
FUNCTION
TERTIARY
FUNCTION
QUATERNARY
FUNCTION
PULSE
TRAIN
TIMER
INPUT
GPIO
INTERRUPT
P4.5
SPIM0A_SS2
SPIS0A_MOSI/
SDIO0
PT_PT5
TIMER_TMR1 GPIO_INT(P4)
P4.6
SPIM0A_SS3
SPIS0A_MISO/
SDIO1
PT_PT6
TIMER_TMR2 GPIO_INT(P4)
P4.7
SPIM0A_SS4
SPIS0A_SSEL
PT_PT7
TIMER_TMR3 GPIO_INT(P4)
P5.0
SPIM2B_SCK
PT_PT8
TIMER_TMR4 GPIO_INT(P5)
P5.1
SPIM2B_MOSI/
SDIO0
PT_PT9
TIMER_TMR5 GPIO_INT(P5)
P5.2
SPIM2B_MISO/
SDIO1
PT_PT10
TIMER_TMR0 GPIO_INT(P5)
P5.3
SPIM2B_SS0
UART3A_RX
UART3B_TX
PT_PT11
TIMER_TMR1 GPIO_INT(P5)
P5.4
SPIM2B_SDIO2
UART3A_TX
UART3B_RX
PT_PT12
TIMER_TMR2 GPIO_INT(P5)
P5.5
SPIM2B_SDIO3
UART3A_
CTS
UART3B_RTS
PT_PT13
TIMER_TMR3 GPIO_INT(P5)
P5.6
SPIM2B_SR
UART3A_
RTS
UART3B_CTS
PT_PT14
TIMER_TMR4 GPIO_INT(P5)
P5.7
I2CM2A/S0C_SDA
SPIM2B_SS1
PT_PT15
TIMER_TMR5 GPIO_INT(P5)
P6.0
I2CM2A/S0C_SCL
SPIM2B_SS2
PT_PT0
TIMER_TMR0 GPIO_INT(P6)
P6.1
SPIM2C_SCK
SPIS0B_SCK
PT_PT1
TIMER_TMR1 GPIO_INT(P6)
P6.2
SPIM2C_MOSI/SDIO0
SPIS0B_MOSI/
SDIO0
PT_PT2
TIMER_TMR2 GPIO_INT(P6)
P6.3
SPIM2C_MISO/SDIO1
SPIS0B_MISO/
SDIO1
PT_PT3
TIMER_TMR3 GPIO_INT(P6)
P6.4
SPIM2C_SS0
SPIS0B_SSEL
PT_PT4
TIMER_TMR4 GPIO_INT(P6)
P6.5
SPIM2C_SDIO2
SPIS0B_SDIO2
PT_PT5
TIMER_TMR5 GPIO_INT(P6)
P6.6
SPIM2C_SDIO3
SPIS0B_SDIO3
PT_PT6
TIMER_TMR0 GPIO_INT(P6)
P6.7
SPIM2C_SR0
I2CM2B/SE_SDA
PT_PT7
TIMER_TMR1 GPIO_INT(P6)
P7.0
SPIM2C_SS1
I2CM2B/SE_SCL
PT_PT8
TIMER_TMR2 GPIO_INT(P7)
P7.1
SPIM2C_SS2
I2CM1B/SD_
SDA
PT_PT9
TIMER_TMR3 GPIO_INT(P7)
P7.2
SPIM2C_SR1
I2CM1B/SD_SCL
PT_PT10
TIMER_TMR4 GPIO_INT(P7)
P7.3
SPIS0C_SCK
I2CM2C/SG_SDA
PT_PT11
TIMER_TMR5 GPIO_INT(P7)
P7.4
SPIS0C_MOSI/SDIO0
I2CM2C/SG_SCL
PT_PT12
TIMER_TMR0 GPIO_INT(P7)
P7.5
SPIS0C_MISO/SDIO1
PT_PT13
TIMER_TMR1 GPIO_INT(P7)
P7.6
SPIS0C_SS0
PT_PT14
TIMER_TMR2 GPIO_INT(P7)
P7.7
SPIS0C_SDIO2
I2CM1C/SF_SDA
PT_PT15
TIMER_TMR3 GPIO_INT(P7)
P8.0
SPIS0C_SDIO3
I2CM1C/SF_SCL
PT_PT0
TIMER_TMR4 GPIO_INT(P8)
PT_PT1
TIMER_TMR5 GPIO_INT(P8)
P8.1
www.maximintegrated.com
Maxim Integrated │ 24
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Ordering Information
FLASH
(MB)
SRAM
(KB)
TRUST PROTECTION
UNIT (TPU)
SECURE
BOOTLOADER
MAX32630IWQ+
2
512
No
No
100 WLP
MAX32630IWQ+T
2
512
No
No
100 WLP
MAX32630ICQ+
2
512
No
No
100 TQFP-EP
MAX32631IWQ+
2
512
Yes
No
100 WLP
MAX32631IWQ+T
2
512
Yes
No
100 WLP
MAX32631ICQ+
2
512
Yes
No
100 TQFP-EP
MAX32632IWQ+
2
512
Yes
Yes
100 WLP
MAX32632IWQ+T
2
512
Yes
Yes
100 WLP
PART
PIN-PACKAGE
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
www.maximintegrated.com
Maxim Integrated │ 25
MAX32630–MAX32632
Ultra-Low-Power Arm Cortex-M4
with FPU-Based Microcontroller (MCU)
with 2MB Flash and 512KB SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/16
1
6/17
2
11/17
Updated Ordering Information, added TQFP-EP,
3/18
Removed MAX32632 part number, updated General Description and Benefits and
Features sections, added TQFP-EP in the Pin Description, updated Arm references
1–26
4
4/18
Added MAX32632, updated General Description, Benefits and Features, Simplified
Block Diagram, Arm references, Pin Description, Detailed Description, Figure 2,
Watchdog Timers, Trust Protection Unit (TPU) (MAX32631/MAX32632), Additional
Documentation, Ordering Information
1–26
5
10/18
Updated title, Benefits and Features, Detailed Description, Figure 2, Trust Protection
Unit (TPU) (MAX32631/MAX32632) sections
3
5.1
PAGES
CHANGED
DESCRIPTION
Initial release
Added MAX32632 description and part numbers, updated Ordering Information,
changed PRNG references to true random number generator, corrected Arm
trademark references
—
1–25
24
Added link to 100 TQFP-EP package outline and land pattern
1, 18, 19,
22, 26
3
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2018 Maxim Integrated Products, Inc. │ 26
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