MAX3265EUE

19-1523; Rev 7, 2/06 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers Features ♦ +3.0V to +5.5V Supply Voltage ♦ Low Deterministic Jitter 14ps (MAX3264) 11ps (MAX3265/MAX3765) ♦ 150ps (max) Edge Speed (MAX3265/MAX3765) 300ps (max) Edge Speed (MAX3264) ♦ Programmable Signal-Detect Function ♦ Choice of CML or PECL Output Interface ♦ 10-Pin µMAX or 16-Pin TSSOP Package Ordering Information PART TEMP RANGE Applications PIN-PACKAGE 0°C to +70°C 16 TSSOP-EP* MAX3264CUE+ 0°C to +70°C 16 TSSOP-EP* MAX3264C/D 0°C to +70°C Dice** MAX3265CUE 0°C to +70°C 16 TSSOP-EP* MAX3265CUE+ 0°C to +70°C 16 TSSOP-EP* MAX3265CUB 0°C to +70°C 10 µMAX-EP* MAX3264CUE Gigabit Ethernet Optical Receivers MAX3265CUB+ 0°C to +70°C 10 µMAX-EP* Fibre Channel Optical Receivers MAX3265EUE -40°C to +85°C 16 TSSOP-EP* System Interconnect MAX3265EUE+ -40°C to +85°C 16 TSSOP-EP* MAX3265C/D ATM Optical Receivers 0°C to +70°C Dice** +Denotes lead-free package. *EP = Exposed paddle. **Dice are designed to operate from 0°C to +70°C, but are tested and guaranteed only at TA = +25°C. Selector Guide appears at end of data sheet. Pin Configurations appear at end of data sheet. Ordering Information continued at end of data sheet. Typical Operating Circuits CAZ VCC CAZ1 VCC VCC CAZ2 MAX3264CUE MAX3265CUE MAX3265EUE CIN 0.01µF RTERM 0.01µF OUT+ IN+ 100Ω IN- MAX3266 MAX3267 0.01µF OUT- CIN 0.01µF RL 100Ω RTERM TH SQUELCH LOS LEVEL LOSS N.C. OF SIGNAL N.C. LOS VCC RTH Typical Operating Circuits continued at end of data sheet. N.C. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 General Description The 1.25Gbps MAX3264/MAX3268/MAX3768 and the 2.5Gbps MAX3265/MAX3269/MAX3765 limiting amplifiers are designed for Gigabit Ethernet and Fibre Channel optical receiver systems. The amplifiers accept a wide range of input voltages and provide constantlevel output voltages with controlled edge speeds. Additional features include RMS power detectors with programmable loss-of-signal (LOS) indication, an optional squelch function that mutes the data output signal when the input voltage falls below a programmable threshold, and excellent jitter performance. The MAX3264/MAX3265/MAX3765 feature current-mode logic (CML) data outputs that are tolerant of inductive connectors and a 16-pin TSSOP package, making these circuits ideal for GBIC receivers. The MAX3268/ MAX3269/MAX3768 feature standards-compliant positive-referenced emitter-coupled logic (PECL) data outputs and are available in a tiny 10-pin µMAX package that is ideal for small-form-factor (SFF) receivers. MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ............................................-0.5V to +6.0V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at SQUELCH, CAZ1, CAZ2, LOS, LOS, TH..................................-0.5V to (VCC + 0.5V) Voltage at LEVEL...................................................-0.5V to +2.0V Current into LOS, LOS ..........................................-1mA to +9mA Differential Input Voltage (IN+ - IN-) .....................................2.5V Continuous Current at CML Outputs (OUT+, OUT-) ..........................-25mA to +25mA Continuous Current at PECL Outputs (OUT+, OUT-) .........50mA Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 27mW/°C above +70°C) .........2162mW 10-Pin µMAX (derate 20mW/°C above +70°C) ...........1600mW Operating Ambient Temperature Range .............-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Processing Temperature (dice) .......................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Data outputs terminated per Figure 1, VCC = +3.0V to +5.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Data Rate Input Voltage Range Deterministic Jitter Random Jitter CONDITIONS MAX3264/MAX3268/MAX3768 1.25 2.5 MAX 5 1200 MAX3265/MAX3269/MAX3765 10 1200 MAX3264/MAX3268/MAX3768 (Notes 2, 3) 14 30 MAX3265/MAX3269/MAX3765 (Notes 2, 3) 11 25 MAX3264/MAX3268/MAX3768 (Notes 2, 4) 15 MAX3265/MAX3269/MAX3765 (Notes 2, 4) 8 80 MAX3265/MAX3765 (Note 6) MAX3268/MAX3768 (Note 5) 80 LOS Hysteresis (Notes 2, 7) LOS Assert/Deassert Time (Notes 7, 8) Low LOS Assert Level RTH = 2.5kΩ Low LOS Deassert Level RTH = 2.5kΩ 2.5 UNITS Gbps MAX3264/MAX3268/MAX3768 MAX3269 (Note 6) 2 TYP MAX3265/MAX3269/MAX3765 MAX3264 (Note 5) Data Output Edge Speed MIN mV psp-p psRMS 175 300 100 150 150 300 100 150 ps 4.4 dB 1 µs MAX3264/MAX3268/MAX3768 1.20 2.6 MAX3265/MAX3269/MAX3765 2.20 4.8 MAX3264/MAX3268/MAX3768 4.5 MAX3265/MAX3269/MAX3765 8.5 _______________________________________________________________________________________ mV mV +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers (Data outputs terminated per Figure 1, VCC = +3.0V to +5.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS Medium LOS Assert Level RTH = 7kΩ Medium LOS Deassert Level RTH = 7kΩ High LOS Assert Level RTH = 20kΩ High LOS Deassert Level RTH = 20kΩ MIN TYP MAX3264/MAX3268/MAX3768 5.6 9 MAX3265/MAX3269/MAX3765 9.9 16 15 19.8 MAX3265/MAX3269/MAX3765 40.5 MAX3264/MAX3268/MAX3768 9.4 27 21.6 MAX3265/MAX3269/MAX3765 18.0 41.5 MAX3264/MAX3268/MAX3768 35 MAX3265/MAX3269/MAX3765 67 Input-Referred Noise CML Output Voltage IN+ to IN- UNITS mV MAX3264/MAX3268/MAX3768 Squelch Input Current Differential Input Resistance MAX mV mV mV 0 80 400 µA 97 100 103 Ω MAX3264/MAX3268/MAX3768 150 MAX3265/MAX3269/MAX3765 230 LEVEL = open, RLOAD = 50Ω 550 LEVEL = GND, RLOAD = 75Ω 1100 µVRMS 1200 1270 1800 mV PECL Output High Voltage Referenced to VCC -1.025 -0.880 V PECL Output Low Voltage Referenced to VCC -1.810 -1.620 V LOS Output High Voltage ILOS = -30µA LOS Output Low Voltage ILOS = +1.2mA 0.4 V Output Signal When Squelched Outputs AC-coupled 20 Power-Supply Rejection Ratio Low-Frequency Cutoff Output Resistance (Single Ended) Power-Supply Current 2.4 V mV f < 2MHz 20 dB CAZ = open 2 MHz CAZ = 0.1µF 2 kHz MAX3264/MAX3265/MAX3765 85 MAX3268/MAX3269/MAX3768 Figure 2 Output not squelched Output squelched 100 115 4 MAX3268 39 62 MAX3269 48 78 MAX3264 38 62 MAX3265 50 76 MAX3765 50 76 MAX3768 39 62 MAX3765 64 90 Ω mA _______________________________________________________________________________________ 3 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 ELECTRICAL CHARACTERISTICS (continued) MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers ELECTRICAL CHARACTERISTICS—MAX3265EUE (Data outputs terminated per Figure 1, VCC = +3.0V to +5.5V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN Data Rate TYP Input Voltage Range 10 (Notes 2, 3) 11 Random Jitter (Notes 2, 4) 8 Data Output Edge Speed (Note 6) LOS Hysteresis (Notes 2, 7) LOS Assert/Deassert Time (Notes 7, 8) Low LOS Assert Level RTH = 2.5kΩ Low LOS Deassert Level RTH = 2.5kΩ Medium LOS Assert Level RTH = 7kΩ Medium LOS Deassert Level RTH = 7kΩ High LOS Assert Level RTH = 20kΩ High LOS Deassert Level RTH = 20kΩ 100 2.2 2.20 155 ps 1 µs mV 4.8 13.6 mV mV 16 43.0 mV mV 41.5 67 111 mV 0 80 400 µA IN+ to IN- 97 100 103 Ω LEVEL = open, RLOAD = 50Ω 550 LEVEL = GND, RLOAD = 75Ω 1100 Squelch Input Current Input-Referred Noise CML Output Voltage psp-p psRMS dB 27 18.0 25 mV 4.4 8.5 9.9 UNITS Gbps 1200 Deterministic Jitter Differential Input Resistance MAX 2.5 230 µVRMS 1200 1270 1800 mV LOS Output High Voltage ILOS = -30µA LOS Output Low Voltage ILOS = +1.2mA Output Signal When Squelched Outputs AC-coupled 20 mV Power-Supply Rejection Ratio f < 2MHz 20 dB CAZ = open 2 MHz CAZ = 0.1µF 2 Low-Frequency Cutoff Output Resistance (single ended) Power-Supply Current 2.4 85 Figure 2 V 0.450 V kHz 100 115 Ω 50 76 mA Note 1: Specifications for Input Voltage Range, LOS Assert/Deassert Levels, and CML Output Voltage refer to the total differential peak-to-peak signal applied or measured. PECL output voltages are absolute (single-ended) voltages measured at a single output. Note 2: Input edge speed is controlled using four-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum data rate. Note 3: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A. Note 4: Random jitter is measured with the minimum input signal applied after filtering with a four-pole, lowpass, Bessel filter (frequency bandwidth at 75% of the maximum data rate). For Fibre Channel and Gigabit Ethernet applications, the peak-topeak random jitter is 14.1-times the RMS random jitter. Note 5: Input signal applied after a 933MHz Bessel filter. Note 6: Input signal applied after a 1.8GHz Bessel filter. Note 7: Input for LOS assert/deassert and hysteresis tests is a repeating K28.5 pattern. Hysteresis is defined as: 20log (VLOS-DEASSERT / VLOS-ASSERT). Note 8: Response time to a 10dB change in input power. 4 _______________________________________________________________________________________ +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers 1100 MAX3265/MAX3269/MAX3765 700 5.0 RTH = 7kΩ 4.5 6.0 RTH = 25kΩ 4.0 500 2 4 6 8 10 RTH = 4.6kΩ 5.0 4.5 RTH = 16kΩ 3.5 0 12 10 20 30 40 50 60 -40 70 -15 10 35 60 INPUT VOLTAGE (mV) TEMPERATURE (°C) TEMPERATURE (°C) MAX3264/MAX3268/MAX3768 DETERMINISTIC JITTER vs. INPUT AMPLITUDE MAX3264/MAX3268/MAX3768 RANDOM JITTER vs. INPUT AMPLITUDE MAX3265/MAX3269/MAX3765 DETERMINISTIC JITTER vs. INPUT AMPLITUDE 14 12 RMS JITTER (ps) 25 20 15 10 85 30 MAX3264/5/8/9 TOC06 16 MAX3264/5/8/9 TOC04 30 25 20 10 JITTER (ps) 0 5.5 4.0 3.5 300 JITTER (ps) 5.5 MAX3264/5/8/9 TOC03 6.0 LOS HYSTERESIS (dB) 1300 MAX3264/5/8/9 TOC03a MAX3264/MAX3268 6.5 MAX3264/5/8/9 TOC05 OUTPUT VOLTAGE (mV) 1500 6.5 LOS HYSTERESIS (dB) MAX3264/5/8/9 TOC01a 1700 900 MAX3265EUE LOS HYSTERESIS vs. TEMPERATURE MAX3264 LOS HYSTERESIS vs. TEMPERATURE OUTPUT VOLTAGE vs. INPUT VOLTAGE 8 6 15 10 4 0 0 0 200 400 600 800 1000 0 1200 INPUT AMPLITUDE (mV) MAX3265/MAX3269/MAX3765 RANDOM JITTER vs. INPUT AMPLITUDE MAX3264/5/8/9 TOC07 8 7 6 5 10 20 30 40 0 50 200 400 600 800 1000 INPUT AMPLITUDE (mV) INPUT AMPLITUDE (mV) LOSS OF SIGNAL WITH SQUELCH MAX3268/MAX3768 DATA OUTPUT EYE DIAGRAM (MINIMUM INPUT) 1200 MAX3264/5/8/9 TOC08 0 RMS JITTER (ps) 5 2 MAX3264/5/8/9 TOC09 5 VIN VOUT 300mV/div 4 3 VLOS 2 1 0 0 10 20 30 40 50 500ns/div 200ps/div INPUT AMPLITUDE (mV) _______________________________________________________________________________________ 5 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX3264 DATA OUTPUT EYE DIAGRAM AT 1.25Gbps (MINIMUM INPUT) MAX3265/MAX3765 DATA OUTPUT EYE DIAGRAM 2.5Gbps (MINIMUM INPUT) 50mV/div OUTPUT VSWR vs. FREQUENCY 4.0 25 20 3.5 VSWR 15 2.0 5 1.5 0 100ps/div 1.0 100k MAX3264 LOSS-OF-SIGNAL THRESHOLD vs. RTH 25 20 15 10 100M 1G 0.5 1.0 1.5 2.5 2.0 FREQUENCY (GHz) MAX3265/MAX3765 LOSS-OF-SIGNAL THRESHOLD vs. RTH COMMON-MODE REJECTION RATIO vs. FREQUENCY 50 55 30 20 MAX3268/MAX3768 50 45 40 40 3.0 35 30 25 MAX3265/MAX3765 20 15 10 5 0 FREQUENCY (Hz) CMRR (dB) 30 10M MAX3264/5/8/9 TOC19 35 1M 60 LOS ASSERT THRESHOLD (mV) MAX3264/5/8/9 TOC18 40 2.5 MAX3264/5/8/9 TOC20 PSRR (dB) 3.0 10 10 0 5 0 0 6 MAX3264/5/8/9 TOC15 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY MAX3264/5/8/9 TOC14 200ps/div MAX3264/5/8/9 TOC13 150mV/div 100ps/div 200ps/div MAX3265/MAX3765 DATA OUTPUT EYE DIAGRAM 2.5Gbps (MAXIMUM INPUT) 150mV/div MAX3264/5/8/9 TOC12 MAX3264/5/8/9 TOC11 MAX3264/5/8/9 TOC10 MAX3264 DATA OUTPUT EYE DIAGRAM AT 1.25Gbps (MAXIMUM INPUT) 150mV/div LOS ASSERT THRESHOLD (mV) MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers 5 10 15 20 RTH (kΩ) 25 30 35 0 5 10 15 RTH (kΩ) 20 25 30 1M 10M 100M FREQUENCY (Hz) _______________________________________________________________________________________ 1G 10G +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers PIN NAME FUNCTION µMAX TSSOP 1, 4 3, 6 GND Supply Ground 2 4 IN+ Noninverted Input Signal 3 5 IN- Inverted Input Signal 5 8 TH Loss-of-Signal Threshold. A resistor connected from this pin to ground sets the input signal level at which the loss-of-signal (LOS) output(s) is asserted. Refer to Typical Operating Characteristics and Design Procedure. 6 9 LOS Inverted Loss-of-Signal Output. LOS is high when the level of the input signal is above the preset threshold set by the TH input. LOS is asserted low when the signal level drops below the threshold. 7, 10 11, 14 VCC Supply Voltage 8 12 OUT- Inverted Data Output 9 13 OUT+ Noninverted Data Output — 1 CAZ1 Offset-Correction-Loop Capacitor. A capacitor connected between this pin and CAZ2 extends the time constant of the offset correction loop. — 2 CAZ2 Offset-Correction-Loop Capacitor. A capacitor connected between this pin and CAZ1 extends the time constant of the offset correction loop. Refer to Design Procedure. — 7 LEVEL Output Current Level. When this pin is not connected, the CML output current is approximately 16mA. When this pin is connected to ground, the output current increases to approximately 20mA. (In the MAX3265CUB/MAX3765CUB, LEVEL is internally connected to ground.) — 10 LOS Noninverted Loss-of-Signal Output. LOS is low when the level of the input signal is above the preset threshold set by the TH input. LOS asserts high when the signal level drops below the threshold. Squelch Input. The squelch function is disabled when SQUELCH is not connected or is set to a TTL low level. When SQUELCH is set to a TTL high level and LOS is asserted, the data outputs, OUT+, and OUT-, are forced to static levels. See sections PECL Output Buffer and CML Output Buffer for more information. (In the MAX3265/MAX3268/MAX3269 10-pin µMAX, SQUELCH is not connected. In the MAX3765/MAX3768, SQUELCH is internally connected to VCC.) — 15 SQUELCH — 16 N.C. EP EP Exposed Paddle No Connection Ground. The exposed paddle must be soldered to the circuit–board ground for proper thermal performance. _______________________________________________________________________________________ 7 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 Pin Description MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers VCC VCC VCC VCC 100Ω 100Ω 100Ω RTERM 100Ω 300Ω 100Ω COUT 100Ω RTERM 300Ω COUT 2 x RLOAD 150Ω 2 x RLOAD 100Ω COUT COUT MAX3264 MAX3265 MAX3765 MAX3264 MAX3265 MAX3765 (a) MAX3264/MAX3265/MAX3765 WITH 50Ω TERMINATION (b) MAX3264/MAX3265/MAX3765 WITH 75Ω TERMINATION VCC MAX3268 MAX3269 MAX3768 OUTOUT+ RTERM 50Ω 50Ω (c) MAX3268/MAX3269/MAX3768 OUTPUT TERMINATION VCC - 2V Figure 1. Data Output Termination 8 _______________________________________________________________________________________ +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 VCC ICC IOUT 100Ω 100Ω MAX3264CUE: OPEN MAX3265CUE: OPEN SQUELCH MAX3265CUB: GND (INTERNAL) MAX3765CUB: VCC (INTERNAL) CONTROL MAX3264 MAX3265 MAX3765 LEVEL MAX3264CUE: OPEN MAX3265CUE: OPEN MAX3265CUB: GND (INTERNAL) MAX3765CUB: GND (INTERNAL) RTH 2.5kΩ (a) CML SUPPLY CURRENT (ICC) VCC ICC OUT+ MAX3268 MAX3269 MAX3768 OPEN OUTOPEN RTH 2.5kΩ (b) PECL SUPPLY CURRENT (ICC) Figure 2. Power-Supply Current Measurement _______________________________________________________________________________________ 9 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers RMS Power Detect with Loss-of-Signal Indicator _______________Detailed Description Figure 3 is a functional diagram of the MAX3264/ MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 limiting amplifiers. A linear input buffer drives a multistage limiting amplifier and an RMS power-detection circuit. Offset correction with lowpass filtering ensures low deterministic jitter. The output buffer produces a limited output signal. The MAX3264/MAX3265/MAX3765 produce a CML output, while the MAX3268/MAX3269/ MAX3768 produce a PECL-compatible output signal. Schematics of these input/output circuits are shown in Figures 4 through 7. An RMS power detector looks at the signal from the input buffer and compares it to a threshold set by the TH resistor (see Typical Operating Characteristics for appropriate resistor values). The signal-detect information is provided to the LOS outputs, which are internally terminated with 8kΩ (MAX3265/MAX3269/MAX3765) or 16kΩ (MAX3264/MAX3268/MAX3768) pullup resistors. The LOS outputs meet TTL voltage specifications when loaded with a resistor ≥ 4.7kΩ. TH VCC RLOS = 8kΩ (MAX3265/MAX3269/MAX3765) RLOS = 16kΩ (MAX3264/MAX3268/MAX3768) MAX3264 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768 RLOS LOS TTL VCC POWER DETECT WITH COMPARATOR RLOS LOS TTL GAIN IN+ OUT+ 100Ω INPUT BUFFER OUTPUT BUFFER IN- OUT- SQUELCH LOWPASS OFFSET CORRECTION CONTROL LEVEL 100pF CAZ1 CAZ2 TOTAL GAIN = 55dB (MAX3264/MAX3268/MAX3768) TOTAL GAIN = 49dB (MAX3265/MAX3269/MAX3765) Figure 3. Functional Diagram 10 ______________________________________________________________________________________ +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers CML Output Buffer The MAX3264/MAX3265/MAX3765 CML output circuits (Figure 7) provide high tolerance to impedance mismatches and inductive connectors. The output current can be set to two levels. When the LEVEL pin is left unconnected, output current is approximately 16mA. Connecting LEVEL to ground sets the output current to approximately 20mA. Gain Stage and Offset Correction The squelch function is enabled when the SQUELCH pin is set to a TTL-high level or connected to VCC. The squelch function holds OUT+ and OUT- at a static voltage whenever the input signal power drops below the loss-of-signal threshold. In the 10-pin µMAX package of the MAX3265/MAX3268/MAX3269, the SQUELCH function is left internally unconnected. In the MAX3765/ MAX3768, the SQUELCH function is always enabled by internally connecting it to VCC. SQUELCH operation for the MAX3264/MAX3265 is described in Table 1. The limiting amplifier provides approximately 55dB (MAX3264/MAX3268/MAX3768) or 49dB (MAX3265/ MAX3269/MAX3765) of gain. This large gain makes the amplifier susceptible to small DC offsets in the input signal. DC offsets as low as 1mV reduce the accuracy of the power-detection circuit and may cause deterministic jitter. A low-frequency feedback loop is integrated into the limiting amplifier to reduce input offset, typically to less than 100µV. An external capacitor connected between CAZ1 and CAZ2, in parallel with internal capacitance, determines the time constant of the offset-correction circuit. The offset-correction circuit requires an average data-input mark density of 50% to prevent an increase in dutycycle distortion and to ensure low deterministic jitter. Table 1. LEVEL PIN VOLTAGE WHEN SQUELCHED OUT- OUT+ Open VCC - 100mV VCC GND VCC - 100mV VCC - 100mV Internal Input/Output Schematics VCC 500Ω 500Ω VCC 0.25pF IN+ 110Ω IN- RT 0.25pF LOS ESD STRUCTURES ESD STRUCTURE GND RT = 8kΩ (MAX3265/MAX3269/MAX3765) RT = 16kΩ (MAX3264/MAX3268/MAX3768) GND Figure 4. Input Circuit Figure 5. LOS Output Circuit ______________________________________________________________________________________ 11 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 Input Buffer The input buffer is designed to accept input signals from the MAX3266/MAX3267 transimpedance amplifiers. The input buffer provides a 100Ω input impedance between IN+ and IN-. Input VSWR is typically less than 2.0 for frequencies less than 2GHz. DC-coupling the inputs is not recommended; this prevents the DC offset-correction circuitry from functioning properly. MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers VCC VCC ESD STRUCTURES ESD STRUCTURES 100Ω 100Ω OUT+ OUT- OUT+ OUT- GND GND LEVEL Figure 6. PECL Output Circuit Figure 7. CML Output Circuit The buffer’s output impedance is determined by the parallel combination of internal and external pullup resistors, which are chosen to match the impedance of the transmission line (Figure 1). The output buffer can be AC- or DC-coupled to the load. minimized when the input low-frequency cutoff (fIN) is placed at a low frequency: fIN = 1 / [2π(50)(C)] For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) ≥ 0.01µF, which provides fIN < 320kHz. For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides fIN < 32kHz. PECL Output Buffer The MAX3268/MAX3269/MAX3768 offer an industrystandard PECL output. The PECL outputs should be terminated to VCC - 2V. Figure 6 shows the PECL output circuit. The squelch function forces OUT+ to a high level and OUT- to a low level when the input is below the programmed LOS threshold. In the 10-pin µMAX, SQUELCH is left unconnected. __________________Design Procedure Program the LOS Assert Threshold The loss-of-signal threshold is programmed by external resistor RTH. See the LOS Threshold vs. RTH graph in the Typical Operating Characteristics. Select the Coupling Capacitors The coupling capacitors (CIN, COUT) should be selected to minimize the receiver’s deterministic jitter. Jitter is 12 Select the Offset-Correction Capacitor (MAX3264/MAX3265 TSSOP Only) To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC-offset-correction circuit. fOC = 75 / [2π 60k (CAZ + 100pF)] = 200 x 10 -6 / (CAZ + 100pF) For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, leave pins CAZ1, and CAZ2 open (fOC = 2MHz). For ATM/SONET or other applications using scrambled NRZ data, select CAZ ≥ 0.1µF, which typically provides fOC = 2kHz. ______________________________________________________________________________________ +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers Optical Hysteresis In an optical receiver, the electrical power change at the limiting amplifier is 2x the optical power change. As an example, if a receiver’s optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the limiting amplifier also increases by a factor of two. The optical power change is 10log(2x / x) = 10log(2) = +3dB. At the limiting amplifier, the electrical power change is: 10log (2VIN )2 / RIN VIN2 / RIN = 10log(22 ) = 20log(2) = + 6dB The MAX3264/MAX3265/MAX3268/MAX3269/MAX3765s’ typical voltage hysteresis is 4.4dB. This provides an optical hysteresis of 2.2dB. VCC_MODULE MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 Applications Information HOST VCC_HOST GBIC MODULE 4.7kΩ MAX3264 MAX3265 MAX3268 LOS MAX3269 MAX3765 MAX3768 GENERALPURPOSE NPN Figure 8. Recommended GBIC LOS Circuit GBIC Loss of Signal In a GBIC application, the GBIC’s LOS output must be high impedance when VCC_MODULE = GND. Figure 8 shows the recommended circuit to maintain high impedance. ESD protection diodes on the MAX3264/ MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 LOS outputs can be turned on when V CC_ HOST > VCC_MODULE. PECL Terminations The standard PECL termination (50Ω to VCC - 2V) is recommended for best performance and output characteristics (see Figure 1). The data outputs operate at high speed and should always drive transmission lines with matched, balanced terminations. Figure 9 shows an alternate method for terminating the data outputs. The technique provides approximately 8mA DC bias current, with a 45Ω AC load, for the output termination. This technique is useful for viewing the output on an oscilloscope or changing the PECL reference voltage. OUT+ 470Ω 50Ω 470Ω 50Ω MAX3268 MAX3269 MAX3768 OUT- DRIVING 50Ω TO GROUND Figure 9. Alternative PECL Termination Wire Bonding Dice For high current density and reliable operation, the MAX3264/MAX3265/MAX3268/MAX3269 use gold metalization. Make connections to the dice with gold wire only, and use ballbonding techniques (wedge bonding is not recommended). Die-pad size is 4-mils square, with a 6-mil pitch. Die thickness is 15 mils (0.375mm). ______________________________________________________________________________________ 13 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers Typical Operating Circuits (continued) VCC VCC MAX3268CUB MAX3269CUB MAX3768CUB CIN 0.01µF OUT+ IN+ 100Ω IN- MAX3266 MAX3267 OUT- CIN 0.01µF 50Ω 50Ω LOS TH RTH VCC - 2V SIGNAL DETECT Ordering Information (continued) PART TEMP RANGE Pin Configurations PIN-PACKAGE MAX3268CUB 0°C to +70°C 10 µMAX-EP* MAX3268CUB+ 0°C to +70°C 10 µMAX-EP* MAX3268C/D 0°C to +70°C Dice** MAX3269CUB 0°C to +70°C 10 µMAX-EP* MAX3269CUB+ 0°C to +70°C 10 µMAX-EP* MAX3269C/D 0°C to +70°C Dice** MAX3765CUB 0°C to +70°C 10 µMAX-EP* MAX3765CUB+ 0°C to +70°C 10 µMAX-EP* MAX3768CUB 0°C to +70°C 10 µMAX-EP* MAX3768CUB+ 0°C to +70°C 10 µMAX-EP* +Denotes lead-free package. *EP = Exposed paddle. **Dice are designed to operate from 0°C to +70°C, but are tested and guaranteed only at TA = +25°C. TOP VIEW CAZ1 1 16 N.C. CAZ2 2 15 SQUELCH GND 3 14 VCC IN+ 4 IN- 5 MAX3264 MAX3265 13 OUT+ 12 OUT- GND 6 11 VCC LEVEL 7 10 LOS 9 TH 8 TSSOP NOTE: EXPOSED PADDLE IS GROUND. GND 1 IN+ 10 VCC 2 IN- 3 GND 4 TH 5 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768 9 OUT+ 8 OUT- 7 VCC 6 LOS µMAX 14 LOS ______________________________________________________________________________________ +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers PART OUTPUT DATA RATE (Gbps) PINPACKAGE SQUELCH FUNCTION CML OUTPUT LEVEL MAX3264 CML 1.25 MAX3265 CML 2.5 MAX3268 PECL 1.25 16 TSSOP-EP 16 TSSOP-EP 10 µMAX-EP 10 µMAX-EP Selectable Selectable Disabled Disabled Selectable Selectable Maximum* N/A MAX3269 PECL 2.5 10 µMAX-EP Disabled N/A MAX3765 MAX3768 CML PECL 2.5 1.25 10 µMAX-EP 10 µMAX-EP Enabled Enabled Maximum* N/A *LEVEL pin grounded Chip Topographies MAX3264/MAX3265/MAX3765 MAX3268/MAX3269/MAX3768 N.C. CAZ1 CAZ2 SQUELCH GND VCC IN+ OUT+ IN- OUT- GND VCC LEVEL LOS TH N.C. LOS 0.061" (1.55mm) N.C. CAZ1 0.061" (1.55mm) CAZ2 SQUELCH GND VCC IN+ OUT+ IN- OUT- 0.061" (1.55mm) VCC GND LOS TH N.C. LOS 0.061" (1.55mm) MAX3264/MAX3265/MAX3765 TRANSISTOR COUNT: 726 MAX3268/MAX3269/MAX3768 TRANSISTOR COUNT: 728 SUBSTRATE CONNECTED TO GND ______________________________________________________________________________________ 15 MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 Selector Guide Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) e 10LUMAX.EPS MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers 4X S 10 INCHES 10 H Ø0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 0.120 E1 0.116 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF 0.0106 b 0.007 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0° 6° MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 2.89 3.00 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0° 6° E2 GAGE PLANE A2 c A b D1 FRONT VIEW A1 α E1 L L1 SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 16 ______________________________________________________________________________________ REV. 1 1 +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers TSSOP 4.4mm BODY.EPS XX XX PACKAGE OUTLINE, TSSOP, 4.40 MM BODY, EXPOSED PAD 21-0108 E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)