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MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with
256KB Flash and 96KB SRAM
General Description
In the DARWIN family, the MAX32660 is an ultra-low-power, cost-effective, highly-integrated 32-bit microcontroller
designed for battery-powered devices and wireless sensors. It combines a flexible and versatile power management unit with the powerful Arm® Cortex®-M4 processor
with floating point unit (FPU) in the industry’s smallest form
factor: 1.6mm x 1.6mm, 16-bump WLP or 4mm x 4mm,
20-pin TQFN-EP, or 3mm x 3mm, 24-pin TQFN-EP.
The MAX32660 enables designs with complex sensor
processing without compromising battery life. It also offers
legacy designs an easy and cost optimal upgrade path
from 8- or 16-bit microcontrollers.
The device supports SPI, UART, and I2C communication
while also integrating up to 256KB of flash memory and
96KB of RAM to accommodate application and sensor
code. An optional bootloader through I2C, UART, or SPI is
available.
Applications
●● Sports Watches
●● Fitness Monitors
●● Wearable Medical Patches
●● Portable Medical Devices
●● Industrial Sensors
●● IoT
●● Optical Modules: QSFP-DD, QSFP, 400G
Benefits and Features
●● High-Efficiency Microcontroller for Wearable Devices
• Internal Oscillator Operates Up to 96MHz
• 256KB Flash Memory
• 96KB SRAM, Optionally Preserved in Lowest
Power Backup Mode
• 16KB Instruction Cache
• Memory Protection Unit (MPU)
• Low 1.1V VCORE Supply Voltage
• 3.6V GPIO Operating Range
• Internal LDO Provides Operation from Single Supply
• Wide Operating Temperature: -40°C to +105°C
●● Power Management Maximizes Uptime for Battery
Applications
• 85μA/MHz Active Executing from Flash
• 2μA Full Memory Retention Power in Backup Mode
at VDD = 1.8V
• 450nA Ultra-Low Power RTC at VDD = 1.8V
• Internal 80kHz Ring Oscillator
●● Optimal Peripheral Mix Provides Platform Scalability
• Up to 14 General-Purpose I/O Pins
• Up to Two SPI Master/Slave
• I2S Master/Slave
• Up to Two UARTs
• Up to Two I2C Master/Slave, 3.4Mbps High Speed
• Four-Channel Standard DMA Controller
• Three 32-Bit Timers
• Watchdog Timer
• CMOS-Level 32.768kHz RTC Output
Ordering Information appears at end of data sheet.
Arm and Cortex are registered trademarks of Arm Limited (or
its subsidiaries) in the US and/or elsewhere.
19-100236; Rev 8; 9/19
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Simplified Block Diagram
MAX32660
HFIO UP TO 96MHz
32.768kHz
80kHz
HOST
ARM CORTEX-M4
PROCESSOR
WITH FPU CPU
NVIC
32-BIT TIMER
RSTN
POR,
BROWNOUT
MONITOR,
SUPPLY VOLTAGE
MONITORS
FLASH
256KB
SRAM
96KB
VCORE
VDD
REGULATOR/
POWER CONTROL
VSS
16KB CACHE
STANDARD DMA
WATCHDOG TIMER
BUS MATRIX – AHB, APB, IBUS, DBUS…
MEMORY
2 × SPI MASTER/
SLAVE
I2S SLAVE
2 × I2C MASTER/
SLAVE
2 × UART
GPIO AND
SHARED PAD
FUNCTIONS
TIMER
SPI
I2C
UART
I2S
32kHz OUTPUT
GPIO
/ALTERNATE
FUNCTION
UP TO 14
EXTERNAL
INTERRUPTS
SERIAL WIRE DEBUG
(SWD)
2 × 32 BIT TIMER
32KIN
32KOUT
RTC
www.maximintegrated.com
Maxim Integrated │ 2
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Absolute Maximum Ratings
(All voltages with respect to VSS, unless otherwise noted.)
VCORE.................................................................-0.3V to +1.21V
VDD......................................................................-0.3V to +3.63V
32KIN, 32KOUT...........................................-0.3V to VDD + 0.3V
RSTN, GPIO.................................................-0.3V to VDD + 0.3V
Total Current into All GPIO Combined (sink)....................100mA
VSS....................................................................................100mA
Output Current (sink) by Any GPIO Pin..............................25mA
Output Current (source) by Any GPIO Pin.........................-25mA
Continuous Package Power Dissipation
20 TQFN-EP (multilayer board) TA = +70°C
(derate 30.3mW/°C above +70°C)..........................2424.2mW
Continuous Package Power Dissipation
24 TQFN-EP (multilayer board) TA = +70°C
(derate 16.3mW/°C above +70°C).............................1305mW
Operating Temperature Range.......................... -40°C to +105°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
16 WLP
Package Code
W161K1+1
Outline Number
21-100241
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
66.34 °C/W
Junction to Case (θJC)
N/A
20 TQFN-EP
Package Code
T2044+5C
Outline Number
21-0139
Land Pattern Number
90-0429
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
48°C/W
Junction to Case (θJC)
2°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
33°C/W
Junction to Case (θJC)
2°C/W
24 TQFN-EP
Package Code
T2433+2C
Outline Number
21-100264
Land Pattern Number
90-100089
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
61.3°C/W
Junction to Case (θJC)
2.2°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 3
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER SUPPLIES/BOTH SINGLE SUPPLY OPERATION AND DUAL SUPPLY OPERATION
Supply Voltage
Supply Voltage, Core
VDD
VCORE
Dual-supply
operation
1.71
1.8
3.63
0.855
0.9
0.945
OVR = [01]
0.95
1.0
1.05
Default OVR = [10]
1.045
1.1
1.155
OVR = [00]
Single-supply operation
Power-Fail Reset Voltage
VRST
Power-On Reset Voltage
VPOR
V
Not used
Monitors VDD
1.63
1.71
Monitors VCORE during dual-supply
operation
0.80
0.845
Monitors VDD
1.4
Monitors VCORE during dual supply
operation
0.65
V
V
Sleep Mode Resume Time
tSLP_ON
0.57
μs
Deep Sleep Mode Resume
Time
tDSL_ON
150
μs
Backup Mode Resume
Time
tBKU_ON
150
μs
POWER SUPPLIES/SINGLE SUPPLY OPERATION (VDD ONLY)
VDD Dynamic Current, Active Mode
VDD Fixed Current, Active
Mode
www.maximintegrated.com
IDD_DACT
IDD_FACT
HFIO enabled,
total current into
VDD pin, CPU
in Active mode,
inputs tied to
VSS or VDD,
outputs source/
sink 0mA
HFIO enabled,
total current
into VDD pin,
CPU in Active
mode 0MHz
execution,
inputs tied to
VSS or VDD,
outputs source/
sink 0mA
OVR = [10], Internal
regulator set to 1.1V,
fSYS_CLK(MAX) = 96MHz
85
OVR = [01], Internal
regulator set to 1.0V,
fSYS_CLK(MAX) = 48MHz
74
OVR = [00], Internal
regulator set to 0.9V,
fSYS_CLK(MAX) = 24MHz
50
OVR = [10], Internal
regulator set to 1.1V,
fSYS_CLK(MAX) = 96MHz
488
OVR = [01], Internal
regulator set to 1.0V,
fSYS_CLK(MAX) = 48MHz
394
OVR = [00], Internal
regulator set to 0.9V,
fSYS_CLK(MAX) = 24MHz
324
μA/MHz
μA
Maxim Integrated │ 4
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
VDD Dynamic Current,
Sleep Mode
VDD Fixed Current, Sleep
Mode
VDD Fixed Current, Deep
Sleep Mode
VDD Fixed Current, Backup
Mode
SYMBOL
IDD_DSLP
IDD_FSLP
IDD_FDSL
IDD_FBKU
CONDITIONS
HFIO enabled,
total current
into VDD pin,
CPU in Sleep
mode, standard
DMA with two
channels active
HFIO enabled,
total current into
VDD pin, CPU
in Sleep mode,
inputs tied to
VSS or VDD,
outputs source/
sink 0mA
MIN
TYP
OVR = [10], Internal
regulator set to 1.1V,
fSYS_CLK(MAX) = 96MHz
30.3
OVR = [01], Internal
regulator set to 1.0V,
fSYS_CLK(MAX) = 48MHz
27
OVR = [00], Internal
regulator set to 0.9V,
fSYS_CLK(MAX) = 24MHz
24
OVR = [10], Internal
regulator set to 1.1V,
fSYS_CLK(MAX) = 96MHz
485
OVR = [01], Internal
regulator set to 1.0V,
fSYS_CLK(MAX) = 48MHz
391
OVR = [00], Internal
regulator set to 0.9V,
fSYS_CLK(MAX) = 24MHz
321
Standby state with full data retention and
96kB SRAM retained
4.2
0KB SRAM retained with RTC enabled;
VDD=1.8V
0.53
16KB SRAM retained with RTC enabled;
VDD=1.8V
0.99
32KB SRAM retained with RTC enabled;
VDD=1.8V
1.20
64KB SRAM retained with RTC enabled;
VDD=1.8V
1.64
96KB SRAM retained with RTC enabled;
VDD=1.8V
1.94
MAX
UNITS
μA/MHz
μA
μA
μA
POWER SUPPLIES / DUAL SUPPLY OPERATION (VDD AND VCORE)
VCORE Dynamic Current,
Active Mode
Total current into VCORE pin, HFIO
enabled, fSYS_CLK(MAX) = 96MHz, OVR =
ICORE_DACT [10], executing code from cache memory,
CPU in Active mode, inputs tied to VSS or
VDD,outputs source/sink 0mA
85
μA/MHz
VCORE Fixed Current, Active Mode
HFIO enabled, OVR = [10], total current
into VCORE pin, CPU in Active mode 0MHz
ICORE_FACT
execution, inputs tied to VSS or VDD, outputs
source/sink 0mA
403
μA
www.maximintegrated.com
Maxim Integrated │ 5
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
VDD Dynamic Current, Active Mode
VDD Fixed Current, Active
Mode
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IDD_DACT
HFIO enabled, OVR = [10], fSYS_CLK(MAX) =
96MHz, total current into VDD pin, executing
code from cache memory, CPU in Active
mode, inputs tied to VSS or VDD, outputs
source/sink 0mA
0.40
μA/MHz
IDD_FACT
HFIO enabled, OVR = [10], total current
into VDD pin, CPU in Active mode 0MHz
execution, inputs tied to VSS or VDD, outputs
source/sink 0mA
84.8
μA
27.7
μA/MHz
HFIO enabled, OVR [10], total current into
VCORE pin, CPU in Sleep mode, standard
DMA with two channels active
270.3
μA
VCORE Dynamic Current,
Sleep Mode
HFIO enabled, OVR = [10], total current into
ICORE_DSLP VCORE pin, CPU in Sleep mode, standard
DMA with two channels active
VCORE Fixed Current,
Sleep Mode
ICORE_FSLP
VDD Dynamic Current,
Sleep Mode
IDD_DSLP
HFIO enabled, OVR = [10], total current into
VDD pin, CPU in Sleep mode, standard DMA
with two channels active
0.20
μA/MHz
VDD Fixed Current, Sleep
Mode
IDD_FSLP
HFIO enabled, OVR = [10], total current into
VDD pin, CPU in Sleep mode, standard DMA
with two channels active
65
μA
5.7
μA
4.2
μA
5
μA
VCORE Fixed Current,
Deep-Sleep Mode
VDD Fixed Current, Deep
Sleep Mode
VCORE Fixed Current,
Backup Mode
VDD Fixed Current, Backup
Mode
www.maximintegrated.com
ICORE_FDSL VDD = 1.8V; VCORE=1.1V
IDD_FDSL
ICORE_FBKU
IDD_FBKU
VDD = 1.8V, VCORE=1.1V
VDD = 1.8V; VCORE = 1.1V, 96KB SRAM
retained
0KB SRAM retained with RTC enabled; VDD
= 1.8V; VCORE = 0V or unbiased
0.53
16KB SRAM retained with RTC enabled;
VDD = 1.8V; VCORE = 0V or unbiased
0.99
32KB SRAM retained with RTC enabled;
VDD = 1.8V; VCORE = 0V or unbiased
1.20
64KB SRAM retained with RTC enabled;
VDD = 1.8V; VCORE = 0V or unbiased
1.64
96KB SRAM retained with RTC enabled;
VDD = 1.8V; VCORE = 0V or unbiased
1.94
μA
Maxim Integrated │ 6
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 ×
VDD
V
GENERAL-PURPOSE I/O
Input Low Voltage for All
GPIO, RSTN
VIL_GPIO
Pin configured as GPIO
Input High Voltage for All
GPIO, RSTN
VIH_GPIO
Pin configured as GPIO
Output Low Voltage for All
GPIO Except P0.2, P0.3,
P0.8, and P0.9
Output Low Voltage for
GPIO P0.2, P0.3, P0.8,
P0.9
Output High Voltage for All
GPIO Except P0.2, P0.3,
P0.8, and P0.9
VOL_GPIO
VOL_I2C
VOH_GPIO
Output High Voltage for
GPIO P0.2, P0.3, P0.8,
P0.9
VOH_I2C
Combined IOL, All GPIO
IOL_TOTAL
Combined IOH, All GPIO
IOH_TOTAL
Input Hysteresis (Schmitt)
Input/Output Pin
Capacitance for All Pins
0.7 × VDD
V
VDD = 1.71V, IOL = 1mA, DS[1:0] = 00
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 2mA, DS[1:0] = 10
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 4mA, DS[1:0] = 01
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 6mA, DS[1:0] = 11
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 2mA, DS = 0 (Note 1)
0.2
0.4
VDD = 1.71V, IOL = 10mA, DS = 1 (Note 1)
0.2
0.4
V
VDD = 1.71V, IOH = 1mA, DS[1:0] = 00
(Note 1)
VDD - 0.4
VDD = 1.71V, IOH = 2mA, DS[1:0] = 10
(Note 1)
VDD - 0.4
VDD = 1.71V, IOH = 4mA, DS[1:0] = 01
(Note 1)
VDD - 0.4
VDD = 1.71V, IOH = 6mA, DS[1:0] = 11
(Note 1)
VDD - 0.4
VDD = 1.71V, IOH = 2mA, DS = 0 (Note 1)
VDD - 0.4
VDD = 1.71V, IOH = 10mA, DS = 1 (Note 1)
VDD - 0.4
V
V
V
32
-32
mA
mA
VIHYS
300
mV
CIO
4
pF
Input Leakage Current Low
IIL
VIN = 0V, internal pullup disabled
-500
+500
nA
Input Leakage Current
High
IIH
VIN = 3.6V, internal pulldown disabled
-500
+500
nA
Input Pullup Resistor to
RSTN
RPU_VDD
www.maximintegrated.com
Pullup to VDD = 1.62V
22
Pullup to VDD = 3.63V
10.5
kΩ
Maxim Integrated │ 7
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
Input Pullup Resistor for
All GPIO
Input Pulldown Resistor for
All GPIO
SYMBOL
RPU
RPD
CONDITIONS
MIN
TYP
Pin configured as GPIO, pullup to VDD =
1.62V
22
Pin configured as GPIO, pullup to VDD =
3.63V
10.5
MAX
UNITS
kΩ
Pin configured as GPIO, pulldown to VSS,
VDD = 1.62V
20
Pin configured as GPIO, pulldown to VSS,
VDD = 3.63V
8.8
kΩ
CLOCKS
System Clock Frequency
System Clock Period
fSYS_CLK
fHFIO
Nanoring Oscillator
Frequency
fNANO
RTC Input Frequency
f32KIN
RTC Power-Up Time
IRTC
96
1/fSYS_
tSYS_CLK
High-Frequency Internal
Oscillator (HFIO)
RTC Operating Current
24
μs
CLK
Default OVR = [10]
93.5
32.768kHz watch crystal, CL = 6pF, ESR <
90kΩ, C0 < 2pF
All power modes, RTC enabled
tRTC_ ON
96
MHz
98.5
MHz
80
kHz
32.768
kHz
0.45
μA
250
ms
FLASH MEMORY
Flash Erase Time
Flash Programming Time
Per Word
tM_ERASE
Mass erase
30
tP_ERASE
Page erase
30
32-bit programming mode, fFLC_CLK = 1MHz
60
tPROG
Flash Endurance
Data Retention
tRET
TA = +85°C
ms
μs
10
kcycles
10
years
Note 1: When using a GPIO bias voltage of 2.97V, the drive current capability of the GPIO is 2x that of its drive strength when using
a GPIO bias voltage of 1.62V.
www.maximintegrated.com
Maxim Integrated │ 8
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
VBAT
1.71V TO 3.63V
VDD
1µF
LiON
2.7 to 5.5V
MAX32660
POWER
MANAGEMENT
0.855V TO 1.155V
VCORE
1µF
VSS
DUAL SUPPLY OPERATION
VBAT
1.71V TO 3.63V
STANDARD
CELL
VDD
1µF
MAX32660
VCORE
1µF
VSS
SINGLE SUPPY OPERATION
Figure 1. Power Supply Operational Modes
www.maximintegrated.com
Maxim Integrated │ 9
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics—SPI
(TIming specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
48
MHz
MASTER MODE
SPI Master Operating
Frequency
fMCK
fSYS_CLK = 96MHz,
fMCK(MAX) = fSYS_CLK/2
SPI Master SCK Period
tMCK
SCK Output Pulse-Width
High/Low
tMCH, tMCL
tMCK/2
ns
MOSI Output Hold Time
After SCK Sample Edge
tMOH
tMCK/2
ns
MOSI Output Valid to
Sample Edge
tMOV
tMCK/2
ns
MISO Input Valid to SCK
Sample Edge Setup
tMIS
5
ns
MISO Input to SCK
Sample Edge Hold
tMIH
tMCK/2
ns
1/fMCK
ns
SLAVE MODE
SPI Slave Operating
Frequency
fSCK
SPI Slave SCK Period
tSCK
1/fSCK
SCK Input Pulse-Width
High/Low
tSCH, tSCL
tSCK/2
SSx Active to First Shift
Edge
tSSE
10
ns
MOSI Input to SCK Sample
Edge Rise/Fall Setup
tSIS
5
ns
MOSI Input from SCK
Sample Edge Transition
Hold
tSIH
1
ns
MISO Output Valid After
SCLK Shift Edge Transition
tSOV
5
ns
SCK Inactive to SSx Inactive
tSSD
10
ns
SSx Inactive Time
tSSH
1/fSCK
μs
MISO Hold Time After SSx
Deassertion
tSLH
10
ns
www.maximintegrated.com
48
MHz
ns
Maxim Integrated │ 10
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
SHIFT SAMPLE SHIFT SAMPLE
SSx
(SHOWN ACTIVE LOW)
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
SCK
CKPOL/CKPHA
0/0 OR 1/1
tMCH
tMCL
tMOH
MOSI/SDIOx
(OUTPUT)
MSB
tMOV
tMLH
tMIS
MISO/SDIOx
(INPUT)
LSB
MSB-1
tMIH
MSB
MSB-1
LSB
Figure 2. SPI Master Mode Timing Diagram
SSx
(SHOWN ACTIVE LOW)
SCK
CKPOL/CKPHA
0/1 OR 1/0
tSSE
SHIFT SAMPLE SHIFT SAMPLE
tSSH
tSCH
SCK
CKPOL/CKPHA
0/0 OR 1/1
MOSI/SDIOx
(INPUT)
tSSD
tSCK
tSCL
tSIS
MSB
tSIH
MSB-1
LSB
tSOV
MISO/SDIOx
(OUTPUT)
MSB
MSB-1
tSLH
LSB
Figure 3. SPI Slave Mode Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 11
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics—I2C
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STANDARD MODE
Output Fall Time
tOF
Standard mode, from VOL_I2C(MIN) to
VOL_I2C(MAX)
150
ns
SCL Clock Frequency
fSCL
0
Low Period SCL Clock
tLOW
4.7
100
kHz
μs
High Time SCL Clock
tHIGH
4.0
μs
Setup Time for Repeated
Start Condition
tSU;STA
4.7
μs
Hold Time for Repeated
Start Condition
tHD;STA
4.0
μs
Data Setup Time
tSU;DAT
300
ns
Data Hold Time
tHD;DAT
10
ns
Rise Time for SDA and SCL
tR
800
ns
Fall Time for SDA and SCL
tF
200
ns
Setup Time for a Stop
Condition
tSU;STO
4.0
μs
tBUS
4.7
μs
Data Valid Time
tVD;DAT
3.45
μs
Data Valid Acknowledge
Time
tVD;ACK
3.45
μs
Bus Free Time Between a
Stop and Start Condition
FAST MODE
Output Fall Time
tOF
Pulse Width Suppressed by
Input Filter
tSP
From VOL_I2C(MIN) to VOL_I2C(MAX)
150
ns
75
ns
SCL Clock Frequency
fSCL
0
Low Period SCL Clock
tLOW
1.3
400
kHz
μs
High Time SCL Clock
tHIGH
0.6
μs
Setup Time for Repeated
Start Condition
tSU;STA
0.6
μs
Hold Time for Repeated
Start Condition
tHD;STA
0.6
μs
Data Setup Time
tSU;DAT
125
ns
Data Hold Time
tHD;DAT
10
ns
Rise Time for SDA and SCL
tR
30
ns
Fall Time for SDA and SCL
tF
30
ns
Setup Time for a Stop
Condition
www.maximintegrated.com
tSU;STO
0.6
μs
Maxim Integrated │ 12
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics—I2C (continued)
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
Bus Free Time Between a
Stop and Start Condition
CONDITIONS
MIN
TYP
MAX
UNITS
tBUS
1.3
μs
Data Valid Time
tVD;DAT
0.9
μs
Data Valid Acknowledge
Time
tVD;ACK
0.9
μs
FAST MODE PLUS
Output Fall Time
tOF
Pulse Width Suppressed by
Input Filter
tSP
SCL Clock Frequency
fSCL
From VOL_I2C(MIN) to VOL_I2C(MAX)
80
ns
75
ns
0
1000
kHz
Low Period SCL Clock
tLOW
0.5
μs
High Time SCL Clock
tHIGH
0.26
μs
Setup Time for Repeated
Start Condition
tSU;STA
0.26
μs
Hold Time for Repeated
Start Condition
tHD;STA
0.26
μs
Data Setup Time
tSU;DAT
50
ns
Data Hold Time
tHD;DAT
10
ns
Rise Time for SDA and SCL
tR
50
ns
Fall Time for SDA and SCL
tF
30
ns
Setup Time for a Stop
Condition
tSU;STO
0.26
μs
tBUS
0.5
μs
Data Valid Time
tVD;DAT
0.45
μs
Data Valid Acknowledge
Time
tVD;ACK
0.45
μs
Bus Free Time Between a
Stop and Start Condition
STOP
START
REPEAT
START
START
tBUS
SDA
tOF
tR
tSU;DAT
tSU;STO
tSP
tSU;STA
tHIGH
SCL
tHD;STA
tHD;DAT
tVD;DAT
tVD;ACK
tLOW
Figure 4. I2C Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 13
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Electrical Characteristics—I2S Slave
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
Bit Clock Frequency
BCLK High Time
SYMBOL
fBCLK
CONDITIONS
MIN
TYP
96kHz LRCLK frequency
3.072
tWBCLKH
BCLK Low Time
LRCLK Setup Time
MAX
UNITS
MHz
0.5
1/fBCLK
0.5
1/fBCLK
tLRCLK_BLCK
25
ns
Delay Time, BCLK to SD
(Output) Valid
tBCLK_SDO
12
ns
Setup Time for SD (Input)
tSU_SDI
6
ns
Hold Time SD (Input)
tHD_SDI
3
ns
tBLK
tWBCLKH tWBCLKL
BCLK
tLRCLK_BCLK
LRCLK
tBCLK_SDO
SD
(output)
LSB
MSB
tSU_SDI
SD
(input)
LSB
WORD N-1 RIGHT CHANNEL
MSB
WORD N LEFT CHANNEL
LSB
MSB
LSB
MSB
tHD_SDI
WORD N RIGHT CHANNEL
CONDITIONS: I2S_LJ = 0; I2S_MONO = 0;
CPOL = 0; CPHA = 0
Figure 5. I2S Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 14
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
3
4
32KOUT
32KIN
VDD
VCORE
A
VSS
P0.9
P0.8
P0.0
P0.1
P0.6
P0.7
15
14
13
12
11
P0.6 16
10
P0.5 17
B
RSTN
P0.9
2
P0.8
1
+
P0.11
MAX32660
P0.10
TOP VIEW
TOP VIEW
P0.7
Pin Configurations
MAX32660
P0.4 18
P0.3 19
P0.2 20
16 WLP
1.6mm x 1.6mm
P0.4
P0.5
22
21
20
4
P0.12
5
RSTN
6
MAX32660
EP*
VSS
7
8
9
10
11
12
VDD
P0.13
VCORE
3
VSS
NC
32KIN
2
3
4
5
VDD
8
32KIN
7
32KOUT
6
VSS
20 TQFN-EP
4mm x 4mm
P0.6
VDD
23
+
2
9
19
P0.6
18
P0.7
17
P0.10
16
P0.11
15
NC
14
P0.8
13
P0.9
P0.9
P0.3
P0.1
P0.0
VSS
24
1
P0.1
32KOUT
TOP VIEW
P0.2
*EP = EXPOSED PAD.
1
RSTN
P0.5
P0.12
P0.4
P0.13
P0.3
P0.0
P0.2
EP*
+
D
P0.1
C
VCORE
24 TQFN-EP
3mm x 3mm
*EP = EXPOSED PAD
Pin Description
PIN
16 WLP
20
TQFNEP
24
TQFNEP
NAME
FUNCTION
POWER
A3
9
www.maximintegrated.com
11, 22
VDD
Digital Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. The device can operate soley from this
one power supply pin without the need to connect VCORE by utilizing the internal
VCORE regulator. The internal VCORE regulator automatically operates if the presence of a voltage on the VCORE pin is not detected. This provides single supply
battery operation capability.
Maxim Integrated │ 15
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Pin Description (continued)
PIN
16 WLP
20
TQFNEP
24
TQFNEP
NAME
FUNCTION
Core Supply Voltage. This pin provides dual supply operation to support PMICbased
systems and should be left open-circuit for single supply operation. This pin must
always
be bypassed to VSS with a 1.0μF capacitor as close as possible to the package
regardless of the supply mode of operation.
A4
10
12
VCORE
B2
6
7, 10
VSS
Digital Ground
—
—
—
EP
Exposed Pad (TQFN only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
A2
8
9
32KIN
A1
7
8
32KOUT
CLOCK
32.768kHz Crystal Oscillator Input. Connect a 6pF 32.768kHz crystal between
32KIN and 32KOUT for RTC operation. Optionally, an external clock source can be
driven on 32KIN if the 32KOUT pin is left unconnected.
32.768kHz Crystal Oscillator Output
RESET
B1
5
6
RSTN
Hardware Power Reset (Active-Low) Input. The device remains in reset while this
pin is in its active state. When the pin transitions to its inactive state, the device
performs a POR reset (resetting all logic on all supplies except for real-time clock
circuitry) and begins execution. This pin is internally connected with an internal
pullup to the VDD supply as indicated in the Electrical Characteristics table. This pin
should be left unconnected if the system design does not provide a reset signal to
the device.
GENERAL-PURPOSE I/O (See Table 3 and Table 4 for pin mapping.)
C1
2
2
P0.0
C2
1
1
P0.1
D1
20
24
P0.2
D2
19
23
P0.3
D3
18
21
P0.4
D4
17
20
P0.5
C3
16
19
P0.6
C4
15
18
P0.7
B4
12
14
P0.8
B3
11
13
P0.9
—
14
17
P0.10
—
13
16
P0.11
—
4
5
P0.12
—
3
4
P0.13
www.maximintegrated.com
General-Purpose I/O. Most port pins have multiple special functions. See Table 3
and Table 4 for details.
Maxim Integrated │ 16
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Detailed Description
Memory
The MAX32660 is an ultra-low power, cost-effective,
highly-integrated microcontroller designed for batterypowered devices and wireless sensors. It combines a
flexible and versatile power management unit with the
powerful Arm Cortex-M4 processor with FPU. The device
enables designs with complex sensor processing without
compromising battery life. It also offers legacy designs an
easy and cost optimal upgrade path from 8- or 16-bit microcontrollers. The device integrates up to 256KB of flash
memory and 96KB of RAM to accommodate application
and sensor code.
The device features four powerful and flexible power
modes. It can operate from a single- or dual-supply battery
voltage, typically provided by a PMIC. The I2C port supports
standard, fast, fast-plus, and high-speed modes, operating
up to 3400kbps. The SPI ports can run up to 48MHz in
both master and slave mode, and the UARTs can run up to
4000kbaud. Three general-purpose 32-bit timers, a watchdog timer, and a real-time clock are also provided. An I2S
interface provides audio streaming to a codec.
Internal Flash Memory
256KB of internal flash memory provides nonvolatile
storage of program and data memory.
Internal SRAM
The internal 96KB SRAM provides low-power retention of
application information in all power modes except shutdown. The SRAM can be divided into granular banks that
create a flexible SRAM retention architecture. This data
retention feature is optional, and is configurable. This
granularity allows the application to minimize its power
consumption by only retaining the most essential data.
Clocking Scheme
The high-frequency internal oscillator (HFIO) operates at
a nominal frequency of 96MHz.
Optionally, two other oscillators can be selected depending
upon power needs:
●● 80kHz nano-ring oscillator
●● 32.768kHz oscillator (external crystal required)
This clock is the primary clock source for the digital logic
and peripherals.
An external 32.768kHz timebase is required when using
the RTC.
RTC
CALIBRATION
OUTPUT
32KCAL
XTAL DRIVER OR
EXTERNAL CLOCK
ALWAYS-ON DOMAIN
32KIN
RTC
OSC
CKT
32kHz
CRYSTAL
4kHz
REAL-TIME CLOCK
32.768kHz
NANO-RING
~80kHz
32KOUT
POWER SEQUENCER
GCR_CLKCN.CLKSEL
HFIO
HIGHFREQUENCY
INTERNAL
OSCILLATOR
PRESCALER
CPU
÷2
PERIPHERALS
Figure 6. System Clocking Diagram
www.maximintegrated.com
Maxim Integrated │ 17
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
General-Purpose I/O and Special Function Pins
Most general-purpose I/O (GPIO) pins share both a
firmware-controlled I/O function and one or more special
function signals associated with peripheral modules. Pins
can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function
usually supersedes its use as a firmware-controlled I/O.
Though this multiplexing between peripheral and GPIO
functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are
identical whether the pin is configured as an I/O or special
function, except where explicitly noted in the Electrical
Characteristics tables.
In GPIO mode, each pin of a port has an interrupt function
that can be independently enabled, and configured as a
level- or edge-sensitive interrupt. All GPIOs share the
same interrupt vector. Some packages do not have all of
the GPIOs available.
When configured as GPIOs, the following features are
provided. These features can be independently enabled
or disabled on a per-pin basis.
●● Configurable as input, output, bidirectional, or highimpedance
●● Optional internal pullup resistor or internal pulldown
resistor when configured as input
●● Exit from low-power modes on rising or falling edge
●● Selectable standard- or high-drive modes
The MAX32660 provides up to 14 GPIOs for the 20-pin
TQFN and up to 10 GPIOs for the 16-bump WLP.
Standard DMA Controller
The standard DMA (direct memory access) controller provides a means to off-load the CPU for memory/peripheral
data transfer leading to a more power-efficient system. It
allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals.
The transfers are done without using CPU resources. The
following transfer modes are supported:
●● 4 channel
●● Peripheral to data memory
●● Data memory to peripheral
●● Data memory to data memory
●● Event support
All DMA transactions consist of an AHB burst read into the
DMA FIFO followed immediately by an AHB burst write
from the FIFO.
www.maximintegrated.com
Power Management
Power Management Unit
The power management unit (PMU) provides high-performance operation while minimizing power consumption. It
exercises intelligent, precise control of power distribution
to the CPU and peripheral circuitry.
The PMU provides the following features:
●● User-configurable system clock
●● Automatic enabling and disabling of crystal oscillators
based on power mode
●● Multiple clock domains
●● Fast wake-up of powered-down peripherals when
activity detected
Active Mode
In this mode, the CPU is executing application code
and all digital and analog peripherals are available on
demand. Dynamic clocking disables peripherals not in
use, providing the optimal mix of high-performance and
low-power consumption.
Sleep Mode
This mode allows for low-power consumption operation.
The CPU is asleep, peripherals are on and the standard
DMA block is available. The GPIO or any active peripheral
can be configured to interrupt and cause transition to the
Active mode.
Deep-Sleep Mode
This mode corresponds to the Arm Cortex-M4 processor
with FPU Deep-sleep mode. In this mode, the register settings and all volatile memory is preserved. The GPIO pins
retain their state in this mode. The high-speed oscillator
that generates the 96MHz system clock can be shut down
to provide additional power savings over Sleep mode.
Multiple system events can cause the device to wake
from Deep-sleep mode and return to the Active mode,
including:
●● RTC alarm
●● Enabled GPIO interrupt
Backup Mode
This mode places the CPU in a static, low-power state.
In Backup mode, all of the SRAM can be retained. Data
retention in this mode is maintained by the VDD supply
only. SRAM retention can be 0KB, 16KB, 32KB, 64KB,
or full 96KB. Backup mode supports the same wake-up
sources as Deep-sleep mode.
Maxim Integrated │ 18
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Real-Time Clock
A real-time clock (RTC) keeps the time of day in absolute
seconds. The 32-bit seconds register can count up to
approximately 136 years and be translated to calendar
format by application software.
The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days.
When configured for long intervals, the time-of-day alarm
can be used as a power-saving timer, allowing the device
to remain in an extremely low-power mode, but still awaken
periodically to perform assigned tasks. A second independent 32-bit 1/4096 subsecond alarm can be programmed
between 244μs and 12 days. Both can be configured as
recurring alarms. When enabled, either alarm can cause an
interrupt or wake the device from most low power modes.
The time base is generated by a 32.768kHz crystal or an
external clock source that must meet the electrical/timing
requirements in the Electrical Characteristics table.
An RTC calibration feature provides the ability for user-software to compensate for minor variations in the RTC oscillator, crystal, temperature, and
board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the RTC.
External hardware can measure the frequency and
adjust the RTC frequency in increments of ±127ppm
with 1ppm resolution. Under most circumstances,
the oscillator does not require any calibration.
Watchdog Timer
Microcontrollers are often used in harsh environments
where electrical noise and electromagnetic interference
(EMI) are abundant. Without proper safeguards, these
hazards can disturb device operation and corrupt program
execution. One of the most effective countermeasures is
the watchdog timer (WDT), which detects runaway code
or system unresponsiveness.
APB
BUS
TIMER CONTROL
REGISTER
32-BIT COMPARE
REGISTER
APB
CLOCK
The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically reset by the application software. Failure to reset the
WDT within the user-configurable timeout period indicates
that the application software is not operating correctly and
results in a WDT timeout. A WDT timeout can trigger an
interrupt, system reset, or both. Either response forces
the instruction pointer to a known good location before
resuming instruction execution.
The MAX32660 provides one instance of the watchdog
timer (WDT0).
Programmable Timers
General-purpose, 32-bit timers provide timing, capture/
compare, or generation of pulse-width modulated (PWM)
signals with minimal software interaction. Each of the
32-bit timers can also be split into two 16-bit timers.
The timer provides the following features:
●● 32-bit up/down autoreload
●● Programmable prescaler
●● PWM output generation
●● Capture, compare, and capture/compare capability
●● External pin multiplexed with GPIO for timer input,
clock gating, or capture
●● Timer output pin
●● Configurable as 2 × 16-bit general-purpose timers
●● Timer interrupt
The MAX32660 provides three 32-bit timers: TIMER0,
TIMER1, and TIMER2.
I/O functionality is supported for TIMER0 only (TIMER_TMR0
pin). Note that the function of a port can be multiplexed with
other functions on the GPIO pins, so it might not be possible
to use all the ports depending on the device configuration.
32-BIT TIMER BLOCK
COMPARE
INTERRUPT
PWM AND TIMER
OUTPUT
CONTROL
32-BIT TIMER
(WITH PRESCALER)
32-BIT
PWM/COMPARE
TIME INTERRUPT
REGISTER
COMPARE
TIMER
INTERRUPT
TIMER
OUTPUT
TIMER
INPUT
Figure 7. 32-Bit Timer
www.maximintegrated.com
Maxim Integrated │ 19
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Serial Peripherals
I2C Interface
The I2C interface is a bidirectional, two-wire serial bus that
provides a medium-speed communications network. It can
operate as a one-to-one, one-to-many or many-to-many
communications medium. These engines support standard-mode, fast-mode, fast-mode plus and high-speed
mode I2C speeds. It provides the following features:
●● Master or slave mode operation
• Supports up to 4 different slave addresses in slave
mode
●● Supports standard 7-bit addressing or 10-bit addressing
●● RESTART condition
●● Interactive receive mode
●● Tx FIFO preloading
●● Support for clock stretching to allow slower slave
devices to operate on higher speed busses
●● Multiple transfer rates
• Standard mode: 100kbps
• Fast mode: 400kbps
• Fast mode plus: 1000kbps
• High-speed mode: 3400kbps
●● Internal filter to reject noise spikes
●● Receiver FIFO depth of 8 bytes
●● Transmitter FIFO depth of 8 bytes
The MAX32660 provides two instances of the I2C
peripheral (I2C0 and I2C1).
www.maximintegrated.com
Serial Peripheral Interface
The serial peripheral interface (SPI) is a highly configurable, flexible, and efficient synchronous interface
between multiple SPI devices on a single bus. The bus
uses a single clock signal and multiple data signals,
and one or more slave select lines to address only the
intended target device. The SPI operates independently
and requires minimal processor overhead.
The provided SPI peripherals can operate in either slave
or master mode and provide the following features:
●● SPI modes 0, 1, 2, 3 for single-bit communication
●● 3- or 4-wire mode for single-bit slave device
communication
●● Full-duplex operation in single-bit, 4-wire mode
●● Multimaster mode fault detection
●● Programmable interface timing
●● Programmable SCK frequency and duty cycle
●● 32-byte transmit and receive FIFOs
●● Slave select assertion and deassertion timing with
respect to leading/trailing SCK edge
The MAX32660 provides two instances of this SPI
peripheral (SPI0, SPI1) with the following specifications
(Table 1):
Table 1. SPI Configuration Options
SLAVE
SELECT
LINES
MAXIMUM
MAXIMUM
FREQUENCY FREQUENCY
(MASTER
(SLAVE
MODE) (MHz) MODE) (MHz)
INSTANCE
DATA
SPI0
3 wire,
4 wire
1
1
48
48
SPI1
3 wire,
4 wire
1
1
48
48
20
16
TQFN WLP
Maxim Integrated │ 20
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
I2S Interface
The I2S interface is a bidirectional, four-wire serial bus
that provides serial communications for codecs and audio
amplifiers compliant with the I2S Bus Specification, June
5, 1996. It provides the following features:
●● Slave mode operation
●● Normal and left-justified data alignment
●● 16-bit audio transfer
●● Wake-up on FIFO status (full/empty/threshold)
●● Interrupts generated for FIFO status
●● Receiver FIFO depth of 32 bytes
●● Transmitter FIFO depth of 32 bytes
The MAX32660 provides one instance of the I2S
peripheral that is multiplexed with the SPI1 peripheral.
UART
The universal asynchronous receiver-transmitter (UART)
interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes
to prevent data overruns. If HFC mode is enabled on a
given port, the system uses two extra pins to implement
the industry standard request to send (RTS) and clear to
send (CTS) flow control signaling. Each UART is individually programmable.
●● 2-wire interface or 4-wire interface with flow control
●● 8-byte send/receive FIFO
●● Full-duplex operation for asynchronous data transfers
●● Interrupts available for frame error, parity error, CTS,
Rx FIFO overrun and FIFO full/partially full conditions
●● Automatic parity and frame error detection
●● Independent baud-rate generator
●● Programmable 9th bit parity support
●● Multidrop support
●● Start/stop bit support
●● Hardware flow control using RTS/CTS
Table 2. UART Configuration Options
FLOW CONTROL
20 TQFP
16 WLP
MAXIMUM BAUD
RATE (KB)
UART0
Yes
Yes
4000
UART1
Yes
No
4000
INSTANCE
Bootloader
The MAX32660 bootloader is a small embedded firmware
that provides the MAX32660 with the ability to update
application code by a host microcontroller. The bootloader can be accessed through the I2C, SPI, or UART
interface. These interfaces provide the data channel
and the control channel for communicating between the
host microcontroller and the MAX32660. The bootloader
application load mode is enabled and disabled by either a
serial command or hardware connectivity. The serial command is interpreted by the application, which configures
the device to enter the bootloader mode. When using the
hardware connectivity option, a single GPIO pin and the
RSTN pin on the MAX32660 can be configured to allow
the MAX32660 to enter the bootloader mode. For detailed
information, refer to the MAX32660 Bootloader User
Guide (UG6471).
Debug and Development Interface (SWD)
The serial wire debug interface is used for code loading
and ICE debug activities. All devices in mass production
have the debugging/development interface enabled.
Additional Documentation and Technical Support
Designers must have the following documents to use all
the features of this device:
●● This data sheet, which contains electrical/timing specifications, package information, and pin descriptions
●● The corresponding revision-specific errata sheet
●● The corresponding user guide, which contains
detailed information and programming guidelines for
core features and peripherals
●● 4000kb maximum baud rate
●● Two DMA channels can be connected (read and
write FIFOs)
●● Programmable word size (5 bits to 8 bits)
The MAX32660 provides two instances of the
UART peripheral (UART0 and UART1) with the
specifications shown in Table 2.
www.maximintegrated.com
Maxim Integrated │ 21
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Applications Information
Table 3. GPIO and Alternate Function Matrix, 16 WLP
GPIO
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
ALTERNATE FUNCTION 3
P0.0
SWDIO**
SPI1_MISO (I2S_SDI)†
UART1_TX**
P0.1
SWDCLK**
SPI1_MOSI (I2S_SDO)†
UART1_RX**
P0.2
I2C1_SCL
SPI1_SCK (I2S_BCLK)†
32KCAL
P0.3
I2C1_SDA
SPI1_SS0 (I2S_LRCLK)†
TMR0
P0.4
SPI0_MISO
UART0_TX
—
P0.5
SPI0_MOSI
UART0_RX
—
P0.6
SPI0_SCK
UART0_CTS
UART1_TX**
P0.7
SPI0_SS0
UART0_RTS
UART1_RX**
P0.8
I2C0_SCL
SWDIO**
—
P0.9
I2C0_SDA
SWDCLK**
—
P0.10*
—
—
—
P0.11*
—
—
—
P0.12*
—
—
—
P0.13*
—
—
—
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†These pins support I2S functionality. Refer to the User Guide for details.
Table 4. GPIO and Alternate Function Matrix, 20 TQFN and 24 TQFN
GPIO
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
ALTERNATE FUNCTION 3
P0.0
SWDIO**
SPI1_MISO (I2S_SDI)†**
UART1_TX**
P0.1
SWDCLK**
SPI1_MOSI (I2S_SDO)†**
UART1_RX**
P0.2
I2C1_SCL
SPI1_SCK (I2S_BCLK)†**
32KCAL
P0.3
I2C1_SDA
SPI1_SS0 (I2S_LRCLK)†**
TMR0
P0.4
SPI0_MISO
UART0_TX
—
P0.5
SPI0_MOSI
UART0_RX
—
P0.6
SPI0A_SCK
UART0_CTS
UART1_TX**
P0.7
SPI0A_SS0
UART0_RTS
UART1_RX**
P0.8
I2C0_SCL
SWDIO**
—
P0.9
I2C0_SDA
SWDCLK**
—
P0.10
SPI1_MISO (I2S_SDI)†**
UART1_TX
—
P0.11
SPI1_MOSI (I2S_SDO)†**
UART1_RX
—
P0.12
SPI1_SCK (I2S_BCLK)†**
UART1_CTS
—
P0.13
SPI1_SS0 (I2S_LRCLK)†**
UART1_RTS
—
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled.
www.maximintegrated.com
Maxim Integrated │ 22
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Typical Application Circuit
VBAT
1.71V TO 3.63V
1µF
STANDARD
CELL
VBAT
4.7kΩ
VDD
RSTN
I2C1_SCL
I2C1_SDA
SPI1_MOSI
SPI1_MISO
SPI1_CLK
SPI1_SS0
4.7kΩ
SWDIO
SWDCLK
P0.8
100nF
10Ω
NOISE
SNUBBER
UART0_TX
UART0_RX
UART0_CTS
UART0_RTS
P0.9
1.0µF
VCORE
VSS
32KIN 32KOUT
32.768kHz, 6pF
www.maximintegrated.com
Maxim Integrated │ 23
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Ordering Information
FLASH (KB)
SRAM (KB)
BOOT
LOADER
MAX32660GWE+
256
96
No
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GWE+T
256
96
No
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GTP+
256
96
No
20 TQFN-EP (4mm x 4mm x 0.75mm, 0.5mm pitch)
MAX32660GTP+T
256
96
No
20 TQFN-EP (4mm x 4mm x 0.75mm, 0.5mm pitch)
MAX32660GTG+
256
96
No
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
MAX32660GTG+T
256
96
No
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
MAX32660GWEBL+
256
96
Yes
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GWEBL+T
256
96
Yes
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GTGBL+
256
96
Yes
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
MAX32660GTGBL+T
256
96
Yes
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.5mm pitch)
MAX32660GWELA+*
128
64
No
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GWELA+T*
128
64
No
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GTGLA+*
128
64
No
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
MAX32660GTGLA+T*
128
64
No
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
MAX32660GWELB+*
64
32
No
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GWELB+T*
64
32
No
16 WLP (1.6mm x 1.6mm x 0.65mm, 0.35mm pitch)
MAX32660GTGLB+*
64
32
No
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
MAX32660GTGLB+T*
64
32
No
24 TQFN-EP (3mm x 3mm x 0.75mm, 0.4mm pitch)
PART
PIN-PACKAGE
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel. Full reel.
*Future product—contact factory for availability.
www.maximintegrated.com
Maxim Integrated │ 24
MAX32660
Tiny, Ultra-Low-Power Arm Cortex-M4 Processor with
FPU-Based Microcontroller (MCU) with 256KB
Flash and 96KB SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
1/18
Initial release
1
4/18
Updated General Description, Applications, Benefits and Features, Absolute Maximum
Ratings, Package Information, Electrical Characteristics table, Pin Configurations, Pin
Descriptions, Table 4 title, Ordering Information, and added Typical Application Circuit
1, 3, 8, 15,
16, 22–24
2
6/18
Updated Simplified Block Diagram, Electrical Characteristics table, Figure 1, Figure 2,
Figure 3, Clocking Scheme section, Figure 6, and Ordering Information table
2, 4–6, 8–10,
11, 17, 24
3
8/18
Updated Ordering Information
4
8/18
Updated Ordering Information
5
10/18
Updated title and General Description
6
12/18
Updated Ordering Information
7
2/19
Updated title, General Description, Pin Configuration, Ordering Information, Additional
Documentation and Technical Support, and added Bootloader section
8
9/19
Updated Benefits and Features, Simplified Block Diagram, Electrical Characteristics
table, Clocking Scheme, Figure 6, Real-Time Clock, UART, Table 4
DESCRIPTION
—
24
24
1–25
24
1–25
1, 2, 4–6, 8, 17,
19, 21, 22
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc. │ 25
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