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MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
General Description
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
±15kV ESD-protected level translators provide the level
shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL,
set the logic levels on either side of the device. A lowvoltage logic signal present on the VL side of the device
appears as a high-voltage logic signal on the VCC side of
the device, and vice-versa. The MAX3374E/MAX3375E/
MAX3376E/MAX3379E and MAX3390E–MAX3393E unidirectional level translators level shift data in one direction (VL → VCC or VCC → VL) on any single data line.
The MAX3372E/MAX3373E and MAX3377E/MAX3378E
bidirectional level translators utilize a transmission-gatebased design (Figure 2) to allow data translation in
either direction (VL ↔ VCC) on any single data line. The
MAX3372E–MAX3379E and MAX3390E–MAX3393E
accept VL from +1.2V to +5.5V and VCC from +1.65V to
+5.5V, making them ideal for data transfer between lowvoltage ASICs/PLDs and higher voltage systems.
All devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family feature a three-state output mode
that reduces supply current to less than 1μA, thermal
shortcircuit protection, and ±15kV ESD protection on the
VCC side for greater protection in applications that route
signals externally. The MAX3372E/MAX3377E operate
at a guaranteed data rate of 230kbps. Slew-rate limiting reduces EMI emissions in all 230kbps devices.
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E operate at a guaranteed data
rate of 8Mbps over the entire specified operating voltage
range. Within specific voltage domains, higher data rates
are possible. (See the Timing Characteristics table.)
The MAX3372E–MAX3376E are dual level shifters available in 3 x 3 UCSP™, 8-pin TDFN, and 8-pin SOT23-8
packages. The MAX3377E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E are quad level shifters available
in 3 x 4 UCSP, 14-pin TDFN, and 14-pin TSSOP packages.
Applications
●●
●●
●●
●●
●●
●●
●●
●●
●●
●●
SPI, MICROWIRE, and I2C Level Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
Cell-Phone Cradles
Portable POS Systems
Portable Communication Devices
Low-Cost Serial Interfaces
Cell Phones
GPS
Telecommunications Equipment
19-2328; Rev 7; 2/20
Features
●● Logic-Level Translators Simplify Design by Enabling
Data Transfer Between Lower and Higher Voltage
Systems
●● Operation Down to +1.2V on VL
●● Guaranteed Data Rate Options
• 230kbps
• 8Mbps (+1.2V ≤ VL ≤ VCC ≤ +5.5V)
• 10Mbps (+1.2V ≤ VL ≤ VCC ≤ +3.3V)
• 16Mbps (+1.8V ≤ VL ≤ VCC ≤ +2.5V and
+2.5V ≤ VL ≤ VCC ≤ +3.3V)
●● Bidirectional Level Translation (MAX3372E/
MAX3373E and MAX3377E/MAX3378E)
●● Low Power Consumption Reduces Thermal
Dissipation
●● Quiescent Current (130µA typ)
●● 1μA Supply Current in Three-State Output Mode
●● Slew-Rate Limiting Lowers EMI
●● Protection Features Increase System Reliability
●● ±15kV ESD Protection on I/O VCC Lines
●● Thermal Short-Circuit Protection
Ordering Information continued at end of data sheet.
Selector Guide appears at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
Pin Configurations
TOP VIEW
+
14 VCC
I/O VL1
1
I/O VL2
2
N.C.
4
11 N.C.
I/O VL3
5
10 VL
I/O VL4
6
9 I/0 VCC3
GND
7
8 I/0 VCC4
13 I/0 VCC1
MAX3377E/
MAX3378E THREE-STATE 3
12 I/0 VCC2
TDFN-14
(3mm x 3mm)
Pin Configurations continued at end of data sheet.
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Absolute Maximum Ratings
(All voltages referenced to GND.)
VCC...........................................................................-0.3V to +6V
I/O VCC_.................................................... -0.3V to (VCC + 0.3V)
I/O VL_.......................................................... -0.3V to (VL + 0.3V)
THREE-STATE............................................. -0.3V to (VL + 0.3V)
Short-Circuit Duration I/O VL, I/O VCC to GND.........Continuous
Short-Circuit Duration I/O VL or I/O VCC to GND
Driven from 40mA Source
(except MAX3372E and MAX3377E).....................Continuous
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 5.6mW/°C above +70°C)........444.4mW
8-Pin TDFN (derate 18.5mW/°C above +70°C).........1482mW
3 x 3 UCSP (derate 4.7mW/°C above +70°C).............379mW
3 x 4 UCSP (derate 6.5mW/°C above +70°C).............520mW
14-Pin TSSOP (derate 9.1mW/°C above +70°C).........727mW
14-Pin TDFN (derate 18.5mW/°C above +70°C).......1482mW
Operating Temperature Range............................ -40°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, I/O VL_ and I/O VCC_ unconnected, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
VL Supply Range
VCC Supply Range
Supply Current from VCC
Supply Current from VL
VCC Three-State Output Mode
Supply Current
VL Three-State Output Mode
Supply Current
Three-State Output Mode
Leakage Current
I/O VL_ and I/O VCC_
VL
1.2
5.5
V
VCC
1.65
5.50
V
IQVCC
130
300
µA
IQVL
16
100
µA
ITHREE-STATE-VCC
TA = +25°C, THREE-STATE = GND
0.03
1
µA
ITHREE-STATE-VL
TA = +25°C, THREE-STATE = GND
0.03
1
µA
ITHREE-STATE-LKG
TA = +25°C, THREE-STATE = GND
0.02
1
µA
TA = +25°C
0.02
1
µA
THREE-STATE Pin Input Leakage
ESD PROTECTION
IEC 1000-4-2 Air-Gap Discharge
I/O VCC (Note 3)
±8
IEC 1000-4-2 Contact Discharge
±8
Human Body Model
±15
kV
LOGIC-LEVEL THRESHOLDS (MAX3372E/MAX3377E)
I/O VL_ Input-Voltage High
VIHL
I/O VL_ Input-Voltage Low
VILL
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VL - 0.2
V
0.15
V
Maxim Integrated │ 2
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Electrical Characteristics (continued)
(VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, I/O VL_ and I/O VCC_ unconnected, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
I/O VCC_ Input-Voltage High
VIHC
I/O VCC_ Input-Voltage Low
VILC
CONDITIONS
MIN
TYP
MAX
VCC - 0.4
V
0.15
I/O VL_ Output-Voltage High
VOHL
I/O VL_ source current = 20µA,
I/O VCC_ > VCC - 0.4V
I/O VL_ Output-Voltage Low
VOLL
I/O VL_ sink current = 20µA,
I/O VCC_ < 0.15V
I/O VCC_ Output-Voltage High
VOHC
I/O VCC_ source current = 20µA,
I/O VL _ > VL - 0.2V
I/O VCC_ Output-Voltage Low
VOLC
I/O VCC_ sink current = 20µA,
I/O VL_ < 0.15V
THREE-STATE Input-Voltage
High
VIL-THREE-STATE
THREE-STATE Input-Voltage
Low
VIL-THREE-STATE
UNITS
0.67 x VL
V
V
0.4
0.67 x VCC
V
V
0.4
VL - 0.2
V
V
0.15
V
LOGIC-LEVEL THRESHOLDS (MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E)
I/O VL_ Input-Voltage High
VIHL
I/O VL_ Input-Voltage Low
VILL
I/O VCC_ Input-Voltage High
VIHC
I/O VCC_ Input-Voltage Low
VILC
VL - 0.2
VCC - 0.4
I/O VL_ Output-Voltage High
VOHL
I/O VL_ Output-Voltage Low
VOLL
I/O VL_ sink current = 1mA,
I/O VCC_ ≤ 0.15V
I/O VCC_ Output-Voltage High
VOHC
I/O VCC_ source current = 20µA,
I/O VL_ ≥ VL - 0.2V
I/O VCC_ Output-Voltage Low
VOLC
I/O VCC_ sink current = 1mA,
I/O VL_ ≤ 0.15V
THREE-STATE Input-Voltage
High
VIH-THREE-STATE
THREE-STATE Input-Voltage
Low
VIL-THREE-STATE
V
V
0.15
I/O VL_ source current = 20µA,
I/O VCC_ ≥ VCC - 0.4V
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V
0.15
0.67 x VL
V
V
0.4
0.67 x VCC
V
V
0.4
VL - 0.2
V
V
0.15
V
Maxim Integrated │ 3
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Timing Characteristics
(VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3372E/MAX3377E (CLOAD = 50pF)
I/O VCC_ Rise Time (Note 4)
tRVCC
1100
ns
I/O VCC_ Fall Time (Note 5)
tFVCC
1000
ns
I/O VL _ Rise Time (Note 4)
tRVL
600
ns
I/O VL _ Fall Time (Note 5)
Propagation Delay
Channel-to-Channel Skew
tFVL
1100
ns
I/OVL-VCC
Driving I/O VL _
1.6
I/OVCC-VL
Driving I/O VCC_
1.6
tSKEW
Maximum Data Rate
Each translator equally loaded
CL = 25pF
µs
500
230
ns
kbps
MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E (CLOAD = 15pF, Driver Output Impedance ≤ 50Ω)
+1.2V ≤ VL ≤ VCC ≤ +5.5V
I/O VCC_ Rise Time (Note 4)
tRVCC
I/O VCC_ Fall Time (Note 5)
tFVCC
I/O VL _ Rise Time (Note 4)
tRVL
I/O VL _ Fall Time (Note 5)
tLFV
I/OVL-VCC
7
25
170
400
6
37
20
50
8
30
Open-drain driving
180
400
3
30
Open-drain driving
30
60
Open-drain driving
Open-drain driving
Driving I/O VL _
Propagation Delay
I/OVCC-VL
Channel-to-Channel Skew
Maximum Data Rate
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tSKEW
Driving I/O VCC_
Each translator
equally loaded
Open-drain driving
Open-drain driving
Open-drain driving
5
30
210
1000
4
30
190
1000
20
Open-drain driving
50
ns
ns
ns
ns
ns
ns
8
Mbps
500
kbps
Maxim Integrated │ 4
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Timing Characteristics (continued)
(VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+1.2V ≤ VL ≤ VCC ≤ +3.3V
I/O VCC_ Rise Time (Note 4)
tRVCC
25
ns
I/O VCC_ Fall Time (Note 5)
tFVCC
30
ns
I/O VL _ Rise Time (Note 4)
tRVL
30
ns
I/O VL _ Fall Time (Note 5)
tFVL
30
ns
Propagation Delay
Channel-to-Channel Skew
I/OVL-VCC
Driving I/O VL _
20
I/OVCC-VL
Driving I/O VCC_
20
Each translator equally loaded
10
tSKEW
Maximum Data Rate
10
ns
ns
Mbps
+2.5V ≤ VL ≤ VCC ≤ +3.3V
I/O VCC_ Rise Time (Note 4)
tRVCC
15
ns
I/O VCC_ Fall Time (Note 5)
tFVCC
15
ns
I/O VL _ Rise Time (Note 4)
tRVL
15
ns
15
ns
I/O VL _ Fall Time (Note 5)
Propagation Delay
Channel-to-Channel Skew
tFVL
I/OVL-VCC
Driving I/O VL _
15
I/OVCC-VL
Driving I/O VCC_
15
tSKEW
Each translator equally loaded
Maximum Data Rate
10
16
ns
ns
Mbps
+1.8V ≤ VL ≤ VCC ≤ +2.5V
I/O VCC_ Rise Time (Note 4)
tRVCC
15
ns
I/O VCC_ Fall Time (Note 5)
tFVCC
15
ns
I/O VL _ Rise Time (Note 4)
tRVL
15
ns
I/O VL _ Fall Time (Note 5)
tFVL
15
ns
Propagation Delay
Channel-to-Channel Skew
Maximum Data Rate
I/OVL-VCC
Driving I/O VL _
15
I/OVCC-VL
Driving I/O VCC_
15
Each translator equally loaded
10
tSKEW
16
ns
ns
Mbps
Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure VL < (VCC + 0.3V). During power-up, VL > (VCC + 0.3V) will not damage the device.
Note 3: To ensure maximum ESD protection, place a 1μF capacitor between VCC and GND. See Applications Circuits.
Note 4: 10% to 90%
Note 5: 90% to 10%
www.maximintegrated.com
Maxim Integrated │ 5
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
300
500kbps, OPEN-DRAIN, CLOAD = 15pF
200
100
0
230kbps, CLOAD = 50pF
8Mbps, CLOAD = 15pF
1.5
1.0
0
1.65 2.20 2.75 3.30 3.85 4.40 4.95 5.50
230kbps, CLOAD = 50pF
300
8Mbps, CLOAD = 15pF
250
500kbps, OPEN-DRAIN, CLOAD = 15pF
200
150
100
230kbps, CLOAD = 50pF
50
0
1.65 2.20 2.75 3.30 3.85 4.40 4.95 5.50
-15
-40
10
35
60
85
VCC (V)
VCC (V)
TEMPERATURE (°C)
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
VL SUPPLY CURRENT vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
600
400
230kbps, CLOAD = 50pF
200
10
35
60
100
0
85
25
40
55
70
85
MAX3372E toc06
8Mbps
1500
500kbps, OPEN-DRAIN
1000
230kbps
500
230kbps
10
2000
0
100
10
25
40
55
70
85
100
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
18
tLH
1500
1000
DATA RATE = 230kbps
30
40
50
14
12
tLH
10
8
tHL
6
60
70
80
CAPACITIVE LOAD (pF)
www.maximintegrated.com
90
100
0
10
15
20
25
30
tLH
200
150
DATA RATE = 500kbps,
OPEN-DRAIN
100
tHL
50
DATA RATE = 8Mbps
2
tHL
20
16
4
500
250
MAX3372E toc09
TEMPERATURE (°C)
2000
0
500kbps, OPEN-DRAIN
RISE/FALL TIME (ns)
2500
-15
-40
150
50
MAX3372E toc07
0
200
SUPPLY CURRENT (µA)
500kbps, OPEN-DRAIN, CLOAD = 15pF
800
8Mbps
250
2500
MAX3372E toc08
1000
8Mbps, CLOAD = 15pF
300
MAX3372E toc05
MAX3372E toc04
1200
350
SUPPLY CURRENT (µA)
1400
SUPPLY CURRENT (µA)
2.0
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
350
0.5
1600
RISE/FALL TIME (ns)
2.5
500kbps, OPEN-DRAIN, CLOAD = 15pF
400
SUPPLY CURRENT (µA)
400
3.0
MAX3372E toc02
MAX3372E toc01
8Mbps, CLOAD = 15pF
RISE/FALL TIME (ns)
SUPPLY CURRENT (µA)
500
3.5
SUPPLY CURRENT (µA)
600
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc03
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
35
40
CAPACITIVE LOAD (pF)
45
50
0
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
Maxim Integrated │ 6
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
400
300
tPLH
200
DATA RATE = 230kbps
100
20
30
40
50
60
70
80
90
15
20
25
30
35
40
45
100
0
50
MAX3372E toc12
DATA RATE = 500kbps,
OPEN-DRAIN
150
tPHL
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +2.5V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +2.5V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
DATA RATE = 230kbps
30
40
tLH
8
6
tHL
4
50
60
70
80
90
0
100
200
DATA RATE = 500kbps,
OPEN-DRAIN
150
100
tHL
50
2
tHL
20
10
tLH
250
RISE/FALL TIME (ns)
tLH
DATA RATE = 8Mbps
12
300
MAX3372E toc14
14
10
15
20
25
30
35
40
45
0
50
MAX3372E toc15
CAPACITIVE LOAD (pF)
500
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc16
tHL
1000
500
DATA RATE = 8Mbps
10
RISE/FALL TIME (ns)
2000
1500
12
8
tLH
6
4
tHL
2
tLH
20
30
40
50
60
70
80
CAPACITIVE LOAD (pF)
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90
100
0
10
15
300
250
20
25
30
35
tLH
200
DATA RATE = 500kbps,
OPEN-DRAIN
150
100
tHL
50
40
CAPACITIVE LOAD (pF)
45
50
MAX3372E toc18
CAPACITIVE LOAD (pF)
DATA RATE = 230kbps
RISE/FALL TIME (ns)
10
200
50
RISE/FALL TIME (ns)
RISE/FALL TIME (ns)
100
1000
0
3
tPLH
250
CAPACITIVE LOAD (pF)
1500
2500
6
300
tPLH
2000
0
tPHL
9
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc17
2500
12
0
MAX3372E toc13
0
MAX3372E toc11
tPHL
500
DATA RATE = 8Mbps
RISE/FALL TIME (ns)
PROPAGATION DELAY (ns)
600
15
PROPAGATION DELAY (ns)
MAX3372E toc10
700
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
PROPAGATION DELAY (ns)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
0
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
Maxim Integrated │ 7
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
tPHL
400
300
200
100
40
50
60
70
80
90
2
tPLH
0
100
200
DATA RATE = 500kbps,
OPEN-DRAIN
150
100
tPHL
50
10
15
20
25
30
35
40
45
0
50
MAX3372E toc21
tPLH
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
tHL
1000
500
30
40
50
60
8
tLH
6
4
tHL
2
tLH
20
DATA RATE = 8Mbps
10
RISE/FALL TIME (ns)
1500
12
70
80
90
100
0
10
CAPACITIVE LOAD (pF)
20
350
30
MAX3373E toc24
CAPACITIVE LOAD (pF)
2000
RISE/FALL TIME (ns)
3
250
CAPACITIVE LOAD (pF)
DATA RATE = 230kbps
0
4
300
RISE/FALl TIME (ns)
2500
30
tPHL
1
tPHL
20
5
300
MAX3372E toc23
0
DATA RATE = 8Mbps
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
PROPAGATION DELAY (ns)
500
6
PROPAGATION DELAY (ns)
DATA RATE = 230kbps
MAX3372E toc22
PROPAGATION DELAY (ns)
600
MAX3372E toc19
700
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc20
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
250
200
tLH
150
DATA RATE = 500kbps,
OPEN-DRAIN
100
tHL
50
40
50
0
10
20
CAPACITIVE LOAD (pF)
30
40
RAIL-TO-RAIL DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 50pF, DATA RATE = 230kbps)
MAX3372E toc26
MAX3372E toc25
RAIL-TO-RAIL DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 15pF, DATA RATE = 8Mbps)
I/O VL_
1V/div
I/O VL_
1V/div
I/O VCC_
2V/div
I/O VCC_
2V/div
1µs/div
www.maximintegrated.com
50
CAPACITIVE LOAD (pF)
200ns/div
Maxim Integrated │ 8
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
OPEN-DRAIN DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 15pF, DATA RATE = 500kbps)
EXITING THREE-STATE OUTPUT MODE
(VCC = +3.3V, VL = +1.8V, CLOAD = 50pF)
MAX3372E toc27
MAX3372E toc28
I/O VL_
2V/div
I/O VCC_
1V/div
1V/div
I/O VL_
I/O VCC_
2V/div
1V/div
THREE-STATE
2µs/div
200ns/div
Pin Description
PIN
3x4
UCSP
14
TSSOP
SOT23-8
3x3
UCSP
8 TDFNEP
14 TDFNEP
NAME
FUNCTION
A1
2
5
C2
6
1
I/O VL1
Input/Output 1. Referenced to VL. (Note 6)
A2
3
4
C3
8
2
I/O VL2
Input/Output 2. Referenced to VL. (Note 6)
A3
4
—
—
—
5
I/O VL3
Input/Output 3. Referenced to VL. (Note 6)
A4
5
—
—
—
6
I/O VL4
Input/Output 4. Referenced to VL. (Note 6)
B1
14
7
A1
4
14
VCC
VCC Input Voltage +1.65V ≤ VCC ≤ +5.5V.
B2
1
3
C1
7
10
VL
Logic Input Voltage +1.2V ≤ VL ≤ (VCC + 0.3V)
Three-State Output Mode Enable. Pull THREE-STATE
low to place device in three-state output mode. I/O VCC_
and I/O VL_ are high impedance in three-state output
mode. Note: Logic referenced to VL (for logic thresholds
see the Electrical Characteristics table).
B3
8
6
B1
5
3
THREESTATE
B4
7
2
B3
2
7
GND
C1
13
8
A2
3
13
I/O VCC1
Input/Output 1. Referenced to VCC. (Note 6)
C2
12
1
A3
1
12
I/O VCC2
Input/Output 2. Referenced to VCC. (Note 6)
C3
11
—
—
—
9
I/O VCC3
Input/Output 3. Referenced to VCC. (Note 6)
C4
10
—
—
—
8
I/O VCC4
Input/Output 4. Referenced to VCC. (Note 6)
—
6, 9
—
—
—
4, 11
N.C.
—
—
—
B2
—
—
—
B2 bump is not populated for B9+2 9-UCSP
packages
—
—
—
—
—
—
EP
Exposed Pad. Connect EP to ground.
Ground
No Connection. Not internally connected.
Note 6: For unidirectional devices (MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E–MAX3393E) see the Pin
Configurations for input/output configurations.
www.maximintegrated.com
Maxim Integrated │ 9
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Detailed Description
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
ESD-protected level translators provide the level shifting
necessary to allow data transfer in a multivoltage system.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. A low-voltage logic
signal present on the VL side of the device appears as a
high-voltage logic signal on the VCC side of the device,
and vice-versa. The MAX3374E/MAX3375E/MAX3376E/
MAX3379E and MAX3390E–MAX3393E unidirectional
level translators level shift data in one direction (VL → VCC
or VCC → VL) on any single data line. The MAX3372E/
MAX3373E and MAX3377E/MAX3378E bidirectional
level translators utilize a transmission-gatebased design
(see Figure 2) to allow data translation in either direction
(VL ↔ VCC) on any single data line. The MAX3372E–
MAX3379E and MAX3390E–MAX3393E accept VL from
VL
+1.2V to +5.5V and VCC from +1.65V to +5.5V, making
them ideal for data transfer between low-voltage ASICs/
PLDs and higher voltage systems.
All devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family feature a three-state output mode
that reduces supply current to less than 1μA, thermal
shortcircuit protection, and ±15kV ESD protection on the
VCC side for greater protection in applications that route
signals externally. The MAX3372E/MAX3377E operate
at a guaranteed data rate of 230kbps. Slew-rate limiting reduces EMI emissions in all 230kbps devices.
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E operate at a guaranteed data
rate of 8Mbps over the entire specified operating voltage
range. Within specific voltage domains, higher data rates
are possible. (See the Timing Characteristics table.)
VL
VCC
VL
VCC
VL
VCC
MAX3372E–MAX3379E
AND
MAX3390E–MAX3393E
MAX3372E–MAX3379E
AND
MAX3390E–MAX3393E
I/O VCC_
I/O VL_
GND
VCC
DATA
DATA
RLOAD
I/O VL_
(tRISE,
tFALL < 10ns)
CLOAD
CLOAD
I/O VCC_
I/O VL_
RLOAD
GND
I/O VCC_
(tRISE,
tFALL < 10ns)
tPD-VCC-LH
tPD-VCC-HL
I/O VCC_
tPD-VL-LH
tPD-VL-HL
tRVL
tFVL
I/O VL_
tRVCC
Figure 1a. Rail-to-Rail Driving I/O VL
www.maximintegrated.com
tFVCC
Figure 1b. Rail-to-Rail Driving I/O VCC
Maxim Integrated │ 10
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Level Translation
For proper operation ensure that +1.65V ≤ VCC ≤ +5.5V,
+1.2V ≤ VL ≤ +5.5V, and VL ≤ (VCC + 0.3V). During power-up sequencing, VL ≥ (VCC + 0.3V) will not damage the
device. During power-supply sequencing, when VCC is
floating and VL is powering up, a current may be sourced,
yet the device will not latch up. The speed-up circuitry limits the maximum data rate for devices in the MAX3372E–
MAX3379E, MAX3390E–MAX3393E family to 16Mbps.
The maximum data rate also depends heavily on the load
capacitance (see the Typical Operating Characteristics),
output impedance of the driver, and the operational voltage range (see the Timing Characteristics table).
Speed-Up Circuitry
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E feature a one-shot generator
that decreases the rise time of the output. When triggered, MOSFETs PU1 and PU2 turn on for a short time
VL
to pull up I/O VL_ and I/O VCC_ to their respective supplies (see Figure 2b). This greatly reduces the rise time
and propagation delay for the low-to-high transition. The
scope photo of Rail-to-Rail Driving for 8Mbps Operation in
the Typical Operating Characteristics shows the speed-up
circuitry in operation.
Rise-Time Accelerators
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
the MAX3390E–MAX3393E have internal rise-time accelerators allowing operation up to 16Mbps. The rise-time
accelerators are present on both sides of the device and
act to speed up the rise time of the input and output of the
device, regardless of the direction of the data. The triggering mechanism for these accelerators is both level and
edge sensitive. To prevent false triggering of the rise-time
accelerators, signal fall times of less than 20ns/V are recommended for both the inputs and outputs of the device.
Under less noisy conditions, longer signal fall times may
be acceptable.
VL
VCC
VL
VCC
VL
VCC
MAX3372E–MAX3379E
AND
MAX3390E–MAX3393E
I/O VCC_
I/O VL_
GND
DATA
DATA
RLOAD
I/O VL_
CLOAD
CLOAD
VCC
MAX3373E–MAX3376E,
MAX3378E/MAX3379E
AND
MAX3390E–MAX3393E
I/O VCC_
I/O VL_
GND
RLOAD
I/O VCC_
tPD-VCC-LH
tPD-VCC-HL
I/O VCC_
tPD-VL-LH
tPD-VL-HL
I/O VL_
tRVCC
Figure 1c. Open-Drain Driving I/O VCC
www.maximintegrated.com
tFVCC
tRVL
tFVL
Figure 1d. Open-Drain Driving I/O VL
Maxim Integrated │ 11
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Three-State Output Mode
at I/O VL_ to exceed (VL + 0.3V), or the voltage at I/O
VCC_ to exceed (VCC + 0.3V).
Pull THREE-STATE low to place the MAX3372E–
MAX3379E and MAX3390E–MAX3393E in three-state
output mode. Connect THREE-STATE to VL (logic-high)
for normal operation. Activating the three-state output
mode disconnects the internal 10kΩ pullup resistors on
the I/O VCC and I/O VL lines. This forces the I/O lines to a
high-impedance state, and decreases the supply current
to less than 1μA. The high-impedance I/O lines in threestate output mode allow for use in a multidrop network.
When in three-state output mode, do not allow the voltage
Thermal Short-Circuit Protection
Thermal overload detection protects the MAX3372E–
MAX3379E and MAX3390E–MAX3393E from short-circuit fault conditions. In the event of a short-circuit fault,
when the junction temperature (TJ) reaches +152°C, a
thermal sensor signals the three-state output mode logic
to force the device into three-state output mode. When TJ
has cooled to +142°C, normal operation resumes.
VCC
VL
P
P
GATE
BIAS
I/O VL
I/O VCC
N
Figure 2a. Functional Diagram, MAX3372E/MAX3377E (1 I/O line)
VCC
VL
PU1
ONE-SHOT
BLOCK
ONE-SHOT
BLOCK
PU2
GATE
BIAS
I/O VL_
N
I/O VCC_
Figure 2b. Functional Diagram, MAX3373E/MAX3378E (1 I/O line)
www.maximintegrated.com
Maxim Integrated │ 12
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
±15kV ESD Protection
IEC 1000-4-2
ESD protection can be tested in various ways. The I/O
VCC lines of this product family are characterized for protection to the following limits:
The major difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2, because series resistance is lower
in the IEC 1000-4-2 model. Hence, the ESD with-stand
voltage measured to IEC 1000-4-2 is generally lower than
that measured using the Human Body Model. Figure 4a
shows the IEC 1000-4-2 model, and Figure 4b shows the
current waveform for the ±8kV, IEC 1000-4-2, Level 4,
ESD contact-discharge test.
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O VCC lines have extra protection against static
electricity. Maxim’s engineers have developed state-ofthe-art structures to protect these pins against ESD of
±15kV without damage. The ESD structures withstand
high ESD in all states: normal operation, three-state
output mode, and powered down. After an ESD event,
Maxim’s E versions keep working without latchup, whereas competing products can latch and must be powered
down to remove latchup.
1) ±15kV using the Human Body Model
2) ±8kV using the Contact Discharge method specified
in IEC 1000-4-2
3) ±10kV using IEC 1000-4-2’s Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically
refer to integrated circuits. The MAX3372E–MAX3379E
and MAX3390E–MAX3393E help to design equipment
that meets Level 3 of IEC 1000-4-2, without the need for
additional ESD-protection components.
The air-gap test involves approaching the device with a
charged probe. The contact-discharge method connects
the probe to the device before the probe is energized.
Machine Model
The Machine Model for ESD tests all pins using a 200pF
storage capacitor and zero discharge resistance. Its
objective is to emulate the stress caused by contact that
occurs with handling and assembly during manufacturing.
Of course, all pins require this protection during manufacturing, not just inputs and outputs. Therefore, after PCB
assembly, the Machine Model is less relevant to I/O ports.
Figure 3a shows the Human Body Model and Figure
3b shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
RC 1MΩ
CHARGE-CURRENTLIMIT RESISTOR
RD 1500Ω
IP 100%
90%
DISCHARGE
RESISTANCE
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
Figure 3a. Human Body ESD Test Model
www.maximintegrated.com
DEVICEUNDERTEST
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 3b. Human Body Current Waveform
Maxim Integrated │ 13
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
I
100%
RC 50MΩ to 100MΩ
Cs
150pF
I PEAK
DISCHARGE
RESISTANCE
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
90%
RD 330Ω
DEVICEUNDERTEST
STORAGE
CAPACITOR
10%
t r = 0.7ns to 1ns
t
30ns
60ns
Figure 4a. IEC 1000-4-2 ESD Test Model
Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform
Applications Information
ideal for level translation between a low-voltage ASIC and
an I2C device. A typical application involves interfacing a
low-voltage microprocessor to a 3V or 5V D/A converter,
such as the MAX517.
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with a 0.1μF
capacitor. See the Typical Operating Circuit. To ensure
full ±15kV ESD protection, bypass VCC to ground with a
1μF capacitor. Place all capacitors as close to the powersupply inputs as possible.
I2C Level Translation
The MAX3373E–MAX3376E, MAX3378E/MAX3379E
and MAX3390E–MAX3393E level-shift the data present
on the I/O lines between +1.2V and +5.5V, making them
Push-Pull vs. Open-Drain Driving
All devices in the MAX3372E–MAX3379E and MAX3390E–
MAX3393E family may be driven in a pushpull configuration. The MAX3373E–MAX3376E/MAX3378E/MAX3379E
and MAX3390E–MAX3393E include internal 10kΩ resistors that pull up I/O VL_ and I/O VCC_ to their respective
power supplies, allowing operation of the I/O lines with
open-drain devices. See the Timing Characteristics table
for maximum data rates when using open-drain drivers.
Typical Operating Circuit
+1.8V
+3.3V
0.1µF
0.1µF
VL
+3.3V
SYSTEM
MAX3378E–MAX3383E
DATA
www.maximintegrated.com
VCC
THREE-STATE
+1.8V
SYSTEM
CONTROLLER
I/O VL_
1µF
I/O VCC_
DATA
Maxim Integrated │ 14
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3372E/
MAX3373E
DATA
I/O VCC1
I/O VL1
I/O VCC2
I/O VL2
DATA
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3374E
DATA
www.maximintegrated.com
I VL1
I VL2
O VCC1
O VCC2
DATA
Maxim Integrated │ 15
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3375E
DATA
O VL1
I VCC1
O VCC2
I VL2
DATA
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3376E
DATA
www.maximintegrated.com
O VL1
O VL2
I VCC1
I VCC2
DATA
Maxim Integrated │ 16
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3377E/MAX3378E
I/O VCC1
I/O VL1
DATA
I/O VL2
I/O VL3
I/O VL4
I/O VCC2
I/O VCC3
I/O VCC4
DATA
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3379E
DATA
www.maximintegrated.com
I VL1
O VCC1
I VL3
I VL4
O VCC3
O VCC4
I VL2
O VCC2
DATA
Maxim Integrated │ 17
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3390E
I VL1
O VL1
DATA
O VCC2
I VL2
O VCC3
O VCC4
I VL3
I VL4
DATA
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3391E
DATA
O VL1
O VL2
I VL3
I VL4
www.maximintegrated.com
I VCC1
I VCC2
O VCC3
O VCC4
DATA
Maxim Integrated │ 18
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3392E
DATA
O VL1
I VCC1
O VL3
I VL4
I VCC3
O VCC4
I VCC2
O VL2
DATA
+1.8V
+3.3V
0.1µF
0.1µF
VL
+1.8V
SYSTEM
CONTROLLER
1µF
VCC
THREE-STATE
+3.3V
SYSTEM
MAX3393E
DATA
O VL1
O VL2
O VL3
I VL4
www.maximintegrated.com
I VCC1
I VCC2
I VCC3
I VCC4
DATA
Maxim Integrated │ 19
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Ordering Information
TEMP RANGE
PINPACKAGE
MAX3372EEKA+T
-40°C to +85°C
8 SOT23
MAX3372EEBL+T
-40°C to +85°C
MAX3373EEKA+T
PART
PART
TEMP RANGE
PINPACKAGE
MAX3379EEUD+
-40°C to +85°C
14 TSSOP
9 UCSP
(1.5mm x 1.5mm)
MAX3379EETD+T
-40°C to +85°C
14 TDFN-EP**
(3mm x 3mm)
-40°C to +85°C
8 SOT23
MAX3390EEUD+
-40°C to +85°C
14 TSSOP
MAX3373EEBL+T
-40°C to +85°C
9 UCSP
(1.5mm x 1.5mm)
MAX3391EEUD+
-40°C to +85°C
14 TSSOP
MAX3374EEKA+T
-40°C to +85°C
8 SOT23
MAX3391EEBC+T
-40°C to +85°C
12 UCSP
(1.5mm x 2.0mm)
MAX3375EEKA+T
-40°C to +85°C
8 SOT23
-40°C to +85°C
MAX3375EEBL+T
-40°C to +85°C
9 UCSP
(1.5mm x 1.5mm)
MAX3391EETD+T
14 TDFN-EP**
(3mm x 3mm)
MAX3392EEUD+
-40°C to +85°C
14 TSSOP
MAX3376EEKA+T
-40°C to +85°C
8 SOT23
MAX3393EEUD+
-40°C to +85°C
14 TSSOP
MAX3377EEUD+
-40°C to +85°C
14 TSSOP
MAX3393EEBC+T
-40°C to +85°C
MAX3377EETD+T
-40°C to +85°C
14 TDFN-EP**
(3mm x 3mm)
12 UCSP
(1.5mm x 2.0mm)
MAX3378EEUD+
-40°C to +85°C
14 TSSOP
MAX3378EEBC+T
-40°C to +85°C
12 UCSP
(1.5mm x 2.0mm)
MAX3378EETD+T
-40°C to +85°C
14 TDFN-EP**
(3mm x 3mm)
+Denotes a lead-free package.
**EP = Exposed pad.
T = Tape and reel.
www.maximintegrated.com
Maxim Integrated │ 20
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Selector Guide
LEVEL
TRANSLATION
Tx/
Rx†
MAX3372EEKA+T
ü Bi
2/2
MAX3372EEBL+T
ü Bi
2/2
MAX3372EETA+T
PART
DATA
RATE
230kbps
TOP
MARK
PART
LEVEL
TRANSLATION
Tx/
Rx†
DATA
RATE
TOP
MARK
AAKO
MAX3378EEUD+
ü Bi
4/4
—
AAR
MAX3378EEBC+T
ü Bi
4/4
AAY
ü Bi
2/2
AQG
MAX3378EETD+T
ü Bi
4/4
AAH
MAX3373EEKA+T
ü Bi
2/2
AAKS
MAX3379EEUD+
Uni
4/0
—
MAX3373EEBL+T
ü Bi
2/2
AAZ
MAX3379EEBC+T
Uni
4/0
AAZ
MAX3373EETA+T
ü Bi
2/2
AQH
MAX3379EETD+T
Uni
4/0
AAI
MAX3374EEKA+T
Uni
2/0
AALH
MAX3390EEUD+
Uni
3/1
—
MAX3374EEBL+T
Uni
2/0
ABA
MAX3390EEBC+T
Uni
3/1
ABA
MAX3374EETA+T
Uni
2/0
AQI
MAX3390EETD+T
Uni
3/1
MAX3375EEKA+T
Uni
1/1
AALI
MAX3391EEUD+
Uni
2/2
MAX3375EEBL+T
Uni
1/1
ABB
MAX3391EEBC+T
Uni
2/2
ABB
MAX3375EETA+T
Uni
1/1
AQJ
MAX3391EETD+T
Uni
2/2
AAK
MAX3376EEKA+T
Uni
0/2
AALG
MAX3392EEUD+
Uni
1/3
—
MAX3376EEBL+T
Uni
0/2
AAV
MAX3392EEBC+T
Uni
1/3
ABC
MAX3376EETA+T
Uni
0/2
AQK
MAX3392EETD+T
Uni
1/3
AAL
MAX3377EEUD+
ü Bi
4/4
MAX3377EEBC+T
ü Bi
4/4
MAX3377EETD+T
ü Bi
4/4
8Mbps*
230kbps
8Mbps*
AAJ
—
—
MAX3393EEUD+
Uni
0/4
—
AAX
MAX3393EEBC+T
Uni
0/4
ABD
AAG
MAX3393EETD+T
Uni
0/4
AAM
†Tx
= VL →VCC, Rx = VCC →VL
*Higher data rates are possible (see the Timing Characteristics table).
www.maximintegrated.com
Maxim Integrated │ 21
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Pin Configurations (continued)
A
1
2
3
B
C
I/O VCC2
VCC
THREE-STATE
I/O VCC1
N.C.
VL
I/O VL1
MAX3372E
MAX3373E
1
+
GND 2
VL
7 VCC
3
I/O VL2 4
I/O VCC2
GND
A
2
3
B
5 I/O VL1
I/O VL2
O VCC1
O VCC2
N.C.
GND
MAX3374E
1
2
3
B
3
I V L2
O VCC1
I VCC2
N.C.
GND
1
2
3
B
MAX3375E
VL
I V L1
1
I VCC1
I VCC2
N.C.
GND
O V L2
9 UCSP (1.5mm x 1.5mm)
BOTTOM VIEW
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+
5 THREE-STATE
*EP
O VCC2
1
+
8 I VL2
GND 2
O VCC1
7 VL
6 I VL1
3
VCC 4
5 THREE-STATE
*EP
TDFN-8 (3mm x 3mm)
TOP VIEW
8 I VCC1
7 VCC
6 THREE-STATE
I VL2 4
5 O V L1
O VCC2
1
+
8 I VL2
GND 2
I VCC1
7 VL
6 O VL1
3
VCC 4
5 THREE-STATE
*EP
TDFN-8 (3mm x 3mm)
TOP VIEW
SOT23-8
TOP VIEW
*CONNECT EP TO GND
C
O V L1
5 I VL1
3
O V L2
VL
8 O VCC1
6 THREE-STATE
GND 2
I VCC2
VCC THREE-STATE
6 I/O VL1
3
*CONNECT EP TO GND
9 UCSP (1.5mm x 1.5mm)
BOTTOM VIEW
A
7 VL
VCC 4
SOT23-8
TOP VIEW
C
VL
8 I/O VL2
TDFN-8 (3mm x 3mm)
TOP VIEW
7 VCC
I VL2 4
O VCC2
VCC THREE-STATE
+
GND 2
VL
I VL1
1
9 UCSP (1.5mm x 1.5mm)
BOTTOM VIEW
A
+
*CONNECT EP TO GND
C
VL
1
GND 2
SOT23-8
TOP VIEW
O VCC2
VCC THREE-STATE
I/O VCC2
6 THREE-STATE I/O VCC1
9 UCSP (1.5mm x 1.5mm)
BOTTOM VIEW
1
8 I/O VCC1
MAX3376E
1
+
GND 2
VL
8 I VCC1
7 VCC
3
6 THREE-STATE
O V L2 4
5 O V L1
SOT23-8
TOP VIEW
I VCC2
1
+
8 O VL 2
GND 2
I VCC1
7 VL
6 O V L1
3
VCC 4
5 THREE-STATE
*EP
TDFN-8 (3mm x 3mm)
TOP VIEW
*CONNECT EP TO GND
Maxim Integrated │ 22
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Pin Configurations (continued)
A
1
2
3
4
I/O VL1
I/O VL2
B
C
I/O VCC1
VCC
MAX3377E
MAX3378E
I/O VCC2
VL
I/O VL3 THREE-STATE I/O VCC3
I/O VL4
+
VCC
2
13
I/0 VCC1
I/O VL2
3
12
I/0 VCC2
I/O VL3
4
11
I/0 VCC3
I/O VL4
5
10
I/0 VCC4
N.C.
6
9
N.C.
I/O VL4
6
9
I/0 VCC3
GND
7
8
THREE-STATE
GND
7
8
I/0 VCC4
1
I/O VL1
1
2
3
4
I V L1
I V L2
B
VCC
VL
O VCC1
MAX3379E
O VCC2
+
1
2
3
4
O V L1
I V L2
I V L1
2
13 O VCC1
I V L2
3
12 O VCC2
I VL3
4
11 O VCC3
I VCC1
VCC
GND
I/0 VCC1
12
I/0 VCC2
N.C.
4
11
N.C.
I/O VL3
5
10
VL
O VCC2
O VCC4
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
www.maximintegrated.com
I V L1
1
*EP
I VL2
VCC
13
0 VCC1
12
0 VCC2
N.C.
4
11
N.C.
5
10
VL
6
9
0 VCC3
8
0 VCC4
5
10 O VCC4
6
9
I V L4
8
14
2
N.C.
7
+
THREE-STATE 3
I V L4
N.C.
THREE-STATE
GND
TSSOP-14
TOP VIEW
7
*EP
TDFN-14 (3mm x 3mm)
TOP VIEW
*CONNECT EP TO GND
C
I VL3 THREE-STATE O VCC3
I VL4
13
I V L3
O VCC4
B
VL
2
THREE-STATE 3
14 VCC
1
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
A
VCC
TDFN-14 (3mm x 3mm)
TOP VIEW
VL
GND
GND
I/O VL2
14
*CONNECT EP TO GND
C
I VL3 THREE-STATEO VCC3
I V L4
1
TSSOP-14
TOP VIEW
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
A
I/O VL1
I/O VCC4
GND
+
14
VL
MAX3390E
+
14 VCC
VL
1
O V L1
2
13 I VCC1
I V L2
3
12 O VCC2
I VL3
4
11 O VCC3
I VL4
5
10 O VCC4
N.C.
6
9
N.C.
I VL 4
GND
7
8
THREE-STATE
TSSOP-14
TOP VIEW
O V L1
1
I VL 2
+
14
VCC
2
13
I VCC1
THREE-STATE 3
12
0 VCC2
N.C.
4
11
N.C.
I V L3
5
10
VL
6
9
0 VCC3
8
0 VCC4
GND
7
*EP
TDFN-14 (3mm x 3mm)
TOP VIEW
*CONNECT EP TO GND
Maxim Integrated │ 23
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Pin Configurations (continued)
A
B
C
VL 1
1
2
3
O V L1
VCC
I VCC1
O V L2
VL
I VCC2
MAX3391E
I VL3 THREE-STATE O VCC3
4
I VL4
GND
+
1
2
3
4
VCC
VL
O VL2
O V L2
3
12 I VCC2
THREE-STATE
3
12
I VCC2
N.C.
4
11
N.C.
I V L3 4
11 O VCC3
I VL4 5
10 O VCC4
I V L3
5
10
VL
N.C. 6
9
N.C.
I V L4
6
9
0 VCC3
GND 7
8
THREE-STATE
GND
7
8
0 VCC4
GND
*CONNECT EP TO GND
I VCC1
I VCC2
+
1
2
3
4
O V L2
VCC
VL
VCC
13
I VCC1
O VL 2
O V L2
3
12 I VCC2
THREE-STATE
3
12
I VCC2
O V L3 4
11 I VCC3
N.C.
4
11
N.C.
I VL4 5
10 O VCC4
O V L3
5
10
VL
N.C. 6
9
N.C.
I VL 4
6
9
I VCC3
GND 7
8
THREE-STATE
GND
7
8
0 VCC4
I VCC1
I VCC2
*CONNECT EP TO GND
MAX3393E
+
14 VCC
O V L1
1
+
14
VCC
O V L1
2
13 I VCC1
O VL2
2
13
I VCC1
O V L2
3
12 I VCC2
THREE-STATE
3
12
I VCC2
O V L3 4
11 I VCC3
N.C.
4
11
N.C.
O VL4 5
10 I VCC4
O V L3
5
10
VL
9
O V L4
6
9
I VCC3
8
I VCC4
N.C. 6
8
I VCC4
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
*EP
TDFN-14 (3mm x 3mm)
TOP VIEW
TSSOP-14
TOP VIEW
GND 7
GND
14
2
13 I VCC1
C
O VL3 THREE-STATE I VCC3
O VL4
1
2
VL 1
O V L1
O V L1
O VCC4
B
+
14 VCC
O V L1
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
A
*EP
TDFN-14 (3mm x 3mm)
TOP VIEW
C
O VL3 THREE-STATE I VCC3
I VL4
I VCC1
13 I VCC1
TSSOP-14
TOP VIEW
MAX3392E
O V L2
13
2
VL 1
O V L1
2
1
O VCC4
B
VCC
O V L1
O V L1
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
A
+
14
14 VCC
TSSOP-14
TOP VIEW
N.C.
THREE-STATE
GND
7
TDFN-14 (3mm x 3mm)
TOP VIEW
*CONNECT EP TO GND
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
Maxim Integrated │ 24
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 SOT23
K8SN+1
21-0078
90-0176
9 UCSP
B9+2
21-0093
Refer to Application Note 1891
12 UCSP
B12+1
21-0104
Refer to Application Note 1891
8 TDFN
T833+2
21-0137
90-0059
14 TDFN
T1433+2
21-0137
90-0063
14 TSSOP
U14+1
21-0066
90-0113
www.maximintegrated.com
Maxim Integrated │ 25
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1μA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
1/02
Initial Release
—
1
12/06
Addition of 12-bump ECSP packaging
–
2
11/07
Addition of lead-free options
3
1/13
Updated packaging information; updated Absolute Maximum Ratings
4
2/15
Updated Benefits and Features section
5
10/19
Updated Pin Description table and added package outline drawing for 21-0093
6
11/19
Updated Benefits and Features section
1
7
2/20
Updated Ordering Information table
20
DESCRIPTION
1, 20–31
1, 2, 9, 20–23
1
9, 25
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc. │ 26
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