19-1029; Rev 3; 2/11
KIT
ATION
EVALU
E
L
B
AVAILA
Complete Single-Conversion
Television Tuner
Features
The MAX3541 complete single-conversion television
tuner is designed for use in analog/digital terrestrial applications and digital set-top boxes. This television tuner
draws only 760mW of power from a +3.3V supply voltage.
The MAX3541 is designed to convert PAL or DVB-T signals in the 47MHz to 68MHz, 174MHz to 230MHz, and
470MHz to 862MHz bands to an intermediate frequency
(IF) of 36MHz.
The MAX3541 includes a variable-gain low-noise amplifier (LNA), multiband tracking filters, a harmonic-rejection
mixer, a low-noise IF amplifier, an IF power detector, and
a variable-gain IF amplifier. The MAX3541 also includes
fully monolithic VCOs and tank circuits, as well as a
complete frequency synthesizer. This highly integrated
design allows for low-power tuner-on-board applications
without the cost and power dissipation issues of dualconversion tuner solutions.
The MAX3541 is specified for operation in the -40°C to
+85°C temperature range and is available in a leadless
48-pin flip-chip (fcLGA) package.
o Low Power Consumption: 760mW (typ) from a
+3.3V Supply Voltage
o Integrated Tracking Filters
o Low Noise Figure: 4.9dB (typ)
o Small 7mm x 7mm fcLGA Leadless Package
o IF Overload Detector Controls RF Variable-Gain
Amplifier
o 2-Wire, I2C-Compatible Serial Control Interface
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3541ELM+
-40°C to +85°C
48 LGA-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
Applications
Televisions
Analog/Digital Terrestrial Receivers
Digital Set-Top Boxes
ADDR1
XTALP
XTALN
VCC
CP
MUX
VCC
VTUNE
GND_TUNE
LDO
VCC
+
ADDR2
Pin Configuration/Functional Diagram
48
47
46
45
44
43
42
41
40
39
38
37
SCL 1
36 IFOUT1÷R
PD
CP
SDA 2
35 IFOUT1+
÷N
SERIAL
INTERFACE
VCC 3
34 IFOVLD
VCO
DIVIDER
UHF_IN 4
33 VCC
VHF_IN 5
VREF
+
-
RFGND2 6
32 VCC
31 GND
LEXT 7
30 IFIN+
RFGND3 8
29 IFIN-
RFAGC 9
28 VCC
MAX3541
VCC 10
27 GND
EP
GND 11
26 IFAGC
GND 12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
IFOUT2-
25 IFOUT2+
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX3541
General Description
MAX3541
Complete Single-Conversion
Television Tuner
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V, +3.6V
RFIN, IFIN_ IFOUT1_, IFOUT2_, IFAGC, RFAGC,
VTUNE, LDO, MUX, CP,
XTAL to GND ....................................-0.3V to (VCC + 0.3V)
SDA, SCL, ADDR2, ADDR1 to GND......................-0.3V to +3.6V
IFOUT__ Short-Circuit Duration .....................................Indefinite
RF Input Power ...............................................................+10dBm
Continuous Power Dissipation (TA = +70°C)
48-Pin fcLGA (derate 25mW/°C above +70°C) ..............1.4W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+250°C
Soldering Temperature (reflow) .......................................+240°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA = -40°C to +85°C, no RF signals at RF inputs, default register settings, VRFAGC = VIFAGC
= +3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+3.5
V
SUPPLY VOLTAGE AND CURRENT
Supply Voltage
Supply Current
RF and IF AGC Input Bias Current
RF and IF AGC Control Voltage (Note 1)
+3.1
Receive mode
230
Shutdown mode
275
5
At +0.5V and +3V
-50
Minimum attenuation
+3
+50
Maximum attenuation
+0.5
Digital Input Logic-Level Low
0.3 x VCC
Digital Input Logic-Level High
0.7 x VCC
mA
μA
V
V
V
SERIAL INTERFACE
Input Logic-Level Low
0.3 x VCC
Input Logic-Level High
0.7 x VCC
Input Hysteresis
Output Logic-Level Low
Output Logic-Level High
2
V
0.05 x VCC
SDA, SCL Input Current
-10
3mA sink current
V
+10
0.4
VCC - 0.5
_______________________________________________________________________________________
V
μA
V
V
Complete Single-Conversion
Television Tuner
(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA = -40°C to +85°C, 75Ω system impedance, default register settings, VRFAGC = VIFAGC =
+3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RF INPUT TO IFOUT1 OUTPUT
Operating Frequency Range
(see Table 7)
Gain specification met across these
frequency bands
47
68
174
230
470
Analog channel PIX carrier
Output Frequency
Source impedance
= 75Ω, load
impedance = 200Ω
Voltage Gain
Maximum gain
(VRAVGC = 3V)
862
38.9
Digital channel center frequency
MHz
36
33
MHz
41
49
dB
Minimum gain
(VRAVGC = 0.5V)
-10
Input Return Loss
Selected channel
10
dB
Noise Figure
Maximum gain (VRFAGC = 3V)
4.9
dB
Maximum gain (VRFAGC = 3V)
20
At 12.5dB of gain
30
Input IP2 (In-Band and Out-of-Band Tones)
Input IP3 (In-Band and Out-of-Band Tones)
Input P1dB
Beats Within Output
Beats, Converted to Output
Maximum gain (VRFAGC = 3V)
At 12.5dB of gain
dBm
-10
dBm
10
Maximum gain (VRFAGC = 3V)
-38
At 12.5dB of gain
-5
0dBmV PIX carrier level
-40
VHF input, 140MHz to 500MHz
-60
VHF input, 500MHz to 1400MHz
-50
UHF input, 950MHz to 1400MHz
-60
dBm
dBc
dBc
Gain Flatness
47MHz to 54MHz
Isolation
5MHz to 50MHz, RF input to IF output,
relative to desired channel
60
dBc
Port-to-Port Isolation
Isolation between RF input ports at 215MHz
27
dB
Image Rejection
Measured at 77.8MHz above desired
channel’s center frequency
70
dBc
Spurious Leakage at RF Input
Phase Noise (Single-Sideband)
Output Return Loss
2.5
57
5Hz to 65MHz
-40
65MHz to 878MHz
-40
1kHz
-80
10kHz offset
-85
100kHz offset (1.5kHz loop bandwidth)
-105
1MHz offset (1.5kHz loop bandwidth)
-125
Balanced 50Ω load
dBP-P
dBmV
dBc/Hz
20
dB
2000
Ω
IF VARIABLE-GAIN AMPLIFIER
Input Impedance
Balanced
Output Impedance
Balanced (Note 1)
300
Ω
_______________________________________________________________________________________
3
MAX3541
AC ELECTRICAL CHARACTERISTICS
MAX3541
Complete Single-Conversion
Television Tuner
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA = -40°C to +85°C, 75Ω system impedance, default register settings, VRFAGC = VIFAGC =
+3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
Passband Voltage Gain
CONDITIONS
Source load =
1.1kΩ,
output load = 1kΩ
Maximum gain setting
(VIFAGC = 3V)
MIN
TYP
MAX
54
59
63
UNITS
dB
Minimum gain setting
(VIFAGC = 0.5V)
21
Passband Gain Flatness
32MHz to 40MHz (Note 1)
1.2
dB
Output Voltage
VIFAGC = 3V (Note 1)
2.5
VP-P
AGC Gain Slope
VIFAGC = 3V to 0.5V (Note 1)
27
dB/V
Equivalent Input Voltage Noise Density
At 36MHz, maximum gain (VIFAGC = 3V)
(Note 1)
7.3
nV/√Hz
Noise Figure Change vs. Attenuation
IM3
< 0.35
VOUT = 1VP-P, 40dB < gain < 60dB (Note 1)
dB/dB
-56
dBc
IF OVERLOAD DETECTOR (See the IF Overload Detector Section)
Output Overload Attack Point
Attack Point Accuracy
OD REG = 3
Detector Output Voltage Range
Negative polarity, overload reduces VDET
(open collector, 0.3mA sink)
0.7
VP-P
±1
dB
0.5
Detector Gain
3.0
V
70
V/V
8
MHz
FREQUENCY SYNTHESIZER
REFERENCE OSCILLATOR
Frequency
DIVIDERS
RF N-Divider Ratio
256
32,767
RF R-Divider Ratio
16
127
LO PHASE DETECTOR AND CHARGE PUMP
Comparison Frequency
63
CP = 00
Charge-Pump Current
250
CP = 01
1
CP = 10
1.5
CP = 11
2
Charge-Pump Three-State Current
mA
±5
Charge-Pump Compliance Range
kHz
0.5
VCC 0.4
0.4
Charge-Pump Current Matching
nA
5
V
%
LOCAL OSCILLATOR
VCO Tuning Range
Tank frequency
VCO Tuning Gain
Tank oscillator gain
2200
4400
MHz
500
MHz/V
400
kHz
2-WIRE SERIAL INTERFACE
Clock Frequency
Note 1: Guaranteed by design and characterization.
4
_______________________________________________________________________________________
Complete Single-Conversion
Television Tuner
-40°C
220
-40°C
40
+25°C
20
0
fRF = 801MHz
UHF VOLTAGE GAIN (dB)
224
60
MAX3541 toc02
MAX3541 toc01
228
fRF = 64.5MHz
VHF VOLTAGE GAIN (dB)
SUPPLY CURRENT (mA)
+85°C
UHF VOLTAGE GAIN vs. RFAGC VOLTAGE
VHF VOLTAGE GAIN vs. RFAGC VOLTAGE
60
MAX3541 toc03
SUPPLY CURRENT vs. SUPPLY VOLTAGE
232
+85°C
-40°C
40
20
+25°C
0
+25°C
+85°C
-20
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
0.5
VHF VOLTAGE GAIN vs. FREQUENCY
VHF VOLTAGE GAIN (dB)
42
+25°C
40
2.5
0.5
3.0
1.5
2.0
RFAGC VOLTAGE (V)
2.5
3.0
60
MAX3541 toc05
50
1.0
UHF VOLTAGE GAIN vs. FREQUENCY
VHF VOLTAGE GAIN vs. FREQUENCY
44
-40°C
45
40
-40°C
50
40
+25°C
30
+25°C
+85°C
+85°C
+85°C
20
35
50
55
60
FREQUENCY (MHz)
65
70
170
180
190
200
210
FREQUENCY (MHz)
220
+55°C
+85°C
+25°C
470
230
NOISE FIGURE (dB)
5
0°C
670
770
FREQUENCY (MHz)
7
+55°C
+25°C
3
570
870
VHF NOISE FIGURE vs. FREQUENCY
VHF NOISE FIGURE vs. FREQUENCY
7
MAX3541 toc07
45
-40°C
+85°C
MAX3541 toc08
38
NOISE FIGURE (dB)
VHF VOLTAGE GAIN (dB)
-40°C
1.5
2.0
RFAGC VOLTAGE (V)
55
MAX3541 toc04
46
1.0
UHF VOLTAGE GAIN (dB)
3.1
MAX3541 toc06
216
-20
5
3
0°C
-40°C
1
1
48
51
54
57
FREQUENCY (MHz)
60
63
175
185
195
205
FREQUENCY (MHz)
215
225
_______________________________________________________________________________________
5
MAX3541
Typical Operating Characteristics
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25°C, unless otherwise noted.)
VHF NOISE FIGURE vs. RFAGC VOLTAGE
UHF NOISE FIGURE vs. FREQUENCY
fRF = 224.25MHz
+85°C
16
NOISE FIGURE (dB)
5
3
+25°C
0°C
MAX3541 toc10
+85°C
+55°C
NOISE FIGURE (dB)
20
MAX3541 toc09
7
+55°C
12
+25°C
8
4
-40°C
0°C
-40°C
0
1
560
650
740
FREQUENCY (MHz)
1.8
830
UHF NOISE FIGURE vs. RFAGC VOLTAGE
fRF = 631.25MHz
+25°C
12
+55°C
2.8
3.0
VHF IMAGE REJECTION vs. FREQUENCY
-40°C
VHF IMAGE REJECTION (dB)
NOISE FIGURE (dB)
16
2.2
2.4
2.6
RFAGC VOLTAGE (V)
80
MAX3541 toc11
20
2.0
+85°C
8
-40°C
0°C
4
MAX3541 toc12
470
0°C
78
76
+25°C
74
+55°C
72
+85°C
0
70
2.0
2.2
2.4
2.6
RFAGC VOLTAGE (V)
2.8
3.0
47
VHF IMAGE REJECTION vs. FREQUENCY
-40°C
0°C
63
UHF IMAGE REJECTION vs. FREQUENCY
74
UHF IMAGE REJECTION (dB)
76
55
59
FREQUENCY (MHz)
76
MAX3541 toc13
77
51
75
+25°C
74
73
MAX3541 to14
1.8
VHF IMAGE REJECTION (dB)
MAX3541
Complete Single-Conversion
Television Tuner
0°C
72
70
+25°C
-40°C
+55°C
68
66
+85°C
72
175
6
+55°C
+85°C
185
195
205
FREQUENCY (MHz)
64
215
225
470
570
670
770
FREQUENCY (MHz)
_______________________________________________________________________________________
870
Complete Single-Conversion
Television Tuner
VHF PHASE NOISE AT 10kHz OFFSET
vs. CHANNEL FREQUENCY
VHF PHASE NOISE AT 10kHz OFFSET
vs. CHANNEL FREQUENCY
-97
-99
-101
-103
-92
-94
-96
-98
-105
-100
50
55
60
65
CHANNEL FREQUENCY (MHz)
70
170
UHF PHASE NOISE AT 10kHz OFFSET
vs. CHANNEL FREQUENCY
240
VHF PHASE NOISE vs. OFFSET FREQUENCY
MAX3541 toc17
-83
190 200 210 220 230
CHANNEL FREQUENCY (MHz)
-60
fRF = 64.5MHz
VHF PHASE NOISE (dBc/Hz)
-86
-89
-92
-95
-80
-100
-120
-140
400
500
600
700
800
CHANNEL FREQUENCY (MHz)
900
0.1
-70
5
MAX3541 toc19
fRF = 801MHz
0
IFOUT1 POWER (dBm)
-80
-90
-100
-110
1000
IFOUT1 NORMALIZED FREQUENCY RESPONSE
(5MHz to 200MHz)
UHF PHASE NOISE vs. OFFSET FREQUENCY
-60
1
10
100
OFFSET FREQUENCY (kHz)
MAX3541 toc20
UHF PHASE NOISE (dBc/Hz)
-80
180
MAX3541 toc18
45
UHF PHASE NOISE (dBc/Hz)
MAX3541 toc16
MAX3541 toc15
-90
VHF PHASE NOISE (dBc/Hz)
VHF PHASE NOISE (dBc/Hz)
-95
-5
-10
-15
-120
-130
-20
0.1
1
10
100
OFFSET FREQUENCY (kHz)
1000
1
10
100
FREQUENCY (MHz)
1000
_______________________________________________________________________________________
7
MAX3541
Typical Operating Characteristics (continued)
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25°C, unless otherwise noted.)
IFVGA VOLTAGE GAIN vs. IFAGC VOLTAGE
IFVGA IM3 vs. IFAGC VOLTAGE
50
-20
VOUT = 1.5 VP-P
PIN
-30
IFVGA IM3 (dBc)
+25°C
40
+85°C
30
-40
-40
-60
INPUT POWER (dBm)
-40°C
MAX3541 toc22
-20
MAX3541 toc21
60
IFVGA VOLTAGE GAIN (dB)
MAX3541
Complete Single-Conversion
Television Tuner
-50
20
IM3
10
-60
0.5
1.0
1.5
2.0
IFAGC VOLTAGE (V)
2.5
3.0
-80
0.5
1.0
1.5
2.0
IFAGC VOLTAGE (V)
2.5
3.0
Pin Description
PIN
NAME
1
SCL
2-Wire Serial-Clock Interface. Requires a pullup resistor to VCC.
2
SDA
2-Wire Serial-Data Interface. Requires a pullup resistor to VCC.
3, 10, 23, 28,
32, 33, 37,
41, 44
VCC
Power Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor.
4
UHF_IN
5
VHF_IN
6
RFGND2
7
LEXT
8
RFGND3
9
RFAGC
DESCRIPTION
UHF RF Input. Requires a DC-blocking capacitor.
VHF RF Input. Requires a DC-blocking capacitor.
RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2
and RFGND3 together.
RF VGA Supply Voltage. Connect through a 270nH pullup inductor to VCC.
RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2
and RFGND3 together.
RF VGA Gain Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain).
11–22, 27, 31
GND
24
IFOUT2-
Inverting IF VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor.
25
IFOUT2+
Noninverting IF VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor.
26
IFAGC
29
IFIN-
Inverting IF VGA Input. Connect to the output of an IF-SAW filter.
30
IFIN+
Noninverting IF VGA Input. Connect to the output of an IF-SAW filter.
8
Ground. Connect to the PCB’s ground plane.
IF VGA Gain Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain).
34
IFOVLD
35
IFOUT1+
Noninverting IF LNA Output. Requires a DC-blocking capacitor.
IF Overload Detector Open-Collector Output. Requires a 10kΩ pullup resistor to VCC.
36
IFOUT1-
Inverting IF LNA Output. Requires a DC-blocking capacitor.
38
LDO
VCO LDO Bypass. Bypass to ground with a 0.47μF capacitor.
_______________________________________________________________________________________
Complete Single-Conversion
Television Tuner
PIN
NAME
39
GND_TUNE
40
VTUNE
42
MUX
DESCRIPTION
VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GNDs must
be connected to this pin (see the Typical Application Circuit).
VCO Tuning Input. Connect to the PLL loop filter output.
Test Output. Leave this pin unconnected during normal operation.
43
CP
45
XTALN
Charge-Pump Output. Connect to PLL loop filter input.
Crystal Oscillator Feedback. See the Typical Application Circuit.
46
XTALP
Crystal Oscillator Feedback. See the Typical Application Circuit.
47
ADDR1
2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the
I2C-compatible serial interface.
48
ADDR2
2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the
I2C-compatible serial interface.
—
EP
Exposed Pad. Solder evenly to the PCB ground plane for proper operation.
_______________________________________________________________________________________
9
MAX3541
Pin Description (continued)
MAX3541
Complete Single-Conversion
Television Tuner
Detailed Description
Register Descriptions
The MAX3541 includes 11 programmable registers and
2 read-only registers. The 11 programmable registers
include two N-divider registers, an R-divider register, a
VCO register, an IFOVLD/Charge Pump/Filter Select
register, a Control register, a Shutdown register, and
Tracking Filter Control registers. These 11 programmable registers are also readable. The read-only registers
include a status register and a ROM table data register.
Recommended default bit settings are provided for
user convenience only and are not guaranteed. The
user must write all registers after power-up and no earlier than 100μs after power-up.
Table 1. Register Configuration
MSB
REGISTER
NAME
LSB
READ/ REGISTER
WRITE ADDRESS
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
N-DIV High
Both
0x00
0
N14
N13
N12
N11
N10
N9
N8
N-DIV Low
Both
0x01
N7
N6
N5
N4
N3
N2
N1
N0
R-DIV
Both
0x02
0
R6
R5
R4
R3
R2
R1
R0
VCO
Both
0x03
VCO4
VCO3
VCO2
VCO1
VCO0
LD
VDIV1
VDIV0
IFOVLD,
Charge Pump,
and Filter Select
Both
0x04
0
IFOVLD2
IFOVLD1
IFOVLD0
CP1
CP0
TF
0
Control
Both
0x05
0
0
0
0
SHDN
_RF
SHDN
_IFVGA
INPT1
INPT0
Shutdown
Both
0x06
SHDN
_MIX1
SHDN
_MIX0
SHDN
_IF
SHDN
_OD
SHDN
_SYN
0
0
0
Tracking Filter
Series Capacitor
Both
0x07
TFS7
TFS6
TFS5
TFS4
TFS3
TFS2
TFS1
TFS0
Tracking Filter
Parallel Capacitor
Both
0x08
FLD
0
TFP5
TFP4
TFP3
TFP2
TFP1
TFP0
Tracking Filter
ROM Address
Both
0x09
0
0
0
0
TFA3
TFA2
TFA1
TFA0
Reserved
Both
0x0A
X
X
X
X
X
X
X
X
ROM Table
Data Readback
Read
0x0B
TFR7
TFR6
TFR5
TFR4
TFR3
TFR2
TFR1
TFR0
Status
Read
0x0C
POR
LD2
LD1
LD0
X
X
X
X
Table 2. N-DIV High Register (Address: 0000b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
RESERVED
7
0
N[14:8]
6-0
0000001
10
FUNCTION
Must be set to 0.
Sets the most significant bits of the PLL integer divider (N). Default
integer divider value is N = 4688. N can range from 256 to 32,767.
______________________________________________________________________________________
Complete Single-Conversion
Television Tuner
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
N[7:0]
7-0
10101011
MAX3541
Table 3. N-DIV Low Register (Address: 0001b)
FUNCTION
Sets the least significant bits of the PLL integer divider (N). Default
integer divider value is N = 4688. N can range from 256 to 32,767.
Table 4. R-DIV Register (Address: 0010b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
RESERVED
7
0
R[6:0]
6-0
0010000
FUNCTION
Must be set to 0.
Sets the PLL reference divider (R). Default reference divider value is
R = 64. R can range from 16 to 127.
Table 5. VCO Register (Address: 0011b)
BIT NAME
VCO[4:3]
BIT LOCATION (0 = LSB)
7-6
RECOMMENDED
DEFAULT
FUNCTION
10
VCO select. Selects one of three possible VCOs.
00 = VCOs shut down
01 = Selects VCO1
10 = Selects VCO2
11 = Selects VCO3
VCO sub-band select. Selects one of eight possible VCO sub-bands.
000 = Selects SB0
001 = Selects SB1
010 = Selects SB2
011 = Selects SB3
100 = Selects SB4
101 = Selects SB5
110 = Selects SB6
111 = Selects SB7
VCO[2:0]
5-3
111
LD
2
1
Lock detect enable.
0 = Disabled
1 = Enabled
10
VCO divider ratio select.
00 = Sets VCO divider to 4
01 = Sets VCO divider to 8
10 = Sets VCO divider to 16
11 = Sets VCO divider to 32
VDIV[1:0]
1-0
______________________________________________________________________________________
11
MAX3541
Complete Single-Conversion
Television Tuner
Table 6. IFOVLD, Charge Pump, and Filter Select Register (Address: 0100b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
RESERVED
7
0
IFOVLD[2:0]
6-4
000
CP[1:0]
3-2
00
TF
1
0
RESERVED
0
0
FUNCTION
Must be set to 0.
Write content of ROM register OD[2:0] to this location.
Selects the typical charge-pump current.
00 = 0.5mA
01 = 1mA
10 = 1.5mA
11 = 2mA
Selects the tracking filter band of operation.
0 = VHF
1 = UHF
Must be set to 0.
Table 7. Control Register (Address: 0101b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
RESERVED
7-4
0000
SHDN_RF
3
0
SHDN_IFVGA
2
0
INPT[1:0]
1-0
01
FUNCTION
Must be set to 0000.
RF shutdown.
0 = RF circuitry enabled
1 = RF circuitry disabled
IF VGA shutdown.
0 = IF VGA enabled
1 = IF VGA disabled
Selects the RF input.
00 = Selects VHF_IN, LPF enabled
01 = Selects VHF_IN, LPF disabled
10 = Selects UHF_IN
11 = Factory use only
Table 8. Shutdown Register (Address: 0110b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
SHDN_MIX
7-6
00
SHDN_IF
5
0
SHDN_OD
4
0
SHDN_SYN
3
0
RESERVED
2-0
000
12
FUNCTION
Mixer shutdown.
00 = Mixer enabled
01,10 = Factory use only
11 = Mixer disabled
IF shutdown.
0 = IF section enabled
1 = IF section disabled
IFOVLD shutdown.
0 = Power detector enabled
1 = Power detector disabled
Frequency synthesizer shutdown.
0 = Synthesizer enabled
1 = Synthesizer disabled
Must be set to 000.
______________________________________________________________________________________
Complete Single-Conversion
Television Tuner
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
TFS[7:0]
7-0
00001111*
MAX3541
Table 9. Tracking Filter Series Capacitor Register (Address: 0111b)
FUNCTION
Programs series capacitor values in the tracking filter.
*See the RF Tracking Filter section.
Table 10. Tracking Filter Parallel Capacitor Register (Address: 1000b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
FLD
7
0
Filter load bit. A 0 to 1 transition of this bit forces the loading of the
ROM Table Data Readback register.
RESERVED
6
0
Must be set to 0.
TFP[5:0]
5-0
001001*
FUNCTION
Programs parallel capacitor values in the tracking filter.
*See the RF Tracking Filter section.
Table 11. Tracking Filter ROM Address Register (Address: 1001b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
FUNCTION
RESERVED
7-4
0000
Must be set to 0000.
TFA[3:0]
3-0
0000*
Address bits of the ROM register to be read.
*See the RF Tracking Filter section.
Table 12. Reserved Register (Address: 1010b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
RESERVED
7-0
N/A
FUNCTION
Reserved. Do not program these bits during normal operation.
Table 13. ROM Table Data Readback Register (Address: 1011b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
TFR[7:0]
7-0
00000000*
FUNCTION
Tracking filter data bits read from the device’s ROM table.
*See the RF Tracking Filter section.
Table 14. Status Register (Address: 1100b)
BIT NAME
BIT LOCATION (0 = LSB)
RECOMMENDED
DEFAULT
POR
7
N/A
Power-on reset.
0 = Status register has been read
1 = Power reset since last status register read
FUNCTION
LD[2:0]
6-4
N/A
VCO tuning voltage indicators.
000 = PLL not in lock, tune to the next lowest sub-band
001–110 = PLL in lock
111 = PLL not in lock, tune to the next higher sub-band
RESERVED
3-0
N/A
Reserved.
______________________________________________________________________________________
13
MAX3541
Complete Single-Conversion
Television Tuner
2-Wire Serial Interface
The MAX3541 use a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX3541 and the master at
clock frequencies up to 400kHz. The master initiates a
data transfer on the bus and generates the SCL signal to
permit data transfer. The MAX3541 behaves as a slave
device that transfers and receives data to and from the
master. Pull SDA and SCL high with external pullup
resistors (1kΩ or greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX3541 (8 data bits and an
ACK/NACK). The data on SDA must remain stable during
the high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3541 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX3541 has a 7-bit slave address that must be
sent to the device following a START condition to initiate communication. The slave address is determined
by the state of the ADDR2 and ADDR1 pins and is
equal to 11000[ADDR2][ADDR1]. The eighth bit (R/W)
following the 7-bit address determines whether a read
or write operation occurs. Table 15 shows the possible
address configurations.
The MAX3541 continuously awaits a START condition
followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
Table 15. MAX3541 Address Configurations
ADDR2
ADDR1
WRITE ADDRESS
READ ADDRESS
0
0
0xC0
0xC1
0
1
0xC2
0xC3
1
0
0xC4
0xC5
1
1
0xC6
0xC7
SLAVE ADDRESS
S
1
1
0
0
0
ADDR2
ADDR1
R/W
ACK
1
2
3
4
5
6
7
8
9
SDA
SCL
NOTE: TIMING PARAMETERS CONFORM WITH I2C BUS SPECIFICATIONS.
Figure 1. MAX3541 Slave Address Byte
14
______________________________________________________________________________________
P
Complete Single-Conversion
Television Tuner
START
Read Cycle
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3541 issues an
ACK if the slave address byte is successfully
received. The master then sends the 8-bit address of
the first register that it wishes to read. The MAX3541
then issues another ACK. Next, the master must issue
a START condition followed by the 7 slave address
bits and a read bit (R/W = 1). The MAX3541 issues an
ACK if it successfully recognizes its address and
begins sending data from the specified register
address starting with the most significant bit (MSB).
Data is clocked out of the MAX3541 on the rising
edge of SCL. On the 9th rising edge of SCL, the master can issue an ACK and continue reading successive registers or it can issue a NACK followed by a
STOP condition to terminate transmission. The read
cycle does not terminate until the master issues a
STOP condition. Figure 3 illustrates an example in
which registers 0 and 1 are read back.
WRITE DEVICE
ADDRESS
R/W
ACK
WRITE REGISTER
ADDRESS
ACK
WRITE DATA TO
REGISTER 0x00
ACK
WRITE DATA TO
REGISTER 0x01
ACK
WRITE DATA TO
REGISTER 0x02
ACK
11000[ADDR2][ADDR1]
0
—
0x00
—
0x0E
—
0xD8
—
0xE1
—
STOP
Figure 2. Example: Write Registers 0 Through 2 with 0x0E, 0xD8, and 0xE1, Respectively
START
WRITE DEVICE
ADDRESS
110000[ADDR2][ADDR1]
R/W ACK
0
—
WRITE DEVICE
WRITE 1ST REGISTER
ACK
R/W ACK
ADDRESS
ADDRESS
START
—
110000[ADDR2][ADDR1] 1
—
0x00
READ DATA
ACK
REG 0
D7–D0
—
READ DATA
NACK
REG 1
STOP
—
D7–D0
Figure 3. Example: Read Data from Registers 0 and 1
______________________________________________________________________________________
15
MAX3541
Write Cycle
When addressed with a write command, the MAX3541
allows the master to write to a single register or to multiple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3541 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to. If the
slave acknowledges the address, the master can then
write one byte to the register at the specified address.
Data is written beginning with the most significant bit.
The MAX3541 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with
the MAX3541 acknowledging each successful transfer,
or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
MAX3541
Complete Single-Conversion
Television Tuner
Application Information
RF Inputs
The MAX3541 features separate UHF and VHF inputs
that are matched to 75Ω. Both inputs require a DCblocking capacitor. The active inputs are selected by
the input registers. In addition, the input registers
enable or disable the lowpass filter, which can be used
when the VHF input is selected. For the 47MHz to
68MHz, select the VHF_IN with the LPF filter enabled
(INPT = 00). For 174MHz to 230MHz, select VHF_IN
with LPF disabled (INPT = 01). For 470MHz to 862MHz,
select UHF_IN (INPT = 10).
RF Gain Control
The gain of the RF low-noise amplifier can be adjusted
over a typical range of 45dB with the RFAGC pin. The
RFAGC input accepts a DC voltage from 0.5V to 3V,
with 3V providing maximum gain. This pin can be controlled with the IF power-detector output to form a
closed RF gain-control loop. See the Closed-Loop RF
Gain Control section for more information.
RF Tracking Filter
The MAX3541 includes a programmable tracking filter
for each band of operation to optimize rejection of
out-of-band interference while minimizing insertion
loss for the desired received signal. The center frequency of each tracking filter is selected by a
switched-capacitor array that is programmed by the
TFS[7:0] bits in the Tracking Filter Series Capacitor
register and the TFP[5:0] bits in the Tracking Filter
Parallel Cap register.
Optimal tracking filter settings for each channel varies
from part to part due to process variations. To accommodate part-to-part variations, each part is factory calibrated by Maxim. During calibration, the y-intercept
and slope for the series and parallel tracking capacitor
arrays is calculated and written into an internal ROM
table. The user must read the ROM table upon powerup and store the data in local memory (8 bytes total) to
calculate the optimal TFS[7:0] and TFP[5:0] settings
for each channel. Table 16 shows the address and
bits for each ROM table entry. See the Interpolating
Tracking Filter Coefficients section for more information on how to calculate the required values.
Reading the ROM Table
Each ROM table entry must be read using a two-step
process. First, the address of the ROM bits to be read
must be programmed into the TFA[3:0] bits in the
Tracking Filter ROM Address register (Table 11).
Table 16. ROM Table
MSB
LSB
DESCRIPTION ADDRESS
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
0x0
OD2
OD1
OD0
X
X
X
X
X
VHF Series
Y-Intercept
0x1
VS0[7]
VS0[6]
VS0[5]
VS0[4]
VS0[3]
VS0[2]
VS0[1]
VS0[0]
VHF Series
Slope
0x2
VS1[7]
VS1[6]
VS1[5]
VS1[4]
VS1[3]
VS1[2]
VS1[1]
VS1[0]
VHF Parallel
Y-Intercept
0x3
VP0[7]
VP0[6]
VP0[5]
VP0[4]
VP0[3]
VP0[2]
VP0[1]
VP0[0]
VHF Parallel
Slope
0x4
VP1[7]
VP1[6]
VP1[5]
VP1[4]
VP1[3]
VP1[2]
VP1[1]
VP1[0]
UHF Series
Y-Intercept
0x5
US0[7]
US0[6]
US0[5]
US0[4]
US0[3]
US0[2]
US0[1]
US0[0]
UHF Series
Slope
0x6
US1[7]
US1[6]
US1[5]
US1[4]
US1[3]
US1[2]
US1[1]
US1[0]
UHF Parallel
Y-Intercept
0x7
UP0[7]
UP0[6]
UP0[5]
UP0[4]
UP0[3]
UP0[2]
UP0[1]
UP0[0]
UHF Parallel
Slope
0x8
UP1[7]
UP1[6]
UP1[5]
UP1[4]
UP1[3]
UP1[2]
UP1[1]
UP1[0]
16
______________________________________________________________________________________
Complete Single-Conversion
Television Tuner
Interpolating Tracking Filter Coefficients
The TFS[7:0] and TFP[5:0] bits must be reprogrammed
for each channel frequency to optimize performance.
The optimal settings for each channel can be calculated from the ROM table data using the equations below:
VHF filter:
VS0
[
TFS = INT[10 256
[
VP0
TFP = INT[10 256
×5+(
VS1
- 1) × 1.5 × 10 -2 × f RF ]
256
]
×5+(
VP1
- 1) ×10 -2 × f RF ]
256
]
UHF filter:
:
[
US0
TFS = INT[10 256
[
UP0
TFP = INT[10 256
×5+(
US1
- 1) × 5 × 10 -3 × f RF ]
256
] − 10
×5+(
UP1
- 1) × 5 × 10 -3 × f RF ]
256
]
where:
fRF = operating frequency in megahertz.
TFS = decimal value of the optimal TFS[7:0] setting
(Table 9) for the given operating frequency.
TFP = decimal value of the optimal TFP[5:0] setting
(Table 10) for the given operating frequency.
VS0, VS1, VP0, VP1, US0, US1, UP0, and UP1 = the
decimal values of the ROM table coefficients (Table
16).
IF Overload Detector
The MAX3541 includes a broadband IF overload detector, which provides an indication of the total power present at the RF input. The overload-detector output voltage
is compared to a reference voltage, and the difference is
amplified. This error signal drives an open-collector transistor whose collector is connected to the IFOVLD pin,
causing the IFOVLD pin to sink current. The nominal fullscale current sunk by the IFOVLD pin is 300μA. The
IFOVLD pin requires a 10kΩ pullup resistor to VCC.
The IF overload detector is calibrated at the factory to
attack at 0.7VP-P at the IFOUT1. Upon power-up, the
baseband processor must read OD[2:0] from the ROM
table and store it in the IFVOLD register.
Closed-Loop RF Gain Control
Closed-loop RF gain control can be implemented by
connecting the IFOVLD output to the RFAGC input.
Using a 10kΩ pullup resistor on the IFOVLD pin as
shown in the Typical Application Circuit results in a
nominal control voltage range of 0.5V to 3V.
VCO and VCO Divider Selection
The MAX3541 frequency synthesizer includes three
VCOs and eight VCO sub-bands to guarantee a
2200MHz to 4400MHz VCO frequency range. The frequency synthesizer also features an additional VCO frequency divider that must be programmed to either 4, 8,
16, or 32 by the VDIV[1:0] bits in the VCO register based
on the channel being received.
To ensure PLL lock, the proper VCO and VCO sub-band
for the channel being received must be chosen by iteratively selecting a VCO and VCO sub-band, then reading
the LD[2:0] bits to determine if the PLL is locked. Any
reading from 001 to 110 indicates the PLL is locked. If
LD[2:0] reads 000, the PLL is unlocked and the selected
VCO is at the bottom of its tuning range; a lower VCO
sub-band must be selected. If LD[2:0] reads 111, the PLL
is unlocked and the selected VCO is at the top of its tuning range; a higher VCO sub-band must be selected. The
VCO and VCO sub-band settings should be progressively increased or decreased until the LD[2:0] reading falls in
the 001 to 110 range.
Due to overlap between VCO sub-band frequencies, it is
possible that multiple VCO settings can be used to tune
to the same channel frequency. System performance at
a given channel should be similar between the various
possible VCO settings, so it is sufficient to select the first
VCO and VCO sub-band that provides lock.
Layout Considerations
The MAX3541 EV kit can serve as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on
all high-frequency traces. The exposed paddle must be
soldered evenly to the board’s ground plane for proper
operation. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at the central
VCC node. The VCC traces branch out from this node,
with each trace going to separate V CC pins of the
MAX3541. Each VCC pin must have a bypass capacitor
with a low impedance to ground at the frequency of
interest. Do not share ground vias among multiple connections to the PCB ground plane.
______________________________________________________________________________________
17
MAX3541
Once the address has been programmed, the data
stored in that address is transferred to the TFR[7:0] bits
in the ROM Table Data Readback register (Table 13).
The ROM data at the specified address can then be
read from the TFR[7:0] bits and stored in the microprocessor’s local memory.
Complete Single-Conversion
Television Tuner
MAX3541
Typical Application Circuit
4.3kΩ
820pF
560pF
2.2kΩ
**
**
0.033μF
VCC
VCC
22pF
**
1000pF
8MHz
1000pF
**
220pF
VCC
48
47
46
45
44
43
÷R
PD
CP
42
47μF
41
40
1000pF
GND_TUNE
39
VCC
1000pF
LDO
VTUNE
VCC
MUX
CP
XTALN
XTALP
ADDR1
ADDR2
2.7kΩ
VCC
220pF
ADDRESS 2
2.7kΩ
VCC
ADDRESS 1
38
680nH
1000pF
37
SCLK
1000pF
2.7kΩ
RFGND3
RFAGC
IFOVLD
0.1μF
1000pF
VCC
VCC
GND
GND
VREF
+
-
6
32
31
7
30
8
29
9
28
MAX3541
27
10
EP
11
26
25
12
GND
13
14
15
16
17
18
19
20
21
22
23
IFOUT1-
VCC
IFOUT1+
0.1μF
10kΩ
IFOVLD
IFOVLD
VCC
VCC
VCC
IF-SAW
FILTER
VCC
1000pF
GND
1000pF
IFIN+
IFINVCC
VCC
GND
1000pF
2.7kΩ
IFAGC
IFOUT2+
VIFAGC
0.1μF
ANTI-ALIASING
FILTER
24
IFOUT2-
270nH
1000pF
5
VCC
LEXT
33
GND
VCC
VCO
DIVIDER
4
GND
RFGND2
34
GND
VHF_IN
1000pF
3
GND
UHF_IN
35
÷N
SERIAL
INTERFACE
GND
100Ω
2
GND
VCC
1000pF
36
GND
SDA
1
GND
VCC
GND
SCL
SDATA
IFOUT+
IFOUT-
VCC
1000pF
** CONNECT TO COMMON GROUND POINT AT PIN 39
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
18
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 LGA-EP
L4877F+15
21-0152
90-0303
______________________________________________________________________________________
Complete Single-Conversion
Television Tuner
REVISION
NUMBER
REVISION
DATE
0
10/07
Initial release
1
12/07
Correct TOC01 graph and a few errors
2
4/08
Converted part number in Ordering Information to lead-free
1
2/11
Corrected soldering temperature and lead temperature in Absolute Maximum
Ratings
2
3
DESCRIPTION
PAGES
CHANGED
—
1, 2, 5, 7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX3541
Revision History
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